RU2816559C2 - Control method, semiconductor storage device and electronic device - Google Patents

Abstract

FIELD: electrical engineering.

SUBSTANCE: invention relates to semiconductor storage devices. Disclosed is a method of controlling a semiconductor memory device, a semiconductor memory device and an electronic device comprising a semiconductor memory device. Disclosed is an impedance control strategy for a data mask pin in a given test mode so that the impedance of the data mask pin in a given test mode can be set. Determined is the ratio between the control signal configured to control whether to use the pin for the data mask in the double data rate synchronous RAM, and a control signal configured to control whether the pin for the data mask is a test object in the output signal generator packet test mode (PODTM mode).

EFFECT: invention enables to check the impedance of the pin for the data mask in a given test mode in order to prevent errors in data processing by the circuit.

16 cl, 12 dwg

Description

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application is filed based on Chinese Patent Application No. 202210307306.6 and claims priority to that application filed on March 25, 2022, entitled “CONTROL METHOD, SEMICONDUCTOR STORAGE, AND ELECTRONIC DEVICE,” the disclosure of which is incorporated by reference in its entirety herein.

TECHNICAL FIELD

[0002] The present disclosure relates to the field of semiconductor memory technology, particularly a control method, a semiconductor memory and an electronic device.

BACKGROUND OF THE ART

[0003] Dynamic Random Access Memory (DRAM) is a semiconductor memory device typically used in computers having at least a data pin and a Data Mask Pin (DM). Herein, the data pin has dual functions of writing data and reading data, and the DM data mask pin is configured to receive a write data mask input signal and shield unnecessary input data during a write operation, and only supports the data write function. In the fifth release of the memory specification (alternatively called 5th Double Data Rate SDRAM (DDR5)), some test modes require checking the impedance of the data mask (DM) pin or the data pin.

DISCLOSURE OF THE INVENTION

[0004] The present disclosure provides a control method, a semiconductor memory device, and an electronic device, and defines a method for controlling the impedance of a data mask (DM) pin in a predetermined test mode for checking the impedance of a data mask (DM) pin in a predetermined test mode, and to prevent circuit processing errors.

[0005] In a first aspect of the present disclosure, a control method applied to a semiconductor memory device is presented. The semiconductor memory device may include a data mask (DM) pin, and the data mask (DM) pin may be configured to receive a write data mask input signal. The method may include the following operations.

[0006] In response to the semiconductor memory device being in a predetermined test mode, when the fourth operand (OP) in the first Model Register (MR) is in the first state, the impedance of the data mask (DM) pin is controlled as the first the value according to the third operand (OP) in the third operating mode register (MR); or when the fourth operand (OP) in the first operating mode register (MR) is in the second state, the impedance of the data mask (DM) pin is controlled as the second value.

[0007] Herein, a fourth operand (OP) is configured to indicate whether a data mask (DM) pin is to be enabled, and a third operand (OP) is configured to indicate whether a data mask (DM) pin is a test pin. object in the specified test mode.

[0008] In a second aspect of the present disclosure, a semiconductor memory device is provided. The semiconductor memory device may include a data mask (DM) pin, a first operating mode register (MR), a third operating mode register (MR), and a first driver circuit. The first driver circuit is connected to the first operating mode register (MR), the third operating mode register (MR) and the data mask (DM) pin, respectively.

[0009] The data mask (DM) pin may be configured to receive a write data mask input signal.

[0010] The first driver circuit may be configured to: control the impedance of a data mask (DM) pin as a first value in accordance with a third operand (OP) in a third operating mode register (MR), in response to the semiconductor memory device is in a specified test mode when the fourth operand (OP) in the first operating mode register (MR) is in the first state; or controlling the impedance of the data mask (DM) pin as a second value when the fourth operand (OP) in the first operating mode register (MR) is in the second state.

[0011] Herein, a fourth operand (OP) is configured to indicate whether a data mask (DM) pin is to be enabled, and a third operand (OP) is configured to indicate whether a data mask (DM) pin is a test pin. object in the specified test mode.

[0012] In a third aspect of the present disclosure, an electronic device is provided, which may include a semiconductor memory device described in the second aspect.

[0013] Embodiments of the present disclosure provide a control method, a semiconductor memory device, and an electronic device. A data mask (DM) pin impedance control strategy in a given test mode is provided such that the data mask (DM) pin impedance can be set in a given test mode. In addition, a relationship is defined between a control signal configured to control whether a data mask (DM) pin is enabled in DDR5 and a control signal configured to check whether a data mask (DM) pin is a test object in Package Output Driver Test Mode (PODTM) The data mask (DM) pin impedance can be tested in a specified test mode to prevent circuit processing errors.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In FIG. 1 is a schematic flow diagram of a control method according to one embodiment of the present disclosure.

[0015] In FIG. 2 is a schematic block diagram of yet another control method according to one embodiment of the present disclosure.

[0016] In FIG. 3 is a schematic diagram of the structure of a semiconductor memory device according to one embodiment of the present disclosure.

[0017] In FIG. 4 is a schematic diagram of the structure of yet another semiconductor memory device according to one embodiment of the present disclosure.

[0018] In FIG. 5 is a schematic diagram of the structure of a first decoding module according to one embodiment of the present disclosure.

[0019] In FIG. 6 is a schematic diagram of the structure of a first driver circuit according to one embodiment of the present disclosure.

[0020] In FIG. 7 is a first schematic diagram of a detailed structure of a first driver circuit according to one embodiment of the present disclosure.

[0021] In FIG. 8 is a second schematic diagram of a detailed structure of a first driver circuit according to one embodiment of the present disclosure.

[0022] In FIG. 9 is a schematic diagram of the structure of a second driver circuit according to one embodiment of the present disclosure.

[0023] In FIG. 10 is a first schematic diagram of a detailed structure of a second driver circuit according to one embodiment of the present disclosure.

[0024] In FIG. 11 is a second schematic diagram of a detailed structure of a second driver circuit according to one embodiment of the present disclosure.

[0025] In FIG. 12 is a schematic diagram of a compositional structure of an electrical device according to one embodiment of the present disclosure.

IMPLEMENTATION OF THE INVENTION

[0026] The technical solutions in the embodiments of the present disclosure will be clearly and fully described in conjunction with the drawings in the embodiments of the present disclosure. It should be understood that these specific embodiments described herein are used only to show the relevant disclosure and are not intended to limit the scope of protection of the disclosure. In addition, it should be noted that for ease of description, only those parts that relate to the corresponding disclosure are shown in the drawings.

[0027] Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art of the present disclosure. The terms used herein are used only for the purpose of describing embodiments of the present disclosure and are not intended to limit the present disclosure.

[0028] In the following description, reference is made to "certain embodiments" which describe a subset of all possible embodiments, but it should be understood that "certain embodiments" may be the same or different subsets of all possible implementations and may be combined with each other without conflict.

[0029] It should be noted that the terms "first\second\third" included in embodiments of the present disclosure are used only to distinguish like objects, and do not represent a specific order of objects. It should be understood that a particular first/second/third order or sequence may be interchangeable under appropriate circumstances, so that embodiments of the disclosure described herein may be implemented in an order different from that shown or described herein.

[0030] The following are explanations of technical terms included in embodiments of the present disclosure and the corresponding relationships of certain terms:

[0031] Dynamic random access memory (DRAM);

[0032] Synchronous dynamic random access memory (SDRAM);

[0033] Double Data Rate (DDR) SDRAM;

[0034] DDR5 Specification (DDR5 SPEC);

[0035] Data pin (DQ);

[0036] Data mask pin ((DM));

[0037] Burst Output Conditioner Test Mode (PODTM);

[0038] Operating Mode Register (MR);

[0039] Operand (OP);

[0040] The DDR5 SPEC specification defines a new test mode called PODTM mode, which is configured to enable the output driver for a given DQ pin or data mask (DM) pin through the host computer after the chip is placed in the package, and simultaneously placing other DQ pins or data mask (DM) pins in the operation completion state to check whether the increasing impedance of the engaged DQ pin or data mask (DM) pin in the output driver state is as expected. However, since the output driver state of a data mask (DM) pin is not initially set, the PODTM mode may not be adapted to a given data mask (DM) pin, and circuit data processing errors easily occur.

[0041] Based on this, embodiments of the present disclosure provide a control method. A strategy for controlling the impedance of the data mask (DM) pin in a given test mode is provided, so that the impedance of the data mask (DM) pin in a given test mode can be set. In addition, a relationship is defined between a control signal configured to control whether a given data mask (DM) pin is enabled in DDR5 and a control signal configured to control whether a data mask (DM) pin is a test object in PODTM mode. The data mask (DM) pin impedance can be tested in a specified test mode to prevent circuit processing errors.

[0042] Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0043] In one embodiment of the present disclosure, a control method is provided, which may include the following: in response to a semiconductor memory device being in a predetermined test mode when a data mask (DM) pin is selected as the test object, by an impedance the data mask (DM) pin is controlled as a first impedance parameter, via a first operating mode register (MR); or when the data mask (DM) pin is not the test object, the impedance of the data mask (DM) pin is controlled as a second impedance parameter, through a second operating mode register (MR).

[0044] It should be noted that this control method is applied to a semiconductor memory device. The semiconductor memory device includes a data mask (DM) pin and at least one DQ pin. Herein, the DQ pin is configured to receive or output data and has a write function or a read function, and also has a completion state and an output driver state. The data mask (DM) pin is configured to receive a write data mask input signal and has only a write function and also has a completion state.

[0045] In this embodiment of the present disclosure, the specified test mode refers to the PODTM mode introduced in DDR5, wherein the PODTM mode is configured to test the impedance of a data mask (DM) pin or at least one DQ pin after mounting the die in the package . More specifically, PODTM mode allows the host to test the rising impedance of the data mask (DM) pin or DQ pin.

[0046] When the data mask (DM) pin is selected as a test object in PODTM mode, the first operating mode register (MR) is enabled to control the impedance of the data mask (DM) pin as the first impedance parameter. In this case, since the first operation mode register (MR) is configured to indicate the rising impedance of the DQ pin in the output signal driver state, the host computer can check the rising impedance related to the output gain for the data mask (DM) pin and there is no need Set the output driver state for the data mask (DM) pin.

[0047] When the data mask (DM) pin is not a test object in PODTM mode, the second operating mode register (MR) is allowed to control the impedance of the data mask (DM) pin as a second impedance parameter. In this case, since the second operating mode register (MR) is configured to indicate the impedance in the termination state, the influence of the data mask (DM) pin on the test result of the selected test object can be eliminated.

[0048] Thus, when the semiconductor memory device is in a predetermined test mode, the first operating mode register (MR) and the second operating mode register (MR) are enabled to directly set the impedance of the data mask (DM) pin. For a data mask (DM) pin, there is no need to further set the state of the output driver and associated control circuitry for a given test mode to ensure that said specified test mode is adapted to that data mask (DM) pin. The data mask (DM) pin impedance can be checked in a specified test mode to prevent circuit data processing errors.

[0049] In some embodiments, the method further includes the following: in response to the semiconductor memory device being in a predetermined test mode when the DQ pin is selected as a test object, the impedance of the DQ pin is controlled as a first impedance parameter, via a first register operating mode (MR); or when the DQ pin is not the test object, the impedance of the DQ pin is controlled as a second impedance parameter, through a second operating mode register (MR).

[0050] Thus, when the DQ pin is selected as a test object in the PODTM mode, the increasing impedance of the output driver for the DQ pin is controlled through the first operating mode register (MR) so as to obtain a test result of the DQ pin. When the DQ pin is not selected as a test object in PODTM mode, the DQ pin is controlled to put it into a completed state via the second Run Mode Register (MR) and thus avoids the DQ pin influencing the test result of the selected test object .

[0051] In some embodiments, it is determined through a third operating mode register (MR) that the semiconductor memory device is entering a predetermined test mode and a test object is selected; or it is determined through a third operating mode register (MR) that the semiconductor memory device is not in a predetermined test mode.

[0052] It should be understood that each operating mode register (MR) has several operand (OP) bits to provide associated control functions. In this embodiment of the present disclosure, the operand (OP) related to the embodiment of the present disclosure in the first operating mode register (MR) is called the first operand (OP), the operand (OP) related to the embodiment of the present disclosure in the second operating mode register ( MR) is called a second operand (OP), and an operand (OP) related to an embodiment of the present disclosure in a third operating mode register (MR) is called a third operand (OP).

[0053] Thus, in this embodiment of the present disclosure, it is determined through the third OP in the third operating mode register (MR) whether the semiconductor memory device enters the PODTM mode, and in the case of entering the PODTM mode, a test object is selected from the data mask pin ( DM) and at least one DQ. The impedance of the selected test object is then controlled as the first impedance parameter (essentially the increasing impedance of the output driver) through the first operand (OP) in the first operating mode register (MR), and the impedance of the unselected pin is controlled as the second impedance parameter (essentially the termination impedance) , through the second operand (OP) in the second operating mode register (MR) so as to obtain the result of the impedance tests for the test object. The data mask (DM) pin should not contribute to setting the state of the output driver and its associated control circuitry for a given test mode to ensure that the specified test mode is adapted to the data mask (DM) pin. The data mask (DM) pin impedance can be checked in a specified test mode to prevent circuit data processing errors.

[0054] In some embodiments, the standard number of the first operating mode register (MR) is 5, and the first operand (OP) is the operand (OP) from the second bit to the first bit stored in the first operating mode register (MR), represented as MR5 OP[2:1]. The standard number of the second operating mode register (MR) is 34, and the second operand (OP) is the operand (OP) from the second bit to the 0th bit stored in the second operating mode register (MR), represented as MR34 OP[2:0 ]. The standard number of the third operating mode register (MR) is 61, and the third operand (OP) is the operand (OP) from the 4th bit to the 0th bit stored in the third operating mode register (MR), represented as MR61 OP[4 :0]. In this case, the standard number refers to the serial number of the operating mode register (MR) in DDR5.

[0055] The third operand MR61 OP[4:0], the first operand MR5 OP[2:1], and the second operand MR34 OP[2:0] are specifically described below in conjunction with Tables 1-3.

[0056] As shown in Table 1, the operand MR61 OP[4:0] is configured to determine whether to enter the PODTM mode and determine the selected pin. It should be understood that the numbers of bits for data mask (DM) and DQ data are different for semiconductor memories with different bits. For 4-bit memory (X4), there is one data mask (DM) pin with low-level bits (represented as DML) and four DQ pins with low-level bits (respectively called DQL0-DQL3). For 8-bit memory (X8), there is one data mask (DM) pin with low-level bits (represented as DML) and eight DQ pins with low-level bits (respectively called DQL0-DQL7). For 16-bit memory (X16), there is one data mask (DM) pin with low-level bits (represented as DML), one data mask (DM) pin with high-level bits (represented as DMU), eight DQ pins with low-level bits bits (respectively called DQL0-DQL8) and eight DQ pins with high-level bits (respectively called DQU0-DQU8).

[0057] If the operand MR61 OP[4:0]=00000 _B , it means that the semiconductor memory device is not in PODTM mode. If the value of operand MR61 OP[4:0] is any combination other than 00000B in Table 1, it means that the semiconductor memory device is in PODTM mode. Specifically, if MR61 OP[4:0]=00001 _B , it means the test object is a DML pin. If MR61 OP[4:0]=00010 _B , this means that the test object is the DMU pin (only valid for 16-bit memory). If MR61 OP[4:0]=10000 _B , it means the test object is the 0-bit data pin of DQL0. Others may be understood by analogy and will not be explained separately.

Table 1 Mode register (MR) and operand register (OP) bits Function Parameter description MR61 OP[4:0] Batch test mode of the output signal driver 00000 _B : Batch test canceled (Default)
00001 _B : DML Batch Test
00010 _B : DMU burst test (X16 only)
10000 _B : Batch test DQL0
10001 _B : DQL1 Batch Test
10010 _B : DQL2 Batch Test
10011 _B : DQL3 Batch Test
10100 _B : DQL4 Batch Test (X8 and X16 only)
10101 _B : DQL5 batch test (X8 and X16 only)
10110 _B : DQL6 batch test (X8 and X16 only)
10111 _B : DQL7 batch test (X8 and X16 only)
11000 _B : DQU0 burst test (X16 only)
11001 _B : DQU1 burst test (X16 only)
11010 _B : DQU2 burst test (X16 only)
11011 _B : DQU3 batch test (X16 only)
11100 _B : DQU4 burst test (X16 only)
11101 _B : DQU5 batch test (X16 only)
11110 _B : DQU6 batch test (X16 only)
11111 _B : DQU7 batch test (X16 only)

[0058] As shown in Table 2, the MR5 OP[2:1] operand is configured to determine a rising output driver impedance for the DQ pin, such that the impedance of the selected pin is controlled as the first impedance parameter, via the MR5 OP[2:1] operand in PODTM mode.

[0059] If MR5 OP[2:1]=00 _B , this means that the increasing impedance of the input amplifier should be RZQ/7, i.e. 34 Ohm. If MR5 OP[2:1]=01 _B , this means that the input amplifier's boost impedance should be RZQ/6, i.e. 40 Ohm. If MR5 OP[2:1]=10 _V , this means that the input amplifier's increasing impedance should be RZQ/5, i.e. 48 Ohm. In this case, RZQ represents the standard value of active resistance, i.e. 240 Ohm.

table 2 Mode register (MR) and operand register (OP) bits Function Parameter description MR5 OP[2:1] Increasing impedance of the output signal driver 00 _B : RZQ/7 (34)
01 _B : RZQ/6 (40)

[0060] As shown in Table 3, the MR34 OP[2:0] operand is configured to determine the termination impedance (RTT_PARK) of a DQ pin or a data mask (DM) pin, such that the impedance of the unselected pin is controlled as a second impedance parameter, via the operand MR34 OP[2:0] in PODTM mode.

[0061] If MR5 OP[2:0]=001 _B , it means that the termination impedance is RZQ, i.e. 240 Ohm. If MR5 OP[2:0]=010 _B , it means that the termination impedance is RZQ/2, i.e. 120 Ohm. Other operands can be understood by analogy and will not be explained separately.

Table 3 Mode register (MR) and operand register (OP) bits Function Parameter description MR34 OP[2:0] RTT_PARK 000 _B : RTT_OFF default
001 _B : RZQ (240)
010 _B : RZQ/2 (120)
011 _B : RZQ/3 (80)
100 _B : RZQ/4 (60)
101 _B : RZQ/5 (48)
110 _B : RZQ/6 (40)
111 _B : RZQ/7 (34)

[0062] In addition, unexplained portions in Tables 1-3 can be understood with reference to the DDR5 Specification.

[0063] As can be seen from the above, when the DRAM is in PODTM mode, the host computer is allowed to independently turn on the output driver circuitry of a single pin in the DRAM and control the other pins so that they are in the completion state at the same time to execute testing the characteristics of the DRAM memory located in the housing. To enable PODTM mode, the host computer selects the data mask (DM) pin or DQ pin as the test target by setting the operand MR61:OP[4:0], and the host computer also controls the increasing impedance value of the test target output driver circuit so that this value is 34 ohms by setting MR5 OP[2:1]=00 _B . At the same time, the impedance state of the remaining data mask (DM) pins or DQ data pins in the DRAM is set to RTT_PARK via the MR34 OP[2:0] operand. It should be noted that whether the Data Mask (DM) pin is enabled or disabled is determined by the MR5 OP[5] operand. In addition, if the data mask (DM) pin is selected as the test target in PODTM mode, the DRAM can set the impedance of the data mask (DM) pin according to the MR5 OP[2:1] operand.

[0064] In some embodiments, when determining whether a semiconductor memory device has been entered into a predetermined test mode, the method further includes the following steps.

[0065] A first operand (OP) is stored in a first operating mode register (MR), a second operand (OP) is stored in a second operating mode register (MR), and a third operand (OP) is stored in a third operating mode register (MR).

[0066] Decoding processing is performed on the third operand to obtain a first test flag signal and at least one second test flag signal. Herein, the first test flag signal indicates whether the data mask (DM) pin is a test object, and the second test flag signal indicates whether the DQ pin is a test object.

[0067] One of the first and second operands (OP) is selected to control the impedance of the data mask (DM) pin according to the first test flag signal.

[0068] It should be noted that the first test flag signal is an internal flag signal input to the data mask (DM) pin to indicate whether the data mask (DM) pin is a test object in PODTM mode. The second test flag signal is an internal flag signal input to the DQ data pin to indicate whether the DQ pin is a test object in PODTM mode. Both the first test flag signal and the second test flag signal are obtained by decoding in accordance with the MR61 operand OP[4:0] shown in detail in Table 1 above.

[0069] To implement the above mechanism, a specific signal processing method is given below as an example.

[0070] In some embodiments, with respect to a data mask (DM) pin, the method further includes the following steps.

[0071] A first non-test state control signal and a second impedance control signal are determined.

[0072] In response to the semiconductor memory device being in a predetermined test mode, a first impedance control signal is determined based on one of the first operand (OP) and the second operand (OP) in accordance with the first test flag signal. Alternatively, in response to the semiconductor memory device not being in a predetermined test mode, a first impedance control signal is determined based on the first non-test state control signal.

[0073] One of the first impedance control signal and the second impedance control signal is selected for controlling the impedance of the data mask (DM) pin in accordance with the operating state of the semiconductor memory device.

[0074] It should be noted that although the functions of the data mask (DM) pin and the DQ data pin are different, the data mask (DM) pin and the DQ pin have similar signal control principles and circuit structures for ease of industrial manufacturing. In particular, each pin can be considered to have a read-related attribute and a write-related attribute, and the final impedance of each pin is controlled by an effective signal in the signal corresponding to the read attribute and the signal corresponding to the read-related attribute. Thus, each pin respectively supports a read function and a write function according to different operating scenarios (although the read function of the data mask (DM) pin is not enabled).

[0075] In one case, the first non-test state control signal is configured to indicate the impedance of the data mask (DM) pin in a state other than the specified test state, and the second impedance control signal is configured to indicate the impedance of the DQ pin in the output driver state. Here, the impedance of a data mask (DM) pin in a state other than a predetermined test state may include an impedance during normal writing and an impedance during non-reading and writing, each of which is related to an attribute related to writing.

[0076] At this time, the first non-test state control signal can be understood as a signal corresponding to a write-related attribute, and the second impedance control signal can be understood as a signal corresponding to a read-related attribute. That is, in the PODTM mode, the first impedance control signal corresponding to the PODTM mode is determined according to one of the first operand (OP) or the second operand (OP); or in the absence of a PODTM mode, the first impedance control signal corresponding to the write-related attribute is determined in accordance with the first non-test state control signal. Then, according to the operating state of the semiconductor memory device, the impedance of the data mask (DM) pin is controlled using a PODTM mode or a first impedance control signal corresponding to a write-related attribute or a second impedance control signal corresponding to a read-related attribute. The first calibration signal is configured to calibrate a standard resistance value in accordance with the following description. Thus, by combining the signal control strategy of the data mask (DM) pin in PODTM mode with the signal control strategy of the record-related attribute, impedance control in PODTM mode is realized.

[0077] In particular, operating states of a semiconductor memory device may include a write state, a read state, a non-read state, a non-write state, and a predetermined test mode (PODTM). Herein, (1), when the semiconductor memory device is in a write state or a non-read state and a non-write state or a predetermined test mode, the impedance of the data mask (DM) pin is controlled using a first impedance control signal. (2) When the semiconductor memory is in the read state, the impedance of the data mask (DM) pin is controlled using the second impedance control signal.

[0078] In another case, the first non-test state control signal is configured to indicate the impedance of the DQ pin in the output signal driver state, and the second impedance control signal is configured to indicate the impedance of the data mask (DM) pin in a state other than the specified test state.

[0079] At this time, the first non-test state control signal may be considered a signal corresponding to a read-related attribute, and the second impedance control signal may be considered a signal corresponding to a write-related attribute. That is, in the PODTM mode, the first impedance control signal corresponding to the PODTM mode is determined in accordance with one of the first operand (OP) or the second operand (OP). Or, in the absence of a PODTM mode, the first impedance control signal corresponding to the read-related attribute is determined in accordance with the first non-test state control signal. Then, according to the operating state of the semiconductor memory device, the impedance of the data mask (DM) pin is controlled using a PODTM mode or a first impedance control signal corresponding to a read-related attribute or a second impedance control signal corresponding to a write-related attribute. Thus, by combining the signal control strategy of the data mask (DM) pin in PODTM mode with the signal control strategy of the read-related attribute, impedance control in PODTM mode is realized.

[0080] In particular, the operating states of the semiconductor memory device may include a write state, a read state, a non-read state, and a non-write state, as well as a predetermined test mode (PODTM). Herein, (1), when the semiconductor memory device is in a write state or a non-read state and a non-write state, the impedance of the data mask (DM) pin is controlled using a second impedance control signal. (2) When the semiconductor memory device is in a read state or a predetermined test mode, the impedance of the data mask (DM) pin is controlled using the first impedance control signal.

[0081] Likewise, a specific signal control method for the DQ pin is described below by way of example.

[0082] In some embodiments, for a DQ pin, the method further includes the following steps.

[0083] A third non-test state control signal, a fourth impedance control signal, and a fifth impedance control signal are determined.

[0084] In response to the semiconductor memory device being in a predetermined test mode, the third impedance control signal is determined based on one of the first OP and the second OP in accordance with the second test flag signal. Alternatively, in response to the semiconductor memory device not being in a predetermined test mode, a third impedance control signal is determined based on the third non-test state control signal.

[0085] According to the operating state of the semiconductor memory device, a third impedance control signal and a fifth impedance control signal are selected to control the impedance of the DQ pin, or a fourth impedance control signal and a fifth impedance control signal are selected to control the impedance of the DQ pin.

[0086] Thus, in one case, the third non-test state control signal is configured to indicate the impedance of the corresponding DQ pin in the termination state, and the fourth impedance control signal and the fifth impedance control signal are collectively configured to indicate the impedance of the corresponding DQ pin in the output signal driver state . Thus, by combining the DQ pin signal control strategy in PODTM mode and the write-related attribute signal control strategy, impedance control in PODTM mode is realized.

[0087] In particular, the operating states of the semiconductor memory device may include a write state, a read state, a non-read state, and a non-write state, as well as a predetermined test mode (PODTM). Herein, when the semiconductor memory device is in a write state or a non-read state and a non-write state or a predetermined test mode, the impedance of the DQ pin is controlled using a second impedance control signal. When the semiconductor memory device is in a read state, the impedance of the DQ pin is controlled using a fourth impedance control signal and a fifth impedance control signal.

[0088] In another case, the third non-test state control signal and the fifth impedance control signal are jointly configured to indicate the impedance of the corresponding DQ pin in the output signal driver state, and the fourth impedance control signal is configured to indicate the impedance of the corresponding DQ pin in the completion state. Thus, by combining the signal control strategy of the DQ pin in PODTM mode with the signal control strategy of the read-related attribute, impedance control in PODTM mode is realized.

[0089] In particular, the operating states of the semiconductor memory device may include a write state, a read state, a non-read state, and a non-write state, as well as a predetermined test mode (PODTM). Herein, (1), when the semiconductor memory device is in the write state or the non-read state and the non-write state, the impedance of the DQ pin is controlled using the fourth impedance control signal and the fifth impedance control signal. (2) when the semiconductor memory device is in a read state or a predetermined test state, the impedance of the DQ pin is controlled using the third impedance control signal and the fifth impedance control signal.

[0090] It should be understood that the write function only covers control of rising impedance (as termination impedance), and the read function covers control of rising impedance and falling impedance simultaneously. Since the data mask (DM) pin only enables the write function and not the read function, the data mask (DM) pin covers only the increasing impedance control signal, and its decreasing impedance control signal will be set as a fixed level signal to disable the impedance decreasing function . In addition, since the DQ pin supports a write function and a read function simultaneously, the DQ pin can cover an impedance-increasing control signal and an impedance-lowering control signal.

[0091] Thus, the read-related attribute of the data mask (DM) pin covers only one signal (the first non-test state control signal or the second impedance control signal) that is configured to control increasing impedance. The read-related attribute of the DQ pin covers two signals (a third non-test state control signal and a fifth impedance control signal, or a fourth impedance control signal and a fifth impedance control signal) that respectively control increasing impedance and decreasing impedance.

[0092] Embodiments of the present disclosure provide a control method. When the semiconductor memory device is in a specified test mode, the first operating mode register (MR) and the second operating mode register (MR) related to the DQ pin are enabled to directly set the impedance of the data mask (DM) pin. The data mask (DM) pin should not contribute to setting the state of the output driver and associated control circuitry for a given test mode to ensure that the specified test mode is adapted to the data mask (DM) pin. The data mask (DM) pin impedance can be checked in a specified test mode to prevent circuit processing errors.

[0093] Additionally, for the above-mentioned control method, after entering a predetermined test mode, the impedance state of the data mask (DM) pin is determined by an internal flag signal (the first test flag signal). However, DDR5 uses an enable control signal configured to indicate whether to enable the data mask (DM) pin. Thus, the enable control signal may also control the impedance state of the data mask (DM) pin, so that the driving strategy of the data mask (DM) pin may be confused, resulting in a data processing error by the circuit. It should be understood that since the DQ pin is always in the enabled state in normal operating mode and does not involve any enable or disable control, this problem does not exist.

[0094] Based on this, in yet another embodiment of the present disclosure with reference to FIG. 1 is a flowchart of a control method according to one embodiment of the present disclosure. As shown in FIG. 1, the method may include the following steps.

[0095] In step S101, in response to the semiconductor memory device being in a predetermined test mode when the fourth operand (OP) in the first operating mode register (MR) is in the first state, the impedance of the data mask (DM) pin is controlled as the first value, in accordance with the third operand (OP) in the third operating mode register (MR); or when the fourth operand (OP) in the first operating mode register (MR) is in the second state, the impedance of the data mask (DM) pin is controlled as the second value.

[0096] It should be noted that the control method provided by this embodiment of the present disclosure is applied to the above-mentioned semiconductor memory device. The semiconductor memory device includes a data mask (DM) pin, wherein the data mask (DM) pin is configured to receive a write data mask input signal. The specified test mode is PODTM mode.

[0097] It should be noted that a fourth operand (OP) is configured to indicate whether the data mask (DM) pin is enabled, and a third operand (OP) is configured to indicate whether the data mask (DM) pin is a test pin. object in the specified test mode.

[0098] In addition, the first operating mode register (MR) is represented as MR5, the third operating mode register (MR) is represented as MR61, and the third operand (OP) is represented as operand MR61 OP[4:0], which can be referenced Refer to the description above for details. In addition, the fourth operand (OP) refers to the 5th operand (OP) stored in the first operating mode register (MR), and is represented as the MR5 operand OP[5].

[0099] Thus, since both the third operand (OP) and the fourth operand (OP) can influence the impedance state of the data mask (DM) pin, to prevent data processing errors in the circuit, the following impedance control strategy is provided: if the fourth operand ( OP) is in the first state, the impedance of the data mask (DM) pin is determined in conjunction with the state of the third operand (OP), and if the fourth (OP) is in the second state, the impedance of the data mask (DM) pin is determined directly. Thus, the impedance of the data mask (DM) pin can be checked in a given test mode to prevent data processing errors by the circuit.

[00100] In some implementations, the first state indicates the data mask (DM) pin is enabled. The first value includes a first impedance parameter and a second impedance parameter. The operation of controlling the impedance of a data mask (DM) pin as a first value in accordance with a third operand (OP) in a third operating mode register (MR) may include the following operations.

[00101] If the third operand (OP) is in the third state, the impedance of the data mask (DM) pin is controlled as a first impedance parameter, in accordance with the first operand (OP) in the first operating mode register (MR). The third state indicates that the data mask (DM) pin is being tested in the specified test mode. If the third operand (OP) is in the fourth state, the impedance of the data mask (DM) pin is controlled as a second impedance parameter in accordance with the second operand (OP) in the second operating mode register (MR). The fourth state indicates that the data mask (DM) pin is not a test object in the specified test mode.

[00102] It should be noted that the semiconductor memory device further includes at least one DQ pin. The DQ pin is configured to receive or output data, wherein a first operand (OP) is configured to indicate that the impedance of at least one DQ pin in the output signal conditioner state is a first impedance parameter, and a second operand (OP) is configured to indicating that the impedance of the at least one DQ pin in the completion state is a second impedance parameter, for which the above description may be referred to for details.

[00103] In this case, the first operand (OP) is represented as an operand MR5 OP[2:1], and the second operand (OP) is represented as an MR34 OP[2:0], for which reference may be made to the above description for details. In addition, in the DDR5 Specification, in the case of MR5 OP[5]=1B, it is defined that the fourth operand (OP) is in the first state, i.e. the data mask (DM) pin will be enabled.

[00104] Thus, when a data mask (DM) pin is selected as a test object in PODTM mode, the first operand (OP) is allowed to control the impedance of the data mask (DM) pin as the first impedance parameter. In this case, since the first operand (OP) is configured to indicate the rising impedance of the DQ pin in the output signal conditioner state, the host computer can check the rising impedance related to the output gain for the data mask (DM) pin, and there is no need to specify state of the data mask (DM) pin output driver. When the data mask (DM) pin is not a test object in PODTM mode, the second operand (OP) is allowed to control the impedance of the data mask (DM) pin as a second impedance parameter. In this case, since the second operand (OP) is configured to indicate an impedance in the termination state, the influence of the data mask (DM) pin on the test result of the selected test object can be avoided.

[00105] In some embodiments, the second value refers to the high Hi-Z impedance condition. The second state indicates that the Data Mask (DM) pin is disabled. As shown in FIG. 2, the operation of controlling the impedance of the data mask (DM) pin as a second value includes the following operation.

[00106] The data mask (DM) pin is controlled to be in a high impedance Hi-Z state via the first fixed level signal.

[00107] It should be noted that in the DDR5 Specification, in the case where MR5 OP[5]=0B, it is defined that the fourth operand (OP) is in the second state, i.e. the data mask (DM) pin will not be used. Currently, the data mask (DM) pin is in the Hi-Z high impedance state.

[00108] In some embodiments, the method further includes the following steps.

[00109] In step S201, a first operand (OP) and a fourth operand (OP) stored in the first operating mode register (MR), a second operand (OP) stored in the second operating mode register (MR), and a third operand (OP) are obtained ), stored in the third operating mode register (MR).

[00110] In step S202, the third operand (OP) and the fourth operand (OP) are decoded respectively to obtain the first test flag signal and the enable control signal.

[00111] In step S203, in response to the semiconductor memory device being in a predetermined test mode, in the case where the enable control signal is in the first level state, the first operand (OP) or the second operand (OP) is selected to control the pin impedance for a data mask (DM) in accordance with the level state of the first test flag signal; or in the case where the enable control signal is in the second level state, the data mask (DM) output pin is controlled as in the high impedance state by the first fixed level signal.

[00112] Here, when the fourth operand (OP) is in the first state, the enable control signal is in the first level state. When the fourth operand (OP) is in the second state, the enable control signal is in the second level state. When the third operand (OP) is in the third state, the first test flag signal is in the first level state. When the third operand (OP) is in the fourth state, the first test flag signal is in the second level state.

[00113] In the following description, the first level state may be logical "1" and the second level state may be logical "0", but this is not a relevant limitation. In the case of adaptive circuit logic tuning, the first level state may be logic "0" and the second level state may be logic "1". Meanwhile, the specific value of the first level latch state also needs to be determined according to the adaptability of the circuit logic.

[00114] The signal control strategy for a given test mode is described in detail below with reference to Table 4. In Table 4, the first test flag signal is represented by PODTM_EN, the destructive control signal is represented by DM_enable, the test enable signal PODTM_EN=1 means that the semiconductor memory device enters PODTM mode, and X, refers to logic "0" or logic "1".

Table 4 PODTM_EN DM_
enable PODTM_DM_EN DM DQ 1 0 X Hi-Z Test object: RONpu (MR5 OP[2:1])
Non-test object: RTT_PARK(MR34 OP[2:0]) 1 1 0 RTT_PARK (MR34 OP[2:0]) Test object: RONpu (MR5 OP[2:1])
Non-test object: RTT_PARK (MR34 OP[2:0]) 1 1 1 RONpu (MR5 OP[2:1]) RTT_PARK (MR34 OP[2:0])

[00115] As shown in Table 4, after entering PODTM mode (PODTM_EN=1), the following situations exist.

[00116] (1) For the data mask (DM) pin, if the enable control signal DM_enable is logic "0", no matter what state the first test flag signal PODTM_DM_EN is in, the data mask (DM) pin is in the state Hi-Z high impedance. For DQ, the impedance of the DQ pin selected as the test object is the first impedance parameter, which is specifically controlled by the first operand MR5 OP[2:1]. The impedance of the DQ pin not selected as a test object is the second impedance parameter, which is specifically controlled by the second operand MR34 OP[2:0].

[00117] (2) For the data mask (DM) pin, if the enable control signal DM_enable is logic "1" and the first test flag signal PODTM_DM_EN is logic "0", it means that the data mask (DM) pin is not is a test object, and its impedance is the second impedance parameter RTT_PARK, which is specifically controlled by the second operand MR34 OP[2:0]. For a DQ pin, the impedance of the DQ pin selected as the test object is the first impedance parameter, which is specifically controlled by the first operand MR5 OP[2:1]. The impedance of the DQ pin not selected as a test object is the second impedance parameter, which is specifically controlled by the second operand MR34 OP[2:0].

[00118] (3) For the data mask (DM) pin, if the enable control signal DM_enable is logic "1" and the first test flag signal PODTM_DM_EN is logic "1", it means that the data mask (DM) pin is test object, and its impedance is the first impedance parameter RONpu, which, in particular, is controlled by the first operand MR5 OP[2:1]. For DQ, all DQ pins are non-test objects, so the DQ pin impedance is the second parameter of the RTT PARK impedance, which is specifically controlled by the second operand MR34 OP[2:0].

[00119] Thus, embodiments of the present disclosure provide an impedance control strategy for a data mask (DM) pin in PODTM mode that allows the impedance of a data mask (DM) pin to be checked in PODTM mode to prevent processing errors by the circuit.

[00120] To implement the above impedance control strategy, a specific signal processing method is given below as an example.

[00121] In some embodiments, the method further includes the following steps.

[00122] A first non-test state control signal and a second impedance control signal are determined.

[00123] In response to the semiconductor memory device being in a predetermined test mode, a first impedance control signal is set based on one of the first fixed level signal, the first operand (OP) and the second operand (OP) in accordance with the level state of the first test flag signal and the state of the activation control signal level. Alternatively, in response to the semiconductor memory not being in a predetermined test mode, a first impedance control signal is set based on the first non-test state control signal.

[00124] One of the first impedance control signal and the second impedance control signal is selected for controlling the impedance of the data mask (DM) pin in accordance with the operating state of the semiconductor memory device.

[00125] In one case, the first non-test state control signal is configured to indicate the impedance of the data mask (DM) pin in a state other than the specified test state, and the second impedance control signal is configured to indicate the impedance of the DQ pin in the output driver state. Thus, by combining the signal control strategy of the data mask (DM) pin in PODTM mode and the signal control strategy of the record-related attribute, impedance control in PODTM mode is realized.

[00126] In another case, the first non-test state control signal is configured to indicate the impedance of the DQ pin in the output signal driver state, and the second impedance control signal is configured to indicate the impedance of the data mask (DM) pin in a state other than the specified test state. Thus, by combining the signal control strategy of the data mask (DM) pin in PODTM mode with the signal control strategy of the read-related attribute, impedance control in PODTM mode is realized.

[00127] Embodiments of the present disclosure provide a control method. Because both the third operand (OP) and the fourth operand (OP) can influence the impedance state of the data mask (DM) pin, to prevent data processing errors by the circuit. The impedance control strategy is as follows: if the fourth operand (OP) is in the first state, the impedance of the data mask (DM) pin is determined in combination with the state of the third operand (OP), and if the fourth operand (OP) is in the second state, the impedance of the pin for The data mask (DM) is determined directly. Thus, a relationship is defined between a control signal configured to control whether a given data mask (DM) pin is enabled in DDR5 and a control signal configured to control whether a data mask (DM) pin is a test object in PODTM mode. The data mask (DM) pin impedance can be tested in a specified test mode to prevent circuit processing errors.

[00128] According to another embodiment of the present disclosure, with reference to FIG. 3 is a schematic diagram of the structure of a semiconductor memory device 30 according to one embodiment of the present disclosure. As shown in FIG. 3, the semiconductor memory device 30 includes a first operating mode (MR) register 301, a third operating mode (MR) register 303, a data mask (DM) pin 310, and a first driver circuit 311, wherein the first driver circuit 311 is connected to the first an operating mode (MR) register 301, a third operating mode (MR) register 303, and a data mask (DM) pin, respectively.

[00129] The data mask (DM) pin 310 is configured to receive a write data mask input signal.

[00130] The first driver circuit 311 is configured to: control, when a fourth operand (OP) in the first operating mode register (MR) 301 is in a first state, the impedance of the data mask (DM) pin 310 as a first value in accordance with the third operand (OP) in the third operating mode register (MR) 303, in response to the semiconductor memory device 30 being in a predetermined test mode; or

[00131] control, when the fourth operand (OP) in the first operation mode register (MR) 301 is in the second state, by the impedance of the data mask (DM) pin 310 as the second value.

[00132] It should be noted that a fourth operand (OP) is configured to indicate whether the data mask (DM) pin is enabled, and a third operand (OP) is configured to indicate whether the data mask (DM) pin is an object tests in a given test mode. The specified test mode may be a PODTM mode that allows the host computer to test the rising impedance of the data mask (DM) pin or DQ pin.

[00133] Thus, the impedance of the data mask (DM) pin can be checked in a specified test mode to prevent data processing errors by the circuit.

[00134] In some embodiments, as shown in FIG. 4, the semiconductor memory device 30 further includes a second operating mode (MR) register 302, wherein the second operating mode (MR) register 302 is connected to the first driver circuit 311. The first value includes a first impedance parameter and a second impedance parameter, wherein the second value refers to a high impedance condition.

[00135] The first driver circuit 311 is particularly configured to control, in the case where the fourth operand (OP) is in the first state and the third operand (OP) is in the third state, the impedance of the data mask (DM) pin 310 as the first impedance parameter in accordance with the first operand (OP) in the first operating mode register (MR) 301; or controlling, in the case where the fourth operand (OP) is in the first state and the third operand (OP) is in the fourth state, the impedance of the data mask (DM) pin 310 as a second impedance parameter in accordance with the second operand (OP) in second operating mode register 302 (MR); or controlling, in the case where the fourth operand (OP) is in the second state, the impedance of the data mask (DM) pin as in a high impedance state in accordance with the first signal at a fixed level.

[00136] In this case, the first state indicates that the data mask (DM) pin is enabled, and the second state indicates that the data mask (DM) pin is not enabled. The third state indicates that the data mask (DM) pin is being tested in the specified test mode. The fourth condition indicates that the data mask (DM) pin is not being tested in the specified test mode. The semiconductor memory device further includes at least one DQ data pin 320. DQ data pin 320 is configured to receive or output data. A first operand (OP) is configured to indicate that the impedance of at least one DQ data pin 320 in the output signal driver state is a first impedance parameter, and a second operand (OP) is configured to indicate that the impedance of the at least one pin 320 DQ data in completion state is the second impedance parameter.

[00137] It should be understood that only one DQ pin 320 is shown in FIG. 4 for illustration, and in fact there are more DQ pins in the semiconductor memory device 30. Embodiments of the present disclosure do not limit the number of data mask (DM) pins 310 and DQ pins 320.

[00138] Thus, in embodiments of the present disclosure, impedance control strategies of the data mask (DM) pin and the DQ pin in PODTM mode are provided so that the impedance of the data mask (DM) pin in PODTM mode can be checked to prevent processing errors data by the circuit.

[00139] In some embodiments, semiconductor memory device 30 further includes a first decoding module 304 and a second decoding module 305.

[00140] The first operating mode register (MR) 301 is configured to store and output a first operand (OP) and a fourth operand (OP).

[00141] The second operating mode register (MR) 302 is configured to store and output a second operand (OP).

[00142] The third operating mode register (MR) 303 is configured to store and output a third operand (OP).

[00143] The first decoding module 304 is configured to receive a third operand (OP), decode the third operand (OP), and output a first test flag signal.

[00144] The second decoding module 305 is configured to receive a fourth operand (OP), decode the fourth operand (OP), and output an enable control signal.

[00145] The first driver circuit 311 is configured to: receive an enable control signal, a first test flag signal, a first fixed-level signal, a first operand (OP), and a second operand (OP); and controlling, in the case where the enable control signal is in the first level state, the impedance of the data mask (DM) pin 310 based on the first operand (OP) or the second operand (OP) in accordance with the level state of the first test flag signal when the semiconductor Memory 30 is in the specified test mode; or controlling, in the case where the enable control signal is in a second level state, the data mask (DM) pin 310 as in a high impedance state through the first fixed level signal.

[00146] It should be noted that when the fourth operand (OP) is in the first state, the enable control signal is in the first level state. When the fourth operand (OP) is in the second state, the enable control signal is in the second level state. When the third operand (OP) is in the third state, the first test flag signal is in the first level state. When the third operand (OP) is in the fourth state, the first test flag signal is in the second level state.

[00147] In some embodiments, as shown in FIG. 4, the semiconductor memory device 30 further includes at least one second driver circuit 321, with each second driver circuit 321 coupled to a first operating mode (MR) register 301, a second operating mode (MR) register 302, and one DQ pin 320 .

[00148] The second driver circuit 321 is configured to: control, if the corresponding DQ pin 320 is selected as the test object, the impedance of the data mask (DM) pin 320 as a first impedance parameter, via a first operand (OP) in the first operating mode register 301 (MR) when the semiconductor memory device 30 is in a predetermined test mode; or controlling, if the corresponding DQ pin 320 is not a test object, the impedance of the DQ pin 320 as a second impedance parameter, via a second operand (OP) in a second operating mode register (MR) 302.

[00149] In some embodiments, a third operand (OP) in the third operating mode register (MR) 303 is also configured to indicate whether the DQ pin is a test object in a given test mode. As shown in FIG. 4, the second driver circuit 321 is also connected to the first decoding module 304.

[00150] The first decoding module 304 is further configured to perform third operand (OP) decoding processing and output at least one second test flag signal. Herein, one second test flag signal is configured to indicate whether one DQ pin is a test object.

[00151] The second driver circuit 321 is further configured to: receive a corresponding second test flag signal, a first operand (OP), and a second operand (OP); and selecting, in the case where the semiconductor memory device 30 is put into a predetermined test mode, one of the first operand (OP) and the second operand (OP) to control the impedance of the DQ pin 320 in accordance with the second test flag signal.

[00152] It should be noted that the first test flag signal is an internal flag signal input to the data mask (DM) pin 310 to indicate whether the data mask (DM) pin 310 is a test object in PODTM mode. The second test flag signal is an internal flag signal input to DQ pin 320 to indicate whether DQ pin 320 is a test object in PODTM mode. Both the first test flag signal and the second test flag signal are obtained by decoding in accordance with the third operand (OP).

[00153] As can be seen from the above, when entering PODTM mode, the impedance of the selected data mask (DM) pin or DQ pin is the first impedance parameter (essentially the increasing impedance of the output driver), and the impedance of the unselected mask pin data (DM) or DQ pin is a second impedance parameter (essentially termination impedance) to thereby obtain the impedance test result of the selected test object. Additionally, the data mask (DM) pin impedance also depends on the enable control signal specified in the DDR5 Specification. In the case where the enable control signal is valid, the first operand (OP) is enabled to control the impedance of the data mask (DM) pin as the first impedance parameter, or the second operand (OP) is enabled to control the impedance of the data mask (DM) pin as the second impedance parameter. In the case where the enable control signal is invalid, the impedance of the data mask (DM) pin is controlled as in a high impedance state. Thus, the data mask (DM) pin should not contribute to setting the state of the output driver and associated control circuitry for a given test mode to ensure that the specified test mode is adapted to a given data mask (DM) pin. The data mask (DM) pin impedance can be checked in a specified test mode to prevent circuit processing errors.

[00154] It should be noted that the standard number of the first operating mode register (MR) is 5, and the first operand (OP) is the operand (OP) from the second bit to the first bit stored in the first operating mode register (MR), represented as MR5 OP[2:1]. The fourth operand (OP) is a 5-bit operand (OP) stored in the first operating mode register (MR) and represented as MR5 OP[5]. The standard number of the second operating mode register (MR) is 34, and the second operand (OP) is the (OP) from the second bit to the 0th bit stored in the second operating mode register (MR), represented as MR34 OP[2:0] . The standard number of the third operating mode register (MR) is 61, and the third operand (OP) is the operand (OP) from the 4th bit to the 0th bit stored in the third operating mode register (MR), represented as MR61 OP[4 :0].

[00155] As shown in FIG. 5, in the 8-bit (X8) semiconductor memory device 30 taken as an example, the first decoding unit 304 is configured to receive the third operand MR61 OP[4:0] and decode to obtain the first test flag signal PODTM_DM_EN and the second signals PODTM_DQ0_EN- PODTM_DQ7_EN testing flag. Here, the second test flag signals PODTM_DQ0_EN-PODTM_DQ7_EN are respectively configured to indicate whether the pins DQ0L0-DQL7 are test objects in PODTM mode. It should be understood that the logic circuit in the first decoding module 304 is designed in accordance with the above-mentioned Table 1.

[00156] Below, by way of example, a specific description of the structure of the first driver circuit 311 is given.

[00157] In this embodiment of the present disclosure, the semiconductor memory device 30 is further configured to determine a first non-test state control signal, a second impedance control signal, and a first calibration signal ZQ1_CODE[N-1:0]. The first calibration signal ZQ1_CODE[N-1:0] is configured to calibrate an increasing value of active resistance.

[00158] As shown in FIG. 6, the first driver circuit 311 may include a first signal processing module 41, a first logic module 42, and a first driver module 43.

[00159] The first signal processing unit 41 is configured to: receive a first test flag signal PODTM_DM_EN, an enable control signal DM_enable, a first fixed level signal, a first operand MR5 OP[2:1], a second operand MR34 OP[2:0], and a first non-test state control signal; and outputting a first impedance control signal based on one of the first fixed-level signal, the first operand MR5 OP[2:1] and the second operand MR34 OP[2:0], in accordance with the level state of the first signal of the test flag PODTM_DM_EN and the signal level state controlling activation of DM_enable when the semiconductor memory device is in a predetermined test state; or outputting a first impedance control signal based on the first non-test state control signal when the semiconductor memory device is not in a predetermined test mode.

[00160] The first logic module 42 is configured to: receive a first impedance control signal, a second impedance control signal, and a first calibration signal ZQ1_CODE[N-1:0]; and selecting and logically combining the first impedance control signal, the second impedance control signal, and the first calibration signal ZQ1_CODE[N-1:0] to output the first target signal PU1_MAIN_CODE.

[00161] The first driver module 43 includes a plurality of first impedance blocks and is configured to receive the first target signal PU1_MAIN_CODE and control the plurality of first impedance blocks using the first target signal PU1_MAIN_CODE so as to control the impedance of the data mask (DM) pin 310.

[00162] It should be understood that the data mask (DM) pin 310 only supports a write function and does not need to output data externally. In the termination state, it only covers the level-up function but not the level-down function, so that the first driver circuit 311 only has a first impedance control signal and a second impedance control signal that are configured to control the level-up function, and does not cover related signals , configured to control the level reduction function. In addition, the increasing resistance value of each first impedance block may be a standard resistance value. However, when environmental parameters such as temperature and voltage change under actual production conditions, the resistance value of the first impedance unit may also change accordingly. Thus, the first calibration signal ZQ1_CODE[N-1:0] is configured to calibrate the active resistance value of each first impedance block to a standard active resistance value. In this case, all first impedance blocks share the first calibration signal ZQ1_CODE[N-1:0].

[00163] It should be noted that the first impedance control signal and the second impedance control signal properly correspond to two attributes, i.e. a write-related attribute and a read-related attribute. It should be understood that in the absence of PODTM mode, according to the actual operating state, one of the first impedance control signal and the second impedance control signal is valid and combined with the first calibration signal ZQ1_CODE[N-1:0] to obtain the first target signal PU1_MAIN_CODE. In contrast, in PODTM mode, the second impedance control signal is unconditionally invalid, and the first impedance control signal and the first calibration signal ZQ1_CODE[N-1:0] are combined to obtain the first target signal PU1_MAIN_CODE. Here, the actual signal in the first impedance control signal and the second impedance control signal is configured to enable or disable the boost function of the first impedance block, and the first calibration signal ZQ1_CODE[N-1:0] is configured to calibrate the resistance value of the first impedance block block with reduction to the standard value of active resistance, when the function of increasing the level of the first impedance block is enabled or disabled.

[00164] In some embodiments, as shown in FIG. 6, the first signal processing unit 41 includes a third decoding unit 411, a fourth decoding unit 412, a first selecting unit 413, a second selecting unit 414, and a third selecting unit 415.

[00165] The third decoding module 411 is configured to receive the first MR5 operand OP[2:1], decode the first MR5 operand OP[2:1], and output the first decoded signal RONpu_CODE[M:0].

[00166] The fourth decoding module 412 is configured to receive the second operand MR34 OP[2:0], decode the second operand MR34 OP[2:0], and output the second decoded signal RTT_CODE[M:0].

[00167] The first selector 413 is configured to: receive a first test flag signal PODTM_DM_EN, a first decoded signal RONpu_CODE[M:0], and a second decoded signal RTT_CODE[M:0]; and selecting one of the first decoded signal RONpu_CODE[M:0] and the second decoded signal RTT_CODE[M:0] to output the first preselection signal in accordance with the level state of the first signal PODTM_DM_EN of the test flag.

[00168] The second selection module 414 is configured to: receive an enable control signal DM_enable, a first preselection signal, and a first fixed-level signal; and selecting one of the first preselection signal and the first fixed-level signal to output a first test state control signal in accordance with the level state of the enable control signal DM_enable.

[00169] The third selector 415 is configured to: receive a test enable signal PODTM_EN, a first test state control signal, and a first non-test state control signal; and selecting one of the first test state control signal and the first non-test state control signal to output a first impedance control signal in accordance with a level state of the test enable signal PODTM_EN. Herein, the test enable signal is configured to indicate whether the semiconductor memory device is in a predetermined test mode.

[00170] It should be noted that the test enable signal PODTM_EN is configured to indicate whether the semiconductor memory device is in a predetermined PODTM test mode, and is also decoded in accordance with the third control code MR61 OP[4:0]. As shown in Table 1 above, when the value of the operand MR61 OP[4:0] is in combinations other than 00000 _B in Table 1, it indicates that the semiconductor memory device is in the specified PODTM test mode, and the signal Test enable PODTM_EN is in the first level state (for example, it has a logical level of "1"). When MR61 OP[4:0]=00000 _B , it indicates that the semiconductor memory device is not in the specified PODTM test mode and the PODTM_EN test enable signal is in the second level state (eg, at logic level "0"). Alternatively, it may also be understood that if one of the first test flag signal or the second test flag signal is in the first level state, the test enable signal PODTM_EN is in the first level state. If the first test flag signal and the second test flag signal are in the second level state, the test enable signal PODTM_EN is in the second level state.

[00171] It should be understood that the logic circuit in the second decoding module 411 is designed in accordance with the above-mentioned Table 2, i.e. the first decoded signal is configured to represent the resistance value (first impedance parameter) of the impedance Ron of the amplifier, and the logic circuit in the third decoding module 412 is designed in accordance with the above-mentioned Table 3, i.e. the second decoded signal is configured to represent a resistance value (second impedance parameter) of the RTT termination impedance. However, M is a positive integer, and its specific value must be determined according to the actual operating scenario.

[00172] For the first driver circuit 311 shown in FIG. 6, according to different assignments of the first non-test state control signal and the second impedance control signal, there may be two specific implementations.

[00173] In one embodiment, the first non-test state control signal is configured to indicate the impedance of the data mask (DM) pin in a state other than the specified test state, and the second impedance control signal is configured to indicate the impedance of the DQ pin in the output driver state . Thus, by combining the signal control strategy of the data mask (DM) pin in PODTM mode with the signal control strategy of the record-related attribute, impedance control in PODTM mode is realized.

[00174] Accordingly, as shown in FIG. 7, the first impedance control signal is represented as ODT_MUX[M:0], and the second impedance control signal is represented as IMPpu_CODE[M:0]. In particular, compared to FIG. 6, the first driver circuit 311 shown in FIG. 7 further includes a first pre-processing module 44 and a second pre-processing module 45. The first pre-processing unit 44 is configured to decode the first operand MR5 OP[2:1] to obtain a second impedance control signal IMPpu_CODE[M:0]. The second pre-processing module 45 is configured to determine a first non-test state control signal in accordance with an operand MR34[5:3] covering RTT_WR, an operand MR35[2:0] covering RTT_NOM_WR, an operand MR35[5:3] covering RTT_NOM_RD, operand MR34[2:0], covering RTT_PARK, and operand MR33[5:3], covering DQS_RTT_PARK. The specific meanings of the signals presented above relate to the instructions of the DDR5 Specification, and part signals do not affect the creation of non-described implementations that will not be described in detail. In addition, in the following description, if the semiconductor memory device 30 is in the PODTM mode, the test enable signal PODTM_EN is at a logic level of "1". If the semiconductor memory device 30 is not in PODTM mode, the test enable signal PODTM_EN is at a logic level of "0". If the data mask (DM) pin 310 is the test object in PODTM mode, the first signal PODTM_DM_EN of the test flag is at a logic level of "1". If the data mask (DM) pin 310 is not tested in PODTM mode, the first signal PODTM_DM_EN of the test flag is at a logic level of "0". If the data mask (DM) pin 310 is enabled, the enable control signal DM_enable is at a logic level of "1". If the data mask (DM) pin 310 is not enabled, the enable control signal DM_enable is at a logic level of "0". The first level-fixed signal is represented as VDD, wherein the first level-fixed signal VDD indicates that the boost functions of all first impedance blocks are not engaged. It should be understood that the specific value of the first fixed level signal depends on the logic principle of the circuit and can be adjusted according to appropriate circuit logic.

[00175] Below with reference to FIG. 7 explains the operating principle using four operating scenarios.

[00176] The first operating scenario is that: the enable control signal DM_enable indicates the enable of the data mask (DM) pin 310. The semiconductor memory 30 enters PODTM mode, and the data mask (DM) pin 310 310 is the test object. At this time, since the first test flag signal PODTM_DM_EN is at a logic level of "1", the first selection unit 413 outputs the first decoded signal RONpu_CODE[M:0] to obtain the first preselection signal. Since the enable control signal DM_enable is logic level "1", the second selection unit 414 outputs a first preselection signal to obtain the first test state control signal. Since the test enable signal PODTM_EN is at a logic level of "1", the third selection unit 415 outputs a first test state control signal to obtain the first impedance control signal ODT_MUX[M:0]. As described above, the second impedance control signal IMPpu_CODE[M:0] in PODTM mode is unconditionally invalid, so that the first logic module 42 essentially logically combines the first impedance control signal ODT_MUX[M:0] and the first calibration signal ZQ1_CODE[N-1: 0] to receive the first target signal PU1_MAIN_CODE, thereby controlling the impedance of the data mask (DM) pin 310 as the first impedance parameter. In this case, cancellation of the second impedance control signal IMPpu_CODE[M:0] can be achieved in at least two ways: by adding a corresponding signal blocking the logic circuit in the first pre-processing module 44; or by adding a corresponding signal to disable the logic circuit in the first logic module 42.

[00177] As can be seen from the above, for the first operating scenario, the impedance of the data mask (DM) pin 310 is actually controlled by the first MR5 operand OP[2:1] and, in particular, is the first impedance parameter.

[00178] The second operating scenario is that: the enable control signal DM_enable indicates the enable of the data mask (DM) pin 310. Semiconductor memory 30 enters PODTM mode, but data mask (DM) pin 310 is not tested. At this time, since the first test flag signal PODTM_DM_EN is at a logic level of "0", the first selection unit 413 outputs a second decoded signal RTT_CODE[M:0] to obtain the first preselection signal. Since the enable control signal DM_enable is at a logic level of "1", the second selection unit 414 outputs a first preselection signal to obtain the first test state control signal. Since the test enable signal PODTM_EN is at a logic level of "1", the third selection unit 415 outputs a first test state control signal to obtain the first impedance control signal ODT_MUX[M:0]. As described above, the second impedance control signal IMPpu_CODE[M:0] in PODTM mode is unconditionally invalid, so that the first logic module 42 actually logically combines the first impedance control signal ODT_MUX[M:0] and the first calibration signal ZQ1_CODE[N-1:0 ] to receive the first target signal PU1_MAIN_CODE, thereby controlling the impedance of the data mask (DM) pin 310 as the second impedance parameter.

[00179] As can be seen from the above, for the second operating scenario, the impedance of the data mask (DM) pin 310 is actually controlled by the second operand MR34 OP[2:0] and, in particular, is the second impedance parameter.

[00180] The third operating scenario is that: the enable control signal DM_enable indicates that the data mask (DM) pin 310 will not be enabled. The semiconductor memory device 30 enters PODTM mode. At this time, since the enable control signal DM_enable is at a logic level of "0", the second selection unit 414 outputs the first fixed-level signal VDD to obtain the first test state control signal. Since the test enable signal PODTM_EN is at a logic level of "1", the third selection unit 415 outputs a first test state control signal to obtain the first impedance control signal ODT_MUX[M:0]. As described above, the second impedance control signal IMPpu_CODE[M:0] in PODTM mode is unconditionally invalid, so that the first logic module 42 actually logically combines the first impedance control signal ODT_MUX[M:0] and the first calibration signal ZQ1_CODE[N-1:0 ] to receive the first target signal PU1_MAIN_CODE. Since the first fixed-level signal VDD indicates that the boost functions of all the first impedance blocks are not enabled, the first target signal PU1_MAIN_CODE may drive the first driver module 43 to be in a disconnected state such that the data mask (DM) pin 310 is in Hi-Z high impedance state.

[00181] As can be seen from the above, in the third operating scenario, the impedance of the data mask (DM) pin 310 is actually driven by the first fixed level VDD signal and, in particular, has a high Hi-Z impedance state.

[00182] The fourth operating scenario is that: the semiconductor memory device 30 does not enter PODTM mode. At this time, since the activation control signal PODTM_EM is at a logic level of "0", the third selection unit 415 outputs a first non-test state control signal determined by the second preprocessing unit 45 to obtain the first impedance control signal ODT_MUX[M:0]. Since the data mask (DM) pin 310 only supports the write function, the second impedance control signal IMPpu_CODE[M:0] in the absence of PODTM mode is invalid, and the first impedance control signal ODT_MUX[M:0] is valid, so that the first logic module 42 combines a first impedance control signal ODT_MUX[M:0] and a first calibration signal ZQ1_CODE[N-1:0] to obtain the first target signal PU1_MAIN_CODE, thereby controlling the impedance of the data mask (DM) pin 310.

[00183] As can be seen from the above, in the fourth operating scenario, the impedance of the data mask (DM) pin 310 is actually controlled by the second preprocessing unit 45 and depends on the actual requirements.

[00184] In another embodiment, the first non-test state control signal is configured to indicate the impedance of the DQ pin in the output driver state, and the second impedance control signal is configured to indicate the DR impedance in any state other than the specified test state. Thus, by combining the PODTM mode DR signal control strategy with the read-related attribute signal control strategy, PODTM mode impedance control is realized.

[00185] Accordingly, as shown in FIG. 8, the first impedance control signal is represented as IMPpu_CODE[M:0], and the second impedance control signal is represented as ODT_CTRL[M:0]. In particular, compared to FIG. 6, semiconductor memory device 30 in FIG. 8 also includes a first preprocessing module 44 and a second preprocessing module 45.

[00186] Likewise, the operating principle of FIG. 8 is explained below for four working scenarios.

[00187] The first operating scenario is that: the enable control signal DM_enable indicates the enable of the data mask (DM) pin 310. The semiconductor memory device 30 enters PODTM mode, and the data mask (DM) pin 310 is a test object. At this time, since the first test flag signal PODTM_DM_EN is at a logic level of "1", the first selection unit 413 outputs the first decoded signal RONpu_CODE[M:0] to obtain the first preselection signal. Since the enable control signal DM_enable is logic level "1", the second selection unit 414 outputs a first preselection signal to obtain the first test state control signal. Since the test enable signal PODTM_EN is at a logic level of "1", the third selection unit 415 outputs a first test state control signal to obtain the first impedance control signal IMPpu_CODE[M:0]. As described above, the second impedance control signal ODT_CTRL[M:0] in PODTM mode is unconditionally invalid, so that the first logic module 42 actually logically combines the first impedance control signal IMPpu_CODE[M:0] and the first calibration signal ZQ1_CODE[N-1:0 ] to obtain the first target signal PU1_MAIN_CODE, thereby controlling the impedance of the data mask (DM) pin 310 as the first impedance parameter.

[00188] Thus, in the first operating scenario, the impedance of the data mask (DM) pin 310 is still controlled by the first MR5 operand OP[2:1] and is the first impedance parameter.

[00189] The second operating scenario is that: the enable control signal DM_enable indicates the enable of the data mask (DM) pin 310. Semiconductor memory 30 enters PODTM mode, but data mask (DM) pin 310 is not a test object. At this time, since the first test flag signal PODTM_DM_EN is at a logic level of "0", the first selection unit 413 outputs a second decoded signal RTT_CODE[M:0] to obtain the first preselection signal. Since the enable control signal DM_enable is logic level "1", the second selection unit 414 outputs a first preselection signal to obtain the first test state control signal. Since the test enable signal PODTM_EN is at a logic level of "1", the third selection unit 415 outputs a first test state control signal to obtain the first impedance control signal IMPpu_CODE[M:0]. As described above, the second impedance control signal ODT_CTRL in PODTM mode is unconditionally invalid, so that the first logic module 42 actually logically combines the first impedance control signal IMPpu_CODE[M:0] and the first calibration signal ZQ1_CODE[N-1:0] to obtain the first target signal PU1_MAIN_CODE, thereby controlling the impedance of the data mask (DM) pin 310 as a second impedance parameter.

[00190] As can be seen from the above, in the second operating scenario, the impedance of the data mask (DM) pin 310 is actually controlled by the second operand MR34 OP[2:0] and, in particular, is the second impedance parameter.

[00191] The third operating scenario is that: the enable control signal DM_enable indicates that the data mask (DM) pin 310 will not be enabled. The semiconductor memory device 30 enters PODTM mode. At this time, since the enable control signal DM_enable is at a logic level of "0", the second selection unit 414 outputs the first fixed-level signal VDD to obtain the first test state control signal. Since the test enable signal PODTM_EN is at a logic level of "1", the third selection unit 415 outputs a first test state control signal to obtain the first impedance control signal IMPpu_CODE[M:0]. As described above, the second impedance control signal ODT_CTRL in PODTM mode is unconditionally invalid, so that the first logic module 42 actually logically combines the first impedance control signal IMPpu_CODE[M:0] and the first calibration signal ZQ1_CODE[N-1:0] to obtain the first target signal PU1_MAIN_CODE. Since the first fixed-level signal VDD indicates that the boost functions of all the first impedance blocks are not enabled, the first target signal PU1_MAIN_CODE may drive the first driver module 43 to be in a disconnected state such that the data mask (DM) pin 310 is in Hi-Z high impedance state.

[00192] As can be seen from the above, in the third operating scenario, the impedance of the data mask (DM) pin 310 is actually driven by the first fixed level VDD signal and, in particular, has a high Hi-Z impedance state.

[00193] The fourth operating scenario is that: the semiconductor memory 30 does not enter PODTM mode. At this time, since the activation control signal PODTM_EM is at a logic level of "0", the third selection unit 415 outputs a first non-test state control signal determined by the first preprocessing unit 44 to obtain the first impedance control signal IMPpu_CODE[M:0]. Meanwhile, the second preprocessing unit 45 outputs a second impedance control signal ODT_CTRL[M:0]. As described above, since the data mask (DM) pin 310 only supports the write function, the first impedance control signal IMPpu_CODE[M:0] in the absence of PODTM mode is invalid, and the second impedance control signal ODT_CTRL[M:0] is valid, so that the first logic module 42 combines the second impedance control signal ODT_CTRL[M:0] and the first calibration signal ZQ1_CODE[N-1:0] to obtain the first target signal PU1_MAIN_CODE, thereby controlling the impedance of the data mask (DM) pin 310.

[00194] Thus, in the fourth operating scenario, the impedance of the data mask (DM) pin 310 is actually controlled by the second preprocessing unit 45 and, in particular, depends on the actual requirements.

[00195] It should also be noted that in FIG. 7 and 8, the "/" marking the signal paths is configured to indicate that in fact there are multiple signal paths, but only one is shown for illustration purposes. In other words, each signal in the operands MR34 OP[2:0], MR5 OP[2:1], RONpu_CODE[M:0], RTT_CODE[M:0], IMPpu_CODE[M:0], ZQ1_CODE[N-1: 0], ODT_CTRL[M:0], ODT_MUX[M:0] and PU1_MAIN_CODE includes many sub-signals, and each sub-signal has its own path.

[00196] Below with reference to FIG. 7 or 8 describes the signal processing process in the first driver circuit 311.

[00197] In some embodiments, as shown in FIG. 7 or 8, each of a first decoded signal RONpu_CODE[M:0], a second decoded signal RTT_CODE[M:0], a first preselection signal, a first fixed-level signal, a first test state control signal, a first non-test state control signal, and a first The impedance control signal includes an (M+1)-bit subsignal represented as [M:0]. The first selection module 413 includes (M+1) first data selectors, the second selection module 414 includes (M+1) second data selectors, and the third selection module 415 includes (M+1) third data selectors. Herein, the input end of one first data selector respectively receives a 1-bit sub-signal of the first decoded signal RONpu_CODE[M:0] and a 1-bit sub-signal of the second decoded signal RTT_CODE[M:0], the output end of one first data selector is configured to output 1 -bit subsignal of the first preselect signal, and the control ends of all first data selectors receive the first PODTM_DM_EN test flag signal. The input end of one second data selector receives a 1-bit subsignal of the first preselect signal and a 1-bit subsignal of the first fixed-level signal, the output end of one second data selector is configured to output a 1-bit subsignal of the first test state control signal, and the control ends of all The second data selectors receive the test enabling signal DM_enable. An input end of one third data selector receives a 1-bit subsignal of a first test state control signal and a 1-bit subsignal of a first non-test state control signal, an output end of one third data selector is configured to output a 1-bit subsignal of a first impedance control signal, and the control ends of all third data selectors receive the test enable signal PODTM_EN. As used herein, M is a positive integer.

[00198] Note that the first test state control signal is represented as a first test state control signal [M:0], the first preselection signal is represented as a first preselection signal [M:0], the first fixed level signal is represented as VDD[ M:0], the first non-test state control signal is represented as the first non-test state control signal [M:0], and the first impedance control signal is represented as the first impedance control signal [M:0]. Thus, the first data selector receives RONpu_CODE[0], RTT_CODE[0] and PODTM_DM_EN respectively, and selects one of RONpu_CODE[0] and RTT_CODE[0] to output the first preselection signal [0] according to PODTM_DM_EN. The first second data selector receives the first preselection signal [0], VDD[0] and DM_enable, respectively, and selects one of the first preselection signal [0] and VDD[0] to output a first test state control signal [0] in accordance with DM_enable . The first third data selector receives the first test state control signal [0], the first non-test state control signal [0], and PODTM_EN, respectively, and selects one of the first test state control signal [0] and the first non-test state control signal [0] to output the first signal. [0] impedance control according to PODTM_EN. Other components can be understood by reference.

[00199] In some embodiments, the second impedance control signal includes an (M+1)-bit subsignal and the first calibration signal ZQ1_CODE[N-1:0] includes N-bit subsignals. The first target signal includes a subsignal group A, and each subsignal group includes N-bit subsignals. The first group of signals in the first target signal is represented as PU1_MAIN_CODE_1[N-1:0], the second group of signals in the first target signal is represented as PPU1_MAIN_CODE_2[N-1:0], and the group A of signals in the first target signal is represented as PU1_MAIN_CODE_A[N- 1:0]. The first driver module 53 includes A first impedance blocks, and each first impedance block is configured to receive a group of sub-signals in the first target signal PU1_MAIN_CODE, i.e. the first first impedance block is configured to receive the signal PU1_MAIN_CODE_1[N1:0], the second first impedance block is configured to receive the signal PU1_MAIN_CODE_2[N1:0], ... The A-th first impedance block is configured to receive the signal PU1_MAIN_CODE_A[N1:0] .

[00200] Herein, as shown in FIG. 7 or 8, the first logic module 42 is particularly configured to: determine whether a boost function of the at least one first impedance block is enabled in accordance with the first impedance control signal and the second impedance control signal; and in the case when the function of increasing the level of the a-th first impedance block is enabled, with the ability to set the state of the level of the a-th group of subsignals in the first target signal PU1_MAIN_CODE in accordance with the first calibration signal in such a way as to control the value of the active resistance of the a-th first impedance block so that it is the standard value of active resistance; or in the case where the boost function of the a-th first impedance block is not enabled, with the ability to determine that the a-th group of subsignals in the first target signal PU1_MAIN_CODE is in the first level state (which can be determined in accordance with the actual circuit logic and does not constitute a relevant limitation). As used herein, a, N, and A are all integers that are less than or equal to A, with (M+1) being less than or equal to A.

[00201] It should be understood that for the first logic module 42 there is only one valid signal between the first impedance control signal and the second impedance control signal. In the case where M+1≤A, a 1-bit subsignal in the actual signal controls the activation of the boost function of one or more first impedance blocks. In addition, the plurality of first impedance blocks are in a parallel state, and each first impedance block can provide a standard resistance value RZQ. Thus, if the boost impedance of the data mask (DM) pin 310 is to be adjusted to RZQ/2, the boost functions of the first two impedance blocks are enabled and the boost functions of the remaining first impedance blocks are not enabled. If the boost impedance of the data mask (DM) pin 310 is to be adjusted to RZQ/3, the boost functions of the first three impedance blocks are enabled and the boost functions of the remaining first impedance blocks are not enabled. Other situations can be understood by reference.

[00202] For example, in the case where M+1=A=7, assuming that the actual signal between the first impedance control signal and the second impedance control signal is represented as IMPpu_CODE[6:0], then IMPpu_CODE[0] controls the first impedance control signal, IMPpu_CODE[1] controls the second first impedance block ... ... IMPpu_CODE[6] controls the seventh first impedance block. In particular, under the assumption that IMPpu_CODE[6:0]=111111, the level values of each group of subsignals (seven groups in total) in the first target signal are the same as the level value of the first calibration signal, so that all increasing resistance values the seven first impedance blocks are RZQ, and the rising resistance of the data mask (DM) pin 310 is RZQ/7. Assuming that IMPpu_CODE[6:0]=1111000, the level values of the first subsignal group for the third subsignal group in the first target signal are in the first level state, and all the level values of each subsignal group in the fourth subsignal group for the seventh subsignal group are respectively the same same as the level value of the first calibration signal, so that all blocks from the first impedance block to the third first impedance block are disconnected. The increasing resistance values of all impedance blocks from the fourth first impedance block to the seventh first impedance block are RZQ, so that the increasing impedance of the data mask (DM) pin 310 is RZQ/4. Other situations can be understood by reference.

[00203] For example, in the case where M+1=4 and A=7, assuming that the actual signal between the first impedance control signal and the second impedance control signal is represented as IMPpu_CODE[3:0], the IMPpu_CODE signal[0] controls the first first impedance control signal, the IMPpu_CODE[1] signal controls the second first impedance block and the third first impedance block, the IMPpu_CODE[2] signal controls the fourth first impedance block and the fifth impedance block, and the IMPpu_CODE[3] signal controls the sixth first impedance block and seventh impedance block. In particular, under the assumption that IMPpu_CODE[3:0]=1111, the level values of each group of subsignals in the first target signal are the same as the level value of the first calibration signal, so that all increasing resistance values of the first seven impedance blocks are RZQ, and the rising resistance of the data mask (DM) pin 310 is RZQ/7. Assuming that IMPpu_CODE[3:0]=1100, the level values of the first subsignal group for the third subsignal group in the first target signal are in the first level state, and all the level values of each subsignal group in the fourth subsignal group for the seventh subsignal group are respectively those the same as the level value of the first calibration signal, so that all impedance blocks from the first impedance block to the third first impedance block are disconnected. All increasing resistance values of the impedance blocks from the fourth first impedance block to the seventh first impedance block are RZQ, so that the increasing impedance of the data mask (DM) pin 310 is RZQ/4. Other situations can be understood by reference.

[00204] Thus, if the level increase function of a certain first impedance block is enabled, the rising resistance value of the first impedance block is calibrated to a standard resistance value using the first calibration signal, otherwise, if the level increase function of the first impedance block is not enabled, the related To this end, the first impedance block circuit is disconnected using a fixed signal in the first level state.

[00205] In some embodiments, as shown in FIG. 7 or 8, each first impedance block includes N first switching transistors (eg, first switching transistor 431 in FIG. 7 or 8), N second switching transistors (eg, second switching transistor 432 in FIG. 7 or 8), and 2N first resistors (eg, first resistor 433 in FIG. 7 or 8). The control end of the n-th first switching transistor in the a-th first impedance block is connected to the n-th subsignal in the a-th group of subsignals in the first target signal, the first end of one first switching transistor is connected to the first end of one first resistor, and the second end of one the first switching transistor is connected to the power signal. The control end of one second switching transistor is connected to the second fixed-level signal, the first end of one second switching transistor is connected to the ground signal VSS, the second end of one second switching transistor is connected to the first end of one first resistor, and all the second ends of the 2N first resistors are connected to the pin for 310 for data mask (DM). As used herein, n is less than or equal to N.

[00206] It should be understood that since the data mask (DM) pin 310 does not support a read function and should not enable the pull-down function, the second switching transistor is turned off using a second fixed-level signal, and its specific value can be determined in accordance with actual conditions of the scheme.

[00207] It should be noted that in FIG. 7 or 8, taking the first first impedance block as an example, the first first impedance block is configured to receive a first group of subsignals PU1_MAIN_CODE_1[N-1:0] in the first target signal. The signal PU1_MAIN_CODE_1[N1:0] includes N subsignals PU1_MAIN_CODE_1[0], PU1_MAIN_CODE_1[1] ... ... PU1_MAIN_CODE_1[n-1]. Each sub-signal is configured to control an operating state of one first switching transistor, respectively, so as to control the first impedance unit to perform or not implement a boost function with a standard resistance value.

[00208] Additionally, in FIG. 7 or 8, the first impedance block includes three first switching transistors (only one first switching transistor 431 is designated), three second switching transistors (only one second switching transistor 432 is designated), and six first resistors (only one is designated first resistor 433), but in actual scenarios, all numbers of first switching transistors/second switching transistors/first resistors may be larger or smaller.

[00209] It should be understood that the data mask (DM) pin 310 only supports the data write function and provides the termination impedance, so there is no need to perform a level-down function. Thus, the first ends of all second switching transistors are connected to the second signal at a fixed level, i.e. all second switching transistors are non-conducting. For example, the second fixed-level signal may be a ground signal VSS, but the specific value of its level must be determined in accordance with circuit logic, which is not limited in an embodiment of the present disclosure.

[00210] A specific description of the structure of the second driver circuit 321 is given below as an example. It should be understood that although some signals in the second driver circuit 321 and some signals in the first driver circuit 311 have different names in Chinese, the sources and waveforms of the signals are basically the same, so the same English names are used.

[00211] In this embodiment of the present disclosure, the semiconductor memory device 30 is further configured to set a third non-test state control signal, a fourth impedance control signal, a fifth impedance control signal, a second calibration signal ZQ2_CODE[N-1:0], and a third calibration signal ZQ3_CODE [N-1:0].

[00212] As shown in FIG. 9, the second driver circuit 421 may include a second signal processing module 51, a second logic module 521, a third logic module 522, and a second driver module 53.

[00213] The second signal processing module 51 is configured to: receive a second test flag signal PODTM_DQ_EN (for example, the above-mentioned PODTM_DQ0_EN or PODTM_DQ1_EN, ... or PODTM_DQ7_EN), a first operand MR5 OP[2:1], a second operand MR34 OP[2:0 ] and the third control signal of the non-test state; and outputting, based on one of the first operand MR5 OP[2:1] and the second operand MR34 OP[2:0], a third impedance control signal in accordance with the second test flag signal PODTM_DQ_EN when the semiconductor memory 30 is in a predetermined test mode; or outputting, based on the third non-test state control signal, a third impedance control signal when the semiconductor memory device 30 is not in a predetermined test mode.

[00214] The second logic module 521 is configured to: receive a third impedance control signal, a fourth impedance control signal, and a second calibration signal ZQ2_CODE[N-1:0]; and selecting and logically combining the fourth impedance control signal and the second calibration signal ZQ2_CODE[N-1:0] to produce a second target signal PU2_MAIN_CODE.

[00215] The third logic module 522 is configured to: receive a fifth impedance control signal and a third calibration signal ZQ3_CODE[N-1:0]; and logically combining the fifth impedance control signal and the third calibration signal ZQ3_CODE[N-1:0] to output a third target signal PD_MAIN_CODE.

[00216] The second driver module 53 includes a plurality of second impedance blocks and is configured to: receive a second target signal PU2_MAIN_CODE and a third target signal PD_MAIN_CODE; and driving a plurality of second impedance blocks using the second target signal PU2_MAIN_CODE and the third target signal PD_MAIN_CODE, so as to control the impedance of the corresponding data mask (DM) pin 320.

[00217] It should be noted that each DQ pin 320 is matched to a corresponding second driver circuit 321, and an embodiment of the present disclosure takes only one second driver circuit 321 as an example for explanation.

[00218] It should be understood that the DQ pin 320 supports a write function and a read function, and covers a level-up function and a level-down function simultaneously. Thus, there is not only a third impedance control signal and a third impedance control signal, which are configured to control the level-up function in the second driver circuit 321, but also a fifth impedance control signal, configured to control the level-down function.

[00219] It should be noted that the second calibration signal ZQ2_CODE[N-1:0] is configured to calibrate an increasing value of active resistance, i.e. the second calibration signal ZQ2_CODE[N-1:0] is configured to calibrate the increasing value of the active resistance of each second impedance block to the standard value of the active resistance. The third calibration signal ZQ3_CODE[N-1:0] is designed to calibrate the decreasing value of the active resistance, i.e. the third calibration signal ZQ3_CODE[N-1:0] is configured to calibrate the decreasing value of the active resistance of every second impedance block to the standard value of the active resistance.

[00220] In addition, since the first calibration signal ZQ1_CODE[N-1:0] and the second calibration signal ZQ2_CODE[N-1:0] are both configured to calibrate an increasing value of active resistance, in some embodiments the deviations of the first may be considered impedance block and the second impedance block are within the acceptable error range, so that the first calibration signal ZQ1_CODE[N-1:0] and the second calibration signal ZQ2_CODE[N-1:0] can be the same signal.

[00221] It should also be noted that for the second driver circuit 321, the actual signal between the third impedance control signal and the fourth impedance control signal and the second calibration signal ZQ2_CODE[N-1:0] are combined in the second logic module 521 so as to form a second target a signal PU2_MAIN_CODE configured to control a boost function of the second impedance block 53. The circuit structure and signal processing process of this circuit portion can be suitably understood with reference to the first driver circuit 311, the description of which will not be repeated here. In addition, the second driver circuit 321 also combines the fifth impedance control signal and the third calibration signal ZQ3_CODE[N-1:0] through the third logic module 522 so as to form a third target signal PD_MAIN_CODE configured to control the lowering function of the second impedance block 53.

[00222] In some embodiments, as shown in FIG. 9, the second signal processing unit 51 may include a fifth decoding unit 511, a sixth decoding unit 512, a fourth selecting unit 513, and a fifth selecting unit 514.

[00223] The fifth decoding module 511 is configured to receive the first MR5 operand OP[2:1], decode the first MR5 operand OP[2:1], and output the third decoded signal RONpu_CODE[M:0].

[00224] The sixth decoding module 512 is configured to receive the second operand MR34 OP[2:0], decode the second operand MR34 OP[2:0], and output the fourth decoded signal RTT_CODE[M:0].

[00225] The fourth selector 513 is configured to: receive a second test flag signal PODTM_DQ_EN, a third decoded signal RONpu_CODE[M:0], and a fourth decoded signal RTT_CODE[M:0]; and selecting one of the third decoded signal RONpu_CODE[M:0] and the fourth decoded signal RTT_CODE[M:0] to output a third test state control signal in accordance with the second test flag signal PODTM_DQ_EN.

[00226] The fifth selector 514 is configured to: receive a test enable signal PODTM_EN, a third test state control signal, and a third non-test state signal; and selecting one of a third test state control signal and a third non-test state control signal to output a third impedance control signal in accordance with the test enable signal PODTM_EN. Herein, the test enable signal PODTM_EN is configured to indicate whether the semiconductor memory device 30 is in a predetermined test mode.

[00227] For the second driver circuit 321 shown in FIG. 9, according to the different assignments of the third non-test state control signal and the fourth impedance control signal, there may be two specific implementations.

[00228] According to one embodiment, the third non-test state control signal is configured to indicate the impedance of the corresponding DQ pin in the termination state, and the fourth impedance control signal and the fifth impedance control signal are collectively configured to indicate the impedance of the corresponding DQ pin in the output driver state. Thus, by combining the signal control strategy of the DQ pin in PODTM mode with the signal control strategy of the recording-related attribute, impedance control in PODTM mode is realized.

[00229] Accordingly, as shown in FIG. 10, the third impedance control signal is represented as ODT_MUX[M:0], the fourth impedance control signal is represented as IMPpu_CODE[M:0], and the fifth impedance control signal is represented as IMPpd_CODE[M:0]. In particular, compared to FIG. 9, the second driver circuit 321 in FIG. 10 further includes a third preprocessing module 54 and a fourth preprocessing module 55. The third pre-processing unit 54 is configured to decode the first operand MR5 OP[2:1] to obtain a fourth impedance control signal IMPpu_CODE[M:0]. The fourth preprocessing module 55 is configured to set a third non-test state control signal in accordance with register MR34[5:3] spanning RTT_WR, register MR35[2:0] spanning RTT_NOM_WR, register MR35[5:3] spanning RTT_NOM_RD, register MR34[2:0], covering RTT_PARK, and register MR33[5:3], covering DQS_RTT_PARK. In addition, in the following description, if the semiconductor memory 30 is in the PODTM mode, the test enable signal PODTM_EN is at a logic level of "1". If the corresponding DQ pin 320 is a PODTM mode test object, the corresponding first test flag signal PODTM_DQ_EN is at a logic level of "1".

[00230] Here, the basic operating principle of the second driver circuit 321 in FIG. 10 is essentially the same as the operating principle of the first driver circuit 311 in FIG. 7, and can be understood with reference to the previous description for FIG. 7, which will not be repeated in this embodiment of the present disclosure. In particular, since the DQ pin 320 is generally enabled in the normal operating mode, a signal configured to control whether the DQ pin 320 is enabled is not set in the DDR5 Specification, so that compared with the first driver circuit 311 in FIG. 7, the second driver circuit 321 in FIG. 10 has one less choice module. In addition, compared with the first driver circuit 311 in FIG. 7, the second driver circuit 321 in FIG. 10 has one more impedance level reduction control part, and its signal processing principle can be referred to as follows.

[00231] According to another embodiment, the third non-test state control signal and the fifth non-test state control signal are jointly configured to indicate the impedance of the corresponding DQ pin in the output signal driver state, and the fourth impedance control signal is configured to indicate the impedance of the corresponding DQ pin in the completion state . Thus, by combining the signal control strategy of the DQ pin in PODTM mode with the signal control strategy of the read-related attribute, impedance control in PODTM mode is realized.

[00232] Accordingly, as shown in FIG. 11, the third impedance control signal is represented as IMPpu_CODE[M:0], the fourth impedance control signal is represented as ODT_CTRL[M:0], and the fifth impedance control signal is represented as IMPpd_CODE[M:0]. In particular, compared to FIG. 9, semiconductor memory device 30 in FIG. 11 also includes a third preprocessing module 54 and a fourth preprocessing module 55.

[00233] In this case, the operating principle of the second driver circuit 321 in FIG. 11 is essentially the same as the first driver circuit 311 in FIG. 8, which can be suitably understood with reference to the previous description for FIG. 8, which will not be repeated in this embodiment of the present disclosure. Likewise, compared to the second driver circuit 321 in FIG. 11, the first driver circuit 311 in FIG. 8 has one less selection module. Compared with the first driver circuit 311 in FIG. 8, the second driver circuit 321 in FIG. 11 has one more impedance level reduction control part, and its signal processing principle can be referred to as follows.

[00234] The signal processing process in the second driver circuit 321 will be described below with reference to FIG. 10 or 11.

[00235] In some embodiments, each of the third decoded signal RONpu_CODE[M:0], the fourth decoded signal RTT_CODE[M:0], the third test state control signal, the third non-test state control signal, and the third impedance control signal includes (M +1)-bit subsignal. The fourth selector 513 includes (M+1) fourth data selectors. The fifth selector 514 includes (M+1) fifth data selectors. Herein, the input end of the one fourth data selector receives a 1-bit subsignal of the third decoded signal RONpu_CODE[M:0] and a 1-bit subsignal of the fourth decoded signal RTT_CODE[M:0], the output end of the one fourth data selector is configured to output 1- bit subsignal of the third test state control signal, and the control ends of all fourth data selectors receive the second test flag signal PODTM_DQ_EN. The input end of the one fifth data selector receives a 1-bit subsignal of the third test state control signal and a 1-bit subsignal of the third non-test state control signal, the output end of the one fifth data selector is configured to output a 1-bit subsignal of the third impedance control signal, and the control ends of all The fifth data selectors receive the test enable signal PODTM_EN.

[00236] It should be noted that the third test state control signal is represented as a third test state control signal [M:0], the third non-test state control signal is represented as a third non-test state control signal [M:0], and the third impedance control signal is represented as third signal [M:0] impedance control. Thus, the first fourth data selector receives the RONpu_CODE[0], RTT_CODE[0] and PODTM_DQ_EN signals respectively and selects one of the RONpu_CODE[0] and RTT_CODE[0] signals to output the third test state control signal [0] in accordance with the PODTM_DQ_EN signal . The first fifth data selector receives the third test state control signal [0], the third non-test state control signal [0], and the PODTM_EN signal, respectively, and selects one of the third test state control signal [0] and the third non-test state control signal [0] to output the third impedance control signal [0] in accordance with the PODTM_EN signal. Other data selectors can be understood by reference and analogy.

[00237] In some embodiments, the fourth impedance control signal includes an (M+1)-bit subsignal. The second calibration signal ZQ2_CODE[N-1:0] and the third calibration signal ZQ3_CODE[N-1:0] include N-bit subsignals. The second target signal PU2_MAIN_CODE and the third target signal PD_MAIN_CODE include A groups of subsignals. Each subsignal group includes N-bit subsignals. Here, the second driver module 53 includes A second impedance blocks, and each second impedance block is configured to receive a group of sub-signals in the second target signal PU2_MAIN_CODE and a group of sub-signals in the third target signal PD_MAIN_CODE. Thus, the first second impedance block is configured to receive target signals PU2_MAIN_CODE_1[N-1:0] and PD_MAIN_CODE_1[N-1:0], and the second second impedance block is configured to receive target signals PU2_MAIN_CODE_2[N-1:0] and PD_MAIN_CODE_2[N-1:0], ...... The second impedance block is configured to receive target signals PU2_MAIN_CODE_A[N-1:0] and PD_MAIN_CODE_A[N-1:0].

[00238] Herein, the second logic module 521 is specifically configured to: determine whether a boost function of the at least one second impedance block will be activated in accordance with the third impedance control signal and the fourth impedance control signal; and setting, in the case where the a-th second impedance block level raising function is enabled, the level state of the a-th sub-signal group in the second target signal PU2_MAIN_CODE in accordance with the second calibration signal ZQ2_CODE[N-1:0] for control, thus the value of the active resistance of the second impedance block, so that it is the standard value of the active resistance; or determining, in the case where the a-th second impedance block boost function is not enabled, that the a-th group of subsignals in the second target signal PU2_MAIN_CODE is in the first level state. The third logic module 522 is particularly configured to: determine whether to enable a boost function of the at least one second impedance block in accordance with the fifth impedance control signal; and determining, in the case where the function of lowering the level of the a-th second impedance block is enabled, the state of the level of the a-th group of subsignals in the third target signal PD_MAIN_CODE in accordance with the third calibration signal ZQ3_CODE[N-1:0] to control the value of the active resistance of the second impedance block so that it is the standard value of active resistance; or determining, in the case where the level reduction function of the a-th second impedance block is not engaged, that the a-th group of subsignals in the third target signal PD_MAIN_CODE is in a second level state.

[00239] It should be noted that the actual signal between the third impedance control signal and the fourth impedance control signal and the second calibration signal ZQ2_CODE[N-1:0] are combined through the second logic module 521 so as to obtain the second target signal PU2_MAIN_CODE, thereby controlling function of increasing the level of the second impedance block. The structure and function of the second logic module 521 are essentially the same as those of the first logic module 42, and the operating principle of the second logic module 521 can be related to the above description of the first logic module 42 and will not be described again here.

[00240] The third logic module 533 is configured to combine the fifth impedance control signal IMPpd_CODE[M:0] and the third calibration signal ZQ3_CODE[N-1:0] to obtain the third target signal PD_MAIN_CODE and thereby control the pull-down function of the second impedance block. Likewise, the 1-bit subsignal of the fifth impedance control signal IMPpd_CODE[M:0] controls the activation of the pull-down function of one or more second impedance blocks. On this basis, if the pull-down function of the function of a certain second impedance block is enabled, the drop-down resistance value of the second impedance block is calibrated to the standard resistance value using the third calibration signal ZQ3_CODE[N-1:0], so that the pull-down function is carried out in Otherwise, if the level-lowering function of the second impedance block is not enabled, the corresponding circuit of the second impedance block is disconnected using a fixed signal in the second level state.

[00241] In some embodiments, each second impedance block includes N third switching transistors (e.g., third switching transistor 531 in FIG. 10 or 11), N fourth switching transistors (e.g., fourth switching transistor 532 in FIG. 10 or 11 ) and 2N second resistors (eg, second resistor 533 in FIG. 10 or 11). The control end of the n-th second switching transistor in the a-th third impedance block is connected to the n-th subsignal in the a-th group of subsignals in the second target signal, the first end of one third switching transistor is connected to the first end of one second resistor, and the second end of one the third switching transistor is connected to the power signal. The control end of the n-th fourth switching transistor in the a-th second impedance block is connected to the n-th subsignal in the a-th group of subsignals in the third target signal, the first end of the one fourth switching transistor is connected to the ground signal, the second end of the one fourth switching transistor is connected with the first end of one second resistor, and all the second ends of the second 2N resistors are connected to the pin for DQ.

[00242] It should be noted that in FIG. 10 or 11, with the first second impedance block as an example, the first second impedance block is configured to receive a first group of sub-signals PU2_MAIN_CODE_1[N-1:0] in a second target signal and a first group of sub-signals PD_MAIN_CODE_1[N-1:0] in a third target signal. Herein, the signal PU2_MAIN_CODE_1[N-1:0] includes sub-signals PU2_MAIN_CODE_1[0], PU2_MAIN_CODE_1[1] ... ... PU2_MAIN_CODE_1[n-1], and each sub-signal is configured to correspondingly control the operating state of one third switching transistor thus that it controls a second impedance block that performs the boost function with a standard resistance value or does not perform the boost function. The signal PD_MAIN_CODE_1[N-1:0] includes sub-signals PD_MAIN_CODE_1[0], PD_MAIN_CODE_1[1] ... ... PD_MAIN_CODE_1[n-1], and the sub-signal is configured to correspondingly control the operating state of one fourth switching transistor so that it controls a second impedance block that performs the level reduction function with a standard resistance value or does not perform the level reduction function.

[00243] Additionally, in FIG. 10 or 11, the first second impedance block includes three third switching transistors (only one third switching transistor 531 is provided with a reference designation), three fourth switching transistors (only one fourth switching transistor 532 is provided with a reference designation), and six second resistors (only one second resistor 533 is provided with a reference designation), but in actual scenarios, the number of all third switching transistors/fourth switching transistors/second resistors may be larger or smaller.

[00244] In practical circuit logic, the first level state is a high level state (logic "1") and the second level state is a low level state (logic "0"). The high state refers to the level value that makes an N-channel FET conductive or a P-channel FET non-conducting. The low state refers to the level value that makes an N-channel FET non-conducting or a P-channel FET conducting. All sub-signals in the first fixed-level signal are high-level signals, and the second fixed-level signal is a low-level signal. Here, the selection of the first fixed level signal and the second fixed level signal is determined in accordance with the circuit logic, wherein the first fixed level signal may be a power signal VDD and the second fixed level signal may be a ground signal VSS.

[00245] The first switching transistor and the third switching transistor are both P-channel FETs, and the second switching transistor and the fourth switching transistor are both N-channel FETs. The control end of the P-channel field-effect transistor is the gate, the second end of the P-channel field-effect transistor is the source, and the first end of the P-channel field-effect transistor is the drain. The driving end of the N-channel FET is the gate, the second end of the N-channel FET is the drain, and the first end of the N-channel FET is the source. The standard active resistance value is 240 Ohms.

[00246] Embodiments of the present disclosure provide a semiconductor memory because both the third operand (OP) and the fourth operand (OP) can influence the impedance state of the data mask (DM) pin, and the following strategy is provided to prevent data processing errors by the circuit impedance control: if the fourth operand (OP) is in the first state, the impedance of the data mask (DM) pin is determined in combination with the state of the third operand (OP), and if the fourth operand (OP) is in the second state, the impedance of the data mask pin (DM) is determined directly. Thus, the impedance of the data mask (DM) pin can be checked in a given test mode to prevent data processing errors by the circuit. The relationship between a control signal that is configured to control whether a data mask (DM) pin is enabled in DDR5 and a control signal that is configured to control whether a data mask (DM) pin is a test object is defined in PODTM mode. The data mask (DM) pin impedance can be checked in a specified test mode to prevent circuit processing errors.

[00247] According to another embodiment of the present disclosure, reference is made to FIG. 12, which shows a schematic diagram of the composition structure of the electronic device 60 according to one embodiment of the present disclosure. As shown in FIG. 12, electronic device 60 may include a semiconductor memory device 30 described in any of the preceding embodiments.

[00248] In this embodiment of the present disclosure, the semiconductor memory device 30 may be a DRAM chip.

[00249] Additionally, in some embodiments, the DRAM chip conforms to the DDR5 memory device specification.

[00250] Embodiments of the present disclosure generally relate to a control method and corresponding control circuitry for a data mask (DM) pin of a semiconductor memory device. An impedance control strategy is provided for the data mask (DM) pin in a given test mode. The data mask (DM) pin impedance can be checked in a specified test mode to prevent circuit processing errors.

[00251] The above represents only preferred embodiments of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[00252] It should be noted that in this disclosure, the terms “comprising,” “comprising,” or any other modification thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a sequence of elements includes not only these elements, but also other elements not explicitly listed, or elements inherent to the process, method, article or device. Without further limitation, an element defined by the clause “comprising...” does not preclude the existence of other identical elements in a process, method, article or device incorporating the specified element.

[00253] The above embodiment numbers of the present disclosure are for descriptive purposes only, and do not represent advantages or disadvantages of the embodiments.

[00254] The methods described in several method embodiments provided in the present disclosure may be combined arbitrarily without conflict to produce new method embodiments.

[00255] Features described in multiple product embodiments provided in the present disclosure may be combined arbitrarily without conflict to produce a new product embodiment.

[00256] Features described in several methods or apparatus embodiments provided in the present disclosure may be combined arbitrarily without conflict to produce new method embodiments or apparatus embodiments.

[00257] The above provides only specific embodiments of the present disclosure and is not intended to limit the scope of protection of the present disclosure. Any changes or substitutions apparent to those skilled in the art that are within the technical scope of protection described in the disclosure shall be within the scope of protection of this disclosure. Thus, the scope of protection of the present disclosure should be subordinated to the scope of protection as defined by the claims of the present invention.

INDUSTRIAL APPLICABILITY

[00258] Embodiments of the present disclosure provide a control method, a semiconductor memory device, and an electronic device. An impedance control strategy for the data mask (DM) pin in a given test mode is provided, so that the impedance of the data mask (DM) pin in a given test mode can be set. In addition, a relationship is defined between a control signal configured to control whether a data mask (DM) pin is enabled in a DDR5 memory device and a control signal configured to control whether a data mask (DM) pin is a test object. in PODTM mode. The data mask (DM) pin impedance can be checked in a specified test mode to prevent circuit processing errors.

Claims (70)

1. A control method applied to a semiconductor memory device comprising a data mask pin configured to receive a write data mask input signal, the method including: in response to the semiconductor memory device being in a predetermined test mode, controlling, when a fourth operand in the first operating mode register is in a first state, the impedance of the data mask pin as a first value, in accordance with the third operand in the third operating mode register; or controlling, when the fourth operand in the first operation mode register is in a second state, the impedance of the data mask pin as a second value; wherein the fourth operand is configured to indicate whether the data mask pin is enabled, and the third operand is configured to indicate whether the data mask pin is a test object in a given test mode. 2. The control method according to claim 1, wherein the first value comprises a first impedance parameter and a second impedance parameter, and the first state indicates to enable the data mask pin; wherein controlling the impedance of the data mask pin as the first value, in accordance with the third operand in the third operating mode register, includes: controlling, when the third operand is in the third state, the impedance of the data mask pin as a first impedance parameter, in accordance with the first operand in the first operating mode register, the third state indicating that the data mask pin is a test object in a given test mode; controlling, when the third operand is in the fourth state, the impedance of the data mask pin as a second impedance parameter, in accordance with the second operand in the second operating mode register, the fourth state indicating that the data mask pin is not a test object in the specified test mode; wherein the semiconductor memory device further comprises at least one data pin configured to receive or output data, wherein the first operand is configured to indicate that the impedance of the at least one data pin in the output signal conditioner state is the first impedance parameter and the second operand is configured to indicate that the impedance of the at least one data pin in the completion state is the second impedance parameter. 3. The control method of claim 2, wherein the second value comprises a high impedance state, wherein the second state indicates not to operate said data mask pin; wherein controlling the impedance of the data mask pin as a second value enables controlling the data mask pin to be in a high impedance state by the first fixed level signal. 4. The control method according to claim 3, additionally including: obtaining a first operand and a fourth operand stored in the first operating mode register, a second operand stored in the second operating mode register, and a third operand stored in the third operating mode register; decoding a third operand and a fourth operand, respectively, to obtain a first test flag signal and an enable control signal; And in response to the semiconductor memory device being in a predetermined test mode, selecting, in the case where the enable control signal is in a first level state, a first operand or a second operand for controlling the impedance of the data mask pin in accordance with the level state of the first test flag signal ; or controlling, in the case where the enable control signal is in a second level state, the data mask pin so that it is in a high impedance state by the first fixed level signal; wherein, when the fourth operand is in the first state, the enable control signal is in the first level state; when the fourth operand is in the second state, the enable control signal is in the second level state; when the third operand is in the third state, the first test flag signal is in the first level state; and when the third operand is in the fourth state, the first test flag signal is in the second level state. 5. The control method according to claim 4, according to which the method additionally includes: determining a first non-test state control signal and a second impedance control signal; in response to the semiconductor memory device being in a predetermined test mode, outputting, based on one of the first fixed-level signal, the first operand and the second operand, the first impedance control signal in accordance with the level state of the first test flag signal and the signal level state engagement management; or in response to the semiconductor memory device not being in a predetermined test mode, outputting, based on the first non-test state control signal, a first impedance control signal; And selecting one of the first impedance control signal and the second impedance control signal for controlling the impedance of the data mask pin according to an operating state of the semiconductor memory device; wherein the first non-test state control signal is configured to indicate the impedance of the data mask pin in a state other than the specified test state, and the second impedance control signal is configured to indicate the impedance of the data pin in the output signal driver state; or the first non-test state control signal is configured to indicate the impedance of the data pin in the output signal driver state, and the second impedance control signal is configured to indicate the impedance of the data mask pin in a state other than the specified test state. 6. The control method according to claim 4 or 5, wherein the specified test mode refers to a burst test mode of the output signal driver, wherein said burst test mode is configured to test the impedance of a data mask pin or at least one data pin after packaging ; wherein the standard number of the first operating mode register is 5, the first operand refers to the operand of the second bit to the first bit stored in the first operating mode register, and the fourth operand refers to the operand in the fifth bit stored in the first operating mode register; wherein the standard number of the second operating mode register is 34, and the second operand refers to the operand of the second bit to the 0th bit stored in the third operating mode register; wherein the standard number of the third operating mode register is 61, and the third operand refers to the operand of the 4th bit to the 0th bit stored in the third operating mode register; And the first level state is a high level state, and the second level state is a low level state. 7. A semiconductor memory device comprising a data mask pin, a first operating mode register, a third operating mode register, and a first driver circuit, the first driver circuit being connected to the first operating mode register, the third operating mode register, and the data mask pin, respectively; wherein the data mask pin is configured to receive a write data input mask signal; the first driver circuit is configured, in response to the semiconductor memory device being in a predetermined test mode, to control, when a fourth operand in the first operating mode register is in a first state, the impedance of the data mask pin as a first value, in accordance with the third operand in the third operating mode register; or controlling, when the fourth operand in the first operation mode register is in the second state, the impedance of the data mask pin as a second value; wherein the fourth operand is configured to indicate whether the data mask pin is enabled, and the third operand is configured to indicate whether the data mask pin is a test object in a given test mode. 8. The semiconductor memory device according to claim 7, further comprising a second operating mode register, wherein the second operating mode register is connected to the first driver circuit; the first value contains a first impedance parameter and a second impedance parameter, and the second value refers to a high impedance state; wherein the first driver circuit is, in particular, configured to: control, in the case where the fourth operand is in the first state and the third operand is in the third state, the impedance of the data mask pin as a first impedance parameter, in accordance with the first operand in the first operating mode register; or controlling, in the case where the fourth operand is in the first state and the third operand is in the fourth state, the impedance of the data mask pin as a second impedance parameter, in accordance with the second operand in the second operation mode register; or controlling, in the case where the fourth operand is in a second state, the impedance of the data mask pin so that it is in a high impedance state in accordance with the first fixed level signal; wherein the first state indicates to enable the data mask pin, and the second state indicates not to engage the data mask pin; the third state indicates that the data mask pin is a test object in the specified test mode, and the fourth state indicates that the data mask pin is not a test object in the specified test mode; wherein the semiconductor memory device further comprises at least one data pin configured to receive or output data, the first operand configured to indicate that the impedance of the at least one data pin in the output signal driver state is a first impedance parameter, and the second operand is configured to indicate that the impedance of the at least one data pin in the completion state is a second impedance parameter. 9. The semiconductor memory device according to claim 8, further comprising: a first decoding module and a second decoding module; wherein the first operating mode register is configured to store and output the first operand and the fourth operand; the second operating mode register is configured to store and output the second operand; the third operating mode register is configured to store and output the third operand; the first decoding module is configured to receive a third operand, decode the third operand, and output a first test flag signal; the second decoding module is configured to receive a fourth operand, decode the fourth operand, and output an activation control signal; the first driver circuit is configured to: receive an activation control signal, a first test flag signal, a first fixed-level signal, a first operand, and a second operand; and in response to the semiconductor memory device being in a predetermined test mode, controlling, in the case where the enable control signal is in a first level state, the impedance of the data mask pin based on the first operand or the second operand in accordance with the level state of the first flag signal testing; or controlling, in the case where the enable control signal is in a second level state, the data mask pin so that it is in a high impedance state by the first fixed level signal; wherein, when the fourth operand is in the first state, the enable control signal is in the first level state; when the fourth operand is in the second state, the enable control signal is in the second level state; when the third operand is in the third state, the first test flag signal is in the first level state; and, when the third operand is in the fourth state, the first test flag signal is in the second level state. 10. The semiconductor memory device of claim 9, further configured to determine a first non-test state control signal, a second impedance control signal, and a first calibration signal; wherein the first calibration signal is configured to calibrate the increasing value of the active resistance, and the first driver circuit contains: a first signal processing module configured to receive a first test flag signal, an enable control signal, a first fixed level signal, a first operand, a second operand, and a first non-test state control signal; and outputting, based on one of the first fixed-level signal, the first operand and the second operand, a first impedance control signal in accordance with the level state of the first test flag signal and the level state of the enable control signal in response to the semiconductor memory device being in the specified test mode; or outputting, based on the first non-test state control signal, a first impedance control signal in response to the semiconductor memory device not being in a predetermined test mode; a first logic module configured to receive a first impedance control signal, a second impedance control signal, and a first calibration signal; and selecting and logically combining the first impedance control signal, the second impedance control signal, and the first calibration signal to output the first target signal; And a first driver module comprising a plurality of first impedance blocks and configured to receive the first target signal and control the plurality of first impedance blocks when using the first target signal so as to control the impedance of the data mask pin; wherein the first non-test state control signal is configured to indicate the impedance of the data mask pin in a state other than the specified test state, and the second impedance control signal is configured to indicate the impedance of the data pin in the output signal driver state; or the first non-test state control signal is configured to indicate the impedance of the data pin in the output signal driver state, and the second impedance control signal is configured to indicate the impedance of the data mask pin in a state other than the specified test state. 11. The semiconductor memory device according to claim 10, wherein the first signal processing module comprises: a third decoding module configured to receive the first operand, decode the first operand, and output the first decoded signal; a fourth decoding module configured to receive a second operand, decode the second operand, and output a second decoded signal; a first selector configured to receive a first test flag signal, a first decoded signal, and a second decoded signal; and selecting, in accordance with the first test flag signal, one of the first decoded signal and the second decoded signal to output the first preselection signal; a second selection module configured to receive an activation control signal, a first preselection signal, and a first fixed level signal; and selecting, in accordance with the level state of the activation control signal, one of the first preselection signal and the first fixed-level signal to output the first test state control signal; And a third selection module configured to receive a test enable signal, a first test state control signal, and a first non-test state control signal; and selecting, according to the test enable signal level state, one of the first test state control signal and the first non-test state control signal to output the first impedance control signal; wherein the test enable signal is configured to indicate whether the semiconductor memory device is in a predetermined test mode. 12. The semiconductor memory device of claim 11, wherein each of the first decoded signal, the second decoded signal, the first preselection signal, the first fixed-level signal, the first test state control signal, the first non-test state control signal, and the first impedance control signal comprises (M+1)-bit subsignal, the first selector contains (M+1) first data selectors, the second selector contains (M+1) second data selectors, and the third selector contains (M+1) third data selectors; wherein an input end of one first data selector receives a 1-bit subsignal of a first decoded signal and a 1-bit subsignal of a second decoded signal, an output end of one first data selector is configured to output a 1-bit subsignal of a first preselection signal, and the control ends of all first data selectors receive first test flag signal; the input end of one second data selector receives a 1-bit subsignal of the first preselection signal and a 1-bit subsignal of the first fixed-level signal, the output end of one second data selector is configured to output a 1-bit subsignal of the first test state control signal, and the control ends of all the second data selectors receive an activation control signal; the input end of one third data selector receives a 1-bit subsignal of the first test state signal and a 1-bit subsignal of the first non-test state control signal, the output end of one third data selector is configured to output a 1-bit subsignal of the first impedance control signal, and the control ends of all third data selectors receive the test enable signal; in this case M is a positive integer. 13. The semiconductor memory device of claim 12, wherein the second impedance control signal contains an (M+1)-bit subsignal, the first calibration signal contains N-bit subsignals, the first target signal contains A groups of subsignals, and each group of subsignals contains N- bit subsignals; the first driver module includes first impedance blocks, and each first impedance block is configured to receive a group of subsignals in the first target signal; the first logic module is particularly configured to determine whether the boost function of the at least one first impedance block is enabled in accordance with the first impedance control signal and the second impedance control signal; And determining, in the case where the a-th first impedance block level raising function is enabled, the level state of the a-th group of subsignals in the first target signal in accordance with the first calibration signal so as to control the active resistance value of the a-th first impedance block in such a way, so that it is the standard value of active resistance; or determining that, in a case where the a-th level-raising function of the first impedance block is not engaged, the a-th group of subsignals in the first target signal is in a first level state; Moreover, all of the numbers a, N and A are integers, number a is less than or equal to A and (M+1) is less than or equal to A. 14. The semiconductor memory device of claim 13, wherein each first impedance block includes N first switching transistors, N second switching transistors, and 2N first resistors; the control end of the n-th first switching transistor in the a-th first impedance block is connected to the n-th subsignal in the a-th group of subsignals in the first target signal, the first end of one first switching transistor is connected to the first end of one first resistor, and the second end of one the first switching transistor is connected to the power signal; the control end of one second switching transistor is connected to a second fixed-level signal, the first end of one second switching transistor is connected to a ground signal, the second end of one second switching transistor is connected to the first end of one first resistor, and the second ends of the 2N first resistors are all connected to a pin for data masks; wherein n is an integer, and n is less than or equal to N. 15. Semiconductor memory device according to claim 14, in which: the first switching transistor is a P-channel field-effect transistor, and the second switching transistor is an N-channel field-effect transistor; The control end of the P-channel FET is the gate, the second end of the P-channel FET is the source, the first end of the P-channel FET is the drain, the control end of the N-channel FET is the gate, the second end of the N-channel FET is the drain, and the first end of the N-channel field effect transistor is the source; the first level state is a high level state, the second level state is a low level state, the sub-signals in the first fixed level signal are high level signals, and the second fixed level signal is a low level signal; And The standard active resistance value is 240 Ohms. 16. An electronic device comprising a semiconductor memory device according to any one of claims. 7-15.