CN1375832A

CN1375832A - DDR SDRAM and SDRAM shared module with double data transmission rate

Info

Publication number: CN1375832A
Application number: CN 01109837
Authority: CN
Inventors: 林火元
Original assignee: Giga Byte Technology Co Ltd
Current assignee: Giga Byte Technology Co Ltd
Priority date: 2001-03-21
Filing date: 2001-03-21
Publication date: 2002-10-23
Anticipated expiration: 2021-03-21
Also published as: CN1214397C

Abstract

A sheared module on the main-board that includes Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM) and Synchronous Dynamic Random Access Memory (SDRAM) is described. The value of terminal resistance on the mainboard is confirmed by calculating, accordingly the operating current is in the limit range of SDRAM controller. And that without additional fast switching IC, the purpose that DDRDRAM and SDRAM are designed together can be achieved.

Description

The DDR SDRAM of double data rate and the shared module of SDRAM

The present invention relates to a kind of Synchronous Dynamic Random Access Memory (DDRSDRAM) of double data rate and the shared module of Synchronous Dynamic Random Access Memory (SDRAM), be particularly related to the Synchronous Dynamic Random Access Memory (DDR SDRAM) of following this double data rate and the shared module of Synchronous Dynamic Random Access Memory (SDRAM): need not other integrated circuit, and do not increasing fully under the condition of cost, can realize the common design of DDR SDRAM and SDRAM.

When higher frequency strides forward, the frequency range of bus and the raising of memory speed also will become the key element of left and right sides entire system performance in CPU full speed.Analyze Rambus structure and SDRAM-II standard (Double-Data-Rate Synchronous DRAM that present widely industry member is discussed; DDRSDRAM), both have possessed the advantage that increases data rate in fact.

On the other hand,, and do not need as Rambus, need redefine the socket standard because be compatible on the SDRAM structure of DDR SDRAM structure and present stage, will be easy to the popularization of this standard of what than the former.

And Synchronous Dynamic Random Access Memory (SDRAM) is the new model of DRAM, and is upward more many soon than the time clock speed of legacy memory.Because the bus synchronous of its energy and CPU, and can open two storage pages (PAGE) simultaneously, arithmetic speed can reach 133MHz.

Yet, the Pentium that Intel produces (Pentium) series is used is 100 and the cpu bus of 133MHz, so SDRAM can also support, but following personal computer may use the bus up to 200MHz, SDRAM just is not enough to support, so, exploitation more at a high speed storer such as the Synchronous Dynamic Random Access Memory (DDR-SDRM) of double data rate just become a urgent demand.

The Synchronous Dynamic Random Access Memory of double data rate (DDR-SDRM) because can support the data transmission of twice clock train of thought, thereby can be twice with the data volume lifting of storage chip, and that therefore also claim is SDRM II.

Yet, motherboard supports that jointly the concrete practice of DDR SDRAM and SDRAM is to utilize a quick integrated circuit (Quick Switch IC) that switches to control switching terminal resistance (Terminator) at present, to reach the purpose of the common design of DDR SDRAM and SDRAM.But the method needs 8-10 to switch integrated circuit fast, must increase cost of manufacture comparatively speaking, and for the producer and user of a large amount of manufacturing motherboards, this is a kind of very uneconomic design.

The main purpose of the present invention is to provide the Synchronous Dynamic Random Access Memory (DDR SDRAM) of the double data rate on a kind of motherboard and the shared module of Synchronous Dynamic Random Access Memory (SDRAM), can realize the purpose of the common design of DDR DRAM and SDRAM under the situation that does not need extra quick switching integrated circuit.

The said shared module of the present invention can be set at the terminal resistance on the motherboard between 220 ohm to 1250 ohm after testing, with 330 ohm is preferred value, DDR DRAM and SDRAM can both operate as normal, and working current all satisfies in the scope that sdram controller allows.

Below in conjunction with relevant detailed content of the present invention of description of drawings and technology, wherein:

Fig. 1 is the Synchronous Dynamic Random Access Memory (DDRSDRAM) of double data rate of the present invention and the structural drawing of first embodiment of the shared module of Synchronous Dynamic Random Access Memory (SDRAM); With

Fig. 2 is the Synchronous Dynamic Random Access Memory (DDRSDRAM) of double data rate of the present invention and the structural drawing of second embodiment of the shared module of Synchronous Dynamic Random Access Memory (SDRAM).

Generally speaking, support that control (CMD) signal/address (ADD) signal, the required terminal voltage of data (DATA) signal of DDR SDRAM memory module are 1.25V; Support that control (CMD) signal/address (ADD) signal, the required terminal voltage of data (DATA) signal of SDRAM memory module are 3.3V.But DDR SDRAM memory module needs 33 ohm terminal resistance, and the SDRAM memory module does not then need.

So-called terminal resistance is special a resistance bag or a resistance bolck, can be used to tell terminal point that Computer signal transmits wherein, and guarantees the stability of integrated circuit signal.The effect of terminal resistance can be eliminated the electrical noise that is produced by many cables and equipment as wave filter.

Therefore, DDR SDRAM and SDRAM will design (promptly wanting shared control (CMD) signal/address (ADD) signal, data (DATA) signal) jointly, must under the constant situation of terminal voltage, cooperate appropriate terminal resistance, make that DDR SDRAM and SDRAM all can operate as normal.

General except the termination function that utilizes terminating resistor, also utilize its induction mode measuring ability.When detecting DDR SDRAM device, can be the DDRSDRAM pattern automatically with the bus transfer mode switch.Certainly, whole bus can be transmitted data with fast speeds.As after the design of the present invention, the SDRAM device can be connected in the same passage to reach the purpose of common design.

Fig. 1 is the Synchronous Dynamic Random Access Memory (DDRSDRAM) of double data rate of the present invention and the shared module structural drawing of Synchronous Dynamic Random Access Memory (SDRAM), wherein, by a controller 10 will control (CMD) signal/address (ADD) signal, data (DATA) signal is passed in the shared module 12, this shared module 12 comprises the double pin memory module of at least one DDR SDRAM (Dual In-Line Memory Module; DIMM) and the double pin memory module of at least one SDRAM (Dual In-Line Memory Module; DIMM).

In the first embodiment of the present invention, shared module 12 comprises the double pin memory module 20 of a DDR SDRAM, the double pin memory module 30 of the 2nd DDR SDRAM, the double pin memory module 40 of a SDRAM, reaches the double pin memory module 50 of the 2nd SDRAM.Be respectively applied for the configuration that the DDR of different numbers SDRAM and SDRAM are provided.For example, two DDR SDRAM (double pin memory module of a DDR SDRAM and the double pin memory module of the 2nd DDR SDRAM) and two SDRAM (double pin memory module of a SDRAM and the double pin memory module of the 2nd SDRAM); A DDR SDRAM (the double pin memory module of DDR SDRAM) and three SDRAM (the double pin memory module of a SDRAM, the double pin memory module of the 2nd SDRAM and the double pin memory module of Three S's DRAM); Three DDR SDRAM (the double pin memory module of a DDR SDRAM, the double pin memory module of the 2nd DDR SDRAM, the double pin memory module of the 3rd DDR SDRAM) and a SDRAM (the double pin memory module of SDRAM).By the design of

terminal resistance

60,62, under the situation that terminal voltage 70 remains unchanged, reach the purpose of shared module again.

Fig. 2 is the Synchronous Dynamic Random Access Memory (DDRSDRAM) of double data rate of the present invention and the structural drawing of second embodiment of the shared module of Synchronous Dynamic Random Access Memory (SDRAM).As shown in Figure 2, shared module 12 also comprises one the 5th double pin memory module 52, and as the configuration mode of the first above-mentioned embodiment, the user can select the DDRSDRAM of varying number and SDRAM to prepare, and no longer repeats at this.

For the said shared module of the present invention, by calculate and the result of test gained as can be known, when

terminal resistance

60,62 be 220 ohm to 1250 the time, DDR DRAM and SDRAM all can operate as normal, and said operate as normal is meant that the electric current of signal when high and low level of SDRAM drops in the allowed band of sdram controller.

The control of SDRAM (CMD) signal/address (ADD) signal, the electric current (I when data (DATA) signal is high level _H) and the electric current (I when being low level _L) calculating and test result following (is example with 330 ohm terminal resistances):

I _H＝(3.3-1.25)/0.33K＝6.21mA；

I _L=1.25/0.33K=3.79mA; With 330 ohm terminal resistances is example:

I _H＝(3.3-1.25)/0.22K＝9.31mA；

I _L＝1.25/0.22K＝5.68mA；

With 1250 ohm is example

I _H＝(3.3-1.25)/1.25K＝1.64mA；

I _L＝1.25/1.25K＝1mA；

Must constantly refresh the numerical value of (REFRESHED) potential difference (PD) again by what dynamic RAM (DRAM), otherwise potential difference (PD) will be reduced to and can't represent each storage unit place which kind of state of what with enough energy.Learn by aforementioned calculation: change

terminal resistance

60,62 and be 220 ohm between 1250 ohm the time, I _HAnd I _LBetween between the 9.31mA to 1mA, can not influence the signal transmission quality of DDR DRAM, and I _HWith I _LCurrent value all in the allowed band of sdram controller, so be a truly feasible shared module.Therefore the present invention has following effect:

(1) the present invention mainly is to provide a cost less, motherboard memory environments that compatibility is bigger for the user, the user can select best memory module according to the demand of oneself, different with the unicity toward the motherboard memory environments, it is available to the invention provides two kinds of memory modules; For computer manufacturer, price is more flexible; For DIY master-hand, or assembling tool, can reach best expense/price ratio.

(2) the present invention need not other integrated circuit, is not increasing the purpose that realizes DDRDRAM and the common design of SDRAM under the condition of cost fully.

(3) reduce a plurality of quick switching integrated circuit (IC) design, reduce cost of manufacture, and the design space of more motherboards is provided, and reduce the electromagnetic interference problem that complicated circuit causes.

Though more than disclose above preferred embodiment of the present invention; but this is not to be used to limit the present invention; those of ordinary skill in the art can do some many changes and improvement under the situation that does not break away from the spirit and scope of the present invention, so protection scope of the present invention is determined by the accompanying Claim book.

Claims

1. the shared module of the Synchronous Dynamic Random Access Memory of a double data rate (DDR SDRAM) and Synchronous Dynamic Random Access Memory (SDRAM) comprises at least:

The double pin memory module of at least one DDR SDRAM;

The double pin memory module of at least one SDRAM;

Terminal resistance is coupled to shared module, and outlet terminal voltage;

Wherein, by a controller, will control (CMD) signal/address (ADD) signal, data (DATA) signal is passed in the shared module.

2. the shared module of Synchronous Dynamic Random Access Memory of double data rate as claimed in claim 1 (DDR SDRAM) and Synchronous Dynamic Random Access Memory (SDRAM) is characterized in that the required terminal voltage of DDR SDRAM memory module is 1.25V.

3. the shared module of Synchronous Dynamic Random Access Memory of double data rate as claimed in claim 1 (DDR SDRAM) and Synchronous Dynamic Random Access Memory (SDRAM) is characterized in that the required terminal voltage of SDRAM memory module is 3.3V.

4. the shared module of the Synchronous Dynamic Random Access Memory of double data rate as claimed in claim 1 (DDR SDRAM) and Synchronous Dynamic Random Access Memory (SDRAM), it is characterized in that terminal resistance is used to notify the computing machine terminal point that relevant signal transmits wherein, and guarantee the stability of integrated circuit signal.

5. the shared module of the Synchronous Dynamic Random Access Memory of double data rate as claimed in claim 1 (DDR SDRAM) and Synchronous Dynamic Random Access Memory (SDRAM), the resistance that it is characterized in that terminal resistance is between 220 ohm to 1250 ohm.