CN116841951A - LDPC coding and decoding computing system based on RISC-V architecture - Google Patents
LDPC coding and decoding computing system based on RISC-V architecture Download PDFInfo
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Abstract
The invention discloses an LDPC coding and decoding computing system based on RISC-V architecture, which comprises a RISC-V processor and an LDPC coding and decoding computing coprocessor; the RISC-V processor is used for executing general calculation and instructions, performing software programming and realizing flexible function change; the LDPC encoding and decoding calculation coprocessor is used for receiving a self-defined instruction from the RISC-V processor, determining an instruction function according to instruction decoding, performing LDPC encoding and decoding operations on input information according to an input sequence by using different functional components and calculation units, and simultaneously, is provided with a complete verification module, obtains an encoded result, performs storage processing, returns a calculation result to the RISC-V processor according to a corresponding instruction, and waits for a user to use. The invention realizes the integration of the LDPC encoding and decoding calculation coprocessor and the RISC-V processor through the custom instruction. The system has high efficiency and low power consumption.
Description
Technical Field
The invention belongs to the technical field of integrated circuits and digital communication, and particularly relates to an LDPC coding and decoding computing system based on a RISC-V architecture.
Background
In the information age, digital communication is extremely important in the life of people, and the requirements of people on communication accuracy are also higher and higher; in recent years, LDPC codes have been increasingly sought in the industry and scientific circles, and have played an important role in the fields of 5G communication, internet of things, and the like.
Meanwhile, an open source instruction set architecture (RISC-V) based on a reduced instruction set principle attracts a large number of open source workers, and a plurality of technological companies in the introduction invest in RISC-V greatly, so that RISC-V instruction sets are developed better and better; RISC-V instruction sets eliminate unnecessary instructions compared to other instruction sets, RISC-V processors with a smaller number of transistors typically consume less power, and are therefore more suitable for consumer electronics devices.
Conventional digital communication devices, which want to implement digital communication based on some kind of ECC (such as low density check code, LDPC code), need to establish a path between a CPU and a dedicated chip supporting such ECC to operate, and the speed and efficiency of communication are greatly reduced.
Disclosure of Invention
The invention aims to provide an LDPC coding and decoding computing system based on RISC-V architecture, which has high efficiency and low power consumption.
The LDPC coding and decoding computing system based on RISC-V architecture comprises a RISC-V processor and an LDPC coding and decoding computing coprocessor; the RISC-V processor is used for executing general calculation and instructions, performing software programming, and controlling the LDPC encoding and decoding calculation coprocessor through the custom expansion assembly instructions; the LDPC encoding and decoding calculation coprocessor is used for receiving a self-defined instruction from the RISC-V processor, determining an instruction function according to instruction decoding, performing LDPC encoding and decoding operations on input information according to an input sequence by using different functional components and calculation units, and simultaneously, providing a complete verification module, obtaining an encoded result, performing storage processing, returning a calculation result to the RISC-V processor according to a corresponding instruction, and waiting for a user to use;
the LDPC encoding and decoding calculation coprocessor comprises an instruction unit and an LDPC encoding and decoding calculation unit;
the LDPC encoding and decoding calculation unit comprises a calculation module, a control module, a verification module and a storage module;
the computing module processes the information to be encoded and decoded, which is obtained through analysis, in the instruction sent by the RISC-V processor, and obtains an LDPC encoding and decoding result, processes the information to be encoded and decoded, which is obtained through analysis, in the instruction sent by the RISC-V processor, and sends the LDPC encoding and decoding result to the control module; different computing processing stages are designed on the basis of pipeline structures in the module; different structures are responsible for different kinds of computation, and meanwhile, in each computation stage, the computation module and the storage module perform data interaction, are controlled by the control module, and verify the result of each stage through the verification module;
the control module is used for carrying out time sequence control on each flow in the received LDPC coding and decoding pipeline, and simultaneously, when the checking module recognizes errors or the RISC-V processor sends out an interrupt instruction, the control module can timely pause the coding and decoding process of corresponding information and return a status code;
the verification module performs verification on the result obtained by each calculation stage in the LDPC encoding and decoding pipeline, and transmits the verification result to the control module, and the control module determines whether to perform LDPC encoding and decoding calculation of the next stage; if the verification is correct, transmitting the calculation result to a storage module for storage, and if the verification is correct, returning an error code to the RISC-V processor;
the storage module is used for storing the coding result obtained in each stage and the check matrix used in the current processing stage and waiting for the access of the next stage; the storage module releases the result stored in the previous stage after receiving the signal of the verification module for verifying the previous calculation stage; the final stored content of the module is a final coding and decoding result with a number, and meanwhile, a result return instruction is sent out by the RISC-V processor;
the instruction unit comprises an instruction receiving unit, an instruction analyzing unit, a number generating unit, a state returning unit and a result returning unit;
the instruction receiving unit is used for receiving custom instruction data from the RISC-V processor;
the instruction analysis unit is used for receiving the instruction from the instruction receiving unit, analyzing the instruction, converting the received instruction into enabling signals of each unit module, and sending the instruction information to the corresponding unit;
the number generating unit carries out number processing on the information to be LDPC coded or decoded, enables the information to carry corresponding numbers when the information is reported wrong or returned, and transmits the numbered information to a subsequent module for processing, so that the subsequent information can be conveniently called;
the state returning unit returns the state code to the RISC-V processor according to the state code returned by the control module, so that the RISC-V processor obtains the working state of the LDPC encoding and decoding unit;
the result returning unit searches the corresponding result when the RISC-V processor accesses the related result under the condition that the state codes returned by the control module all represent the normal state, and returns the corresponding result to the RISC-V processor;
the custom instruction of the RISC-V processor specifically comprises:
(1) A reset instruction: the REET is used for resetting the whole computing system, and the resetting comprises a resetting instruction unit, an LDPC encoding and decoding computing module, a control module, a storage module and a verification module; the operand reservation description includes:
RD: retaining; r1: retaining; r2: retaining;
(2) Calculation instructions: ACTY for setting input data and calculation modes; the operand reservation description includes:
RD: retaining; r1: inputting a start address of the data;
(3) Calculation instructions: COTE, which is used for numbering information and calculating; the operand reservation description includes:
RD: retaining; r1: numbering information of the data; r2: retaining;
(4) The result returns the instruction: RERN, is used for returning the structure, including returning LDPC encoding and decoding calculation result of the specific number; the operand reservation description includes:
RD: retaining; r1: information number of data to be read; r2: retaining;
(5) A check matrix setting initialization instruction: MAIT, is used for presuming the check matrix that the system uses, including presuming the check matrix row, column number and value of the concrete position that the system uses; the operand reservation description includes:
RD: retaining; r1: the number of the check matrix rows to be input; r2: the number of check matrix columns to be input;
(6) Check matrix setting input instruction: MAIN, which is used to input the check matrix used by the system; the operand reservation description includes:
RD: data; r1: inputting data of an nth row; r2: inputting data of an nth column;
the workflow of the LDPC coding and decoding computing system based on RISC-V architecture specifically comprises the following steps:
s1, an LDPC encoding and decoding operation is executed by a RISC-V processor;
s2, sending an initialization instruction;
s3, sending a calculation instruction;
s4, sending a result return instruction;
s5, the RISC-V processor executes LDPC encoding and decoding operation to finish;
the RISC-V processor in step S1 executes LDPC encoding and decoding operations, and specifically includes:
the RISC-V processor needs to execute LDPC encoding and decoding calculation work, and starts the LDPC encoding and decoding calculation coprocessor through a custom coprocessor interface;
the sending an initialization command in step S2 specifically includes:
the RISC-V processor sends a reset instruction through a self-defined coprocessor interface;
the sending a calculation instruction in step S3 specifically includes:
the RISC-V processor sequentially sends ACTY instructions, and sets input data and calculation modes; transmitting a COTE instruction, numbering the information and starting calculation;
the sending result return instruction in step S4 specifically includes:
the RISC-V processor sends a result return instruction through a self-defined coprocessor interface; and sending a RERN instruction and reading the operation result of the designated number.
The LDPC coding and decoding computing system based on RISC-V architecture realizes the integration of the LDPC coding and decoding computing coprocessor and the RISC-V processor through the custom instruction; the LDPC encoding and decoding calculation coprocessor has configurability, supports the configuration of the coprocessor through a user-defined instruction, and comprises a calculation mode and a check matrix; the system has high efficiency and low power consumption.
Drawings
FIG. 1 is a schematic diagram of functional modules of the system of the present invention.
FIG. 2 is a schematic diagram of an instruction unit module of the system of the present invention.
Fig. 3 is a schematic diagram of an LDPC codec calculation unit module of the system of the present invention.
Detailed Description
FIG. 1 is a schematic diagram of the functional modules of the system of the present invention: the LDPC coding and decoding computing system based on RISC-V architecture comprises a RISC-V processor and an LDPC coding and decoding computing coprocessor; the RISC-V processor is used for executing general calculation and instructions, performing software programming to realize flexible function change, and controlling the LDPC encoding and decoding calculation coprocessor through the custom expansion assembly instructions; the LDPC encoding and decoding calculation coprocessor is used for receiving a self-defined instruction from the RISC-V processor, determining an instruction function according to instruction decoding, performing LDPC encoding and decoding operations on input information according to an input sequence by using different functional components and calculation units, and simultaneously, providing a complete verification module, obtaining an encoded result, performing storage processing, returning a calculation result to the RISC-V processor according to a corresponding instruction, and waiting for a user to use;
the LDPC encoding and decoding calculation coprocessor comprises an instruction unit and an LDPC encoding and decoding calculation unit;
FIG. 2 is a schematic diagram of an LDPC codec calculation unit of the system according to the present invention: the LDPC encoding and decoding calculation unit comprises a calculation module, a control module, a verification module and a storage module;
the computing module processes the information to be encoded and decoded, which is obtained through analysis, in the instruction sent by the RISC-V processor, and obtains an LDPC encoding and decoding result, processes the information to be encoded and decoded, which is obtained through analysis, in the instruction sent by the RISC-V processor, and sends the LDPC encoding and decoding result to the control module; different computing processing stages are designed on the basis of pipeline structures in the module; different structures are responsible for different kinds of computation, and meanwhile, in each computation stage, the computation module and the storage module perform data interaction, are controlled by the control module, and verify the result of each stage through the verification module;
the control module is used for carrying out time sequence control on each flow in the received LDPC coding and decoding pipeline, and simultaneously, when the checking module recognizes errors or the RISC-V processor sends out an interrupt instruction, the control module can timely pause the coding and decoding process of corresponding information and return a status code;
the verification module performs verification on the result obtained by each calculation stage in the LDPC encoding and decoding pipeline, and transmits the verification result to the control module, and the control module determines whether to perform LDPC encoding and decoding calculation of the next stage; if the verification is correct, transmitting the calculation result to a storage module for storage, and if the verification is correct, returning an error code to the RISC-V processor;
the storage module is used for storing the coding result obtained in each stage and the check matrix used in the current processing stage and waiting for the access of the next stage; the storage module releases the result stored in the previous stage after receiving the signal of the verification module for verifying the previous calculation stage; the final stored content of the module is a final coding and decoding result with a number, and meanwhile, a result return instruction is sent out by the RISC-V processor;
FIG. 3 is a schematic diagram of the instruction unit modules of the system of the present invention: the instruction unit comprises an instruction receiving unit, an instruction analyzing unit, a number generating unit, a state returning unit and a result returning unit;
the instruction receiving unit is used for receiving custom instruction data from the RISC-V processor;
the instruction analysis unit is used for receiving the instruction from the instruction receiving unit, analyzing the instruction, converting the received instruction into enabling signals of each unit module, and sending the instruction information to the corresponding unit;
the number generating unit carries out number processing on the information to be LDPC coded or decoded, enables the information to carry corresponding numbers when the information is reported wrong or returned, and transmits the numbered information to a subsequent module for processing, so that the subsequent information can be conveniently called;
the state returning unit returns the state code to the RISC-V processor according to the state code returned by the control module, so that the RISC-V processor obtains the working state of the LDPC encoding and decoding unit;
the result returning unit searches the corresponding result when the RISC-V processor accesses the related result under the condition that the state codes returned by the control module all represent the normal state, and returns the corresponding result to the RISC-V processor;
the custom instruction of the RISC-V processor specifically comprises:
(1) A reset instruction: the REET is used for resetting the whole computing system, and the resetting comprises a resetting instruction unit, an LDPC encoding and decoding computing module, a control module, a storage module and a verification module; the operand reservation description includes:
RD: retaining; r1: retaining; r2: retaining;
(2) Calculation instructions: ACTY for setting input data and calculation modes; the operand reservation description includes:
RD: retaining; r1: inputting a start address of the data;
(3) Calculation instructions: COTE, which is used for numbering information and calculating; the operand reservation description includes:
RD: retaining; r1: numbering information of the data; r2: retaining;
(4) The result returns the instruction: RERN, is used for returning the structure, including returning LDPC encoding and decoding calculation result of the specific number; the operand reservation description includes:
RD: retaining; r1: information number of data to be read; r2: retaining;
(5) A check matrix setting initialization instruction: MAIT, is used for presuming the check matrix that the system uses, including presuming the check matrix row, column number and value of the concrete position that the system uses; the operand reservation description includes:
RD: retaining; r1: the number of the check matrix rows to be input; r2: the number of check matrix columns to be input;
(6) Check matrix setting input instruction: MAIN, which is used to input the check matrix used by the system; the operand reservation description includes:
RD: data; r1: inputting data of an nth row; r2: inputting data of an nth column;
the workflow of the LDPC coding and decoding computing system based on RISC-V architecture specifically comprises the following steps:
s1, an LDPC encoding and decoding operation is executed by a RISC-V processor;
s2, sending an initialization instruction;
s3, sending a calculation instruction;
s4, sending a result return instruction;
s5, the RISC-V processor executes LDPC encoding and decoding operation to finish;
the RISC-V processor in step S1 executes LDPC encoding and decoding operations, and specifically includes:
the RISC-V processor needs to execute LDPC encoding and decoding calculation work, and starts the LDPC encoding and decoding calculation coprocessor through a custom coprocessor interface;
the sending an initialization command in step S2 specifically includes:
the RISC-V processor sends a reset instruction through a self-defined coprocessor interface;
the sending a calculation instruction in step S3 specifically includes:
the RISC-V processor sequentially sends ACTY instructions, and sets input data and calculation modes; transmitting a COTE instruction, numbering the information and starting calculation;
the sending result return instruction in step S4 specifically includes:
the RISC-V processor sends a result return instruction through a self-defined coprocessor interface; and sending a RERN instruction and reading the operation result of the designated number.
Claims (10)
1. An LDPC coding and decoding computing system based on RISC-V architecture comprises a RISC-V processor and an LDPC coding and decoding computing coprocessor; the RISC-V processor is used for executing general calculation and instructions, performing software programming, and controlling the LDPC encoding and decoding calculation coprocessor through the custom expansion assembly instructions; the LDPC encoding and decoding calculation coprocessor is used for receiving a self-defined instruction from the RISC-V processor, determining an instruction function according to instruction decoding, performing LDPC encoding and decoding operations on input information according to an input sequence by using different functional components and calculation units, and simultaneously, is provided with a complete verification module, obtains an encoded result, performs storage processing, returns a calculation result to the RISC-V processor according to a corresponding instruction, and waits for a user to use.
2. The LDPC codec computing system based on RISC-V architecture as claimed in claim 1, wherein the LDPC codec computing coprocessor comprises an instruction unit and an LDPC codec computing unit;
the LDPC encoding and decoding calculation unit comprises a calculation module, a control module, a verification module and a storage module;
the instruction unit comprises an instruction receiving unit, an instruction analyzing unit, a number generating unit, a state returning unit and a result returning unit.
3. The LDPC coding and decoding computing system based on RISC-V architecture as recited in claim 2, wherein the LDPC coding and decoding computing unit comprises a computing module, a control module, a checking module and a storage module, and specifically comprises:
the computing module processes the information to be encoded and decoded, which is obtained through analysis, in the instruction sent by the RISC-V processor, and obtains an LDPC encoding and decoding result, processes the information to be encoded and decoded, which is obtained through analysis, in the instruction sent by the RISC-V processor, and sends the LDPC encoding and decoding result to the control module; different computing processing stages are designed on the basis of pipeline structures in the module; different structures are responsible for different kinds of computation, and meanwhile, in each computation stage, the computation module and the storage module perform data interaction, are controlled by the control module, and verify the result of each stage through the verification module;
the control module is used for carrying out time sequence control on each flow in the received LDPC coding and decoding pipeline, and simultaneously, when the checking module recognizes errors or the RISC-V processor sends out an interrupt instruction, the control module can timely pause the coding and decoding process of corresponding information and return a status code;
the verification module performs verification on the result obtained by each calculation stage in the LDPC encoding and decoding pipeline, and transmits the verification result to the control module, and the control module determines whether to perform LDPC encoding and decoding calculation of the next stage; if the verification is correct, transmitting the calculation result to a storage module for storage, and if the verification is correct, returning an error code to the RISC-V processor;
the storage module is used for storing the coding result obtained in each stage and the check matrix used in the current processing stage and waiting for the access of the next stage; the storage module releases the result stored in the previous stage after receiving the signal of the verification module for verifying the previous calculation stage; the final stored content of the module is the final coded and decoded result with the number, and meanwhile, the RISC-V processor waits for sending a result return instruction.
4. The LDPC codec computing system based on RISC-V architecture as claimed in claim 2, wherein the instruction unit comprises an instruction receiving unit, an instruction parsing unit, a number generating unit, a status returning unit, a result returning unit, specifically comprising:
the instruction receiving unit is used for receiving custom instruction data from the RISC-V processor;
the instruction analysis unit is used for receiving the instruction from the instruction receiving unit, analyzing the instruction, converting the received instruction into enabling signals of each unit module, and sending the instruction information to the corresponding unit;
the number generating unit carries out number processing on the information to be LDPC coded or decoded, enables the information to carry corresponding numbers when the information is reported wrong or returned, and transmits the numbered information to a subsequent module for processing, so that the subsequent information can be conveniently called;
the state returning unit returns the state code to the RISC-V processor according to the state code returned by the control module, so that the RISC-V processor obtains the working state of the LDPC encoding and decoding unit;
and the result return unit searches the corresponding result when the RISC-V processor accesses the related result under the condition that the state codes returned by the control module all represent the normal state, and returns the corresponding result to the RISC-V processor.
5. The LDPC codec computing system according to claim 4 wherein the RISC-V processor custom instruction comprises:
(1) A reset instruction: the REET is used for resetting the whole computing system, and the resetting comprises a resetting instruction unit, an LDPC encoding and decoding computing module, a control module, a storage module and a verification module; the operand reservation description includes:
RD: retaining; r1: retaining; r2: retaining;
(2) Calculation instructions: ACTY for setting input data and calculation modes; the operand reservation description includes:
RD: retaining; r1: inputting a start address of the data;
(3) Calculation instructions: COTE, which is used for numbering information and calculating; the operand reservation description includes:
RD: retaining; r1: numbering information of the data; r2: retaining;
(4) The result returns the instruction: RERN, is used for returning the structure, including returning LDPC encoding and decoding calculation result of the specific number; the operand reservation description includes:
RD: retaining; r1: information number of data to be read; r2: retaining;
(5) A check matrix setting initialization instruction: MAIT, is used for presuming the check matrix that the system uses, including presuming the check matrix row, column number and value of the concrete position that the system uses; the operand reservation description includes:
RD: retaining; r1: the number of the check matrix rows to be input; r2: the number of check matrix columns to be input;
(6) Check matrix setting input instruction: MAIN, which is used to input the check matrix used by the system; the operand reservation description includes:
RD: data; r1: inputting data of an nth row; r2: data of the nth column is input.
6. The LDPC codec computing system according to claim 5, wherein the workflow of the LDPC codec computing system based on RISC-V architecture comprises:
s1, an LDPC encoding and decoding operation is executed by a RISC-V processor;
s2, sending an initialization instruction;
s3, sending a calculation instruction;
s4, sending a result return instruction;
s5, the RISC-V processor executes LDPC encoding and decoding operation.
7. The LDPC codec computing system according to claim 6 wherein the RISC-V processor in step S1 performs LDPC codec operations, comprising:
RISC-V processor needs to execute LDPC coding and decoding calculation work, and starts LDPC coding and decoding calculation coprocessor through custom coprocessor interface.
8. The LDPC codec computing system based on RISC-V architecture according to claim 7, wherein the sending initialization instruction in step S2 specifically includes:
the RISC-V processor sends a reset instruction through a custom coprocessor interface.
9. The LDPC codec computing system based on RISC-V architecture according to claim 8, wherein the sending the computing instruction in step S3 specifically includes:
the RISC-V processor sequentially sends ACTY instructions, and sets input data and calculation modes; and sending a COTE instruction, numbering the information and starting calculation.
10. The LDPC codec computing system based on RISC-V architecture according to claim 9, wherein the sending result return instruction in step S4 specifically includes:
the RISC-V processor sends a result return instruction through a self-defined coprocessor interface; and sending a RERN instruction and reading the operation result of the designated number.
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