CN117782079A - Combined navigation computing system based on RISC-V architecture - Google Patents
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Abstract
The invention discloses an integrated navigation computing system based on RISC-V architecture, which comprises a RISC-V architecture processor and a BDS/INS integrated navigation computing coprocessor; the RISC-V processor is used for executing general calculation and instructions, performing software programming to realize flexible function change, and controlling the combined navigation calculation coprocessor through the custom expansion assembly instructions; the integrated navigation computing coprocessor is used for receiving the self-defined instruction from the RISC-V processor, determining the instruction function according to the instruction decoding, adjusting the information processing mode of the integrated navigation computing unit, obtaining the integrated navigation information, simultaneously carrying out rationality test through the checking unit, and finally returning to the RISC-V processor to wait for the user to call. The invention realizes the integration of the combined navigation computing coprocessor and the RISC-V processor through the custom instruction. The navigation method and the navigation device have the advantages of improving navigation precision and communication efficiency.
Description
Technical Field
The invention belongs to the technical field of integrated circuit technology and navigation control, and particularly relates to a combined navigation computing system based on a RISC-V architecture.
Background
Nowadays, the unmanned technique is more and more paid attention to, and people have higher and higher requirements on the navigation precision and speed of an unmanned system, and in practical navigation application, single use of a Beidou satellite navigation system BDS for navigation can cause some key problems, including temporary loss of satellite signals under partial conditions, easy interference and deception of signals; therefore, people explore the mode of collaborative navigation of the BDS and the INS of the Beidou satellite navigation system, fully demonstrate the feasibility of the BDS and the INS of the inertial navigation system, and simultaneously improve the fault tolerance and the reliability of the system by adopting the combined navigation mode; however, the power consumption and the time delay of the combined navigation mode are relatively high, and certain limitations still exist in practical application.
Meanwhile, an open source instruction set architecture RISC-V based on a reduced instruction set principle attracts a large number of open source workers, a plurality of technological companies in the introduction invest in RISC-V greatly, RISC-V instruction sets develop better and better, and RISC-V processors with fewer transistors consume low power by eliminating unnecessary instructions, so that the RISC-V processors are selected as main processors to deploy coprocessors, and the overall power consumption of the system can be reduced.
If the system design is based on the integrated navigation, a channel needs to be established between the CPU and a special chip supporting the navigation mode to work, and the communication efficiency is greatly reduced.
In summary, the existing computing system combining the Beidou satellite navigation system BDS and the inertial navigation system INS for collaborative navigation has the problems of low communication efficiency, high power consumption and difficult guarantee of collaborative speed.
Disclosure of Invention
The invention aims to provide a combined navigation computing system based on a RISC-V architecture, which has the advantages of improved navigation precision, improved communication efficiency, reduced power consumption and stable cooperative speed.
The combined navigation computing system based on RISC-V architecture provided by the invention comprises: RISC-V architecture processor, BDS/INS combined navigation computation coprocessor; the RISC-V processor is used for executing general calculation and instructions, performing software programming to realize flexible function change, and controlling the BDS/INS combined navigation calculation coprocessor through the custom expansion assembly instructions; the BDS/INS integrated navigation computing coprocessor is used for receiving a self-defined instruction from the RISC-V processor, determining an instruction function according to instruction decoding, adjusting the information processing mode of the integrated navigation computing unit to obtain integrated navigation information, checking the rationality through the checking unit, and finally returning to the RISC-V processor to wait for a user to call;
the BDS/INS combined navigation calculation coprocessor comprises an instruction unit and a BDS/INS combined navigation calculation unit;
the BDS/INS integrated navigation calculation unit comprises a calculation module, a storage module, a control module, a verification module and an information fusion module; each structure module is designed based on a pipeline structure, is responsible for different kinds of calculation, performs data interaction with the storage module in each calculation stage, is controlled by the control module, and performs verification on a calculation result obtained in each stage through the verification module;
the control module performs time sequence control on each flow in the information fusion module, the BDS resolving module and the INS resolving module, and the whole computing system is suspended in time and returns to the state when errors are identified by the verification module or an interrupt instruction is sent by the RISC-V processor to the BDS/INS combined navigation computing coprocessor;
the verification module verifies the result obtained by each calculation stage in the BDS/INS integrated navigation calculation module, transmits the verification result to the control module, and the control module determines whether to continue calculation. If the verification is correct, transmitting the calculation result to a storage module for storage; if the verification is wrong, an error code is returned;
the storage module is used for storing the calculation results obtained in each stage, meanwhile, after the calculation of each stage is finished, the last piece of navigation information stored in the storage module is combined for comparison and evaluation, and when the calculation results of the corresponding stage are reasonably stored in the results, the stored last piece of navigation information is released;
the resolving module comprises a BDS resolving module and an INS resolving module, wherein the BDS resolving module acquires information through a Beidou satellite navigation system, and performs noise reduction and resolving processing on the acquired information to acquire initial information of the BDS; the INS calculation module inputs information acquired by the integrated navigation computing system based on the RISC-V architecture through the inertial navigation system, and performs noise reduction and calculation processing on the acquired information to obtain initial information of the INS; after the verification module verifies that the result is correct, the result is sent to the information fusion module; meanwhile, the information fusion module corrects the resolving module through a final calculation result;
the information fusion module carries out fusion calculation through the navigation information provided by the resolving module, and returns the information to the resolving module after the information fusion module obtains a final result, so that the settlement module can carry out dynamic correction; meanwhile, a user can adjust the information fusion module according to actual conditions, so that the information fusion module is more suitable for navigation scenes;
the instruction unit comprises an instruction receiving unit, an instruction analyzing unit, a state returning unit and a result returning unit;
the instruction receiving unit receives instructions from the RISC-V processor and transmits the instructions to the instruction analyzing unit;
the instruction analysis unit receives the instruction of the instruction unit, performs analysis processing, converts the received instruction into enabling signals of each unit module and sends instruction information to the corresponding unit;
the state returning unit returns the state code returned by the control module in the BDS/INS integrated navigation computing unit to the RISC-V processor, so that the RISC-V processor can obtain the working state of the BDS/INS integrated navigation computing unit;
the result returning unit obtains the calculation result of the BDS/INS integrated navigation calculation unit under the condition that the state codes returned by the control module in the BDS/INS integrated navigation calculation unit are all normal, and searches the corresponding result and returns the result to the RISC-V processor when the RISC-V processor accesses the related result;
the custom instruction of the RISC-V processor specifically comprises:
(1) Global reset instruction: the REET is used for resetting the whole computing system and comprises a resetting instruction unit and a BDS/INS combined navigation computing unit; the operand reservation description includes:
RD: retaining; r1: retaining; r2: retaining;
(2) Calculation instructions: ACTY, is used for sending the order, make BDS/INS combination navigate calculate unit begin to read and calculate the data, including presume the navigation module that input data and data correspond; the operand reservation description includes:
RD: retaining; r1: inputting a starting address of navigation data; r2: inputting a target navigation module;
(3) Adjustment instructions: the CHIN is used for setting the noise reduction mode and carrying out different noise reduction processes on navigation information from the BDS and the INS; the operand reservation description includes:
RD: retaining; r1: inputting a noise reduction mode single-hot code; r2: inputting a target navigation module;
(4) The result returns the instruction: the RERN is used for returning results, including BDS/INS combined navigation calculation results with specific numbers; the operand reservation description includes:
RD: retaining; r1: retaining; r2: retaining;
(5) A local reset instruction: PRET is used for resetting a specific navigation module of the BDS/INS combined navigation computing system; the operand reservation description includes:
RD: retaining; r1: inputting a target navigation module; r2: retaining;
the workflow of the integrated navigation computing system based on RISC-V architecture specifically comprises:
s1, executing BDS/INS combined navigation operation by a RISC-V processor;
s2, sending an initialization instruction;
s3, sending a calculation instruction;
s4, sending a result return instruction;
s5, executing BDS/INS combined navigation operation by the RISC-V processor to finish;
the RISC-V processor in step S1 executes BDS/INS integrated navigation operation, which comprises the following steps:
RISC-V processor needs to execute BDS/INS combined navigation calculation work, and starts BDS/INS combined navigation calculation coprocessor through self-defined coprocessor interface;
the sending an initialization command in step S2 specifically includes:
the RISC-V processor sends a reset instruction through a self-defined coprocessor interface;
the sending a calculation instruction in step S3 specifically includes:
the RISC-V processor sequentially sends ACTY instructions, and sets the initial address of the input navigation data and the target navigation model; a CHIN instruction is sent, and a noise reduction mode of each system is set;
the sending result return instruction in step S4 specifically includes:
the RISC-V processor sends a result return instruction through a self-defined coprocessor interface; and sending RERN instruction, and reading BDS/INS combined navigation calculation operation result of the navigation data.
The combined navigation computing system based on the RISC-V architecture realizes the integration of the BDS/INS combined navigation computing coprocessor and the RISC-V processor through the custom instruction; the BDS/INS combined navigation computing coprocessor has configurability, supports the configuration of the coprocessor through a user-defined instruction, and comprises navigation module types and a noise reduction mode in a configurability way; the system has the advantages of improved navigation precision, improved communication efficiency, reduced power consumption and stable cooperative speed.
Drawings
FIG. 1 is a schematic diagram of functional modules of the system of the present invention.
FIG. 2 is a schematic diagram of a BDS/INS integrated navigation computation unit of the system of the invention.
FIG. 3 is a schematic diagram of an instruction unit module of the system of the present invention.
Detailed Description
FIG. 1 is a schematic diagram of the functional modules of the system of the present invention: the combined navigation computing system based on RISC-V architecture provided by the invention comprises: RISC-V architecture processor, BDS/INS combined navigation computation coprocessor; the RISC-V processor is used for executing general calculation and instructions, performing software programming to realize flexible function change, and controlling the BDS/INS combined navigation calculation coprocessor through the custom expansion assembly instructions; the BDS/INS integrated navigation computing coprocessor is used for receiving a self-defined instruction from the RISC-V processor, determining an instruction function according to instruction decoding, adjusting the information processing mode of the integrated navigation computing unit to obtain integrated navigation information, checking the rationality through the checking unit, and finally returning to the RISC-V processor to wait for a user to call;
the BDS/INS combined navigation calculation coprocessor comprises an instruction unit and a BDS/INS combined navigation calculation unit;
FIG. 2 is a schematic diagram of a BDS/INS integrated navigation computation unit module of the system of the invention:
the BDS/INS integrated navigation calculation unit comprises a calculation module, a storage module, a control module, a verification module and an information fusion module; each structure module is designed based on a pipeline structure, is responsible for different kinds of calculation, performs data interaction with the storage module in each calculation stage, is controlled by the control module, and performs verification on a calculation result obtained in each stage through the verification module;
the control module performs time sequence control on each flow in the information fusion module, the BDS resolving module and the INS resolving module, and the whole computing system is suspended in time and returns to the state when errors are identified by the verification module or an interrupt instruction is sent by the RISC-V processor to the BDS/INS combined navigation computing coprocessor;
the verification module verifies the result obtained by each calculation stage in the BDS/INS integrated navigation calculation module, transmits the verification result to the control module, and the control module determines whether to continue calculation. If the verification is correct, transmitting the calculation result to a storage module for storage; if the verification is wrong, an error code is returned;
the storage module is used for storing the calculation results obtained in each stage, meanwhile, after the calculation of each stage is finished, the last piece of navigation information stored in the storage module is combined for comparison and evaluation, and when the calculation results of the corresponding stage are reasonably stored in the results, the stored last piece of navigation information is released;
the resolving module comprises a BDS resolving module and an INS resolving module, wherein the BDS resolving module acquires information through a Beidou satellite navigation system, and performs noise reduction and resolving processing on the acquired information to acquire initial information of the BDS; the INS calculation module inputs information acquired by the integrated navigation computing system based on the RISC-V architecture through the inertial navigation system, and performs noise reduction and calculation processing on the acquired information to obtain initial information of the INS; after the verification module verifies that the result is correct, the result is sent to the information fusion module; meanwhile, the information fusion module corrects the resolving module through a final calculation result;
the information fusion module carries out fusion calculation through the navigation information provided by the resolving module, and returns the information to the resolving module after the information fusion module obtains a final result, so that the settlement module can carry out dynamic correction; meanwhile, a user can adjust the information fusion module according to actual conditions, so that the information fusion module is more suitable for navigation scenes;
FIG. 3 is a schematic diagram of the instruction unit modules of the system of the present invention:
the instruction unit comprises an instruction receiving unit, an instruction analyzing unit, a state returning unit and a result returning unit;
the instruction receiving unit receives instructions from the RISC-V processor and transmits the instructions to the instruction analyzing unit;
the instruction analysis unit receives the instruction of the instruction unit, performs analysis processing, converts the received instruction into enabling signals of each unit module and sends instruction information to the corresponding unit;
the state returning unit returns the state code returned by the control module in the BDS/INS integrated navigation computing unit to the RISC-V processor, so that the RISC-V processor can obtain the working state of the BDS/INS integrated navigation computing unit;
the result returning unit obtains the calculation result of the BDS/INS integrated navigation calculation unit under the condition that the state codes returned by the control module in the BDS/INS integrated navigation calculation unit are all normal, and searches the corresponding result and returns the result to the RISC-V processor when the RISC-V processor accesses the related result;
the custom instruction of the RISC-V processor specifically comprises:
(1) Global reset instruction: the REET is used for resetting the whole computing system and comprises a resetting instruction unit and a BDS/INS combined navigation computing unit; the operand reservation description includes:
RD: retaining; r1: retaining; r2: retaining;
(2) Calculation instructions: ACTY, is used for sending the order, make BDS/INS combination navigate calculate unit begin to read and calculate the data, including presume the navigation module that input data and data correspond; the operand reservation description includes:
RD: retaining; r1: inputting a starting address of navigation data; r2: inputting a target navigation module;
(3) Adjustment instructions: the CHIN is used for setting the noise reduction mode and carrying out different noise reduction processes on navigation information from the BDS and the INS; the operand reservation description includes:
RD: retaining; r1: inputting a noise reduction mode single-hot code; r2: inputting a target navigation module;
(4) The result returns the instruction: the RERN is used for returning results, including BDS/INS combined navigation calculation results with specific numbers; the operand reservation description includes:
RD: retaining; r1: retaining; r2: retaining;
(5) A local reset instruction: PRET is used for resetting a specific navigation module of the BDS/INS combined navigation computing system; the operand reservation description includes:
RD: retaining; r1: inputting a target navigation module; r2: retaining;
the workflow of the integrated navigation computing system based on RISC-V architecture specifically comprises:
s1, executing BDS/INS combined navigation operation by a RISC-V processor;
s2, sending an initialization instruction;
s3, sending a calculation instruction;
s4, sending a result return instruction;
s5, executing BDS/INS combined navigation operation by the RISC-V processor to finish;
the RISC-V processor in step S1 executes BDS/INS integrated navigation operation, which comprises the following steps:
RISC-V processor needs to execute BDS/INS combined navigation calculation work, and starts BDS/INS combined navigation calculation coprocessor through self-defined coprocessor interface;
the sending an initialization command in step S2 specifically includes:
the RISC-V processor sends a reset instruction through a self-defined coprocessor interface;
the sending a calculation instruction in step S3 specifically includes:
the RISC-V processor sequentially sends ACTY instructions, and sets the initial address of the input navigation data and the target navigation model; a CHIN instruction is sent, and a noise reduction mode of each system is set;
the sending result return instruction in step S4 specifically includes:
the RISC-V processor sends a result return instruction through a self-defined coprocessor interface; and sending RERN instruction, and reading BDS/INS combined navigation calculation operation result of the navigation data.
Claims (10)
1. An integrated navigation computing system based on RISC-V architecture, comprising: RISC-V architecture processor, BDS/INS combined navigation computation coprocessor; the RISC-V processor is used for executing general calculation and instructions, performing software programming to realize flexible function change, and controlling the BDS/INS combined navigation calculation coprocessor through the custom expansion assembly instructions; the BDS/INS combined navigation computing coprocessor is used for receiving the self-defined instruction from the RISC-V processor, determining the instruction function according to instruction decoding, adjusting the information processing mode of the combined navigation computing unit, obtaining the combined navigation information, checking the rationality through the checking unit, and finally returning to the RISC-V processor to wait for the user to call.
2. The integrated navigation computing system based on RISC-V architecture as claimed in claim 1, wherein said BDS/INS integrated navigation computing coprocessor comprises an instruction unit, a BDS/INS integrated navigation computing unit;
the BDS/INS integrated navigation calculation unit comprises a calculation module, a storage module, a control module, a verification module and an information fusion module;
the instruction unit comprises an instruction receiving unit, an instruction analyzing unit, a state returning unit and a result returning unit.
3. The integrated navigation computing system based on RISC-V architecture as claimed in claim 2, wherein said BDS/INS integrated navigation computing coprocessor comprises an instruction unit and a BDS/INS integrated navigation computing unit, and specifically comprises:
the BDS/INS integrated navigation calculation unit comprises a calculation module, a storage module, a control module, a verification module and an information fusion module; each structure module is designed based on a pipeline structure, is responsible for different kinds of calculation, performs data interaction with the storage module in each calculation stage, is controlled by the control module, and performs verification on a calculation result obtained in each stage through the verification module;
the control module performs time sequence control on each flow in the information fusion module, the BDS resolving module and the INS resolving module, and the whole computing system is suspended in time and returns to the state when errors are identified by the verification module or an interrupt instruction is sent by the RISC-V processor to the BDS/INS combined navigation computing coprocessor;
the verification module verifies the result obtained by each calculation stage in the BDS/INS integrated navigation calculation module, transmits the verification result to the control module, and the control module determines whether to continue calculation. If the verification is correct, transmitting the calculation result to a storage module for storage; if the verification is wrong, an error code is returned;
the storage module is used for storing the calculation results obtained in each stage, meanwhile, after the calculation of each stage is finished, the last piece of navigation information stored in the storage module is combined for comparison and evaluation, and when the calculation results of the corresponding stage are reasonably stored in the results, the stored last piece of navigation information is released;
the resolving module comprises a BDS resolving module and an INS resolving module, wherein the BDS resolving module acquires information through a Beidou satellite navigation system, and performs noise reduction and resolving processing on the acquired information to acquire initial information of the BDS; the INS calculation module inputs information acquired by the integrated navigation computing system based on the RISC-V architecture through the inertial navigation system, and performs noise reduction and calculation processing on the acquired information to obtain initial information of the INS; after the verification module verifies that the result is correct, the result is sent to the information fusion module; meanwhile, the information fusion module corrects the resolving module through a final calculation result;
the information fusion module carries out fusion calculation through the navigation information provided by the resolving module, and returns the information to the resolving module after the information fusion module obtains a final result, so that the settlement module can carry out dynamic correction; meanwhile, a user can adjust the information fusion module according to actual conditions, so that the information fusion module is more suitable for navigation scenes.
4. A combined navigation computing system based on RISC-V architecture as claimed in claim 3, wherein said instruction unit comprises an instruction receiving unit, an instruction parsing unit, a status return unit, a result return unit, and specifically comprises:
the instruction receiving unit receives instructions from the RISC-V processor and transmits the instructions to the instruction analyzing unit;
the instruction analysis unit receives the instruction of the instruction unit, performs analysis processing, converts the received instruction into enabling signals of each unit module and sends instruction information to the corresponding unit;
the state returning unit returns the state code returned by the control module in the BDS/INS integrated navigation computing unit to the RISC-V processor, so that the RISC-V processor can obtain the working state of the BDS/INS integrated navigation computing unit;
and the result returning unit acquires the calculation result of the BDS/INS integrated navigation calculation unit under the condition that the state codes returned by the control module in the BDS/INS integrated navigation calculation unit are all normal, and searches the corresponding result and returns the result to the RISC-V processor when the RISC-V processor accesses the related result.
5. The integrated navigation computing system based on RISC-V architecture as claimed in claim 4, wherein the custom instruction of the RISC-V processor specifically comprises:
(1) Global reset instruction: the REET is used for resetting the whole computing system and comprises a resetting instruction unit and a BDS/INS combined navigation computing unit; the operand reservation description includes:
RD: retaining; r1: retaining; r2: retaining;
(2) Calculation instructions: ACTY, is used for sending the order, make BDS/INS combination navigate calculate unit begin to read and calculate the data, including presume the navigation module that input data and data correspond; the operand reservation description includes:
RD: retaining; r1: inputting a starting address of navigation data; r2: inputting a target navigation module;
(3) Adjustment instructions: the CHIN is used for setting the noise reduction mode and carrying out different noise reduction processes on navigation information from the BDS and the INS; the operand reservation description includes:
RD: retaining; r1: inputting a noise reduction mode single-hot code; r2: inputting a target navigation module;
(4) The result returns the instruction: the RERN is used for returning results, including BDS/INS combined navigation calculation results with specific numbers; the operand reservation description includes:
RD: retaining; r1: retaining; r2: retaining;
(5) A local reset instruction: PRET is used for resetting a specific navigation module of the BDS/INS combined navigation computing system; the operand reservation description includes:
RD: retaining; r1: inputting a target navigation module; r2: and (5) reserving.
6. The integrated navigation computing system based on RISC-V architecture as recited in claim 5, wherein the workflow of the integrated navigation computing system based on RISC-V architecture comprises:
s1, executing BDS/INS combined navigation operation by a RISC-V processor;
s2, sending an initialization instruction;
s3, sending a calculation instruction;
s4, sending a result return instruction;
s5, the RISC-V processor executes BDS/INS combined navigation operation.
7. The integrated navigation computing system based on the RISC-V architecture as claimed in claim 6, wherein the RISC-V processor in step S1 performs BDS/INS integrated navigation operations, and specifically comprises:
the RISC-V processor needs to execute BDS/INS combined navigation calculation work, and starts the BDS/INS combined navigation calculation coprocessor through a custom coprocessor interface.
8. The integrated navigation computing system based on RISC-V architecture as claimed in claim 7, wherein the sending initialization command in step S2 specifically includes:
the RISC-V processor sends a reset instruction through a custom coprocessor interface.
9. The integrated navigation computing system based on RISC-V architecture of claim 8, wherein the sending the computing instruction in step S3 specifically includes:
the RISC-V processor sequentially sends ACTY instructions, and sets the initial address of the input navigation data and the target navigation model; and sending a CHIN instruction, and setting the noise reduction mode of each system.
10. The integrated navigation computing system based on RISC-V architecture as claimed in claim 9, wherein the sending result return instruction in step S4 specifically includes:
the RISC-V processor sends a result return instruction through a self-defined coprocessor interface; and sending RERN instruction, and reading BDS/INS combined navigation calculation operation result of the navigation data.
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