CN116840817A - TOF measurement circuit and measurement method based on column sharing TDC - Google Patents

Abstract

The invention discloses a TOF measurement circuit and a TOF measurement method based on column sharing TDC, wherein the TOF measurement circuit comprises a pixel array, a time address detection circuit and a readout circuit; the pixel array detects photons and outputs avalanche signals; the time address detection circuit measures the flight time of photons and encodes the row address of pixels responding to the photons; the reading circuit sequentially reads the flight time data and the address data column by column; the time address detection circuit provided by the invention can furthest avoid the problem of inaccurate measurement results caused by photon event collision while quantifying the photon flight time, and can directly encode the row address, read the photon flight time data and the row address data through the reading circuit without an additional column address encoding and control logic circuit, thereby effectively reducing the circuit complexity and saving the chip area; in addition, the invention has simple structure and is easy to realize large-scale pixel array expansion integration.

Description

TOF measurement circuit and measurement method based on column sharing TDC

Technical Field

The invention relates to the technical field of single photon detection imaging, in particular to a TOF measurement circuit and a TOF measurement method based on column sharing TDC.

Background

A photon flight Time (TOF) detector based on a Single Photon Avalanche Diode (SPAD) obtains the position information of a target by measuring the flight time of an optical signal between the detector and the target, has the advantages of high detection efficiency, large dynamic range, high response speed and the like, and is widely applied to the fields of 3D imaging, face recognition, AR/VR, fluorescence lifetime imaging and the like. TOF detectors typically employ an on-chip time-to-digital converter (TDC) to quantitatively read out the photon time of flight, and the architecture of the TOF measurement circuit can be divided into pixel-by-pixel TDCs and shared TDCs, depending on whether the TDCs are placed inside the pixel.

The configuration of the TDC circuit for each SPAD in a pixel-by-pixel TDC architecture results in a low pixel fill factor, a large array area, and in some weak light detection applications, the TDCs in the array still operate and quantify a large amount of invalid TOF information when the SPAD does not detect photon events. The architecture sharing the TDC places the TDC at the periphery of the pixel array, and the quantity of the TDC can be configured according to the practical application environment, so that the defect of the pixel-by-pixel architecture is overcome to a certain extent. However, since multiple pixels share one or several TDCs, the shared architecture may inevitably suffer from photon event collisions, especially for very close in time signal photons. In addition, for the architecture of sharing the TDC, all pixels need to perform column-row address coding and read out address information together with TOF information to distinguish spatial positions, and most of the shared architecture adopts an event-driven manner to read out, so that the complexity of logic control and data post-processing of the circuit is quite high, which is not beneficial to the expansion of the pixel scale.

Disclosure of Invention

This section is intended to outline some aspects of embodiments of the application and to briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section as well as in the description of the application and in the title of the application, which may not be used to limit the scope of the application.

The present application has been made in view of the above-described problems.

Therefore, the technical problems solved by the application are as follows: photon event collision, complex address coding scheme and complex logic control of readout circuits existing in the existing architecture sharing the TDC.

In a first aspect of an embodiment of the present application, there is provided a column-sharing TDC-based TOF measurement circuit including an n×m pixel array, a time address detection circuit, and a readout circuit;

the n multiplied by m pixel array is composed of m columns of pixels, each column of pixels corresponds to the time address detection circuit and the readout circuit, the input end VHH of the pixel column is externally connected with bias voltage, and the output ends P1-Pn of the pixel column are correspondingly connected with the input ends L1-Ln of the time address detection circuit;

the input end Start of the time address detection circuit is externally connected with an initial signal, the time information output ends TOF [1] to TOF [ k ] of the time address detection circuit are correspondingly connected with the input ends B [1] to B [ k ] of the readout circuit, and the address information output ends AD [1] to AD [ k ] of the time address detection circuit are correspondingly connected with the input ends C [1] to C [ k ] of the readout circuit;

The input end sel of the reading circuit is externally connected with a segment selection signal, the input end IN of the reading circuit is connected with the output end OUT of the reading circuit of the previous column, the input end IN of the reading circuit of the first column is grounded, and the output end OUT of the reading circuit of the last column is a data output port.

As a preferable scheme of the TOF measurement circuit based on column sharing TDC according to the present invention, wherein: the j-th column pixel of the n multiplied by m pixel array comprises n pixels P <1, j > -P < n, j >, wherein the pixels consist of single photon avalanche diodes and analog front-end circuits;

cathodes of the single photon avalanche diodes in all pixels are connected with an input end VHH of the pixel column, and anodes of the single photon avalanche diodes are connected with an input end of the analog front end circuit;

the output end of the analog front-end circuit is correspondingly connected with the output ends P1-P n of the pixel columns, and the analog front-end circuit can conduct avalanche quenching on the single photon avalanche diode which senses photons and generate avalanche signals with narrow pulse width to be sent into the time address detection circuit for subsequent processing.

As a preferable scheme of the TOF measurement circuit based on column sharing TDC according to the present invention, wherein: the time address detection circuit consists of an anti-collision address coding circuit, a time sequence generation logic and GRO_TDC <1> to GRO_TDC < k >;

The input ends I1-In of the anti-collision address coding circuit are correspondingly connected with the input ends L1-Ln of the time address detection circuit, the output end Stop of the anti-collision address coding circuit is connected with the input end A of the time sequence generation logic, and the output ends H1-Hk of the anti-collision address coding circuit are connected with the address information output ends AD 1-AD k of the time address detection circuit;

the input end B of the time sequence generating logic is connected with the input end Start of the time address detection circuit, and EN 1-ENk of the time sequence generating logic are correspondingly connected with the input ends in of GRO_TDC <1> -GRO_TDC < k >;

the output end out of the GRO_TDC <1> -GRO_TDC < k > is correspondingly connected with the time information output end TOF [1] -TOF [ k ] of the time address detection circuit, and the GRO_TDC quantifies the time interval between the rising edges of the Start and Stop signals through a counting clock generated by internal ring vibration, wherein the time interval is photon flight time.

As a preferable scheme of the TOF measurement circuit based on column sharing TDC according to the present invention, wherein: the anti-collision address coding circuit consists of a step-by-step cascade structure formed by a judging circuit, a data selector MUX (multiple input multiple output) or a logic gate and address storage and reading logic;

The cascade structure comprises x stages, wherein the 1 st stage comprises 1 judging circuit, the 2 nd stage comprises 2 judging circuits and 1 alternative data selector MUX, the 3 rd stage comprises 4 judging circuits and 2 alternative data selector MUX, and the like, and the x th stage comprises n/2 judging circuits and n/4 alternative data selector MUX, wherein n represents the number of pixels;

in the 1 st to the x-1 st stages, the input ends I1 and I2 of each stage of judging circuit are connected with the output ends Q of two adjacent judging circuits of the subsequent stage, and the input ends of the judging circuits In the x-th stage are connected with the input ends I1 to In of the anti-collision address coding circuitThe output end Q of the 1 st stage judging circuit is connected with the output end Stop of the anti-collision address coding circuit, the input ends 0 and 1 of the one-for-two data selector MUX of each stage are correspondingly connected with the address zone bit output ends A of the two adjacent judging circuits of the stage, and the output end A of the 1 st stage judging circuit outputs the address zone bit A ₁ The output end of the 2 nd-level alternative data selector MUX outputs the address flag bit A ₂ In the 3 rd to the x rd stages, the output end of the one-out-of-two data selector MUX of each stage is connected with the input end of the OR gate on the stage, and the address flag bit A is output through the OR gate ₃ ～A _x In the 2 nd to the x th stages, the selection input end S of the one-out-of-two data selector MUX of each stage is controlled by the address flag bit output by the previous stage;

address flag bit A ₁ ～A _x The address storage and reading logic is input in parallel, the output ends M1-Mk of the address storage and reading logic are correspondingly connected with the output ends H1-Hk of the anti-collision address coding circuit, and the address storage and reading logic outputs the row address information of the response photon pixel in series.

As a preferable scheme of the TOF measurement circuit based on column sharing TDC according to the present invention, wherein: the judging circuit comprises a first D trigger, a second D trigger, a first OR gate, a second OR gate, a third OR gate, a fourth OR gate, a delay circuit with double-end input and double-end output and an RS trigger;

the input ends I1 and I2 of the judging circuit are respectively connected with the input ends CK of the first D trigger and the second D trigger, the other input ends D of the first D trigger and the second D trigger are simultaneously connected with the high level VDD, the output end Q of the first D trigger is simultaneously connected with the input end A of the second OR gate, the input end B of the fourth OR gate, the input end S of the RS trigger and the first input end of the delay circuit, the output end Q of the second D trigger is simultaneously connected with the input end B of the first OR gate, the input end A of the fourth OR gate, the input end R of the RS trigger and the second input end of the delay circuit, the two output ends of the delay circuit are respectively connected with the two input ends A and B of the third OR gate, the output end Q of the third OR gate is simultaneously connected with the input end A of the first OR gate and the input end B of the second OR gate, the output end Q of the first OR gate and the output end Y of the second OR gate are respectively connected with the output end Y of the output end of the second OR gate and the output end Q of the delay circuit is connected with the output end Q of the output end of the trigger of the high level judging circuit.

As a preferable scheme of the TOF measurement circuit based on column sharing TDC according to the present invention, wherein: the judging circuit is used for judging whether two input signals I1 and I2 collide in a time window t, the duration of the time window t is determined by the delay circuit, if the two input signals I1 and I2 collide, only the signal which arrives first is judged to be effective, otherwise, the signals are judged to be effective;

the judging circuit outputs an effective signal I1 or I2 and simultaneously outputs an address zone bit of the signal, wherein the address zone bit of the effective signal I1 is 1, and the address zone bit of the effective signal I2 is 0.

As a preferable scheme of the TOF measurement circuit based on column sharing TDC according to the present invention, wherein: the time sequence generating logic consists of a timing unit <1>, a timing unit < k >, a D trigger and a two-input AND gate;

the input end I1 of the timing unit <1> is connected with a high level VDD, the output end O of the timing unit <1> is connected with the input end I1 of the timing unit <2>, the output end O of the timing unit <2> is connected with the input end I1 of the timing unit <3>, and so on, the timing units <1> -k > form a chain structure, the output end O of the timing unit < k > is grounded, the output ends EN of the timing units <1> -k > are sequentially connected with the output ends EN [1] to EN [ k ] of the timing generation logic, the input end B of the timing generation logic is simultaneously connected with the input end I2 of the timing units <1> -k > and the clock input end CK of the D trigger, and the input end A of the timing generation logic is simultaneously connected with the input ends I3 of the timing units <1> -k >;

The input end D of the D trigger is connected with a high level VDD, the output end Q of the D trigger is connected with the input end i1 of the two-input AND gate, the input end i2 of the two-input AND gate is connected with the output end EN of the timing unit < k >, and the output end Y of the two-input AND gate is simultaneously connected with the reset ends R of the timing units <1> - < k > and the reset end Rst of the D trigger.

As a preferable scheme of the TOF measurement circuit based on column sharing TDC according to the present invention, wherein: the timing unit consists of a D trigger, a first two-input NOR gate and a second two-input NOR gate;

the input end I1 of the timing unit is connected with the clock input end CK of the D trigger, the input end I2 of the timing unit is connected with the input end D of the D trigger, the input end I3 of the timing unit is connected with the input end A of the second input NOR gate, the reset end R of the timing unit is connected with the reset end Rst of the D trigger, the output end O of the timing unit is simultaneously connected with the output end Q of the D trigger and the input end B of the first two-input NOR gate, and the output end EN of the timing unit is simultaneously connected with the output end Y of the first two-input NOR gate and the input end B of the second two-input NOR gate;

The input end A of the first two-input NOR gate is connected with the output end Y of the second two-input NOR gate.

As a preferable scheme of the TOF measurement circuit based on column sharing TDC according to the present invention, wherein: the reading circuit consists of a data selector and a shift register;

the input ends T1-Tk of the data selector are correspondingly connected with the input ends B1-B k of the readout circuit, the input ends D1-Dk of the data selector are correspondingly connected with the input ends C1-C k of the readout circuit, the input end S of the data selector is connected with the input end sel of the readout circuit, and the output end O of the data selector is connected with the input end I of the shift register;

the input data_in of the shift register is connected to the input IN of the readout circuit and the output data_out of the shift register is connected to the output OUT of the readout circuit.

A second aspect of an embodiment of the present invention provides a TOF measurement method based on column sharing TDC, applied to a TOF measurement circuit according to any embodiment of the present invention, wherein the TOF measurement method includes a TOF measurement stage and a readout stage;

the TOF measurement stage comprises that a laser emits laser under the control of a Start signal Start of a j-th row of pixels, and meanwhile, the output ends EN 1-ENk of the time sequence generation logic are converted into high-level driving GRO_TDC <1> -GRO_TDC < k > to Start timing;

When the j-th row of pixels detects the first echo Photon, the operation of the time address detection circuit is carried out simultaneously in two steps, wherein the first step is that the anti-collision address coding circuit judges a single Photon avalanche diode responding to the echo Photon according to the output of an analog front-end circuit in the pixel and stores row address data AD [1] of the single Photon avalanche diode, and the second step is that the anti-collision address coding circuit generates a Stop signal to pull down the output end EN1 of the time sequence generation logic, stops the timing of GRO_TDC1 > and latches flight time data TOF [1] of the echo Photon;

when the j-th row of pixels detects the second echo Photon, the anti-collision address coding circuit judges whether the second echo Photon collides with the first echo Photon in a time window t, if so, the second echo Photon is ignored, if not, the operation of the time address detection circuit is repeated, in the next echo Photon detection, the anti-collision address coding circuit continuously judges whether the echo Photon collides with the previous echo Photon in the time window t, if not, the operation of the time address detection circuit is repeated until the GRO_TDC is completely responded, and the echo Photon detected by the j-th row of pixels after the GRO_TDC is ignored;

The reading stage comprises that the time-of-flight data and address data of each column are sequentially transmitted to the shift register through the data selector to be serially output to LVDS according to the sequence of TOF [1], AD [1], TOF [2], AD [2] … TOF [ k ] and AD [ k ] under the drive of an external control signal S, the time-of-flight data is transmitted when the external control signal S is in a high level, the address data is transmitted when the external control signal S is in a low level, and the high level and the low level duration of the external control signal S are respectively determined by the bit numbers of the time-of-flight data and the address data.

The invention has the beneficial effects that:

(1) according to the TOF measurement circuit provided by the invention, a TDC column sharing mode is adopted, so that on one hand, the TDC circuit is arranged at the periphery of the pixel array, the pixel filling factor can be improved, and on the other hand, the number of TDCs shared by each column of pixels can be configured according to the actual application scene and the size of the pixel array, the photon detection efficiency can be effectively improved, and the unnecessary waste of chip area and power consumption is reduced;

(2) the anti-collision address coding circuit provided by the invention can prevent avalanche signal loss caused by photon event collision to the greatest extent on one hand, and can directly code row addresses through the two-in-one data selector on the other hand, and the coding scheme is very simple and reliable;

(3) The readout circuit provided by the invention can realize that the row address information and the TOF information are simultaneously sent out through the data selector and the shift register without an additional control logic circuit, and a column address coding is not needed by adopting a column-by-column readout method, so that the circuit complexity is further reduced, and the chip area is saved;

(4) the invention has novel structure and simple realization, and compared with the prior art, the invention is easier to realize the ultra-large scale pixel array.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:

fig. 1 is a schematic diagram of the overall structure of a TOF measurement circuit based on a column-sharing TDC according to the present invention;

fig. 2 is a schematic diagram of a single column circuit structure of a TOF measurement circuit based on column sharing TDC according to the present invention;

fig. 3 is a schematic diagram of an anti-collision address coding circuit in a time address conversion circuit of a TOF measurement circuit based on column sharing TDC according to the present invention;

Fig. 4 is a schematic diagram of a judging circuit structure in an anti-collision address coding circuit of a TOF measurement circuit based on column sharing TDC according to the present invention;

FIG. 5 is a schematic diagram of a timing generation logic structure in a time address translation circuit of a TOF measurement circuit based on column sharing TDC according to the present invention;

FIG. 6 is a timing diagram of the TOF measurement circuit and method based on column sharing TDC according to the present invention;

fig. 7 is a schematic diagram of simulation results of a TOF measurement circuit and a measurement method based on column sharing TDC according to the present invention.

Detailed Description

So that the manner in which the above recited objects, features and advantages of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present invention is not limited to the specific embodiments disclosed below.

Further, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic can be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.

While the embodiments of the present invention have been illustrated and described in detail in the drawings, the cross-sectional view of the device structure is not to scale in the general sense for ease of illustration, and the drawings are merely exemplary and should not be construed as limiting the scope of the invention. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

Also in the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper, lower, inner and outer", etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first, second, or third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

The terms "mounted, connected, and coupled" should be construed broadly in this disclosure unless otherwise specifically indicated and defined, such as: can be fixed connection, detachable connection or integral connection; it may also be a mechanical connection, an electrical connection, or a direct connection, or may be indirectly connected through an intermediate medium, or may be a communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.

Example 1

Referring to fig. 1 to 6, an embodiment of the present invention includes:

in a first aspect of the present disclosure, there is provided a column-sharing TDC-based TOF measurement circuit comprising:

as shown in fig. 1, the TOF measurement circuit is composed of an n×m pixel array, a time address detection circuit T <1, 2..m >, a readout circuit R <1, 2..m >, the measurement circuit is divided into m columns of pixels as a whole, and each column of pixels has a corresponding time address detection circuit T < j > (j=1, 2,3 … m) and readout circuit R < j > (j=1, 2,3 … m);

as shown in FIG. 2, the input end VHH of the pixel column is externally connected with bias voltage, and the output ends P1-P n of the pixel column are correspondingly connected with the input ends L1-L n of the time address detection circuit; the input end Start of the time address detection circuit is externally connected with an initial signal, the time information output ends TOF [1] to TOF [ k ] of the time address detection circuit are correspondingly connected with the input ends B [1] to B [ k ] of the readout circuit, and the address information output ends AD [1] to AD [ k ] of the time address detection circuit are correspondingly connected with the input ends C [1] to C [ k ] of the readout circuit; the input terminal sel of the readout circuit is externally connected with a segment selection signal, the input terminal IN of the readout circuit is connected with the output terminal OUT of the readout circuit of the previous column, the input terminal IN of the readout circuit of the first column is grounded, and the output terminal OUT of the readout circuit of the last column is a data output port.

Specifically, each column of the n×m pixel array includes n pixels P <1> to P < n >, and each pixel is composed of a Single Photon Avalanche Diode (SPAD) and an analog front end circuit (AFE);

it should be noted that the cathodes of the Single Photon Avalanche Diodes (SPAD) in all the pixels are connected to the input VHH of the pixel columns, the anodes of the Single Photon Avalanche Diodes (SPAD) being connected to the input of the analog front-end circuit (AFE); the output end of the analog front-end circuit (AFE) is correspondingly connected with the output ends P1-P n of the pixel columns, and the analog front-end circuit (AFE) can conduct avalanche quenching on a Single Photon Avalanche Diode (SPAD) which senses photons and generate avalanche signals with narrow pulse width to be sent to a time address detection circuit for subsequent processing.

Further, the time address detection circuit consists of an anti-collision address coding circuit, a time sequence generation logic and GRO_TDC <1> to GRO_TDC < k >;

it should be noted that, the input terminals I1 to In of the anti-collision address coding circuit are correspondingly connected with the input terminals L1 to ln of the time address detection circuit, the output terminal Stop of the anti-collision address coding circuit is connected with the input terminal a of the time sequence generating logic, and the output terminals H1 to Hk of the anti-collision address coding circuit are connected with the address information output terminals AD 1 to AD k of the time address detection circuit; the input end B of the time sequence generating logic is connected with the input end Start of the time address detection circuit, and EN 1-ENk of the time sequence generating logic are correspondingly connected with the input ends in of GRO_TDC <1> -GRO_TDC < k >; the output end out of GRO_TDC <1> -GRO_TDC < k > is correspondingly connected with the time information output end TOF [1] -TOF [ k ] of the time address detection circuit, and the GRO_TDC quantifies the time interval between the rising edges of the Start and Stop signals through a counting clock generated by internal ring vibration, wherein the time interval is photon flight time;

Specifically, as shown in fig. 3, the anti-collision address coding circuit is composed of a step-by-step cascade structure formed by a judging circuit, a data selector MUX or a logic gate, and address storage and readout logic;

it should be noted that, the cascade structure includes x stages, in which the 1 st stage includes 1 judgment circuit (judgment circuit <1_1 >), the 2 nd stage includes 2 judgment circuits (judgment circuit <2_1> and judgment circuit <2_1 >) and 1 alternative data selector (MUX <2_1 >), the 3 rd stage includes 4 judgment circuits (judgment circuit <3_1>, judgment circuit <3_2>, judgment circuit <3_3> and judgment circuit <3_4 >) and 2 alternative data selectors (MUX <3_1> and MUX <3_2 >), and so on, the x-th stage includes n/2 judgment circuits (judgment circuit < x_1 >), judgment circuit < x_2> … judgment circuit < x_n/2 >) and n/4 alternative data selectors (MUX < x_1 >), MUX < x_2> … MUX < x_n/4 >), where n represents the number of pixels;

in the 1 st to x-1 st stages, the input ends I1 and I2 of each stage of judging circuit are connected with the output ends Q of two adjacent judging circuits of the next stage, the input ends of the judging circuits In the x-th stage are sequentially connected with the input ends I1 to In of the anti-collision address coding circuit, the output ends Q of the 1 st stage of judging circuits are connected with the output end Stop of the anti-collision address coding circuit, the input ends 0 and 1 of the alternative data selector MUX of each stage are correspondingly connected with the address zone bit output ends A of the two adjacent judging circuits of the stage, and the output end A of the 1 st stage of judging circuit outputs the address zone bit A ₁ The output end of the 2 nd-level alternative data selector MUX outputs the address flag bit A ₂ In the 3 rd to the x rd stages, the output of the one-out-of-two data selector MUX of each stageThe ends are connected with the input end of the OR logic gate on the stage, and the address flag bit A is output through the OR logic gate ₃ ～A _x In the 2 nd to the x th stages, the selection input end S of the one-out-of-two data selector MUX of each stage is controlled by the address flag bit output by the previous stage; address flag bit A ₁ ～A _x The parallel input is connected to address storage and readout logic, the output terminals M1-MK of the address storage and readout logic are correspondingly connected with the output terminals H1-Hk of the anti-collision address coding circuit, and the address storage and readout logic responds to the row address information (A of the photon picture elements ₁ ,A ₂ ,…A _x ) Serial output.

Specifically, as shown in fig. 4, the judging circuit includes a first D flip-flop (dff_1), a second D flip-flop (dff_2), a first OR gate (or_1), a second OR gate (or_2), a third OR gate (or_3), a fourth OR gate (or_4), a Delay circuit (Delay) with double-ended input and double-ended output, and an RS flip-flop (Latch);

it should be noted that the input terminals I1 and I2 of the judgment circuit are connected to the input terminals CK of the first D flip-flop (dff_1) and the second D flip-flop (dff_2), respectively, the other input terminal D of the first D flip-flop (dff_1) and the second D flip-flop (dff_2) are simultaneously connected to the high level VDD, the output terminal Q of the first D flip-flop (dff_1) is simultaneously connected to the input terminal a of the second OR gate (or_2), the input terminal S of the input B, RS flip-flop (Latch) of the fourth OR gate (or_4) and the first input terminal of the Delay circuit (Delay), the output terminal Q of the second D flip-flop (dff_2) is simultaneously connected to the input terminal B of the first OR gate (or_1), the input terminal R of the fourth OR gate (or_2) and the second input terminal of the Delay circuit (Delay), respectively, the two output terminals Q of the Delay circuit (Delay) are simultaneously connected to the input terminal S of the third or_2 and the input terminal S of the first OR gate (or_1) and the output terminal q_2 of the second OR gate (or_2) respectively, the output end O of the RS trigger (Latch) is connected with the address zone bit output end A of the judging circuit;

It should be noted that the judging circuit is configured to judge whether the two input signals I1 and I2 collide within a time window t, where the duration of the time window t is determined by a Delay circuit (Delay), and if the two input signals I1 and I2 collide, only the signal that arrives first is judged to be valid, otherwise, both the signals are judged to be valid; the judging circuit outputs an effective signal I1 or I2 and simultaneously outputs an address zone bit of the signal, wherein the address zone bit of the effective signal I1 is 1, and the address zone bit of the effective signal I2 is 0.

Specifically, as shown in FIG. 5, the timing generation logic consists of a timing unit <1> -a timing unit < k >, a D flip-flop (DFF) AND a two-input AND gate (AND);

it should be noted that, the input terminal I1 of the timing unit <1> is connected to the high level VDD, the output terminal O thereof is connected to the input terminal I1 of the timing unit <2>, the output terminal O of the timing unit <2> is connected to the input terminal I1 of the timing unit <3>, and so on, the timing units <1> to < k > form a chain structure, the output terminal O of the timing unit < k > is grounded, the output terminals EN of the timing units <1> to < k > are sequentially connected to the output terminals EN [1] to EN [ k ] of the timing generation logic, the input terminal B of the timing generation logic is simultaneously connected to the input terminal I2 of the timing unit <1> to the timing unit < k > and the clock input terminal CK of the D flip-flop (DFF), and the input terminal a of the timing generation logic is simultaneously connected to the input terminals I3 of the timing units <1> -k >; the input end D of the D trigger (DFF) is connected with the high level VDD, the output end Q of the D trigger is connected with the input end i1 of the two-input AND gate (AND), the input end i2 of the two-input AND gate (AND) is connected with the output end EN of the timing unit < k >, AND the output end Y of the D trigger is simultaneously connected with the reset ends R of the timing units <1> - < k > AND the reset end Rst of the D trigger (DFF).

Specifically, the timing unit consists of a D trigger (DFF), a first two-input NOR gate (NOR_1) and a second two-input NOR gate (NOR_2);

it should be noted that, the input terminal I1 of the timing unit is connected to the clock input terminal CK of the D flip-flop (DFF), the input terminal I2 thereof is connected to the input terminal D of the D flip-flop (DFF), the input terminal I3 thereof is connected to the input terminal a of the second input NOR gate nor_2, the reset terminal R thereof is connected to the reset terminal Rst of the D flip-flop (DFF), the output terminal O thereof is simultaneously connected to the output terminal Q of the D flip-flop (DFF) and the input terminal B of the first two input NOR gate (nor_1), and the output terminal EN thereof is simultaneously connected to the output terminal Y of the first two input NOR gate (nor_1) and the input terminal B of the second two input NOR gate (nor_2); the input a of the first two-input NOR gate (nor_1) is connected to the output Y of the second two-input NOR gate (nor_2).

Still further, the read-out circuit is made up of data selector and shift register;

it should be noted that, the input terminals T1 to Tk of the data selector are correspondingly connected to the input terminals B1 to B k of the readout circuit, the input terminals D1 to Dk of the data selector are correspondingly connected to the input terminals C1 to C k of the readout circuit, the input terminal S of the data selector is connected to the input terminal sel of the readout circuit, and the output terminal O of the data selector is connected to the input terminal I of the shift register; the input data_in of the shift register is connected to the input IN of the readout circuit and the output data_out of the shift register is connected to the output OUT of the readout circuit.

In a second aspect of the disclosure, a TOF measurement method based on column sharing TDC is provided, applied to a TOF measurement circuit according to any embodiment of the disclosure;

specifically, as shown in fig. 6, the TOF measurement method includes a TOF measurement stage and a readout stage;

it should be noted that the TOF measurement phase includes,

under the control of a Start signal Start, the laser emits laser light, and meanwhile, output ends EN 1-ENk of the time sequence generation logic are converted into high level driving GRO_TDC <1> -GRO_TDC < k >;

when the j-th row of pixels detects the first echo Photon, the operation of the time address detection circuit is carried out simultaneously in two steps, wherein the first step is that the anti-collision address coding circuit judges a Single Photon Avalanche Diode (SPAD) responding to the echo Photon according to the output of an analog front end circuit (AFE) in the pixel and stores row address data AD [1] of the Single Photon Avalanche Diode (SPAD), and the second step is that the anti-collision address coding circuit generates an output end EN1 of a Stop signal pull-down time sequence generation logic, stops the timing of GRO_TDC <1> and latches flight time data TOF [1] of the echo Photon;

when the j-th row of pixels detect the second echo Photon, the anti-collision address coding circuit judges whether the second echo Photon collides with the first echo Photon in the time window t, if so, the second echo Photon is ignored, if not, the operation of the time address detection circuit is repeated, in the next echo Photon detection, the anti-collision address coding circuit continuously judges whether the echo Photon collides with the previous echo Photon in the time window t, if not, the operation of the time address detection circuit is repeated until the GRO_TDC is fully responded, and the echo Photon detected after the j-th row of pixels is fully responded is ignored;

It should be noted that the read-out phase comprises,

the method is characterized in that the method is carried out from the 1 st column to the next column, the flight time data and the address data of each column are sequentially transmitted to a shift register through a data selector to be serially output to LVDS according to the sequence of TOF [1], AD [1], TOF [2], AD [2] … TOF [ k ] and AD [ k ] under the drive of an external control signal S, the flight time data is transmitted when the external control signal S is in a high level, the address data is transmitted when the external control signal S is in a low level, and the high level and the low level duration of the external control signal S are respectively determined by the flight time data and the bit number of the address data.

The TOF measuring circuit provided by the invention adopts a TDC column sharing mode, on one hand, the TDC circuit is arranged at the periphery of the pixel array, so that the pixel filling factor can be improved, and on the other hand, the number of TDCs shared by each column of pixels can be configured according to the actual application scene and the size of the pixel array, so that the photon detection efficiency can be effectively improved, and the unnecessary waste of chip area and power consumption can be reduced; (2) the anti-collision address coding circuit provided by the invention can prevent avalanche signal loss caused by photon event collision to the greatest extent on one hand, and can directly code row addresses through the two-in-one data selector on the other hand, and the coding scheme is very simple and reliable; (3) the readout circuit provided by the invention can realize that the row address information and the TOF information are simultaneously sent out through the data selector and the shift register without an additional control logic circuit, and a column address coding is not needed by adopting a column-by-column readout method, so that the circuit complexity is further reduced, and the chip area is saved; (4) the invention has novel structure and simple realization, and compared with the prior art, the invention is easier to realize the ultra-large scale pixel array.

Example 2

Referring to fig. 7, a second embodiment of the present invention is different from the first embodiment in that a verification test of a TOF measurement circuit and a measurement method based on a column sharing TDC is provided, and a technical solution adopted in the method is verified and described.

In the embodiment, a TOF measurement circuit is simulated based on a standard 0.18 mu m CMOS process, and simulation parameters are specifically as follows: taking a row of four pixels sharing two GRO_TDCs as an example, four photon analog signals are sequentially arranged at positions 22.6ns, 24.6ns, 50.6ns and 71ns from the rising edge of a Start signal and are respectively sent to SPAD2, SPAD1, SPAD0 and SPAD3, a time window generated by a delay circuit is set to be 5ns, and a counting clock period generated by internal ring vibration of the GRO_TDC is set to be 1ns.

The simulation results are shown in fig. 7: in the figure, the abscissa represents the simulation time, and the ordinate represents the voltage value of the output terminal.

As can be seen from fig. 7, after the rising edge of the Start signal arrives, the output terminals EN1 and EN2 of the timing generation logic become high level, at this time, the two gro_tdcs Start to count, and when the SPAD2 detects the first photon, the output terminal EN1 of the timing generation logic becomes low level, and the gro_tdc1 stops to count to obtain the time of flight data TOF [1] and the address data AD [1] corresponding thereto; when the SPAD1 detects the second photon, the anti-collision detection circuit recognizes that the anti-collision detection circuit collides with the first photon and ignores the first photon; when SPAD0 detects the third photon, the output EN2 of the timing generation logic goes low, and gro_tdc2 stops timing to obtain the time-of-flight data TOF 2 and the address data AD2 corresponding thereto. Gro_tdc is full at this point and is directly ignored when SPAD3 detects the fourth photon. In the readout phase, TOF [1], AD [1], TOF [2], AD [2] are sequentially read out.

Therefore, the simulation shows that the time address detection circuit provided by the invention can furthest avoid the problem of inaccurate measurement results caused by photon event collision while quantifying the photon flight time, and can directly encode the row address, read the photon flight time data and the row address data through the reading circuit without an additional column address encoding and control logic circuit, thereby effectively reducing the circuit complexity and saving the chip area.

It should be noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present invention may be modified or substituted without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered in the scope of the claims of the present invention.

Claims (10)

1. The TOF measurement circuit based on column sharing TDC is characterized by comprising an n multiplied by m pixel array, a time address detection circuit and a readout circuit;

the n multiplied by m pixel array is composed of m columns of pixels, each column of pixels corresponds to the time address detection circuit and the readout circuit, the input end VHH of the pixel column is externally connected with bias voltage, and the output ends P1-Pn of the pixel column are correspondingly connected with the input ends L1-Ln of the time address detection circuit;

The input end Start of the time address detection circuit is externally connected with an initial signal, the time information output ends TOF [1] to TOF [ k ] of the time address detection circuit are correspondingly connected with the input ends B [1] to B [ k ] of the readout circuit, and the address information output ends AD [1] to AD [ k ] of the time address detection circuit are correspondingly connected with the input ends C [1] to C [ k ] of the readout circuit;

the input end sel of the reading circuit is externally connected with a segment selection signal, the input end IN of the reading circuit is connected with the output end OUT of the reading circuit of the previous column, the input end IN of the reading circuit of the first column is grounded, and the output end OUT of the reading circuit of the last column is a data output port.

2. The column-sharing TDC-based TOF measurement circuit of claim 1, wherein: the j-th column pixel of the n multiplied by m pixel array comprises n pixels P <1, j > -P < n, j >, wherein the pixels consist of single photon avalanche diodes and analog front-end circuits;

cathodes of the single photon avalanche diodes in all pixels are connected with an input end VHH of the pixel column, and anodes of the single photon avalanche diodes are connected with an input end of the analog front end circuit;

the output end of the analog front-end circuit is correspondingly connected with the output ends P1-P n of the pixel columns, and the analog front-end circuit can conduct avalanche quenching on the single photon avalanche diode which senses photons and generate avalanche signals with narrow pulse width to be sent into the time address detection circuit for subsequent processing.

3. The column-sharing TDC-based TOF measurement circuit of claim 1, wherein: the time address detection circuit consists of an anti-collision address coding circuit, a time sequence generation logic and GRO_TDC <1> to GRO_TDC < k >;

the input ends I1-In of the anti-collision address coding circuit are correspondingly connected with the input ends L1-Ln of the time address detection circuit, the output end Stop of the anti-collision address coding circuit is connected with the input end A of the time sequence generation logic, and the output ends H1-Hk of the anti-collision address coding circuit are connected with the address information output ends AD 1-AD k of the time address detection circuit;

the input end B of the time sequence generating logic is connected with the input end Start of the time address detection circuit, and EN 1-ENk of the time sequence generating logic are correspondingly connected with the input ends in of GRO_TDC <1> -GRO_TDC < k >;

the output end out of the GRO_TDC <1> -GRO_TDC < k > is correspondingly connected with the time information output end TOF [1] -TOF [ k ] of the time address detection circuit, and the GRO_TDC quantifies the time interval between the rising edges of the Start and Stop signals through a counting clock generated by internal ring vibration, wherein the time interval is photon flight time.

4. The column-sharing TDC-based TOF measurement circuit according to claim 3, wherein: the anti-collision address coding circuit consists of a step-by-step cascade structure formed by a judging circuit, a data selector MUX (multiple input multiple output) or a logic gate and address storage and reading logic;

the cascade structure comprises x stages, wherein the 1 st stage comprises 1 judging circuit, the 2 nd stage comprises 2 judging circuits and 1 alternative data selector MUX, the 3 rd stage comprises 4 judging circuits and 2 alternative data selector MUX, and the like, and the x th stage comprises n/2 judging circuits and n/4 alternative data selector MUX, wherein n represents the number of pixels;

in the 1 st to x-1 st stages, the input ends I1 and I2 of each stage of judging circuit are connected with the output ends Q of two adjacent judging circuits of the next stage, the input ends of the judging circuits In the x-th stage are sequentially connected with the input ends I1 to In of the anti-collision address coding circuit, the output ends Q of the 1 st stage of judging circuits are connected with the output end Stop of the anti-collision address coding circuit, the input ends 0 and 1 of the one-for-two data selector MUX of each stage are correspondingly connected with the address mark bit output ends A of the two adjacent judging circuits of the stage, and the output end A of the 1 st stage of judging circuit outputs the address mark bit A ₁ The output end of the 2 nd-level alternative data selector MUX outputs the address flag bit A ₂ In the 3 rd to the x rd stages, the output end of the one-out-of-two data selector MUX of each stage is connected with the input end of the OR gate on the stage, and the address flag bit A is output through the OR gate ₃ ～A _x In the 2 nd to the x th stages, the selection input end S of the one-out-of-two data selector MUX of each stage is controlled by the address flag bit output by the previous stage;

address flag bit A ₁ ～A _x The address storage and reading logic is input in parallel, the output ends M1-Mk of the address storage and reading logic are correspondingly connected with the output ends H1-Hk of the anti-collision address coding circuit, and the address storage and reading logic outputs the row address information of the response photon pixel in series.

5. The column-sharing TDC based TOF measurement circuit according to claim 4, wherein: the judging circuit comprises a first D trigger, a second D trigger, a first OR gate, a second OR gate, a third OR gate, a fourth OR gate, a delay circuit with double-end input and double-end output and an RS trigger;

the input ends I1 and I2 of the judging circuit are respectively connected with the input ends CK of the first D trigger and the second D trigger, the other input ends D of the first D trigger and the second D trigger are simultaneously connected with the high level VDD, the output end Q of the first D trigger is simultaneously connected with the input end A of the second OR gate, the input end B of the fourth OR gate, the input end S of the RS trigger and the first input end of the delay circuit, the output end Q of the second D trigger is simultaneously connected with the input end B of the first OR gate, the input end A of the fourth OR gate, the input end R of the RS trigger and the second input end of the delay circuit, the two output ends of the delay circuit are respectively connected with the two input ends A and B of the third OR gate, the output end Q of the third OR gate is simultaneously connected with the input end A of the first OR gate and the input end B of the second OR gate, the output end Q of the first OR gate and the output end Y of the second OR gate are respectively connected with the output end Y of the output end of the second OR gate and the output end Q of the delay circuit is connected with the output end Q of the output end of the trigger of the high level judging circuit.

6. The column-sharing TDC based TOF measurement circuit according to claim 5, wherein: the judging circuit is used for judging whether two input signals I1 and I2 collide in a time window t, the duration of the time window t is determined by the delay circuit, if the two input signals I1 and I2 collide, only the signal which arrives first is judged to be effective, otherwise, the signals are judged to be effective;

the judging circuit outputs an effective signal I1 or I2 and simultaneously outputs an address zone bit of the signal, wherein the address zone bit of the effective signal I1 is 1, and the address zone bit of the effective signal I2 is 0.

7. The column-sharing TDC-based TOF measurement circuit according to claim 3, wherein: the time sequence generating logic consists of a timing unit <1>, a timing unit < k >, a D trigger and a two-input AND gate;

the input end I1 of the timing unit <1> is connected with a high level VDD, the output end O of the timing unit <1> is connected with the input end I1 of the timing unit <2>, the output end O of the timing unit <2> is connected with the input end I1 of the timing unit <3>, and so on, the timing units <1> -k > form a chain structure, the output end O of the timing unit < k > is grounded, the output ends EN of the timing units <1> -k > are sequentially connected with the output ends EN [1] to EN [ k ] of the timing generation logic, the input end B of the timing generation logic is simultaneously connected with the input end I2 of the timing units <1> -k > and the clock input end CK of the D trigger, and the input end A of the timing generation logic is simultaneously connected with the input ends I3 of the timing units <1> -k >;

The input end D of the D trigger is connected with a high level VDD, the output end Q of the D trigger is connected with the input end i1 of the two-input AND gate, the input end i2 of the two-input AND gate is connected with the output end EN of the timing unit < k >, and the output end Y of the two-input AND gate is simultaneously connected with the reset ends R of the timing units <1> - < k > and the reset end Rst of the D trigger.

8. The column-sharing TDC based TOF measurement circuit of claim 7, wherein: the timing unit consists of a D trigger, a first two-input NOR gate and a second two-input NOR gate;

the input end I1 of the timing unit is connected with the clock input end CK of the D trigger, the input end I2 of the timing unit is connected with the input end D of the D trigger, the input end I3 of the timing unit is connected with the input end A of the second input NOR gate, the reset end R of the timing unit is connected with the reset end Rst of the D trigger, the output end O of the timing unit is simultaneously connected with the output end Q of the D trigger and the input end B of the first two-input NOR gate, and the output end EN of the timing unit is simultaneously connected with the output end Y of the first two-input NOR gate and the input end B of the second two-input NOR gate;

The input end A of the first two-input NOR gate is connected with the output end Y of the second two-input NOR gate.

9. The column-sharing TDC-based TOF measurement circuit of claim 1, wherein: the reading circuit consists of a data selector and a shift register;

the input ends T1-Tk of the data selector are correspondingly connected with the input ends B1-B k of the readout circuit, the input ends D1-Dk of the data selector are correspondingly connected with the input ends C1-C k of the readout circuit, the input end S of the data selector is connected with the input end sel of the readout circuit, and the output end O of the data selector is connected with the input end I of the shift register;

the input data_in of the shift register is connected to the input IN of the readout circuit and the output data_out of the shift register is connected to the output OUT of the readout circuit.

10. A TOF measurement method based on column sharing TDC, which is applied to a TOF measurement circuit as claimed in any one of claims 1 to 9, and is characterized in that the TOF measurement method comprises a TOF measurement stage and a readout stage;

the TOF measurement stage comprises that a laser emits laser under the control of a Start signal Start of a j-th row of pixels, and meanwhile, the output ends EN 1-ENk of the time sequence generation logic are converted into high-level driving GRO_TDC <1> -GRO_TDC < k > to Start timing;

When the j-th row of pixels detects the first echo Photon, the operation of the time address detection circuit is carried out simultaneously in two steps, wherein the first step is that the anti-collision address coding circuit judges a single Photon avalanche diode responding to the echo Photon according to the output of an analog front-end circuit in the pixel and stores row address data AD [1] of the single Photon avalanche diode, and the second step is that the anti-collision address coding circuit generates a Stop signal to pull down the output end EN1 of the time sequence generation logic, stops the timing of GRO_TDC1 > and latches flight time data TOF [1] of the echo Photon;

when the j-th row of pixels detects the second echo Photon, the anti-collision address coding circuit judges whether the second echo Photon collides with the first echo Photon in a time window t, if so, the second echo Photon is ignored, if not, the operation of the time address detection circuit is repeated, in the next echo Photon detection, the anti-collision address coding circuit continuously judges whether the echo Photon collides with the previous echo Photon in the time window t, if not, the operation of the time address detection circuit is repeated until the GRO_TDC is completely responded, and the echo Photon detected by the j-th row of pixels after the GRO_TDC is ignored;

The reading stage comprises that the time-of-flight data and address data of each column are sequentially transmitted to the shift register through the data selector to be serially output to LVDS according to the sequence of TOF [1], AD [1], TOF [2], AD [2] … TOF [ k ] and AD [ k ] under the drive of an external control signal S, the time-of-flight data is transmitted when the external control signal S is in a high level, the address data is transmitted when the external control signal S is in a low level, and the high level and the low level duration of the external control signal S are respectively determined by the bit numbers of the time-of-flight data and the address data.