CN116830183A - Display device and display correction system - Google Patents

Abstract

Provided is a display device which is excellent in the size reduction, the power consumption reduction, and the degree of freedom of the arrangement of an arithmetic device. The display device comprises a pixel circuit, a driving circuit and a functional circuit. The driving circuit has a function of outputting an image signal for display in the pixel circuit. The functional circuit includes a CPU including a CPU core having a flip-flop electrically connected to the backup circuit. The display device includes a first layer and a second layer. The first layer includes a driving circuit and a CPU. The second layer includes pixel circuits and backup circuits. The first layer includes a semiconductor layer including silicon in a channel formation region. The second layer includes a semiconductor layer including a metal oxide in the channel formation region. The CPU has a function of correcting the image signal according to the amount of current flowing through the pixel circuit.

Description

Display device and display correction system

Technical Field

One embodiment of the present invention relates to a display device and a display correction system.

Note that one embodiment of the present invention is not limited to the above-described technical field. Examples of the technical field of one embodiment of the present invention disclosed in the present specification and the like include a semiconductor device, an image pickup device, a display device, a light emitting device, a power storage device, a display system, an electronic device, a lighting device, an input/output device, a driving method thereof, and a manufacturing method thereof.

Note that in this specification and the like, a semiconductor device refers to all devices that can operate by utilizing semiconductor characteristics. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, illumination devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may be referred to as semiconductor devices. Alternatively, they can be said to include semiconductor devices at times.

Background

Further, as electronic devices provided with a display device for augmented Reality (AR: augmented Reality) or Virtual Reality (VR), wearable electronic devices and stationary electronic devices are becoming popular. As wearable electronic devices, there are, for example, head mounted displays (HMD: head Mounted Display), glasses type electronic devices, and the like. As the stationary electronic apparatus, there is, for example, a Head-Up Display (HUD) and the like.

An electronic device having a display unit such as an HMD near a user has the following problems: the user may feel a strong granular feeling by easily seeing the pixels, and may sometimes weaken the immersion and the presence of AR or VR. Therefore, the HMD is preferably provided with a display device having fine pixels so that the pixels are not visible to the user. Patent document 1 discloses a method of realizing an HMD with fine pixels by using a transistor capable of high-speed driving.

[ Prior Art literature ]

[ patent literature ]

[ patent document 1] Japanese patent application laid-open No. 2000-2856

Disclosure of Invention

Technical problem to be solved by the invention

By providing the display device with fine pixels, the pixel density can be increased. Thus, more pixels can be provided in the display device, and a high immersion or a feeling of presence can be obtained. To further obtain immersion or presence, pixel defects (bright or dark spots, etc.) are preferably small.

In order to eliminate the pixel defect, a configuration is effective in which the pixel defect is corrected by an arithmetic device such as a CPU. However, when an arithmetic device such as a CPU and a display device are separately provided, there is a concern that an electronic apparatus including the device may become large. In addition, when an arithmetic process for correcting a pixel defect is performed in an arithmetic device such as a CPU, there is a concern that the function of the display device may be damaged due to heat generation or the like of the arithmetic device. Further, when integrating the operation device with the display device, there is a concern that the degree of freedom of arrangement of the operation device may be reduced depending on the shape of the display device or the like.

An object of one embodiment of the present invention is to provide a display device or a display correction system, etc. having a novel structure. Another object of one embodiment of the present invention is to provide a display device, a display correction system, or the like that can be miniaturized. Another object of one embodiment of the present invention is to provide a display device, a display correction system, or the like capable of reducing power consumption. Another object of one embodiment of the present invention is to provide a display device, a display correction system, or the like, in which the degree of freedom in arrangement of the arithmetic device is improved.

Note that the description of the plurality of purposes does not hinder the existence of each other. One embodiment of the present invention does not necessarily achieve all of the above objects. The objects other than the above are naturally known from the descriptions of the specification, drawings, claims and the like, and these objects can also be the objects of one embodiment of the present invention.

Means for solving the technical problems

One embodiment of the present invention is a display device including a pixel circuit, a driving circuit, and a functional circuit, the driving circuit having a function of outputting a signal for display in the pixel circuit, the functional circuit including a CPU core having a flip-flop electrically connected to a backup circuit, the display device further including a first layer including the driving circuit and the CPU, and a second layer including the pixel circuit and the backup circuit, the first layer and the second layer being provided in different layers.

One embodiment of the present invention is a display device including a pixel circuit, a driving circuit, and a functional circuit, the driving circuit having a function of outputting an image signal for display in the pixel circuit, the functional circuit including a CPU core having a flip-flop electrically connected to a backup circuit, the display device further including a first layer including the driving circuit and the CPU, and a second layer including the pixel circuit and the backup circuit, the first layer and the second layer being provided in different layers, the CPU having a function of correcting the image signal according to an amount of current flowing through the pixel circuit.

One embodiment of the present invention is a display device including a pixel circuit, a driver circuit, and a functional circuit, the driver circuit having a function of outputting an image signal for display in the pixel circuit, the functional circuit including a CPU core having a flip-flop electrically connected to a back-up circuit, the display device further including a first layer including the driver circuit and the CPU, and a second layer including the pixel circuit and the back-up circuit, the first layer including a first transistor having a semiconductor layer including silicon in a channel formation region, the second layer including a second transistor having a semiconductor layer including metal oxide in the channel formation region, the CPU having a function of correcting the image signal according to an amount of current flowing through the pixel circuit.

In the display device according to one embodiment of the present invention, the metal oxide preferably contains In, an element M (M is Al, ga, Y, or Sn), and Zn.

In the display device according to one embodiment of the present invention, the backup circuit preferably has a function of holding data held by the flip-flop in a state where supply of the power supply voltage is stopped when the CPU is not operating.

In the display device according to one embodiment of the present invention, the functional circuit preferably includes an accelerator, and the accelerator is a circuit for performing a product-sum operation.

In the display device according to one embodiment of the present invention, the pixel circuit preferably includes an organic EL device, and the organic EL device is a light-emitting device which is processed by photolithography.

In the display device according to one embodiment of the present invention, the backup circuit preferably includes a first transistor provided in the first layer and a capacitor electrically connected to the first transistor, and the capacitor is preferably provided in the first layer.

One embodiment of the present invention is a display correction system including a pixel circuit, a driving circuit, and a functional circuit, the driving circuit having a function of outputting an image signal for display in the pixel circuit, the functional circuit including a CPU core having a flip-flop electrically connected to a backup circuit, the display correction system further including a first layer including the driving circuit and the CPU, and a second layer including the pixel circuit and the backup circuit, the backup circuit having a function of holding data in the flip-flop by turning off a first transistor including a semiconductor layer including silicon in a channel formation region when the CPU is not in operation, the CPU having a function of correcting the image signal by estimating a defective pixel from an amount of current flowing through the pixel circuit, and correcting an amount of current flowing through the pixel circuit of a pixel adjacent to the defective pixel in the correction.

Note that other modes of the present invention are described in the following description of the embodiments and the drawings.

Effects of the invention

One embodiment of the present invention can provide a display device, a display correction system, or the like having a novel structure. In addition, according to one embodiment of the present invention, a display device, a display correction system, or the like, which can be miniaturized can be provided. Further, according to one embodiment of the present invention, a display device, a display correction system, or the like, which can reduce power consumption can be provided. Further, according to one aspect of the present invention, a display device, a display correction system, or the like, in which the degree of freedom in arrangement of an arithmetic device is improved, can be provided.

Note that the description of these effects does not hinder the existence of other effects. Furthermore, one embodiment of the present invention need not have all of the above effects. Further, it is apparent that effects other than the above-described effects exist in the descriptions of the specification, drawings, claims, and the like, and effects other than the above-described effects can be obtained from the descriptions of the specification, drawings, claims, and the like.

Brief description of the drawings

Fig. 1 is a block diagram showing a structural example of a display device.

Fig. 2 is a block diagram showing a structural example of the display device.

Fig. 3 is a block diagram showing a structural example of the display device.

Fig. 4A and 4B are block diagrams showing a configuration example of the display device.

Fig. 5 is a block diagram showing a structural example of the display device.

Fig. 6 is a block diagram showing a structural example of the display device.

Fig. 7A and 7B are circuit diagrams showing a configuration example of the display device.

Fig. 8A and 8B are circuit diagrams showing a configuration example of the display device.

Fig. 9 is a block diagram showing a structural example of the display device.

Fig. 10A and 10B are circuit diagrams showing a configuration example of the display device.

Fig. 11 is a timing chart showing an example of a driving method of the display device.

Fig. 12A to 12C are circuit diagrams and schematic diagrams showing a structural example of the display device.

Fig. 13 is a block diagram showing a structural example of the display device.

Fig. 14A and 14B are circuit diagrams showing a configuration example of the display device.

Fig. 15A and 15B are circuit diagrams showing a configuration example of the display device.

Fig. 16 is a circuit diagram showing a structural example of the display device.

Fig. 17 is a circuit diagram showing a configuration example of the display device.

Fig. 18 is a circuit diagram showing a configuration example of the display device.

Fig. 19 is a circuit diagram showing a configuration example of the display device.

Fig. 20A and 20B are circuit diagrams showing a configuration example of the display device.

Fig. 21A and 21B are circuit diagrams showing a configuration example of the display device.

Fig. 22A and 22B are circuit diagrams showing a configuration example of the display device.

Fig. 23A and 23B are circuit diagrams showing a configuration example of the display device.

Fig. 24A and 24B are circuit diagrams showing a configuration example of the display device.

Fig. 25A and 25B are circuit diagrams showing a configuration example of the display device.

Fig. 26A and 26B are circuit diagrams showing a configuration example of the display device.

Fig. 27A and 27B are block diagrams showing a configuration example of the display device.

Fig. 28 is a cross-sectional view showing a structural example of the display device.

Fig. 29 is a sectional view showing a structural example of the display device.

Fig. 30A is a block diagram showing a structural example of the display device. Fig. 30B is a sectional view showing a structural example of the display device.

Fig. 31 is a sectional view showing a structural example of the display device.

Fig. 32 is a sectional view showing a structural example of the display device.

Fig. 33 is a sectional view showing a structural example of the display device.

Fig. 34 is a sectional view showing a structural example of the display device.

Fig. 35A is a plan view showing a structural example of the transistor. Fig. 35B and 35C are sectional views showing structural examples of the transistor.

Fig. 36A to 36C are diagrams showing structural examples of the display device.

Fig. 37A to 37C are diagrams showing structural examples of the display device.

Fig. 38A to 38C are diagrams showing structural examples of the display device.

Fig. 39A is a diagram illustrating classification of crystal structures of IGZO. Fig. 39B is a diagram illustrating XRD spectrum of the CAAC-IGZO film. Fig. 39C is a diagram illustrating a nano-beam electron diffraction pattern of the CAAC-IGZO film.

Fig. 40A and 40B are diagrams showing an example of a display IC.

Fig. 41A to 41D are diagrams showing one example of an electronic device.

Fig. 42A and 42B are diagrams showing an example of an electronic device.

Modes for carrying out the invention

Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments may be embodied in a number of different forms, and one of ordinary skill in the art will readily recognize that there could be variations in the form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below.

In the drawings, the size, thickness of layers, or regions are sometimes exaggerated for clarity of illustration. Accordingly, the present invention is not limited to the dimensions in the drawings. In addition, in the drawings, ideal examples are schematically shown, and therefore the present invention is not limited to the shapes, numerical values, and the like shown in the drawings.

In the present specification and the like, unless otherwise specified, the off-state current refers to the drain when the transistor is in the off-state (also referred to as a non-conducting state or an interrupted state)A current. In an n-channel transistor, the off state refers to the voltage V between the gate and the source, unless otherwise specified _gs Below threshold voltage V _th (V in p-channel transistor) _gs Higher than V _th ) Is a state of (2).

In the present specification and the like, metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, which may also be simply referred to as OS), and the like. For example, in the case where a metal oxide is used for an active layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, the OS transistor may be referred to as a transistor including an oxide or an oxide semiconductor.

(embodiment 1)

In this embodiment, a display device and a display correction system according to an embodiment of the present invention will be described.

< structural example of display device >

Fig. 1 is a block diagram schematically showing a configuration example of a display device 10 as a display device according to an embodiment of the present invention. The display device 10 includes the layer 20 and the layer 30, and for example, the layer 30 may be stacked over the layer 20. An interlayer insulator, a conductor for electrically connecting different layers, and the like may be provided between the layers 20 and 30.

The transistor provided in the layer 20 may be, for example, a transistor including silicon in a channel formation region (also referred to as a Si transistor), and may be, for example, a transistor including single crystal silicon in a channel formation region. In particular, when a transistor including single crystal silicon in a channel formation region is used as a transistor provided in the layer 20, on-state current of the transistor can be increased. This is preferable because the circuit included in the layer 20 can be driven at high speed. In addition, since the Si transistor can be formed by micromachining with a channel length of 3nm to 10nm, the display device 10 provided with an accelerator such as a CPU, GPU, or the like, an application processor, or the like can be realized.

The transistors provided in the layer 30 may be, for example, OS transistors. In particular, as the OS transistor, a transistor including an oxide including at least one of indium, an element M (element M is aluminum, gallium, yttrium, or tin), and zinc in a channel formation region is preferably used. Such an OS transistor has a characteristic that an off-state current is extremely low. Therefore, in particular, when an OS transistor is used as a transistor provided in a pixel circuit included in a display portion, analog data written to the pixel circuit can be held for a long period of time, which is preferable.

The layer 20 is provided with a driving circuit 40 and a functional circuit 50. The Si transistor of layer 20 may increase the on-state current of the transistor. Thus enabling the circuits to be driven at high speed.

The layer 30 is provided with a display portion 60 including a plurality of pixels 61. The pixel 61 is provided with pixel circuits 62R, 62G, 62B for controlling light emission of red, green, and blue. The pixel circuits 62R, 62G, 62B are used as sub-pixels of the pixel 61. Since the pixel circuits 62R, 62G, 62B include OS transistors, analog data written to the pixel circuits can be held for a long period of time. Further, the pixels 61 included in the layer 30 are each provided with a backup circuit 82. Note that the backup circuit is sometimes referred to as a memory circuit or a memory circuit.

The driving circuit 40 includes a gate line driving circuit, a source line driving circuit, and the like for driving the pixel circuits 62R, 62G, 62B. As an example, the driving circuit 40 includes a gate line driving circuit and a source line driving circuit for driving the pixels 61 of the display portion 60. By disposing the driving circuit 40 in the layer 20 different from the layer 30 in which the display portion is provided, the occupied area of the display portion in the layer 30 can be increased. In addition, the driving circuit 40 may also include an LVDS (LowVoltage Differential Signaling: low voltage differential signaling) circuit or a D/a (Digital to Analog: analog-to-digital) conversion circuit or the like serving as an interface for receiving data such as image data from outside the display device 10. The Si transistor of layer 20 may increase the on-state current of the transistor. The channel length, channel width, and the like of the Si transistor may be different depending on the operation speed of each circuit.

The functional circuit 50 includes a CPU for arithmetic processing of data. The CPU includes a plurality of CPU cores. A trigger is included within the CPU core. The flip-flop includes a plurality of scan flip-flops. The data (backup data) of the scan flip-flop is input and output between the flip-flop 80 and the backup circuit 82. Fig. 1 shows backup data BD as a data signal held by the backup circuit 82.

For example, a memory including an OS transistor is suitable for the backup circuit 82. Since the OS transistor has the characteristic of extremely small off-state current, the backup circuit formed by the OS transistor has the following advantages: voltage drop can be suppressed according to data to be backed up; little power is consumed in holding data, and the like. The backup circuit 82 including an OS transistor may be provided in the display portion 60 configured with a plurality of pixels 61. Fig. 1 shows a state in which the backup circuit 82 is provided in each pixel 61.

The backup circuit 82 constituted by OS transistors may be provided stacked with the layer 20 including Si transistors. The backup circuits 82 may be arranged in a matrix like the sub-pixels in the pixel 61, or one backup circuit 82 may be provided for a plurality of pixels. That is, the backup circuit 82 may be configured within the layer 30 without being limited by the configuration of the pixels 61. Therefore, the backup circuit 82 can be arranged so as to increase the degree of freedom of the display section/circuit layout without increasing the circuit area, and the storage capacity of the backup circuit 82 required for the arithmetic processing can be increased.

< structural example of Pixel Circuit and backup Circuit >

A configuration example of the arrangement of the backup circuit 82 and the pixel circuits 62R, 62G, 62B as sub-pixels in the display section 60 will be described with reference to fig. 2 to 4.

Fig. 2 shows a structure in which a plurality of pixels 61 are arranged in a matrix in the display unit 60. The pixel 61 includes a backup circuit 82 in addition to the pixel circuits 62R, 62G, 62B. As described above, the backup circuit 82 and the pixel circuits 62R, 62G, and 62B can each be configured by an OS transistor, and thus can be disposed in the same pixel.

Fig. 3 shows a structure in which a plurality of pixels 61 are arranged in a matrix in the display unit 60, and fig. 3 shows unit pixels 61UNI as pixels 61 of 2 rows and 2 columns. The pixel 61 includes pixel circuits 62R, 62G, 62B. The unit pixel 61UNI includes a backup circuit 82 at a position surrounded by four pixels 61. As described above, the backup circuit 82 and the pixel 61 can be configured by OS transistors, and thus can be disposed in the same unit pixel 61UNI.

Fig. 4A shows a structure in which pixels 61PEN to which Pentile arrangement is applied are arranged in a display section. As an example, the pixel 61PEN includes a backup circuit 82 in addition to the pixel circuits 62R, 62G or the pixel circuits 62B, 62G. As described above, the backup circuit 82 and the pixel circuits 62R and 62G or the pixel circuits 62B and 62G can be configured by OS transistors, and thus can be disposed in the same pixel.

Fig. 4B shows a structure in which pixels 61PEN are arranged in a matrix in the display unit 60, and fig. 4B shows unit pixels 61UNI as pixels 61PEN of 2 rows and 2 columns. The pixel 61PEN includes pixel circuits 62R, 62G or pixel circuits 62B, 62G. The unit pixel 61UNI includes a backup circuit 82 at a position surrounded by four pixels 61 PEN. As described above, the backup circuit 82 and the pixel 61PEN can be configured by OS transistors, and thus can be disposed in the same unit pixel 61UNI.

< block diagram of display device >

Next, fig. 5 shows a block diagram for explaining each structure in the display device 10. The display device includes a driving circuit 40, a functional circuit 50, and a display unit 60.

As an example, the driving circuit 40 includes a gate driver 41 and a source driver 42. The gate driver 41 has a function of driving a wiring GL serving as a gate line for outputting signals to the pixel circuits 62R, 62G, 62B. The source driver 42 has a function of driving a wiring SL serving as a source line for outputting signals to the pixel circuits 62R, 62G, 62B. Further, the driving circuit 40 supplies voltages for display by the pixel circuits 62R, 62G, 62B to the pixel circuits 62R, 62G, 62B through a plurality of wirings.

The functional circuit 50 includes a CPU51. The CPU51 includes a CPU core 53. The CPU core 53 includes a flip-flop 80 for temporarily holding data used for the arithmetic processing. The flip-flop 80 includes a plurality of scan flip-flops 81, and each scan flip-flop 81 is electrically connected to a backup circuit 82 provided in the display unit 60.

The display unit 60 includes a plurality of pixels 61 provided with pixel circuits 62R, 62G, 62B and a backup circuit 82. As described in the description of fig. 2 to 4, the backup circuit 82 is not necessarily disposed in the pixel 61 as a repeating unit. The configuration may be freely set according to the shape of the display portion 60, the shape of the pixel circuits 62R, 62G, 62B, and the like.

Fig. 6 is a schematic diagram for explaining the positional relationship between the layer 30 and the light-emitting element 70 provided on the layer 20. Fig. 6 corresponds to an example of a schematic cross-sectional view of the display device 10 shown in fig. 1.

Fig. 6 shows a structure in which the layer 20 includes the driving circuit 40 and functional circuits 50A and 50B as one example of the functional circuit 50. The driving circuit 40 and the functional circuits 50A and 50B include Si transistors. The functional circuits 50A and 50B are functional circuits having different functions.

In fig. 6, the layer 30 includes pixel circuits 62R, 62G, 62B and a backup circuit 82 provided at positions overlapping with the driving circuit 40 and the functional circuits 50A, 50B. Fig. 6 shows a structural example in which each pixel circuit includes a backup circuit.

In fig. 6, the light emitting element 70 includes light emitting elements 70R, 70G, 70B connected to the pixel circuits 62R, 62G, 62B, respectively. For example, the light emitting element 70R, the pixel circuit 62R, the backup circuit 82, and the driving circuit 40 are provided so as to overlap in the region 71.

As shown in fig. 6, the functional circuits 50A and 50B are connected to different backup circuits 82 via wirings 72 and 73. As shown in fig. 6, the pixel circuits 62R, 62G, 62B are connected to the light emitting elements 70R, 70G, 70B, respectively, through wirings 74.

As shown in fig. 6, the backup circuit 82 may be provided in the layer 30 provided with the OS transistor, and thus may be provided stacked on the layer 20 including the Si transistor. The backup circuit 82 may be configured within the layer 30 without being limited by the configuration of the pixels 61. Therefore, the backup circuit 82 can be arranged in such a manner that the degree of freedom of the display section/circuit layout is improved without increasing the circuit area, and the storage capacity of the backup circuit 82 required for the arithmetic processing can be increased. As a result, the functional circuits 50A and 50B can be intermittently operated, and power saving can be achieved.

< structural example of Pixel Circuit >

Fig. 7A and 7B show a structural example of a pixel circuit 62 which can be used as the pixel circuits 62R, 62G, 62B, and a light-emitting element 70 connected to the pixel circuit 62. Fig. 7A is a diagram showing connection of the respective elements, and fig. 7B is a diagram schematically showing the vertical relationship of the driving circuit 40, the pixel circuit 62, and the light emitting element 70.

In this specification and the like, the "element" may be sometimes referred to as a "device". For example, the display element, the light-emitting element, and the liquid crystal element may be referred to as a display device, a light-emitting device, and a liquid crystal device, for example.

The pixel circuit 62 illustrated in fig. 7A and 7B includes a switch SW21, a switch SW22, a transistor M21 and a capacitor C21. Here, the switches SW21 and SW22 may be transistors. Note that the switches SW21 and SW22 may be transistors. The switch SW21, the switch SW22 and the transistor M21 may be formed of OS transistors. Each of the OS transistors of the switch SW21, the switch SW22 and the transistor M21 preferably includes a back gate electrode, and in this case, may have a structure in which the same signal as the gate electrode is supplied to the back gate electrode or a structure in which a signal different from the gate electrode is supplied to the back gate electrode.

The transistor M21 includes a gate electrode electrically connected to the switch SW21, a first electrode electrically connected to the light emitting element 70, and a second electrode electrically connected to the wiring ANO. The wiring ANO is a wiring for supplying a potential for supplying current to the light emitting element 70.

The switch SW21 includes a first terminal electrically connected to the gate electrode of the transistor M21, a second terminal electrically connected to the wiring SL serving as the source line, and has a function of controlling a conductive state or a nonconductive state based on the potential of the wiring GLA serving as the gate line.

The switch SW22 includes a first terminal electrically connected to the wiring V0, a second terminal electrically connected to the light emitting element 70, and has a function of controlling a conductive state or a nonconductive state based on the potential of the wiring GLB serving as a gate line. The wiring V0 is a wiring for supplying a reference potential and a wiring for outputting a current flowing through the pixel circuit 62 to the driving circuit 40 or the functional circuit 50.

The capacitor C21 includes a conductive film electrically connected to the gate electrode of the transistor M21 and a conductive film electrically connected to the second terminal of the switch SW 22.

The light emitting element 70 includes a first electrode electrically connected to the first electrode of the transistor M21 and a second electrode electrically connected to the wiring VCOM. The wiring VCOM is a wiring for supplying a potential for supplying a current to the light-emitting element 70.

Thereby, the intensity of light emitted by the light emitting element 70 can be controlled according to the image signal supplied to the gate electrode of the transistor M21. Further, the amount of current flowing through the light emitting element 70 can be controlled according to the reference potential of the wiring V0 supplied through the switch SW 22. Further, by monitoring the amount of current flowing through the wiring V0 by an external circuit, the amount of current flowing through the light emitting element can be estimated. Thereby, defects and the like of the pixels can be detected.

The light-emitting element described in one embodiment of the present invention is a self-light-emitting display element such as an organic EL element (also referred to as OLED (Organic Light Emitting Diode)). The light-emitting element electrically connected to the pixel circuit may be a self-light-emitting element such as an LED (Light Emitting Diode: light-emitting diode), a micro LED, a QLED (Quantum-dot Light Emitting Diode: quantum dot light-emitting diode), or a semiconductor laser. Alternatively, a liquid crystal element or the like may be used as the display element.

In the structure illustrated in fig. 7B, wiring electrically connecting the pixel circuit 62 and the driving circuit 40 can be shortened, whereby wiring resistance of the wiring can be reduced. Accordingly, since data can be written at a high speed, the display device 10 can be driven at a high speed. Thus, a sufficient frame period can be ensured even if the display device 10 includes many pixels 61, and thus the pixel density of the display device 10 can be increased. Further, by increasing the pixel density of the display device 10, the resolution of the image displayed by the display device 10 can be increased. For example, the pixel density of the display device 10 may be set to 1000ppi or more, 5000ppi or more, or 7000ppi or more. Accordingly, the display device 10 may be, for example, a display device for AR or VR, and may be suitably used for an electronic apparatus in which a display unit such as an HMD is located closer to a user.

In fig. 7B, the wiring GLA, the wiring GLB, the wiring ANO, the wiring VCOM, the wiring V0, and the wiring SL are supplied from the driving circuit 40 below the pixel circuit 62 through the wirings, but one embodiment of the present invention is not limited to this. For example, the wirings for supplying signals and voltages to the driving circuit 40 may be routed around the outer periphery of the display unit 60 and electrically connected to the pixel circuits 62 arranged in a matrix in the layer 30. At this time, a structure in which the gate driver 41 included in the driving circuit 40 is provided in the layer 30 is effective. That is, it is effective to adopt a structure of an OS transistor as the transistor of the gate driver 41. A structure in which a part of the functions of the source driver 42 included in the driver circuit 40 is provided in the layer 30 is effective. For example, it is effective to provide a demultiplexer for distributing the signal output from the source driver 42 to each source line in the layer 30. It is effective to adopt a structure of an OS transistor as a transistor of the demultiplexer.

Note that fig. 7A and 7B illustrate a pixel circuit 62 including a total of three transistors of two transistors serving as switches and one transistor serving as a driving transistor, but one mode of the present invention is not limited thereto. For example, the pixel circuit 62A shown in fig. 8A or the pixel circuit 62B shown in fig. 8A may be employed.

The pixel circuit 62A shown in fig. 8A is a pixel circuit including two transistors, namely, a switch SW21 and a transistor M21. The capacitor C21 in fig. 7A and 7B may be omitted when the gate capacitance of the transistor M21 is used. The pixel circuit 62B shown in fig. 8B is a pixel circuit including a switch SW23 having a gate electrode electrically connected to the wiring GLC between the transistor M21 and the wiring ANO in the pixel circuit 62 shown in fig. 7A and 7B. That is, the pixel circuit 62B shown in fig. 8B is a pixel circuit including four transistors. The pixel circuit 62 is not limited to the number of transistors of the pixel circuit 62A and the pixel circuit 62B illustrated, and a pixel circuit having another circuit structure may be applied.

In the pixel circuits described with reference to fig. 7A to 8B, the wiring connected to the back gate electrode is shown to be different from the wiring connected to the gate electrode and to supply a different potential, but other structures may also be employed. For example, a structure in which a back gate electrode and a gate electrode are connected to each other may be employed. Alternatively, a different connection structure may be used for a transistor serving as a switch and a driving transistor for controlling current flowing through the light emitting element 70. For example, a structure in which a back gate electrode and a gate electrode are connected to each other may be employed in a transistor serving as a switch, and a structure in which a back gate electrode is connected to a source side of the transistor (for example, a wiring side connected to the light-emitting element 70) may be employed in a driving transistor.

< structural example of functional Circuit >

As an example of a circuit included in the functional circuit, a CPU including a CPU core that can perform power gating is described.

Fig. 9 shows a configuration example of the CPU51 included in the functional circuit 50. The CPU51 includes a CPU Core (CPU Core) 53, an L1 (level 1) Cache (L1 Cache) 54, an L2 Cache (L2 Cache) 55, a Bus interface section (Bus I/F) 56, power switches 57A to 57C, and a Level Shifter (LS) 58.CPU core 53 includes flip-flop 80.

The cpu core 53, the L1 cache device 54, and the L2 cache device 55 are connected to each other through the bus interface section 56.

PMU59 generates clock signal GCLK1 and various PG (power gating) control signals (PG control signals) from signals such as interrupt signals (Interrupts) input from the outside and signals SLEEP1 generated by CPU51. The clock signals GCLK1 and PG control signals are input to the CPU51. The PG control signal controls the power switches 57A to 57C, and the flip-flop 80.

The power switches 57A and 57B control supply voltages VDDD and VDD1 to virtual power supply lines v_vdd (hereinafter, referred to as v_vdd lines), respectively. The power switch 57C controls supply of the voltage VDDH to a virtual power supply line v_vdh (hereinafter, referred to as v_vdh line). CPU51 and PMU59 are not supplied with voltage VSSS via a power switch. PMU59 is not input voltage VDDD through the power switch.

The voltages VDDD and VDD1 are drive voltages for CMOS circuits. The voltage VDD1 is a driving voltage in a sleep state lower than the voltage VDDD. The voltage VDDH is a driving voltage for the OS transistor and is higher than the voltage VDDD.

Each of the L1 cache 54, L2 cache 55, and bus interface 56 includes at least one power domain capable of power gating. A power domain capable of power gating is provided with one or more power switches. The power switch is controlled by a PG control signal.

Flip-flop 80 is used for registers. The flip-flop 80 is provided with a backup circuit. Hereinafter, the trigger 80 is explained.

Fig. 10A shows a circuit configuration example of a Flip-flop 80 (Flip-flop). The Flip-flop 80 includes a Scan Flip-flop (Scan Flip-flop) 81 and a backup Circuit (backup Circuit) 82.

The scan flip-flop 81 includes nodes D1, Q1, SD, SE, RT, CK, and a clock buffer circuit 81A.

Node D1 is a data (data) input node, node Q1 is a data output node, and node SD is an input node for scan test data. Node SE is the input node for signal SCE. The node CK is an input node of the clock signal GCLK 1. The clock signal GCLK1 is input to the clock buffer circuit 81A. The analog switch of the scan flip-flop 81 is connected to the nodes CK1 and CKB1 of the clock buffer circuit 81A. The node RT is an input node of a reset signal (reset signal).

Signal SCE is a scan enable signal that is generated at PMU 59. PMU59 generates signals BK, RC. The level shifter 58 level-shifts the signals BK, RC to generate signals BKH, RCH. The signals BK, RC are the backup signal, the recovery signal, respectively.

The circuit configuration of the scan flip-flop 81 is not limited to fig. 10A, and a flip-flop prepared in a standard circuit library may be used.

The backup circuit 82 includes nodes sd_in, SN11, transistors M11 to M13, and a capacitor C11.

The node sd_in is an input node of scan test data, and is connected to the node Q1 of the scan flip-flop 81. Node SN11 is a holding node of the backup circuit 82. The capacitor C11 is a holding capacitor for holding the voltage of the node SN 11.

Transistor M11 controls the on state between node Q1 and node SN 11. Transistor M12 controls the on state between node SN11 and node SD. The transistor M13 controls the on state between the node sd_in and the node SD. The on/off of the transistors M11, M13 is controlled by the signal BKH, and the on/off of the transistor M12 is controlled by the signal RCH.

As with the transistors included in the memory cell 62 described above, the transistors M11 to M13 are OS transistors. The drawings show that the transistors M11 to M13 employ a structure including a back gate. An example in which the back gates of the transistors M11 to M13 are electrically connected to the power supply line of the supply voltage VBG1 is shown.

Preferably, at least the transistors M11, M12 are OS transistors. By virtue of the feature that the off-state current of the OS transistor is extremely small, the voltage drop of the node SN11 can be suppressed, and little power is consumed when data is held, so the backup circuit 82 has a nonvolatile characteristic. Since the data is rewritten by charging and discharging the capacitor C11, the backup circuit 82 is not limited in number of times of rewriting in principle, and can write and read data with low energy.

It is particularly preferred that all transistors of the backup circuit 82 are OS transistors. As shown in fig. 10B, a backup circuit 82 may be laminated on a scan flip-flop 81 composed of a silicon CMOS circuit.

The number of elements of the backup circuit 82 is very small compared with the scan flip-flop 81, and thus it is not necessary to change the circuit configuration and layout of the scan flip-flop 81 in order to stack the backup circuit 82. That is, the backup circuit 82 is a backup circuit having very high versatility. Further, the backup circuit 82 may be provided in an overlapping manner in the region where the scan flip-flop 81 is formed, whereby the area overhead of the flip-flop 80 can be made 0 even if the backup circuit 82 is mounted. Thus, by providing the backup circuit 82 at the flip-flop 80, power gating of the CPU core 53 can be performed. The power gating requires little energy, so the power gating of the CPU core 53 can be performed efficiently.

By providing the backup circuit 82, although the parasitic capacitance generated by the transistor M11 is added to the node Q1, it is smaller than the parasitic capacitance generated by the logic circuit connected to the node Q1, and thus does not affect the operation of the scan flip-flop 81. That is, even if the backup circuit 82 is provided, the performance of the flip-flop 80 is not substantially degraded.

As the low power consumption state (non-operation state) of the CPU core 53, for example, a clock gating state, a power gating state, and a sleep state can be set. PMU59 selects a low power mode for CPU core 53 based on the interrupt signal, signal SLEEP1, etc. For example, PMU59 stops generating clock signal GCLK1 when transitioning from the normal operating state to the clock-gated state.

For example, PMU59 may perform voltage and/or frequency regulation when transitioning from a normal operating state to a sleep state. For example, in performing voltage adjustment, in order to input the voltage VDD1 to the CPU core 53, the pmu59 turns off the power switch 57A and turns on the power switch 57B. The voltage VDD1 is a voltage that does not disappear the data of the scan flip-flop 81. During frequency adjustment, PMU59 causes the frequency of clock signal GCLK1 to decrease.

When the CPU core 53 is shifted from the normal operation state to the power gating state, an operation of backing up the data of the scan flip-flop 81 to the backup circuit 82 is performed. The restoration operation of writing back the data of the backup circuit 82 again to the flip-flop 81 is performed when the CPU core 53 is restored from the power-gating state to the normal operation state.

Fig. 11 shows an example of the power gating sequence of the CPU core 53. Note that in fig. 11, t1 to t7 denote timings. Signals PSE0 through PSE2 are control signals for power switches 57A through 57C, generated at PMU 59. When the signal PSE0 is "H"/"L", the power switches 57A to 57C are turned on/off. The same applies to both PSE1 and PSE 2.

Time t1 is preceded by a Normal Operation state (Normal Operation). The power switch 57A is turned on, and the CPU core 53 is inputted with the voltage VDDD. The scan flip-flop 81 performs normal operation. At this time, the level shifter 58 is not required to be operated, so the power switch 57C is turned off, and the signal SCE, BK, RC is at "L". Node SE is at "L", so scan flip-flop 81 stores the data of node D1. Note that in the example of fig. 11, the node SN11 of the backup circuit 82 is at "L" at time t 1.

The following describes the operation at the time of Backup (Backup). At operation time t1, PMU59 stops clock signal GCLK1 and places signals PSE2, BK at "H". The level shifter 58 becomes active and outputs a signal BKH of "H" to the backup circuit 82.

The transistor M11 of the backup circuit 82 is turned on, and the data of the node Q1 of the scan flip-flop 81 is written to the node SN11 of the backup circuit 82. If the node Q1 of the scan flip-flop 81 is "L", the node SN11 maintains "L", and if the node Q1 is "H", the node SN11 becomes "H".

At time t2, PMU59 causes signals PSE2, BK to be "L", and at time t3, PMU59 causes signal PSE0 to be "L". At time t3, the state of the CPU core 53 transitions to the power-gating state. In addition, the signal PSE0 may be lowered at the timing when the signal BK is lowered.

The operation at Power-gating (Power-gating) is described below. The voltage of the v_vdd line drops when signal PSE0 is at "L", so the data of node Q1 disappears. Node SN11 continues to hold the data of node Q1 at time t 3.

The operation at the time of Recovery (Recovery) is described below. At time t4, PMU59 turns signal PSE0 to "H" and thus transitions from the power gating state to the recovery state. When the voltage on the v_vdd line reaches VDDD (time t 5), PMU59 changes signals PSE2, RC, SCE to "H".

Transistor M12 is turned on and the charge of capacitor C11 is distributed between node SN11 and node SD. If node SN11 is "H", the voltage at node SD increases. Node SE is "H", and the data of node SD is written into the input side latch circuit of scan flip-flop 81. At time t6, the clock signal GCLK1 is input to the node CK, and the data of the input-side latch circuit is written to the node Q1. That is, the data of the node SN11 is written to the node Q1.

At time t7, PMU59 causes signals PSE2, SCE, RC to go to "L" and ends the recovery operation.

The backup circuit 82 using OS transistors has small dynamic and static power consumption and is therefore well suited for normally-off operation. Even if the flip-flop 80 is mounted, a performance degradation of the CPU core 53 and an increase in dynamic power hardly occur.

In addition, CPU core 53 may also include multiple power domains that enable power gating. The plurality of power domains are provided with one or more power switches for controlling the input of voltage. In addition, CPU core 53 may also have one or more power domains that are not power gated. For example, a power gating control circuit for controlling the control of the flip-flop 80 and the power switches 57A to 57C may be provided in a power domain where power gating is not performed.

Note that the application of the flip-flop 80 is not limited to the CPU51. In the arithmetic device, the flip-flop 80 may be used for a register provided in a power supply fixed domain capable of power supply gating.

< structural example of display correction System >

The display correction system according to one embodiment of the present invention corrects the current I flowing through the light emitting element 70 _EL Display failure due to defective pixels such as bright spots and dark spots can be reduced.

The circuit diagram shown in fig. 12A is a diagram in which a part of the pixel circuit 62 shown in fig. 5 is extracted. A current I flowing through the light emitting element 70 in a defective pixel causing a bright spot, a dark spot, or the like, as compared with a pixel of normal display _EL Too large or too small.

The CPU51 periodically acquires the monitor current I flowing through the switch SW23 _MONI Is a data of (a) a data of (b). The monitor current I _MONI The amount of current of (c) is converted into digital data that can be processed by the CPU51, and arithmetic processing is performed by the CPU51 using the digital data. Defective pixels are estimated by the arithmetic processing of the CPU51, and correction is made in the CPU51 so that display defects caused by the defective pixels are not easily seen. For example, in the case where the pixel 61D shown in fig. 12B is a defective pixel, the current I flowing through the light emitting element 70 of the adjacent pixel 61N is corrected _EL 。

In the correction, the correction amount may be estimated by performing an operation based on an artificial neural network such as a Deep Neural Network (DNN), a Convolutional Neural Network (CNN), a Recurrent Neural Network (RNN), an automatic encoder, a Deep Boltzmann Machine (DBM), a Deep Belief Network (DBN), or the like.

As shown in fig. 12C, by the current I flowing through the adjacent pixel 61N _EL Corrected to current I _{EL_C} Defective pixels can be usedThe pixel 61G combined with the pixel 61N performs display. As a result, display failure of defective pixels due to bright spots, dark spots, or the like can be prevented from being easily seen, and normal display can be performed.

In addition, in the above CPU51, the operation performed by the display correction system to correct the current flowing through the pixel can be kept as backup data continuously with the data during the operation. This is particularly effective in terms of an arithmetic process with a large amount of computation such as an arithmetic operation using an artificial neural network. Further, by using the CPU51 as an application processor, by combining driving or the like in which the frame rate is made variable, it is possible to realize low power consumption in addition to reduction of display failure.

< modified example of display device >

Fig. 13 to 27 show modified examples of the respective components included in the display device 10 described above.

The block diagram of the display device 10A shown in fig. 13 corresponds to a configuration in which an accelerator 52 is added to the functional circuit 50 in the display device 10 of fig. 5.

When the display correction system performs an operation based on an artificial neural network, product-sum operation is repeated. The accelerator 52 is used as a dedicated arithmetic circuit for the product-sum arithmetic processing of the artificial neural network NN. In the operation using the accelerator 52, correction due to the display failure, processing for correcting the outline of the image by up-converting the display data, or the like may be performed. In addition, by adopting a configuration in which power gating of the CPU51 is performed at the time of the arithmetic processing by the accelerator 52, low power consumption can be achieved.

The circuit diagrams shown in fig. 14A and 14B are diagrams in which the pixel circuit 62 shown in fig. 7A and the backup circuit 82 shown in fig. 10A are combined. Fig. 14A shows a structure in which one electrode of the capacitor C11 included in the backup circuit 82 is connected to the wiring VCOM. In addition, fig. 14B shows a structure in which one electrode of the capacitor C11 included in the backup circuit 82 is connected to the wiring ANO. As shown in fig. 14A and 14B, by sharing wirings in the pixel circuit 62 and the backup circuit 82 having different circuit structures in the layer 30, the reduction in the number of wirings can be achieved.

Note that the transistor M12 and the transistor M13 may be omitted from the backup circuit 82 shown in fig. 14A and 14B. Fig. 15A and 15B show this structure, respectively. In addition to being used for data backup in the flip-flop 80, the memory circuit 82B shown in fig. 15A and 15B can also be used as a memory circuit with high versatility. For example, the memory circuit 82B may be used as a memory circuit of the functional circuit 50.

Note that fig. 15A and 15B show a structure in which one electrode of the capacitor C11 of the memory circuit 82B is connected to the wiring VCOM or the wiring ANO, but other structures may be employed. For example, a structure connected to the wiring V0, the wiring GL, or the like may be employed.

The circuit diagram shown in fig. 16 shows one example of a pixel circuit and a memory circuit provided in a plurality of rows. In fig. 16, a pixel circuit 62_1r, a pixel circuit 62_1g, and a pixel circuit 62_1b are shown as pixel circuits serving as sub-pixels of the first row. In fig. 16, light-emitting elements 70r_1, 70g_1, and 70b_1 are shown as light-emitting elements in the first row. In fig. 16, a memory circuit 82b_1 is shown as a memory circuit of the first row. In fig. 16, the pixel circuits 62_2r, 62_2g, and 62_2b are shown as the pixel circuits serving as the sub-pixels of the second row. In fig. 16, light-emitting elements 70r_2, light-emitting elements 70g_2, and light-emitting elements 70b_2 are shown as light-emitting elements in the second row. In fig. 16, a memory circuit 82b_2 is shown as a memory circuit of the second row. Note that the memory circuits 82b_1 and 82b_2 are connected to nodes holding data in the functional circuits 50_1 and 50_2. The functional circuits 50_1, 50_2 correspond to different terminals in the functional circuit 50.

Fig. 16 shows a wiring gl_1 used as the wiring GL of the first row and a wiring gl_2 used as the wiring GL of the second row. Fig. 16 shows a wiring sl_ R, SL _ G, SL _b, a wiring ANO, and a wiring VCOM used as a source line. Fig. 16 shows a wiring ml_1 which supplies a signal BKH for controlling the memory circuit 82b_1 and a wiring ml_2 which supplies a signal BKH for controlling the memory circuit 82b_2.

Note that in the following description, when the same components of the pixel circuit 62_1r, the pixel circuit 62_1g, the pixel circuit 62_1b, and the like are described, a common portion of the symbol may be shown as the pixel circuit 62_1. In the case where a plurality of constituent elements are described using the same symbol, it is necessary to distinguish them, in particular, a symbol for identifying the number of lines such as "_1", "_2", or the like, or a symbol for identifying each color controlled by a subpixel such as "R", "G", or "B" may be added to the symbol.

Note that, as the pixel circuits 62_1 and 62_2 shown in fig. 16, a case of applying the configuration example of fig. 8A including the switch SW21 and the transistor M21 is shown. As the memory circuits 82b_1 and 82b_2 shown in fig. 16, a configuration example of fig. 15A including the transistor M11 and the capacitor C11 is shown. The memory circuit 82B may be arranged between a group of pixel circuits (pixel circuits 62_1r, 62_1g, and 62_1b) that control RGB.

In fig. 16), the connection of the back gate electrodes of the transistors of the pixel circuits 62_1 and 62_2 and the memory circuits 82b_1 and 82b_2 is omitted, but a configuration in which the back gate electrodes are connected to each other may be adopted. In addition, the back gate electrodes of the transistors of the pixel circuit 62 and the memory circuit 82B located in the same row may be connected to each other. In addition, a structure in which back gate electrodes of transistors included in the pixel circuit 62 are connected to each other and back gate electrodes of transistors included in the memory circuit 82B are connected to each other may also be employed. That is, it is preferable that a wiring connecting the back gate electrode of the transistor included in the pixel circuit 62 is a different wiring from a wiring connecting the back gate electrode of the transistor included in the memory circuit 82B.

As shown in fig. 16, a memory circuit 82B provided together with the pixel circuit 62 may be provided corresponding to the sub-pixels of RGB. The memory circuit 82B can hold data of a circuit provided in the layer 20 by the OS transistor function circuit 50, the CPU51, or the like. The memory circuit 82B provided in the layer 30 provided with the OS transistor can be uniformly arranged in the layer 30, and therefore, unlike the case where the memory circuit 82B is locally arranged, the memory circuit 82B can be easily electrically connected to the functional circuit 50 or the CPU 51.

Fig. 17 shows an example of a pixel circuit and a memory circuit which are arranged in a plurality of rows, unlike the structure of fig. 16. Fig. 16 shows a structure in which the memory circuit 82B is provided corresponding to one set of pixel circuits 62_1, 62_2 that control RGB, but fig. 17 shows a structure in which the memory circuit 82B is arranged in each set of pixel circuits that control RGB. Note that the functional circuits 50_11, 50_12, 50_13, 50_21, 50_22, 50_23 correspond to different terminals in the functional circuit 50. By adopting the structure of fig. 17, more memory circuits 82B can be provided in the layer 30 provided with OS transistors than in the structure of fig. 16. Further, since the memory circuits can be uniformly arranged in the layer 30, unlike the case where the memory circuit 82B is locally arranged, the memory circuit 82B can be easily electrically connected to the functional circuit 50 or the CPU51 independently of the circuit configuration of the functional circuit 50 or the CPU 51.

Fig. 18 shows an example of a pixel circuit and a memory circuit which are arranged in a plurality of rows, unlike the structures of fig. 16 and 17. The wiring ml_1 and the wiring ml_2 in fig. 18 are common wirings ML. The wiring ML is a wiring for supplying a signal BKH for controlling the memory circuit 82b_1 and the memory circuit 82b_2. The wirings ML have a structure in which wirings provided in different rows are connected by wirings parallel to wirings provided in the column direction. For example, by disposing the wiring ml_col parallel to the wiring provided in the column direction between the pixel circuits of the sub-pixels, the influence of noise between the pixel circuits can be reduced.

Fig. 19 shows an example of a pixel circuit and a memory circuit which are arranged in a plurality of rows, different from the structures of fig. 16 to 18. In fig. 19, the memory circuit 82b_1 located in the first row and the memory circuit 82b_2 located in the second row are connected to the same node in the functional circuit 50 that holds data. The memory circuit 82b_1 and the memory circuit 82b_1 can control the transistor M11 at different timings according to different signals, and thus data of a node in the functional circuit 50 can be obtained and held at a plurality of timings.

Fig. 20A shows a modification example of the memory circuit 82B applicable to the memory circuit 82b_1 located in the first row and/or the memory circuit 82b_2 located in the second row shown in fig. 16 to 19. Fig. 20A shows a structure in which a terminal of the capacitor C11 on the side connected to the wiring ANO is connected to a node to which a fixed potential is supplied in the functional circuit 50 on the side of the layer 20. As another structural diagram, fig. 20B shows: the terminal of the capacitor C11 on the side connected to the wiring ANO is connected to a node to which a fixed potential is supplied in the functional circuit 50 on the side of the layer 20, the wiring ML connected to the gate electrode of the transistor M11 is omitted, and a signal for performing control is supplied from the functional circuit 50 on the side of the layer 20. Note that the functional circuits 50_1a, 50_1b, and 50_1c represent different terminals in the functional circuit 50. By adopting this structure, the number of components of the memory circuit 82B in the layer 30 can be reduced, and the occupied area of the pixel circuit 62 can be increased.

Fig. 21A shows a modification example of the memory circuit 82B similarly to fig. 20A and 20B. Fig. 21A shows a structure in which the capacitor C11 in the memory circuit 82B is provided in the functional circuit 50 on the layer 20 side. Fig. 21B shows as another structural diagram: the capacitor C11 in the memory circuit 82B is provided in the functional circuit 50 on the layer 20 side, the wiring ML connected to the gate electrode of the transistor M11 is omitted, and a signal for performing control is supplied from the functional circuit 50 on the layer 20 side. By adopting this structure, the number of components of the memory circuit 82B in the layer 30 can be reduced, and the occupied area of the pixel circuit 62 can be increased.

The circuit diagram shown in fig. 22A uses the backup circuit 82 illustrated in fig. 14B instead of the modified example of the memory circuit 82B illustrated in fig. 16 to 20. Fig. 22A shows a structure in which a terminal of the capacitor C11 in the backup circuit 82 is connected to the wiring ANO. Fig. 22B shows a structure in which a terminal of the capacitor C11 in the backup circuit 82 is connected to the transistor M12. Note that the scan flip-flops 81_a, 81_b, 81_c represent different terminals in the scan flip-flop 81. By adopting this structure, it is also possible to hold data of the node in the functional circuit 50 in the capacitor C11.

Fig. 23A shows a modification example of the backup circuit 82 in the same manner as fig. 22A and 22B. Fig. 23A shows a structure in which the capacitor C11 in the backup circuit 82 is provided on the side of the layer 20 including the scan flip-flop 81. Further, as another structural diagram, fig. 23B shows: the capacitor C11 in the backup circuit 82 is provided on the layer 20 side including the scan flip-flop 81, the wiring connected to the gate electrode of the transistor M11 and the wiring connected to the gate electrode of the transistor M12 are omitted, and signals BUH and RCH for control are supplied from the functional circuit 50 on the layer 20 side. By adopting this configuration, the number of components of the backup circuit 82 in the layer 30 can be reduced, and the occupied area of the pixel circuit 62 can be increased.

Note that connection of the back gate electrodes of the transistors of the pixel circuit 62 and the backup circuit 82 is omitted in fig. 22A to 23B, but a structure in which they are connected to each other may be adopted. In addition, the back gate electrodes of the transistors of the pixel circuit 62 and the back-up circuit 82 located in the same row may be connected to each other. In addition, a structure in which back gate electrodes of transistors included in the pixel circuit 62 are connected to each other and back gate electrodes of transistors included in the back-up circuit 82 are connected to each other may also be employed. That is, it is preferable that a wiring connecting the back gate electrode of the transistor included in the pixel circuit 62 is a different wiring from a wiring connecting the back gate electrode of the transistor included in the back-up circuit 82.

Fig. 24A shows an example of a circuit configuration of the layer 30, which is different from the above-described memory circuit 82B and backup circuit 82. The arithmetic circuit 82C shown in fig. 24A is an example of a circuit that performs a product-sum operation and an activation function operation. The arithmetic circuit 82C shown in fig. 24A is a circuit that performs a product-sum operation of the first data and the second data. In order to perform product-sum operation using a plurality of data, a plurality of operation circuits 82C are preferably provided.

The arithmetic circuit 82C includes a transistor M31, a transistor M32, and a capacitor CP. Note that the transistor M31 is preferably an OS transistor. By using an OS transistor as the transistor M31, leakage current of the transistor M31 can be suppressed. Thus, data necessary for calculation can be held as electric charges for a long period of time in the node NM, and a product-sum arithmetic circuit with high calculation accuracy can be realized. Since the refresh operation of the potential of the node NM can be reduced, the power consumption of the product-sum operation circuit can be reduced.

Further, by using an OS transistor as the transistor M32, the transistor M31 and the transistor M32 can be manufactured simultaneously, and thus the manufacturing process of the product-sum operation circuit can be shortened.

In the arithmetic circuit 82C, a crystalA first terminal of the body transistor M31 is electrically connected to the gate of the transistor M32. First terminal of transistor M32 and wiring V _R And (5) electric connection. A first terminal of the capacitor CP is electrically connected to the gate of the transistor M32.

In the arithmetic circuit 82C, the second terminal of the transistor M31 is electrically connected to the wiring BW, and the gate of the transistor M31 is electrically connected to the wiring WW. Second terminal of transistor M32 and wiring V _Y A second terminal of the capacitor CP is electrically connected to the wiring V _X And (5) electric connection. Note that in fig. 24A, I _AM Representing the slave wiring V _Y Current flowing through the second terminal of transistor M32.

In the arithmetic circuit 82C, by holding the charge corresponding to the data in the node NM and changing the wiring V _X Can change the potential of the gate of the transistor M32 in an electrically floating state, thereby obtaining a current I flowing through the transistor M32 _AM Is the result of the multiplication of the object. Then, by passing the current I through the plurality of arithmetic circuits 82C _AM The addition may perform a product-sum operation corresponding to the sum of multiplication results.

The circuit diagram shown in fig. 24B uses the arithmetic circuit 82C described in fig. 24A instead of the memory circuit 82B or the backup circuit 82 described in fig. 16 to 23. Fig. 25A shows a configuration in which the capacitor CP in the arithmetic circuit 82C is provided on the layer 30 side. The OS transistors provided in the layer 30 may have different transistor characteristics. For example, in order to hold charge, the transistor M31 needs to suppress leakage current, in order to make the current I _AM Through, the transistor M32 is preferably a transistor having a semiconductor layer with high mobility. In this case, the following structure is given as an example: the atomic ratio of In-Ga-Zn-O metal oxide In the semiconductor layer of the transistor M31 is In: ga: zn=1: 3:4 or 1:1:0.5 and the atomic ratio of In-Ga-Zn-O metal oxide In the semiconductor layer of transistor M32 is In: ga: zn=4: 2:3 or 3:1:2.

further, fig. 25B shows, as another structural diagram: the capacitor CP in the arithmetic circuit 82C is provided on the layer 20 side, and the wiring connected to the gate electrode of the transistor M31 and the wiring connected to the transistor M32 are omitted fromThe functional circuit 50 on the layer 20 side is connected to wirings BW, WWL and V _R 、V _Y 、V _X Terminals to which signals for control are supplied. Note that fig. 25B shows that the transistor M31 is an OS transistor provided in the layer 30 and the transistor M32 is a Si transistor provided in the layer 20. By adopting this configuration, the number of components of the arithmetic circuit 82C in the layer 30 can be reduced, and the occupied area of the pixel circuit 62 can be increased.

Note that in fig. 24B to 25B, connection of the back gate electrodes of the transistors of the pixel circuit 62 and the arithmetic circuit 82C is omitted, but a structure in which the back gate electrodes are connected to each other may be adopted. In addition, the back gate electrodes of the transistors of the pixel circuit 62 and the arithmetic circuit 82C located in the same row may be connected to each other. In addition, a structure in which back gate electrodes of transistors included in the pixel circuit 62 are connected to each other and back gate electrodes of transistors included in the arithmetic circuit 82C are connected to each other may also be employed. That is, it is preferable that a wiring connecting the back gate electrode of the transistor included in the pixel circuit 62 is a wiring different from a wiring connecting the back gate electrode of the transistor included in the arithmetic circuit 82C.

Fig. 26A shows an example of a circuit configuration of the layer 30, which is different from the above-described memory circuit 82B and backup circuit 82. The circuit block 82D shown in fig. 26A represents a sequential circuit or a combination circuit such as a flip-flop, an inverter, a shift register, or the like. The plurality of circuit blocks 82D are preferably provided in combination.

The circuit block 82D is provided between wirings for supplying power supply potential (VDD-VSS). As shown in fig. 26A, the circuit block 82D is connected to the transistor M41. Note that the transistor M41 is preferably an OS transistor. The transistor M41 may be set to a period in which the transistor M41 is turned off by the control signal PSW. Node V can be made by turning off transistor M41 _VDD Is smaller than VDD, thereby suppressing leakage current between wirings through which a power supply potential (VDD-VSS) is supplied through the circuit block 82D. Accordingly, power consumption can be reduced by turning off the transistor M41 during the period in which the circuit block 82D is not operating.

The circuit diagram shown in fig. 26B uses the circuit block 82D illustrated in fig. 26A instead of the modified example of the memory circuit 82B or the backup circuit 82 illustrated in fig. 16 to 23. Fig. 26A shows a structure in which the circuit block 82D is provided on the layer 20 side and the transistor M41 is provided on the layer 30 side. By adopting this structure, the transistor M41 can be arranged to overlap the circuit block 82D, whereby power consumption can be reduced without increasing the occupied area of the circuit block 82D.

Fig. 27A is an example of the following structure: as the transistor of the gate driver 41 included in the driving circuit 40 in fig. 1, an OS transistor is used, and the gate driver 41 (the gate driver 41L and the gate driver 41R shown as both sides of the display portion 60 in the drawing) is provided in the layer 30. By adopting this structure, the number of wirings from the driving circuit 40 in the layer 20 to the display portion 60 in the layer 30 can be reduced.

Further, fig. 27B is an example of the following structure: the layer 30 has a part of the function of the source driver 42 included in the driving circuit 40 in fig. 27A. Fig. 27B shows an example of the following structure: the transistor as a demultiplexer for distributing the signal output from the source driver 42 to each source line uses an OS transistor, and the demultiplexer 42DEM is provided in the layer 30. By adopting this structure, the number of wirings from the driving circuit 40 in the layer 20 to the display portion 60 in the layer 30 can be further reduced.

This embodiment mode can be appropriately combined with the description of other embodiment modes.

(embodiment 2)

In this embodiment, a cross-sectional structure example of the display device 10 according to an embodiment of the present invention will be described.

Fig. 28 is a cross-sectional view showing a structural example of the display device 10. The display device 10 includes a substrate 701 and a substrate 705, and the substrate 701 and the substrate 705 are bonded together with a sealant 712.

As the substrate 701, a single crystal semiconductor substrate such as a single crystal silicon substrate can be used. Further, a semiconductor substrate other than a single crystal semiconductor substrate may be used as the substrate 701.

A transistor 441 and a transistor 601 are provided over a substrate 701. The transistor 441 and the transistor 601 can be transistors provided in the layer 20 shown in embodiment mode 1.

The transistor 441 is constituted of a conductor 443 serving as a gate electrode, an insulator 445 serving as a gate insulator, and a part of the substrate 701, and includes a semiconductor region 447 including a channel formation region, a low-resistance region 449a serving as one of a source region and a drain region, and a low-resistance region 449b serving as the other of the source region and the drain region. Transistor 441 may be p-channel or n-channel.

The transistor 441 is electrically separated from other transistors by the element separation layer 403. Fig. 28 shows a case where the transistor 441 and the transistor 601 are electrically separated by the element separation layer 403. The element separation layer 403 can be formed by a LOCOS (LOCal Oxidation ofSilicon: local oxidation of silicon) method, an STI (Shallow Trench Isolation: shallow trench isolation) method, or the like.

Here, in the transistor 441 shown in fig. 28, the semiconductor region 447 has a convex shape. The side surfaces and the top surface of the semiconductor region 447 are covered with the conductor 443 via the insulator 445. Note that fig. 28 does not show a case where the conductor 443 covers the side face of the semiconductor region 447. In addition, a material for adjusting the work function can be used for the conductor 443.

Like the transistor 441, a transistor whose semiconductor region has a convex shape can be referred to as a fin-type transistor because of the use of a convex portion of a semiconductor substrate. Further, an insulator may be provided so as to be in contact with the top surface of the convex portion, and may be used as a mask for forming the convex portion. Although fig. 28 shows a case where a portion of the substrate 701 is processed to form a convex portion, an SOI substrate may be processed to form a semiconductor having a convex portion.

Further, the structure of the transistor 441 shown in fig. 28 is only one example and is not limited to this, and an appropriate transistor may be used according to a circuit structure, a circuit operation method, or the like. For example, the transistor 441 may be a planar transistor.

The transistor 601 can have the same structure as the transistor 441.

An element separation layer 403, a transistor 441, and a transistor 601 are provided over a substrate 701, and an insulator 405, an insulator 407, an insulator 409, and an insulator 411 are provided. Insulator 405, insulator 407, insulator 409, and insulator 411 are each embedded with an electrical conductor 451. Here, the height of the top surface of the conductive body 451 may be substantially the same as the height of the top surface of the insulator 411.

The insulator 421 and the insulator 214 are provided on the conductors 451 and 411. Insulator 421 and insulator 214 have conductor 453 embedded therein. Here, the height of the top surface of the conductor 453 may be made substantially the same as the height of the top surface of the insulator 214.

The insulator 216 is provided on the conductor 453 and the insulator 214. The insulator 216 has a conductive body 455 embedded therein. Here, the top surface of the conductive body 455 may be made substantially the same height as the top surface of the insulator 216.

Insulator 222, insulator 224, insulator 254, insulator 280, insulator 274, and insulator 281 are provided on conductor 455 and insulator 216. Insulator 222, insulator 224, insulator 254, insulator 280, insulator 274, and insulator 281 have conductor 305 embedded therein. Here, the height of the top surface of the conductor 305 may be made substantially the same as the height of the top surface of the insulator 281.

Insulator 361 is provided on conductor 305 and insulator 281. Conductor 317 and conductor 337 are embedded in insulator 361. Here, the top surface of the conductor 337 may be substantially the same height as the top surface of the insulator 361.

The insulator 363 is provided on the conductor 337 and the insulator 361. The insulator 363 is embedded with a conductor 347, a conductor 353, a conductor 355, and a conductor 357. Here, the heights of the top surfaces of the conductors 353, 355, and 357 may be substantially the same as the height of the top surface of the insulator 363.

The conductors 353, 355, 357 and insulator 363 are provided with connection electrodes 760. Further, an anisotropic conductor 780 is provided so as to be electrically connected to the connection electrode 760, and an FPC (Flexible Printed Circuit: flexible circuit board) 716 is provided so as to be electrically connected to the anisotropic conductor 780. By using the FPC716, various signals and the like can be supplied to the display device 10 from the outside of the display device 10.

As shown in fig. 28, a low-resistance region 449b serving as the other of the source region and the drain region of the transistor 441 is electrically connected to the FPC716 through the conductor 451, the conductor 453, the conductor 455, the conductor 305, the conductor 317, the conductor 337, the conductor 347, the conductor 353, the conductor 355, the conductor 357, the connection electrode 760, and the anisotropic conductor 780. In fig. 28, three conductors including a conductor 353, a conductor 355, and a conductor 357 are shown as conductors having a function of electrically connecting a connection electrode 760 and a conductor 347, and one embodiment of the present invention is not limited thereto. The number of conductors having the function of electrically connecting the connection electrode 760 and the conductor 347 may be one, two, four or more. By providing a plurality of conductors having a function of electrically connecting the connection electrode 760 and the conductor 347, contact resistance can be reduced.

A transistor 750 is provided over the insulator 214. The transistor 750 may be a transistor provided in the layer 30 shown in embodiment mode 1. For example, a transistor provided in the pixel circuit 62 may be used. The transistor 750 can use an OS transistor as appropriate. The OS transistor has a feature that an off-state current is extremely low. Thus, image data and the like can be held for a long time, and the refresh frequency can be reduced. Thereby, power consumption of the display device 10 can be reduced.

In addition, the transistor 750 may be a transistor provided in the backup circuit 82. The transistor 750 can use an OS transistor as appropriate. The OS transistor has a feature that an off-state current is extremely low. Thus, image data and the like can be held for a long time, and the refresh frequency can be reduced. Therefore, even during the period when the sharing of the power supply voltage is stopped, the data in the flip-flop can be continuously held. Therefore, a normally-off operation of the CPU (an operation of intermittently stopping the power supply voltage) can be realized. Thereby, power consumption of the display device 10 can be reduced.

Insulator 254, insulator 280, insulator 274, and insulator 281 have conductors 301a and 301b embedded therein. The conductor 301a is electrically connected to one of the source and the drain of the transistor 750, and the conductor 301b is electrically connected to the other of the source and the drain of the transistor 750. Here, the heights of the top surfaces of the conductors 301a and 301b may be substantially the same as the height of the top surface of the insulator 281.

The insulator 361 is embedded with the conductor 311, the conductor 313, the conductor 331, the capacitor 790, the conductor 333, and the conductor 335. The conductor 311 and the conductor 313 are electrically connected to the transistor 750 and function as wirings. The conductor 333 and the conductor 335 are electrically connected to the capacitor 790. Here, the heights of the top surfaces of the conductors 331, 333, and 335 may be substantially the same as the height of the top surface of the insulator 361.

The insulator 363 is embedded with the conductor 341, the conductor 343, and the conductor 351. Here, the height of the top surface of the conductor 351 may be substantially the same as the height of the top surface of the insulator 363.

The insulator 405, the insulator 407, the insulator 409, the insulator 411, the insulator 421, the insulator 214, the insulator 280, the insulator 274, the insulator 281, the insulator 361, and the insulator 363 serve as interlayer films, and may serve as planarizing films each covering the concave-convex shapes thereunder. For example, in order to improve the flatness of the top surface of the insulator 363, the plane thereof may be planarized by a planarization process using a chemical mechanical polishing (CMP: chemical Mechanical Polishing) method or the like.

As shown in fig. 28, the capacitor 790 includes a lower electrode 321, an upper electrode 325. Further, an insulator 323 is provided between the lower electrode 321 and the upper electrode 325. That is, the capacitor 790 has a stacked structure in which an insulator 323 serving as a dielectric is sandwiched between a pair of electrodes. Although fig. 28 shows an example in which the capacitor 790 is provided on the insulator 281, the capacitor 790 may be provided on a different insulator from the insulator 281.

Fig. 28 shows an example in which the conductor 301a, the conductor 301b, and the conductor 305 are formed in the same layer. Further, an example in which the conductor 311, the conductor 313, the conductor 317, and the lower electrode 321 are formed in the same layer is also shown. Further, an example in which the conductor 331, the conductor 333, the conductor 335, and the conductor 337 are formed in the same layer is also shown. Further, an example in which the conductor 341, the conductor 343, and the conductor 347 are formed in the same layer is also shown. Further, an example in which the conductor 351, the conductor 353, the conductor 355, and the conductor 357 are formed in the same layer is also shown. By forming a plurality of conductors in the same layer, the manufacturing process of the display device 10 can be simplified, and thus the manufacturing cost of the display device 10 can be reduced. In addition, they may be formed in different layers and contain different kinds of materials, respectively.

The display device 10 shown in fig. 28 includes a light emitting element 70. The light-emitting element 70 includes a conductor 772, an EL layer 786, and a conductor 788. The EL layer 786 contains an organic compound or an inorganic compound such as quantum dots.

Examples of the material usable for the organic compound include a fluorescent material and a phosphorescent material. Examples of materials that can be used as the quantum dots include colloidal quantum dot materials, alloy type quantum dot materials, core Shell (Core Shell) quantum dot materials, and Core type quantum dot materials.

Further, the conductor 772 is electrically connected to the other of the source and the drain of the transistor 750 through the conductor 351, the conductor 341, the conductor 331, the conductor 313, and the conductor 301 b. The conductor 772 is formed on the insulator 363 and is used as a pixel electrode.

As the conductive body 772, a material having transparency to visible light or a material having reflectivity can be used. As the light-transmitting material, for example, an oxide material containing indium, zinc, tin, or the like can be used. As the reflective material, for example, a material containing aluminum, silver, or the like can be used.

Although not illustrated in fig. 28, the display device 10 may be provided with an optical member (optical substrate) such as a polarizing member, a phase difference member, an antireflection member, or the like.

A light shielding layer 738 and an insulator 734 in contact with the light shielding layer are provided on the substrate 705 side. The light shielding layer 738 has a function of shielding light emitted from the adjacent region. Alternatively, the light shielding layer 738 has a function of preventing external light from reaching the transistor 750 or the like.

The display device 10 shown in fig. 28 is provided with an insulator 730 on the insulator 363. Here, the insulator 730 may cover a portion of the electric conductor 772. Further, the light emitting element 70 includes a light transmitting conductive body 788, and may be a light emitting element of a top emission structure. The light-emitting element 70 may have a bottom emission structure that emits light to one side of the conductor 772 or a double-sided emission structure that emits light to both sides of the conductor 772 and the conductor 788.

The light shielding layer 738 is provided so as to have a region overlapping with the insulator 730. Further, the light shielding layer 738 is covered with an insulator 734. Further, the sealing layer 732 fills the space between the light emitting element 70 and the insulator 734.

A structural body 778 is provided between the insulator 730 and the EL layer 786. Further, a structural body 778 is provided between the insulator 730 and the insulator 734.

Fig. 29 is a cross-sectional view of the Si transistor included in the driving circuit 40 in the layer 20 and the OS transistor (regions 40 and 62) included in the pixel circuit 62 in the layer 30, the Si transistor included in the functional circuit 50 in the layer 20, and the OS transistor (regions 50 and 82) included in the backup circuit 82 in the layer 30 described in embodiment mode 1. The explanation about the sectional view shown in fig. 29 is the same as each structure of the sectional view shown in fig. 28.

As shown in fig. 29, the Si transistor 91 of the driving circuit 40 and the Si transistor 94 of the functional circuit 50 may be provided in the layer 20. In addition, as shown in fig. 29, an OS transistor 92 and a capacitor 93 of the pixel circuit 62 and an OS transistor 95 and a capacitor 96 of the backup circuit 82 may be provided in the layer 30. Further, a light emitting element 70 may be provided in an upper layer of the layer 30.

Fig. 30A schematically shows a data backup state of the functional circuit 50 provided in the layer 20 in the configuration example of the display device 10 described in embodiment 1. Fig. 30A shows an example of a configuration in which a backup circuit 82 is provided in each pixel 61 of the display unit 60 provided in the layer 30.

In the configuration shown in fig. 30A in which the backup circuit 82 is uniformly arranged in the display unit 60, it is preferable that a trigger 80 for transmitting and receiving backup data BD is arranged close to the backup circuit 82. In the configuration in which the backup circuits 82 are uniformly arranged in the display unit 60, backup data can be transmitted and received to and from the backup circuit 82 located immediately above, regardless of the arrangement of the flip-flop 80 at any position of the layer 20.

For example, in the backup circuit 82M of fig. 30A, the backup data may be transmitted and received to and from a circuit (for example, the flip-flop 80) included in the function circuit 50 located immediately below, whereas in the backup circuit 82F of fig. 30A, the backup data may not be transmitted and received to and from a circuit included in the function circuit 50 located immediately below.

Fig. 30B shows a schematic cross-sectional view corresponding to the structure illustrated in fig. 30A. For example, by providing a wiring 97 for electrically connecting the layer 20 and the layer 30 between a circuit included in the functional circuit 50 and the backup circuit 82M for transmitting and receiving backup data, the transistor 94M in the layer 20 can be electrically connected to the transistor 95M and the capacitor 96M in the layer 30.

On the other hand, the wiring 97 for electrically connecting the layer 20 and the layer 30 is not provided between the circuit included in the functional circuit 50 and the backup circuit 82F for transmitting and receiving backup data. By adopting this structure, the transistor 94M in the layer 20 is not electrically connected to the transistor 95M and the capacitor 96M in the layer 30. The terminals of the backup circuit 82F, which are not electrically connected to the circuits included in the functional circuit 50, may be electrically floated or may be connected to a wiring to which a fixed potential is supplied.

As described in the description of fig. 30A and 30B, when a configuration is adopted in which electrical connection between the circuit included in the functional circuit 50 in the layer 20 and the backup circuit 82 in the layer 30 can be selected, even if the arrangement in the layer 20 of the functional circuit 50 that performs the arithmetic processing of data is changed, connection with the backup circuit that performs the data backup can be ensured only by changing the layout of the wiring layer.

Fig. 31 shows a modified example of the display device 10 shown in fig. 28. The display device 10 shown in fig. 31 is different from the display device 10 shown in fig. 28 in that a coloring layer 736 is provided. Further, the coloring layer 736 has a region overlapping with the light emitting element 70. By providing the coloring layer 736, the color purity of the light extracted from the light emitting element 70 can be improved. Accordingly, the display device 10 can display a high-quality image. Further, since all the light emitting elements 70 in the display device 10 can be, for example, light emitting elements that emit white light, it is not necessary to form the EL layer 786 by coating separately, and a high-definition display device 10 can be realized.

The light emitting element 70 may have an optical microcavity resonator (microcavity) structure. Thus, light of a predetermined color can be extracted without providing a coloring layer (for example Such as RGB), whereby the display device 10 is capable of color display. By adopting a structure in which a coloring layer is not provided, absorption of light by the coloring layer can be suppressed. Thereby, the display device 10 can display a high-luminance image, and the power consumption of the display device 10 can be reduced. In addition, when the EL layer 786 is formed in an island shape in each pixel or the EL layer 786 is formed in a stripe shape in each pixel row, that is, the EL layer 786 is formed by separate coating, a structure in which a coloring layer is not provided may be employed. The luminance of the display device 10 may be 500cd/m, for example ² Above, preferably 1000cd/m ² Above 10000cd/m ² Hereinafter, it is more preferably 2000cd/m ² Above and 5000cd/m ² The following is given.

Although fig. 28 and 31 show a structure in which the transistor 441 and the transistor 601 each having a channel formation region formed inside the substrate 701 are provided and an OS transistor is stacked over the transistor 441 and the transistor 601, one embodiment of the present invention is not limited to this. Fig. 32 shows a modified example of fig. 31. The display device 10 shown in fig. 32 is mainly different from the display device 10 shown in fig. 31 in that: the transistor 602 and the transistor 603 including an OS transistor replace the transistor 441 and the transistor 601. In addition, an OS transistor can be used for the transistor 750. That is, the display device 10 shown in fig. 32 is laminated with OS transistors.

An insulator 613 and an insulator 614 are provided over the substrate 701, and a transistor 602 and a transistor 603 are provided over the insulator 614. Further, a transistor or the like may be provided between the substrate 701 and the insulator 613. For example, a transistor having the same structure as the transistor 441 and the transistor 601 shown in fig. 31 may be provided between the substrate 701 and the insulator 613.

The transistor 602 and the transistor 603 can be provided in the layer 20 described in embodiment mode 1.

The transistor 602 and the transistor 603 may have the same structure as the transistor 750. The transistors 602 and 603 may be OS transistors having different structures from the transistor 750.

Insulator 614 is provided with an insulator 616, an insulator 622, an insulator 624, an insulator 654, an insulator 680, an insulator 674, and an insulator 681 in addition to the transistor 602 and the transistor 603. The insulator 654, the insulator 680, the insulator 674, and the insulator 681 are embedded with the conductor 461. Here, the height of the top surface of the conductor 461 may be made substantially the same as the height of the top surface of the insulator 681.

The insulator 501 is provided on the conductor 461 and the insulator 681. The insulator 501 has a conductive body 463 embedded therein. Here, the height of the top surface of the conductor 463 may be made substantially the same as the height of the top surface of the insulator 501.

The insulator 421 and the insulator 214 are provided on the conductor 463 and the insulator 501. Insulator 421 and insulator 214 have conductor 453 embedded therein. Here, the height of the top surface of the conductor 453 may be made substantially the same as the height of the top surface of the insulator 214.

As shown in fig. 32, one of a source and a drain of the transistor 602 is electrically connected to the FPC716 through a conductor 461, a conductor 463, a conductor 453, a conductor 455, a conductor 305, a conductor 317, a conductor 337, a conductor 347, a conductor 353, a conductor 355, a conductor 357, a connection electrode 760, and an anisotropic conductor 780.

The insulator 613, the insulator 614, the insulator 680, the insulator 674, the insulator 681, and the insulator 501 serve as interlayer films, and may be used as planarizing films each covering the concave-convex shapes thereunder.

By adopting the structure of the display device 10 shown in fig. 32, it is possible to use OS transistors as all transistors in the display device 10 while achieving a narrower frame and miniaturization of the display device 10. Thus, for example, a transistor provided in the layer 20 shown in embodiment mode 1 and a transistor provided in the layer 30 can be manufactured using the same device. Thus, the manufacturing cost of the display device 10 can be reduced, and the display device 10 can be provided at low cost.

Fig. 33 is a sectional view showing a structural example of the display device 10. The structure is mainly different from the display device 10 shown in fig. 31 in that: transistor 800 is included between the layer including transistor 750 and the layer including transistor 601 and transistor 441.

In the structure of fig. 33, the layer 20 shown in embodiment mode 1 can be formed of a layer including the transistor 601 and the transistor 441, and a layer including the transistor 800. The transistor 750 may be a transistor provided in the layer 30 shown in embodiment mode 1.

The insulator 821 and the insulator 814 are provided on the conductor 451 and the insulator 411. Insulator 821 and insulator 814 have conductor 853 embedded therein. Here, the top surface of the conductor 853 may be made substantially the same height as the top surface of the insulator 814.

An insulator 816 is provided on the conductor 853 and the insulator 814. A conductor 855 is embedded in the insulator 816. Here, the top surface of the conductor 855 may be made substantially the same height as the top surface of the insulator 816.

Insulator 822, insulator 824, insulator 854, insulator 880, insulator 874, and insulator 881 are provided on conductor 855 and insulator 816. Insulator 822, insulator 824, insulator 854, insulator 880, insulator 874, and insulator 881 are embedded with conductor 805. Here, the top surface of the conductor 805 may be made substantially the same as the top surface of the insulator 881.

Insulator 421 and insulator 214 are provided on conductor 817 and insulator 881.

As shown in fig. 33, the low-resistance region 449b having a function of one of the source region and the drain region of the transistor 441 is electrically connected to the FPC716 through the conductor 451, the conductor 853, the conductor 855, the conductor 805, the conductor 817, the conductor 453, the conductor 455, the conductor 305, the conductor 317, the conductor 337, the conductor 347, the conductor 353, the conductor 355, the conductor 357, the connection electrode 760, and the anisotropic conductor 780.

A transistor 800 is provided over an insulator 814. The transistor 800 may be a transistor provided in the layer 20 shown in embodiment mode 1. Transistor 800 is preferably an OS transistor. For example, the transistor 800 may be a transistor provided in the backup circuit 82.

Insulator 854, insulator 880, insulator 874, and insulator 881 are each embedded with a conductor 801a and a conductor 801b. The conductor 801a is electrically connected to one of the source and the drain of the transistor 800, and the conductor 801b is electrically connected to the other of the source and the drain of the transistor 800. Here, the heights of the top surfaces of the conductors 801a and 801b may be substantially the same as the height of the top surface of the insulator 881.

The transistor 750 may be a transistor provided in the layer 30 shown in embodiment mode 1. For example, the transistor 750 may be a transistor provided in the pixel circuit 62. Transistor 750 is preferably an OS transistor.

The insulator 405, the insulator 407, the insulator 409, the insulator 411, the insulator 821, the insulator 814, the insulator 880, the insulator 874, the insulator 881, the insulator 421, the insulator 214, the insulator 280, the insulator 274, the insulator 281, the insulator 361, and the insulator 363 may be used as interlayer films, or may be used as planarizing films each covering the concave-convex shapes thereunder.

Fig. 33 shows an example in which the conductor 801a, the conductor 801b, and the conductor 805 are formed in the same layer. Further, an example in which the conductor 811, the conductor 813, and the conductor 817 are formed in the same layer is also shown.

Fig. 34 is a sectional view showing a structural example of the display device 10. The display device 10 shown in fig. 34 is mainly different from the display device 10 shown in fig. 31 in that: the layers including the transistor 750 are omitted.

In the structure of fig. 34, as a transistor corresponding to the transistor 750 of the OS transistor, the Si transistor located in the layer 20 shown in embodiment mode 1, for example, the transistor 601 can be used. The transistor 601 is used as a transistor with a small off-state current, and thus it is preferable that its channel length is longer than that of the transistor 441.

Note that in the structure of fig. 34, a layer in which a conductor is used as a wiring is omitted in addition to the layer of the transistor 750 including an OS transistor. A plurality of conductors may be provided between a layer including Si transistors such as the transistor 601 and the transistor 441 and a layer including the light-emitting element 70, so that the layers can be used as wirings. By adopting this structure, the degree of freedom in layout of the display portion and the elements such as transistors located in the lower layer of the display portion can be improved.

At least a part of this embodiment can be implemented in combination with other embodiments described in this specification as appropriate.

Embodiment 3

In this embodiment mode, a transistor and a light-emitting element (a light-emitting device) which can be used for a display device according to one embodiment of the present invention are described.

< structural example of transistor >

Fig. 35A, 35B, and 35C are a top view and a cross-sectional view of a transistor 200A and a periphery of the transistor 200A, which can be used in a display device according to one embodiment of the present invention. The transistor 200A can be applied to a display device according to one embodiment of the present invention.

Fig. 35A is a top view of the transistor 200A. Fig. 35B and 35C are cross-sectional views of the transistor 200A. Here, fig. 35B is a sectional view along the chain line A1-A2 in fig. 35A, which corresponds to a sectional view in the channel length direction of the transistor 200A. Fig. 35C is a sectional view along the dash-dot line A3-A4 in fig. 35A, which corresponds to a sectional view in the channel width direction of the transistor 200A. Note that, for ease of understanding, part of the constituent elements are omitted in the top view of fig. 35A.

As shown in fig. 35, the transistor 200A includes: a metal oxide 230a disposed on a substrate (not shown); a metal oxide 230b disposed on the metal oxide 230a; a conductor 242a and a conductor 242b disposed on the metal oxide 230b and separated from each other; an insulator 280 disposed on the conductors 242a and 242b and forming an opening so as to overlap between the conductors 242a and 242b; a conductor 260 disposed in the opening; an insulator 250 disposed between the metal oxide 230b, the conductor 242a, the conductor 242b, the insulator 280 and the conductor 260; and a metal oxide 230c disposed between the metal oxide 230b, the conductor 242a, the conductor 242b, and the insulator 280 and the insulator 250. Here, as shown in fig. 35B and 35C, the top surface of the conductor 260 preferably substantially coincides with the top surfaces of the insulator 250, the insulator 254, the metal oxide 230C, and the insulator 280. Hereinafter, the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c may be collectively referred to as an oxide 230. The conductors 242a and 242b are sometimes collectively referred to as conductors 242.

In the transistor 200A shown in fig. 35, the side surfaces of the conductors 242a and 242b on the side of the conductor 260 are substantially perpendicular to the bottom surface. The transistor 200A shown in fig. 35 is not limited to this, and may have an angle between the side surfaces and the bottom surfaces of the conductors 242a and 242b of 10 ° or more and 80 ° or less, preferably 30 ° or more and 60 ° or less. Further, the conductor 242a and the conductor 242b may have a structure in which the opposite side surfaces have a plurality of surfaces.

As shown in fig. 35, an insulator 254 is preferably disposed between the insulator 224, the metal oxide 230a, the metal oxide 230b, the conductor 242a, the conductor 242b, and the metal oxide 230c and the insulator 280. Here, as shown in fig. 35B and 35C, the insulator 254 preferably contacts the side surface of the metal oxide 230C, the top surface and the side surface of the conductor 242a, the top surface and the side surface of the conductor 242B, the side surfaces of the metal oxide 230a and the metal oxide 230B, and the top surface of the insulator 224.

Note that in the transistor 200A, a region where a channel is formed (hereinafter also referred to as a channel formation region) and three layers of the metal oxide 230A, the metal oxide 230b, and the metal oxide 230c are stacked in the vicinity thereof, but the present invention is not limited to this. For example, the metal oxide 230b and the metal oxide 230c may have a two-layer structure or a stacked structure of four or more layers. Further, in the transistor 200A, the conductor 260 has a two-layer structure, but the present invention is not limited thereto. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers. The metal oxide 230a, the metal oxide 230b, and the metal oxide 230c may each have a stacked structure of two or more layers.

For example, in the case where the metal oxide 230c has a stacked structure composed of a first metal oxide and a second metal oxide over the first metal oxide, it is preferable that the first metal oxide has the same composition as the metal oxide 230b and the second metal oxide has the same composition as the metal oxide 230 a.

Here, the conductor 260 is used as a gate electrode of a transistor, and the conductor 242a and the conductor 242b are each used as a source electrode or a drain electrode. As described above, the conductor 260 is formed so as to be fitted into the opening of the insulator 280 and to be sandwiched in the region between the conductor 242a and the conductor 242 b. Here, the arrangement of the conductors 260, 242a, and 242b is selected to be self-aligned with respect to the opening of the insulator 280. That is, in the transistor 200A, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. Thus, the conductor 260 can be formed without providing a margin for alignment, and thus the occupied area of the transistor 200A can be reduced. Thus, the display device can be made high definition. In addition, a display device with a narrow frame can be realized.

As shown in fig. 35, the conductor 260 preferably includes a conductor 260a disposed inside the insulator 250 and a conductor 260b disposed so as to be embedded inside the conductor 260 a.

The transistor 200A preferably includes an insulator 214 disposed over a substrate (not shown), an insulator 216 disposed over the insulator 214, a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed over the insulator 216 and the conductor 205, and an insulator 224 disposed over the insulator 222. Preferably, the metal oxide 230a is disposed on the insulator 224.

An insulator 274 and an insulator 281 serving as interlayer films are preferably arranged over the transistor 200A. Here, the insulator 274 is preferably in contact with the top surfaces of the conductor 260, the insulator 250, the insulator 254, the metal oxide 230c, and the insulator 280.

Further, the insulator 222, the insulator 254, and the insulator 274 preferably have a function of suppressing diffusion of at least one of hydrogen (e.g., hydrogen atoms, hydrogen molecules, and the like). For example, insulator 222, insulator 254, and insulator 274 preferably have a lower hydrogen permeability than insulator 224, insulator 250, and insulator 280. Further, the insulator 222 and the insulator 254 preferably have a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, and the like). For example, insulator 222 and insulator 254 preferably have a lower oxygen permeability than insulator 224, insulator 250, and insulator 280.

Here, the insulator 224, the metal oxide 230, and the insulator 250 are separated from the insulator 280 and the insulator 281 by the insulator 254 and the insulator 274. This can prevent impurities such as hydrogen contained in the insulator 280 and the insulator 281, and excessive oxygen from being mixed into the insulator 224, the metal oxide 230a, the metal oxide 230b, and the insulator 250.

Further, the semiconductor device preferably includes the conductors 240 (the conductor 240A and the conductor 240 b) which are electrically connected to the transistor 200A and are used as plugs. Further, an insulator 241 (an insulator 241a and an insulator 241 b) is provided in contact with a side surface of the conductor 240 serving as a plug. That is, the insulator 241 is formed in contact with the inner walls of the openings of the insulator 254, the insulator 280, the insulator 274, and the insulator 281. Further, a first conductor of the conductor 240 may be provided in contact with a side surface of the insulator 241 and a second conductor of the conductor 240 may be provided inside thereof. Here, the height of the top surface of the conductor 240 may be substantially the same as the height of the top surface of the insulator 281. In addition, although the structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked in the transistor 200A is shown, the present invention is not limited to this. For example, the conductor 240 may have a single-layer structure or a stacked structure of three or more layers. When the structure has a laminated structure, ordinals may be given in the order of formation to distinguish between the structures.

In addition, a metal oxide used as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the metal oxide 230 (the metal oxide 230A, the metal oxide 230b, and the metal oxide 230 c) including a channel formation region in the transistor 200A. For example, as the metal oxide to be the channel formation region of the metal oxide 230, a metal oxide having a band gap of 2eV or more, preferably 2.5eV or more is preferably used.

The metal oxide preferably contains at least indium (In) or zinc (Zn). In particular, indium (In) and zinc (Zn) are preferably contained. In addition, the element M is preferably contained. The element M may be one or more of aluminum (Al), gallium (Ga), yttrium (Y), tin (Sn), boron (B), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), tungsten (W), magnesium (Mg), and cobalt (Co). In particular, the element M is preferably one or more of aluminum (Al), gallium (Ga), yttrium (Y), and tin (Sn). Further, the element M more preferably contains one or both of Ga and Sn.

As shown in fig. 35B, the thickness of the region of the metal oxide 230B that does not overlap the conductor 242 may be thinner than the thickness of the region that overlaps the conductor 242. The thin region is formed by removing a part of the top surface of the metal oxide 230b when the conductors 242a and 242b are formed. When a conductive film to be the conductor 242 is deposited on the top surface of the metal oxide 230b, a low-resistance region is sometimes formed near the interface with the conductive film. In this manner, by removing a low-resistance region between the conductor 242a and the conductor 242b on the top surface of the metal oxide 230b, channel formation can be suppressed in this region.

In one embodiment of the present invention, a display device including a transistor having a small size and having high definition can be provided. Further, a display device including a transistor with a large on-state current and having high luminance can be provided. Further, a display device including a transistor which operates at a high speed and which operates at a high speed can be provided. Further, a display device including a transistor with stable electrical characteristics and having high reliability can be provided. Further, a display device including a transistor with a small off-state current and having low power consumption can be provided.

A detailed structure of the transistor 200A which can be used for the display device according to one embodiment of the present invention will be described.

The conductor 205 is arranged to include a region overlapping with the metal oxide 230 and the conductor 260. Further, the electric conductor 205 is preferably provided in such a manner as to be embedded in the insulator 216.

The conductors 205 include conductors 205a, 205b, and 205c. The conductor 205a contacts the bottom surface and the side wall of the opening provided in the insulator 216. The conductor 205b is provided so as to be buried in a recess formed in the conductor 205 a. Here, the top surface of the conductor 205b is lower than the top surface of the conductor 205a and the top surface of the insulator 216. The conductor 205c is in contact with the top surface of the conductor 205b and the side surface of the conductor 205 a. Here, the height of the top surface of the conductor 205c is substantially equal to the height of the top surface of the conductor 205a and the height of the top surface of the insulator 216. In other words, the conductor 205b is surrounded by the conductor 205a and the conductor 205c.

As the conductor 205a and the conductor 205c, a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO2, or the like), copper atoms, or the like is preferably used. Alternatively, a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, and the like) is preferably used.

By using a conductive material having a function of suppressing diffusion of hydrogen as the conductor 205a and the conductor 205c, diffusion of impurities such as hydrogen contained in the conductor 205b into the metal oxide 230 through the insulator 224 or the like can be suppressed. Further, by using a conductive material having a function of suppressing diffusion of oxygen for the conductor 205a and the conductor 205c, oxidation of the conductor 205b and a decrease in conductivity can be suppressed. As the conductive material having a function of suppressing oxygen diffusion, for example, titanium nitride, tantalum nitride, ruthenium oxide, or the like can be used. Thus, the conductive body 205a may be a single layer or a stacked layer of the above-described conductive material. For example, titanium nitride may be used as the conductor 205 a.

Further, the conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, tungsten may be used for the conductor 205 b.

Here, the conductor 260 is sometimes used as a first gate (also referred to as a top gate) electrode. In addition, the conductor 205 is sometimes used as a second gate (also referred to as a bottom gate) electrode. In this case, V of the transistor 200A can be controlled by independently changing the potential supplied to the conductor 205 without making it interlocked with the potential supplied to the conductor 260 _th . In particular, V of the transistor 200A can be made by supplying a negative potential to the conductor 205 _th Greater than 0V and can reduce off-state current. Therefore, in the case where the negative potential is supplied to the conductor 205, the drain current at the potential of 0V supplied to the conductor 260 can be reduced as compared with the case where the negative potential is not supplied to the conductor 205.

The conductor 205 is preferably larger than the channel formation region in the metal oxide 230. In particular, as shown in fig. 35C, the conductor 205 preferably extends to a region outside the end portion intersecting with the metal oxide 230 in the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 overlap each other with an insulator therebetween on the outer side of the side surface in the channel width direction of the metal oxide 230.

By having the above-described structure, the channel formation region of the metal oxide 230 can be electrically surrounded by the electric field of the conductor 260 serving as the first gate electrode and the electric field of the conductor 205 serving as the second gate electrode.

Further, as shown in fig. 35C, the conductor 205 is extended to serve as a wiring. However, the present invention is not limited to this, and an electric conductor used as a wiring may be provided under the electric conductor 205.

The insulator 214 is preferably used as a blocking insulating film for suppressing entry of impurities such as water or hydrogen into the transistor 200A from the substrate side. Therefore, the insulator 214 preferably has a structure that suppresses hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ₂ O、NO、NO ₂ Etc.), the function of diffusion of impurities such as copper atoms (the impurities are not easily penetrated). Alternatively, an insulating material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, and the like) (which is not easily permeable to the oxygen) is preferably used.

For example, aluminum oxide, silicon nitride, or the like is preferably used as the insulator 214. This can suppress diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200A side with respect to the insulator 214. Alternatively, oxygen contained in the insulator 224 or the like may be suppressed from diffusing to the substrate side more than the insulator 214.

The dielectric constants of the insulator 216, the insulator 280, and the insulator 281 used as interlayer films are preferably lower than those of the insulator 214. By using a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 216, the insulator 280, and the insulator 281, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon and nitrogen, silicon oxide having voids, or the like is suitably used.

Insulator 222 and insulator 224 are used as gate insulators.

Here, in the insulator 224 in contact with the metal oxide 230, oxygen is preferably desorbed by heating. In this specification, oxygen desorbed by heating is sometimes referred to as excess oxygen. For example, silicon oxide, silicon oxynitride, or the like may be appropriately used as the insulator 224. By providing an insulator containing oxygen in contact with the metal oxide 230, oxygen vacancies in the metal oxide 230 can be reduced, and thus the reliability of the transistor 200A can be improved.

Specifically, as the insulator 224, an oxide material that releases a part of oxygen by heating is preferably used. The oxide that releases oxygen by heating means that the amount of oxygen released in terms of oxygen atoms in TDS (Thermal Desorption Spectroscopy: thermal desorption Spectrometry) analysis is 1.0X10 ¹⁸ atoms/cm ³ The above is preferably 1.0X10 ¹⁹ atoms/cm ³ The above is more preferably 2.0X10 ¹⁹ atoms/cm ³ Above, or 3.0X10 ²⁰ atoms/cm ³ The oxide film above. The surface temperature of the film in the TDS analysis is preferably in the range of 100 ℃ to 700 ℃, or 100 ℃ to 400 ℃.

As shown in fig. 35C, the thickness of the region of the insulator 224 which does not overlap with the insulator 254 and does not overlap with the metal oxide 230b may be smaller than the thickness of the other regions. In the insulator 224, a region which does not overlap with the insulator 254 and does not overlap with the metal oxide 230b preferably has a thickness sufficient to diffuse the oxygen.

As with the insulator 214 or the like, the insulator 222 is preferably used as a barrier insulating film for suppressing mixing of impurities such as water and hydrogen into the transistor 200A from the substrate side. For example, insulator 222 preferably has a lower hydrogen permeability than insulator 224. By surrounding the insulator 224, the metal oxide 230, the insulator 250, and the like with the insulator 222, the insulator 254, and the insulator 274, entry of impurities such as water or hydrogen into the transistor 200A from the outside can be suppressed.

The insulator 222 preferably has a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule) (the oxygen is not easily permeated). For example, insulator 222 preferably has a lower oxygen permeability than insulator 224. By providing the insulator 222 with a function of suppressing diffusion of oxygen or impurities, diffusion of oxygen contained in the metal oxide 230 to the substrate side can be reduced, which is preferable. Further, the reaction of the conductor 205 with oxygen contained in the insulator 224 or the metal oxide 230 can be suppressed.

As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium as an insulating material is preferably used. As the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. When the insulator 222 is formed using such a material, the insulator 222 is used as a layer which suppresses release of oxygen from the metal oxide 230 or entry of impurities such as hydrogen into the metal oxide 230 from the peripheral portion of the transistor 200A.

Alternatively, for example, alumina, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Further, the insulator may be subjected to nitriding treatment. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator.

The insulator 222 may be formed of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO) ₃ ) Or (Ba, sr) TiO ₃ (BST), etc., is a so-called high-k material. When miniaturization and high integration of transistors are performed, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material as an insulator to be used as a gate insulator, the gate potential of the transistor when operating can be reduced while maintaining physical thickness.

The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to the laminated structure made of the same material, and may be a laminated structure made of a different material. For example, an insulator similar to the insulator 224 may be provided under the insulator 222.

The metal oxide 230 includes a metal oxide 230a, a metal oxide 230b on the metal oxide 230a, and a metal oxide 230c on the metal oxide 230b. When the metal oxide 230a is provided under the metal oxide 230b, diffusion of impurities from a structure formed under the metal oxide 230a to the metal oxide 230b can be suppressed. When the metal oxide 230c is provided over the metal oxide 230b, diffusion of impurities from a structure formed over the metal oxide 230c to the metal oxide 230b can be suppressed.

The metal oxide 230 preferably has a stacked structure of oxide layers in which the atomic ratios of the metal atoms are different from each other. For example, in the case where the metal oxide 230 contains at least indium (In) and the element M, the atomic ratio of the element M to the other element In the constituent elements of the metal oxide 230a is preferably larger than the atomic ratio of the element M to the other element In the constituent elements of the metal oxide 230b. In addition, the atomic number ratio of the element M to In the metal oxide 230a is preferably larger than the atomic number ratio of the element M to In the metal oxide 230b. Here, the metal oxide 230c may use a metal oxide usable for the metal oxide 230a or the metal oxide 230b.

Preferably, the energy of the conduction band bottoms of the metal oxide 230a and the metal oxide 230c is made higher than the energy of the conduction band bottom of the metal oxide 230 b. In other words, the electron affinities of the metal oxide 230a and the metal oxide 230c are preferably smaller than the electron affinities of the metal oxide 230 b. In this case, the metal oxide 230c is preferably a metal oxide that can be used for the metal oxide 230 a. Specifically, the atomic number ratio of the element M to the other elements in the constituent elements of the metal oxide 230c is preferably larger than the atomic number ratio of the element M to the other elements in the constituent elements of the metal oxide 230 b. Further, the atomic number ratio of the element M to In the metal oxide 230c is preferably larger than the atomic number ratio of the element M to In the metal oxide 230 b.

Here, in the junction of the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c, the energy level of the conduction band bottom changes gently. In other words, the above-described case may be expressed as that the energy level of the conduction band bottom of the junction of the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c is continuously changed or continuously joined. For this reason, it is preferable to reduce the defect state density of the mixed layer formed at the interface of the metal oxide 230a and the metal oxide 230b and the interface of the metal oxide 230b and the metal oxide 230 c.

Specifically, by including a common element (main component) in addition to oxygen in the metal oxide 230a and the metal oxide 230b and the metal oxide 230c, a mixed layer having a low defect state density can be formed. For example, in the case where the metal oxide 230b is an in—ga—zn oxide, a ga—zn oxide, gallium oxide, or the like can be used as the metal oxide 230a and the metal oxide 230 c. In addition, the metal oxide 230c may have a stacked structure. For example, a stacked structure of an In-Ga-Zn oxide and a Ga-Zn oxide on the In-Ga-Zn oxide may be used, or a stacked structure of an In-Ga-Zn oxide and a gallium oxide on the In-Ga-Zn oxide may be used. In other words, as the metal oxide 230c, a stacked structure of an in—ga—zn oxide and an oxide containing no In may be used.

Specifically, as the metal oxide 230a, in: ga: zn=1: 3:4[ atomic number ratio ] or 1:1:0.5[ atomic number ratio ]. In addition, as the metal oxide 230b, in: ga: zn=4: 2:3[ atomic number ratio ] or 3:1:2[ atomic number ratio ]. In addition, as the metal oxide 230c, in: ga: zn=1: 3:4[ atomic number ratio ], in: ga: zn=4: 2:3[ atomic number ratio ], ga: zn=2: 1[ atomic ratio ] or Ga: zn=2: 5[ atomic number ratio ]. In addition, as a specific example of the case where the metal oxide 230c has a stacked-layer structure, in: ga: zn=4: 2:3[ atomic ratio ] and Ga: zn=2: 1[ atomic ratio ], in: ga: zn=4: 2:3[ atomic ratio ] and Ga: zn=2: 5[ atomic ratio ], in: ga: zn=4: 2:3[ atomic number ratio ] and a stacked structure of gallium oxide.

At this time, the main path of the carriers is the metal oxide 230b. By providing the metal oxide 230a and the metal oxide 230c with the above-described structure, the defect state density at the interface between the metal oxide 230a and the metal oxide 230b and at the interface between the metal oxide 230b and the metal oxide 230c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and thus the transistor 200A can obtain a large on-state current and high frequency characteristics. In addition, when the metal oxide 230c has a stacked-layer structure, an effect of reducing the defect state density at the interface between the metal oxide 230b and the metal oxide 230c and an effect of suppressing diffusion of constituent elements contained in the metal oxide 230c to the insulator 250 side are expected. More specifically, when the metal oxide 230c has a stacked-layer structure, since an oxide containing no In is located above the stacked-layer structure, in which is diffused to the insulator 250 side can be suppressed. Since the insulator 250 is used as a gate insulator, poor characteristics of the transistor are caused In the case where In diffuses therein. Thus, by providing the metal oxide 230c with a stacked structure, a highly reliable display device can be provided.

A conductor 242 (a conductor 242a and a conductor 242 b) serving as a source electrode and a drain electrode is provided over the metal oxide 230 b. As the conductor 242, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above metal element as a component, an alloy in which the above metal element is combined, or the like is preferably used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like is preferably used. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are conductive materials which are not easily oxidized or materials which absorb oxygen and maintain conductivity are preferable.

By forming the above-described conductor 242 so as to be in contact with the metal oxide 230, the oxygen concentration in the vicinity of the conductor 242 in the metal oxide 230 sometimes decreases. In addition, a metal compound layer including a metal included in the conductor 242 and a component of the metal oxide 230 is sometimes formed near the conductor 242 in the metal oxide 230. In this case, the carrier density increases in the region near the conductor 242 of the metal oxide 230, and the resistance of the region decreases.

Here, a region between the conductors 242a and 242b is formed so as to overlap with the opening of the insulator 280. Accordingly, the conductor 260 can be arranged self-aligned between the conductor 242a and the conductor 242 b.

The insulator 250 is used as a gate insulator. Insulator 250 is preferably disposed in contact with the top surface of metal oxide 230 c. As the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon and nitrogen, silicon oxide having voids can be used. In particular, silicon oxide and silicon oxynitride are preferable because they have thermal stability.

Like the insulator 224, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 250. The thickness of the insulator 250 is preferably 1nm or more and 20nm or less.

Further, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably inhibits oxygen diffusion from insulator 250 to conductor 260. This can suppress oxidation of the conductor 260 due to oxygen in the insulator 250.

In addition, the metal oxide is sometimes used as part of a gate insulator. Therefore, in the case where silicon oxide, silicon oxynitride, or the like is used for the insulator 250, a metal oxide which is a high-k material having a high relative dielectric constant is preferably used as the metal oxide. By providing the gate insulator with a stacked structure of the insulator 250 and the metal oxide, a stacked structure having high thermal stability and a high relative dielectric constant can be formed. Accordingly, the gate potential applied when the transistor operates can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness of the insulator used as the gate insulator (EOT: equivalent oxide thickness) can be reduced.

Specifically, a metal oxide containing one or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used. In particular, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as an insulator containing an oxide of one or both of aluminum and hafnium.

Although the conductor 260 has a two-layer structure in fig. 35, it may have a single-layer structure or a stacked structure of three or more layers.

The conductive material 260a preferably has the above-mentioned function of suppressing a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, and a nitrogen oxide molecule (N ₂ O、NO、NO ₂ Etc.), a conductor having a function of diffusing impurities such as copper atoms. Further, a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, and the like) is preferably used.

Further, when the conductor 260a has a function of suppressing diffusion of oxygen, oxygen contained in the insulator 250 can be suppressed from oxidizing the conductor 260b, resulting in a decrease in conductivity. As the conductive material having a function of suppressing diffusion of oxygen, for example, tantalum nitride, ruthenium oxide, or the like is preferably used.

As the conductor 260b, a conductive material containing tungsten, copper, or aluminum as a main component is preferably used. Further, since the conductor 260 is also used as a wiring, a conductor having high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as a main component may be used. The conductor 260b may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above-described conductive material.

Further, as shown in fig. 35A and 35C, in a region of the metal oxide 230b which does not overlap with the conductor 242, that is, in a channel formation region of the metal oxide 230, a side surface of the metal oxide 230 is covered with the conductor 260. Thereby, the electric field of the conductor 260 used as the first gate electrode can be easily influenced to the side face of the metal oxide 230. This can improve the on-state current and frequency characteristics of the transistor 200A.

The insulator 254 is preferably used as a block insulating film for preventing impurities such as water and hydrogen from being mixed into the transistor 200A from the side of the insulator 280, similarly to the insulator 214 and the like. For example, insulator 254 preferably has a lower hydrogen permeability than insulator 224. Further, as shown in fig. 35B and 35C, the insulator 254 is preferably in contact with the side surface of the metal oxide 230C, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242B, the side surfaces of the metal oxide 230a and the metal oxide 230B, and the top surface of the insulator 224. By adopting such a structure, hydrogen contained in the insulator 280 can be suppressed from entering the metal oxide 230 from the top surface or the side surface of the conductor 242a, the conductor 242b, the metal oxide 230a, the metal oxide 230b, and the insulator 224.

The insulator 254 also has a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule) (the oxygen is not easily permeated). For example, insulator 254 preferably has a lower oxygen permeability than insulator 280 or insulator 224.

The insulator 254 is preferably deposited by sputtering. Oxygen may be added to the vicinity of the region of the insulator 224 in contact with the insulator 254 by depositing the insulator 254 using a sputtering method under an atmosphere containing oxygen. Thereby, oxygen can be supplied from this region into the metal oxide 230 through the insulator 224. Here, by providing the insulator 254 with a function of suppressing diffusion of oxygen to the upper side, diffusion of oxygen from the metal oxide 230 to the insulator 280 can be prevented. Further, by making the insulator 222 have a function of suppressing diffusion of oxygen to the lower side, diffusion of oxygen from the metal oxide 230 to the substrate side can be prevented. Thus, oxygen is supplied to the channel formation region in the metal oxide 230. Thus, oxygen vacancies of the metal oxide 230 can be reduced and normally-on activation of the transistor can be suppressed.

As the insulator 254, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be deposited. Note that as an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used.

By covering the insulator 224, the insulator 250, and the metal oxide 230 with the insulator 254 having a barrier property to hydrogen, the insulator 280 is separated from the insulator 224, the metal oxide 230, and the insulator 250 by the insulator 254. This can suppress the entry of impurities such as hydrogen from the outside of the transistor 200A, and can provide the transistor 200A with good electrical characteristics and reliability.

Insulator 280 is preferably disposed on insulator 224, metal oxide 230 and conductor 242 through insulator 254. For example, the insulator 280 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon and nitrogen, silicon oxide having voids, or the like. In particular, silicon oxide and silicon oxynitride are preferable because they have thermal stability. In particular, a material such as silicon oxide, silicon oxynitride, or silicon oxide having voids is preferable because it is easy to form a region containing oxygen which is released by heating.

Further, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. In addition, the top surface of insulator 280 may also be planarized.

The insulator 274 is preferably used as a barrier insulating film for suppressing the contamination of impurities such as water or hydrogen into the insulator 280 from above, similarly to the insulator 214. As the insulator 274, for example, an insulator that can be used for the insulator 214, the insulator 254, or the like can be used.

An insulator 281 serving as an interlayer film is preferably provided over the insulator 274. As with the insulator 224, the concentration of impurities such as water and hydrogen in the insulator 281 is preferably reduced.

Further, the conductors 240a and 240b are disposed in openings formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 254. The conductors 240a and 240b are disposed so as to sandwich the conductor 260. In addition, the top surfaces of the conductors 240a and 240b may be on the same plane as the top surface of the insulator 281.

Further, an insulator 241a is provided so as to be in contact with the inner walls of the openings of the insulator 281, the insulator 274, the insulator 280, and the insulator 254, and a first conductor of the conductor 240a is formed so as to be in contact with the side surfaces thereof. At least a portion of the bottom of the opening is located a conductor 242a, and conductor 240a is in contact with conductor 242 a. Similarly, an insulator 241b is provided so as to contact the inner walls of the openings of the insulators 281, 274, 280, and 254, and a first conductor of the conductor 240b is formed so as to contact the side surfaces thereof. At least a portion of the bottom of the opening is located a conductor 242b, and conductor 240b is in contact with conductor 242 b.

The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240a and the conductor 240b may have a stacked structure.

When a stacked-layer structure is used as the conductor 240, the conductor having a function of suppressing diffusion of impurities such as water and hydrogen is preferably used as the conductor in contact with the metal oxide 230a, the metal oxide 230b, the conductor 242, the insulator 254, the insulator 280, the insulator 274, and the insulator 281. For example, tantalum nitride, titanium nitride, ruthenium oxide, or the like is preferably used. The conductive material having a function of suppressing diffusion of impurities such as water or hydrogen can be used in a single layer or a stacked layer. By using this conductive material, oxygen added to the insulator 280 can be prevented from being absorbed by the conductors 240a and 240 b. Further, impurities such as water and hydrogen can be prevented from entering the metal oxide 230 from a layer above the insulator 281 through the conductors 240a and 240 b.

As the insulator 241a and the insulator 241b, for example, an insulator that can be used for the insulator 254 or the like may be used. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 254, the metal oxide 230 can be prevented from being mixed with impurities such as water and hydrogen from the insulator 280 through the conductors 240a and 240 b. Further, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240 b.

Although not shown, conductors used as wirings may be arranged so as to be in contact with the top surface of the conductor 240a and the top surface of the conductor 240 b. The conductor used as the wiring preferably uses a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may have a stacked structure, for example, a stacked structure of titanium, titanium nitride, and the above-described conductive material. The conductor may be formed so as to be fitted into the opening of the insulator.

< materials constituting transistors >

The following describes constituent materials that can be used for the transistor.

[ substrate ]

As a substrate for forming the transistor 200A, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used, for example. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon, germanium, or the like, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like. Further, a semiconductor substrate having an insulator region inside the semiconductor substrate may be exemplified by an SOI (Silicon On Insulator; silicon on insulator) substrate or the like. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, a substrate containing a metal nitride, a substrate containing a metal oxide, or the like can be given. Further, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, or the like can be also mentioned. Alternatively, a substrate having an element provided over these substrates may be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light-emitting element, and a memory element.

[ insulator ]

Examples of the insulator include insulating oxides, nitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides.

For example, when miniaturization and high integration of transistors are performed, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material as an insulator used as a gate insulator, a low voltage at the time of transistor operation can be achieved while maintaining physical thickness. On the other hand, by using a material having a low relative dielectric constant for an insulator used as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, the material is preferably selected according to the function of the insulator.

Examples of the insulator having a relatively high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

Examples of the insulator having a low relative dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon and nitrogen, silicon oxide having voids, and resin.

The transistor using the oxide semiconductor is surrounded by an insulator (the insulator 214, the insulator 222, the insulator 254, the insulator 274, or the like) having a function of suppressing permeation of impurities such as hydrogen and oxygen, whereby the electric characteristics of the transistor can be stabilized. As an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, a metal nitride such as aluminum nitride, aluminum titanium nitride, silicon oxynitride, or silicon nitride can be used.

The insulator used as the gate insulator is preferably an insulator having a region containing oxygen which is desorbed by heating. For example, by adopting a structure in which silicon oxide or silicon oxynitride having a region containing oxygen which is desorbed by heating is in contact with the metal oxide 230, oxygen vacancies contained in the metal oxide 230 can be filled.

[ electric conductor ]

As the conductor, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, and the like, an alloy containing the above metal element as a component, an alloy in which the above metal element is combined, or the like is preferably used. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like is preferably used. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are conductive materials which are not easily oxidized or materials which absorb oxygen and maintain conductivity are preferable. Further, a semiconductor having high conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and a silicide such as nickel silicide may be used.

In addition, a plurality of conductive layers formed of the above materials may be stacked. For example, a stacked-layer structure of a material containing the above metal element and a conductive material containing oxygen may be used. In addition, a stacked structure of a material containing the above metal element and a conductive material containing nitrogen may be used. In addition, a stacked-layer structure in which a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may also be employed.

In addition, in the case where a metal oxide is used for a channel formation region of a transistor, a stacked-layer structure in which a material containing the above-described metal element and a conductive material containing oxygen are combined is preferably used as a conductive body to be used as a gate electrode. In this case, it is preferable to provide a conductive material containing oxygen on the channel formation region side. By disposing the conductive material containing oxygen on the channel formation region side, oxygen detached from the conductive material is easily supplied to the channel formation region.

In particular, as the conductor used as the gate electrode, a conductive material containing a metal element and oxygen contained in a metal oxide forming a channel is preferably used. In addition, a conductive material containing the above metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide to which silicon is added may be used. In addition, indium gallium zinc oxide containing nitrogen may also be used. By using the above material, hydrogen contained in the channel-forming metal oxide may be trapped in some cases. Alternatively, hydrogen entering from an insulator or the like outside may be trapped in some cases.

< structural example of light-emitting element 70 >

As shown in fig. 36A, the EL layer 786 included in the light-emitting element 70 may be formed of a plurality of layers such as the layer 4420, the light-emitting layer 4411, and the layer 4430. The layer 4420 may include, for example, a layer containing a substance having high electron injection property (an electron injection layer), a layer containing a substance having high electron transport property (an electron transport layer), or the like. The light-emitting layer 4411 includes, for example, a light-emitting compound. The layer 4430 may include, for example, a layer containing a substance having high hole injection property (a hole injection layer) and a layer containing a substance having high hole transport property (a hole transport layer).

The structure including the layer 4420, the light-emitting layer 4411, and the layer 4430 provided between a pair of electrodes can be used as a single light-emitting unit, and the structure of fig. 36A is referred to as a single structure in this specification.

As shown in fig. 36B, a structure in which a plurality of light-emitting layers (a light-emitting layer 4411, a light-emitting layer 4412, and a light-emitting layer 4413) are provided between the layers 4420 and 4430 is also a modification example of a single structure.

As shown in fig. 36C, a structure in which a plurality of light emitting units (EL layers 786a and 786 b) are connected in series with an intermediate layer (charge generation layer) 4440 interposed therebetween is referred to as a series structure in this specification. In this specification and the like, the structure shown in fig. 36C is referred to as a series structure, but is not limited thereto, and for example, the series structure may be also referred to as a stacked structure. By adopting the series structure, a light-emitting element capable of emitting light with high luminance can be realized.

The light emitting color of the light emitting element 70 may be red, green, blue, cyan, magenta, yellow, white, or the like depending on the material constituting the EL layer 786. In addition, by providing the light-emitting element 70 with a microcavity structure, color purity can be further improved.

The white light-emitting element preferably has a structure in which the light-emitting layer contains two or more kinds of light-emitting substances. In order to obtain white light emission, two or more kinds of light-emitting substances each having a complementary color relationship may be selected.

The light-emitting layer preferably contains two or more light-emitting substances that emit light such as R (red), G (green), B (blue), Y (yellow), and O (orange). Further, it is preferable to include two or more light-emitting substances, wherein the light emission of each light-emitting substance includes spectral components of two or more colors in R, G, B.

< method of Forming light-emitting element 70 >

A method for forming the light emitting element 70 provided in the pixel circuit 62 will be described below.

Fig. 37A is a schematic plan view of a light-emitting element 70 according to an embodiment of the present invention. The light emitting element 70 includes a plurality of light emitting elements 70R that exhibit red, a plurality of light emitting elements 70G that exhibit green, and a plurality of light emitting elements 70B that exhibit blue. In fig. 37A, symbols "R", "G", and "B" are attached to the light emitting regions of the light emitting elements for the convenience of distinguishing the light emitting elements. The structure of the light-emitting element 70 shown in fig. 37A may be referred to as a SBS (Side By Side) structure. Further, although fig. 37A illustrates a structure including three colors of red (R), green (G), and blue (B), it is not limited thereto. For example, the color filter may have a structure including four or more colors.

The light emitting elements 70R, 70G, and 70B are all arranged in a matrix. Fig. 37A shows a so-called stripe arrangement in which light emitting elements emitting the same color are arranged in one direction. Note that the arrangement method of the light emitting elements is not limited to this, and a triangle arrangement, a zigzag arrangement, or the like may be used, or a Pentile arrangement may be used.

As the light-emitting elements 70R, 70G, and 70B, organic EL devices such as an OLED (Organic Light Emitting Diode: organic light-emitting diode) or a QLED (Quantum-dot Light Emitting Diode: quantum dot light-emitting diode) are preferably used. Examples of the light-emitting substance included in the EL element include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), an inorganic compound (quantum dot material, etc.), a substance that exhibits thermally activated delayed fluorescence (Thermally activated delayed fluorescence: TADF) material), and the like. Note that as the TADF material, a material in which a singlet excited state and a triplet excited state are in a thermal equilibrium state may be used. Note that as the TADF material, a material in which a singlet excited state and a triplet excited state are in a thermal equilibrium state may be used.

Fig. 37B is a schematic cross-sectional view corresponding to the chain line A1-A2 in fig. 37A.

Fig. 37B shows a cross section of the light emitting element 70R, the light emitting element 70G, and the light emitting element 70B. The light emitting element 70R, the light emitting element 70G, and the light emitting element 70B are provided over the substrate 251 and include a conductor 772 serving as a pixel electrode and a conductor 788 serving as a common electrode.

The light-emitting element 70R includes an EL layer 786R between a conductor 772 serving as a pixel electrode and a conductor 788 serving as a common electrode. The EL layer 786R contains a light-emitting organic compound that emits light having a peak at least in a red wavelength region. The EL layer 786G in the light-emitting element 70G contains a light-emitting organic compound that emits light having a peak at least in a green wavelength region. The EL layer 786B included in the light-emitting element 70B contains a light-emitting organic compound that emits light having a peak at least in a blue wavelength region.

The EL layer 786R, EL layer 786G and the EL layer 786B may each include one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting organic compound (light-emitting layer).

Each light emitting element is provided with a conductive body 772 serving as a pixel electrode. The conductor 788 used as a common electrode is a continuous layer common to the light-emitting elements. Either one of the conductor 772 serving as a pixel electrode and the conductor 788 serving as a common electrode uses a conductive film having transparency to visible light, and the other uses a conductive film having reflectivity. A bottom emission type (bottom emission structure) display device can be manufactured by making the conductor 772 serving as a pixel electrode light transmissive and the conductor 788 serving as a common electrode light transmissive, whereas a top emission type (top emission structure) display device can be manufactured by making the conductor 772 serving as a pixel electrode light transmissive and the conductor 788 serving as a common electrode light transmissive. Note that by making both the conductor 772 serving as a pixel electrode and the conductor 788 serving as a common electrode have light transmittance, a double-sided emission type (double-sided emission structure) display device can also be manufactured.

The insulating layer 272 is provided so as to cover the end portion of the conductor 772 serving as a pixel electrode. The end of the insulating layer 272 is preferably tapered.

The EL layer 786R, EL layer 786G and the EL layer 786B each include a region in contact with the top surface of the conductive body 772 serving as a pixel electrode and a region in contact with the surface of the insulating layer 272. In addition, the end portions of the EL layer 786R, EL layer 786G and the EL layer 786B are over the insulating layer 272.

As shown in fig. 37B, a gap is provided between the two EL layers between the light emitting elements having different colors. Thus, the EL layers 786R, EL and 786G and 786B are preferably provided so as not to contact each other. Thus, it is possible to appropriately prevent current from flowing through the adjacent two EL layers to generate unintended light emission (also referred to as crosstalk). This can improve contrast, and a display device with high display quality can be realized.

Vacuum using shadow mask such as metal mask the EL layer 786R, EL layer 786G and the EL layer 786G are formed by vapor deposition. The EL layer may be manufactured separately by photolithography. By using the photolithography method, a high-definition display device which is difficult to realize when using a metal mask can be realized.

Further, a protective layer 271 is provided over the conductor 788 serving as a common electrode so as to cover the light-emitting element 70R, the light-emitting element 70G, and the light-emitting element 70B. The protective layer 271 has a function of preventing water and other impurities from going up the light-emitting elements are diffused.

The protective layer 271 may have a single-layer structure or a stacked-layer structure including at least an inorganic insulating film, for example. As the inorganic insulating film, for example, an oxide film or a nitride film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, or a hafnium oxide film can be used. Further, a semiconductor material such as indium gallium oxide or indium gallium zinc oxide may be used for the protective layer 271. Note that the protective layer 271 can be formed by an ALD method, a CVD method, or a sputtering method. Note that although a structure including an inorganic insulating film is illustrated as the protective layer 271, but is not limited thereto. For example, the protective layer 271 may have a stacked structure of an inorganic insulating film and an organic insulating film.

Fig. 37C shows an example different from the above-described structure.

Fig. 37C includes a light-emitting element 70W that emits white light. The light-emitting element 70W includes an EL layer 786W that exhibits white light between a pixel electrode and a conductor 788 serving as a common electrode.

For example, two or more light-emitting layers selected so that the respective light-emitting colors are in a complementary relationship may be stacked as the EL layer 786W. In addition, a stacked EL layer in which a charge generation layer is sandwiched between light-emitting layers may be used.

Fig. 37C shows three light emitting elements 70W in parallel. The upper portion of the light-emitting element 70W on the left is provided with a colored layer 264R. The colored layer 264R is used as a bandpass filter transmitting red light. Similarly, a coloring layer 264G transmitting green light is provided on the upper portion of the middle light-emitting element 70W, and a coloring layer 264B transmitting blue light is provided on the upper portion of the right light-emitting element 70W. Thereby, the display device can be caused to display a color image.

Here, between the adjacent two light emitting elements 70W, the EL layer 786W and the conductor 788 serving as a common electrode are separated from each other. Thus, unintended light emission can be appropriately prevented from occurring by the current flowing through the EL layer 786W in the adjacent two light-emitting elements 70W. In particular, when a stacked EL element having a charge generation layer between two light emitting layers is used as the EL layer 786W, there are the following problems: when the sharpness is higher, that is, the distance between adjacent pixels is smaller, the influence of crosstalk is more remarkable, and the contrast is lowered. Therefore, by adopting such a structure, a display device having both high definition and high contrast can be realized.

The EL layer 786W is preferably separated by photolithography and the conductor 788 is used as a common electrode. Thus, the gap between the light emitting elements can be reduced, and a display device having a high aperture ratio can be realized, for example, as compared with the case of using a shadow mask such as a metal mask.

Note that the light-emitting element of the bottom emission structure may be provided with a coloring layer between the conductor 772 serving as a pixel electrode and the substrate 251.

Fig. 38A shows an example different from the above-described structure. Specifically, in fig. 38A, the insulating layer 272 is not provided between the light-emitting elements 70R, 70G, and 70B. By adopting this structure, a display device having a high aperture ratio can be realized. The protective layer 271 covers the side surfaces of the light-emitting elements 70R, 70G, and 70B. By adopting this structure, impurities (typically, water or the like) which may enter from the side surfaces of the light-emitting elements 70R, 70G, and 70B can be suppressed. In the structure shown in fig. 38A, the top surfaces of the conductor 772, the EL layer 786R, and the conductor 788 are substantially uniform in shape. Such a structure can be formed simultaneously with the formation of the conductor 772, the EL layer 786R, and the conductor 788 using a resist mask or the like. This process can also be referred to as self-aligned patterning because the EL layer 786R and the conductor 788 are processed using the conductor 788 as a mask. Note that although the light-emitting element 70R is described here, the light-emitting element 70G and the light-emitting element 70B may have the same configuration.

In fig. 38A, a protective layer 758 is further provided on the protective layer 271. For example, the region 759 can be provided between the protective layer 271 and the protective layer 758 by forming the protective layer 271 by an apparatus capable of depositing a film having higher coverage (typically, an ALD apparatus or the like) and forming the protective layer 758 by an apparatus capable of depositing a film having lower coverage than the protective layer 271 (typically, a sputtering apparatus). Note that in other words, the region 759 is located between the light emitting element 70R and the light emitting element 70G and between the light emitting element 70G and the light emitting element 70B.

The region 759 contains, for example, any one or more selected from air, nitrogen, oxygen, carbon dioxide, group 18 elements (typically helium, neon, argon, krypton, xenon, or the like), and the like. In addition, the region 759 may contain, for example, a gas used when the protective layer 758 is deposited. For example, when the protective layer 758 is deposited by sputtering, the region 759 may contain any one or more of the group 18 elements described above. Note that when the region 759 contains a gas, gas identification or the like can be performed by gas chromatography or the like. Alternatively, when the protective layer 758 is deposited by sputtering, a gas used for sputtering may be contained in the film of the protective layer 758. In this case, when the protective layer 758 is analyzed by energy dispersive X-ray analysis (EDX analysis (Energy Dispersive X-ray fluorescence)), an element such as argon may be detected.

When the refractive index of the region 759 is lower than that of the protective layer 271, light emitted from the light-emitting element 70R, the light-emitting element 70G, or the light-emitting element 70B is reflected at the interface between the protective layer 271 and the region 759. Thus, light emitted from the light-emitting element 70R, the light-emitting element 70G, or the light-emitting element 70B can be suppressed from entering adjacent pixels. Thus, the light of different colors can be suppressed from being mixed together, and the image quality of the display device can be improved.

In addition, when the structure shown in fig. 38A is employed, a region between the light-emitting elements 70R and 70G or a region between the light-emitting elements 70G and 70B (hereinafter, simply referred to as a distance between the light-emitting elements) may be narrowed. Specifically, the distance between the light-emitting elements may be 1 μm or less, preferably 500nm or less, more preferably 200nm or less, 100nm or less, 90nm or less, 70nm or less, 50nm or less, 30nm or less, 20nm or less, 15nm or less, or 10nm. In other words, the light emitting device has a region in which the distance between the side surface of the light emitting element 70R and the side surface of the light emitting element 70G or the distance between the side surface of the light emitting element 70G and the side surface of the light emitting element 70B is 1 μm or less, preferably a region of 0.5 μm (500 nm) or less, and more preferably a region of 100nm or less.

In addition, for example, when the region 759 contains a gas, mixing of light from each light-emitting element, crosstalk, or the like can be suppressed while element separation between light-emitting elements is performed.

The region 759 may have an insulating layer containing an organic material. For example, the region 759 may be filled with an acrylic resin, a polyimide resin, an epoxy resin, an imine resin, a polyamide resin, a polyimide amide resin, a silicone resin, a siloxane resin, a benzocyclobutene resin, a phenol resin, a precursor of these resins, or the like. The region 759 may be filled with a photosensitive resin. As the photosensitive resin, a photoresist may be used. Positive type materials or negative type materials may be used as the photosensitive resin.

The region 759 may have an insulating layer containing an inorganic material. As the inorganic material, for example, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or an oxynitride insulating film can be used. The inorganic insulating film may have a single-layer structure or a stacked-layer structure. Examples of the oxide insulating film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. The nitride insulating film may be a silicon nitride film, an aluminum nitride film, or the like. As the oxynitride insulating film, a silicon oxynitride film, an aluminum oxynitride film, or the like can be given. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, and the like.

The region 759 preferably contains both the inorganic material and the organic material. For example, the region 759 may be an aluminum oxide film and a photoresist layer formed on the aluminum oxide film.

Fig. 38B shows an example different from the above-described structure. Specifically, the structure shown in fig. 38B is different from that shown in fig. 38A in the structure of the substrate 251. A part of the top surface of the substrate 251 is scraped off and has a concave portion when the light-emitting elements 70R, 70G, and 70B are processed. The protective layer 271 is formed in the recess. In other words, the bottom surface having the protective layer 271 is located in a region below the bottom surface of the electrical conductor 772 when viewed in cross section. By having this region, impurities (typically, water or the like) which can enter the light-emitting element 70R, the light-emitting element 70G, and the light-emitting element 70B from below can be appropriately suppressed. The recessed portions may be formed by removing impurities (also referred to as residues) which may adhere to the side surfaces of the light-emitting elements 70R, 70G, and 70B during processing by wet etching or the like. By covering the side surfaces of each light-emitting element with the protective layer 271 after removing the residues, a highly reliable display device can be realized.

Fig. 38C shows an example different from the above-described structure. Specifically, the structure shown in fig. 38C includes an insulating layer 776 and a microlens array 777 in addition to the structure shown in fig. 38B. The insulating layer 776 is used as an adhesive layer. In addition, when the refractive index of the insulating layer 776 is lower than that of the microlens array 777, the microlens array 777 can collect light emitted from the light emitting elements 70R, 70G, and 70B. Thus, the light extraction efficiency of the display device can be improved. Especially, when the user views the display surface of the display device from the front, a bright image can be seen, which is preferable. As the insulating layer 776, a light-curable adhesive such as an ultraviolet-curable adhesive, a reaction-curable adhesive, a heat-curable adhesive, an anaerobic adhesive, or the like can be used. Examples of such binders include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene-vinyl acetate) resins. Particularly, a material having low moisture permeability such as epoxy resin is preferably used. In addition, a two-liquid mixed type resin may be used. In addition, an adhesive sheet or the like may be used.

In this specification and the like, a device using a Metal Mask or an FMM (Fine Metal Mask) is sometimes referred to as a MM (Metal Mask) structure. In this specification and the like, a device that does not use a metal mask or an FMM is referred to as a MML (Metal Mask Less) structure.

The above is a description of the light emitting element.

At least a part of this embodiment can be implemented in combination with other embodiments described in this specification as appropriate.

Embodiment 4

In this embodiment mode, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment mode is described.

< classification of Crystal Structure >

First, classification of crystal structures in an oxide semiconductor is described with reference to fig. 39A. Fig. 39A is a diagram illustrating classification of crystal structures of an oxide semiconductor, typically IGZO (metal oxide containing In, ga, and Zn).

As shown in fig. 39A, the oxide semiconductor is roughly classified into "amorphus", "Crystal", and "Crystal". Furthermore, completely Amorphous is contained in "Amorphos". In addition, "Crystalline" includes CAAC (c-axis-aligned Crystalline), nc (nanocrystalline) and CAC (closed-aligned composite). In addition, single crystals, poly crystals, and completely amorphous are not included in the category of "crystal". The "Crystal" includes single Crystal and poly Crystal.

The structure in the thickened portion of the outer frame line shown in fig. 39A is an intermediate state between "amorphorus" and "Crystal", and belongs to a new boundary region (New crystalline phase). That is, this structure is said to be a completely different structure from "Crystal" or "amorphorus" which is unstable in energy.

In addition, the crystal structure of the film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Here, fig. 39B shows an XRD spectrum of the CAAC-IGZO film classified as "crystal" obtained by GIXD (grading-incoedence XRD) measurement. Furthermore, the GIXD process is also referred to as a thin film process or a Seemann-Bohlin process. The XRD spectrum obtained by the GIXD measurement shown in fig. 39B is simply referred to as XRD spectrum. Further, the composition of the CAAC-IGZO film shown In fig. 39B is In: ga: zn=4: 2: around 3[ atomic number ratio ]. Further, the CAAC-IGZO film shown in FIG. 39B has a thickness of 500nm.

As shown in fig. 39B, a peak showing clear crystallinity was detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating the c-axis orientation was detected in the vicinity of 2θ=31°. As shown in fig. 39B, the peak around 2θ=31° is asymmetric right and left with the angle at which the peak intensity is detected as the axis.

In addition, the crystal structure of the film or the substrate can be evaluated using a diffraction pattern (also referred to as a nanobeam electron diffraction pattern) observed by a nanobeam electron diffraction method (NBED: nano Beam Electron Diffraction). Fig. 39C shows the diffraction pattern of the CAAC-IGZO film. Fig. 39C is a diffraction pattern observed by the NBED that makes the electron beam incident in a direction parallel to the substrate. Further, the composition of the CAAC-IGZO film shown In fig. 39C is In: ga: zn=4: 2: around 3[ atomic number ratio ]. In addition, in the nano-beam electron diffraction method, an electron diffraction method having a beam diameter of 1nm was performed.

As shown in fig. 39C, a plurality of spots indicating the C-axis orientation were observed in the diffraction pattern of the CAAC-IGZO film.

[ Structure of oxide semiconductor ]

In addition, in the case where attention is paid to the crystal structure of the oxide semiconductor, the classification of the oxide semiconductor may be different from fig. 39A. For example, oxide semiconductors can be classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors other than the single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include the CAAC-OS and nc-OS described above. The non-single crystal oxide semiconductor includes a polycrystalline oxide semiconductor, an a-like OS (amorphorus-like oxide semiconductor), an amorphous oxide semiconductor, and the like.

Details of the CAAC-OS, nc-OS, and a-like OS will be described herein.

[CAAC-OS]

The CAAC-OS is an oxide semiconductor including a plurality of crystal regions, the c-axis of which is oriented in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystallization region is a region having periodicity of atomic arrangement. Note that the crystal region is also a region in which lattice arrangements are uniform when the atomic arrangements are regarded as lattice arrangements. The CAAC-OS may have a region where a plurality of crystal regions are connected in the a-b plane direction, and the region may have distortion. In addition, distortion refers to a portion in which the direction of lattice arrangement changes between a region in which lattice arrangements are uniform and other regions in which lattice arrangements are uniform among regions in which a plurality of crystal regions are connected. In other words, CAAC-OS refers to an oxide semiconductor that is c-axis oriented and has no significant orientation in the a-b plane direction.

Each of the plurality of crystal regions is composed of one or more fine crystals (crystals having a maximum diameter of less than 10 nm). In the case where the crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10nm. In the case where the crystal region is composed of a plurality of fine crystals, the size of the crystal region may be about several tens of nm.

In addition, in-M-Zn oxide (element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, and the like), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) In which a layer containing indium (In) and oxygen (hereinafter, in layer) and a layer containing element M, zinc (Zn) and oxygen (hereinafter, (M, zn layer) are stacked. Furthermore, indium and the element M may be substituted for each other. Therefore, the (M, zn) layer sometimes contains indium. In addition, the In layer sometimes contains an element M. Note that sometimes the In layer contains Zn. The layered structure is observed as a lattice image, for example in a high resolution TEM image.

For example, when structural analysis is performed on a CAAC-OS film using an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in Out-of-plane XRD measurement using θ/2θ scanning. Note that the position (2θ value) of the peak indicating the c-axis orientation may vary depending on the kind, composition, and the like of the metal element constituting the CAAC-OS.

Further, for example, a plurality of bright spots (spots) are observed in the electron diffraction pattern of the CAAC-OS film. In addition, when a spot of an incident electron beam (also referred to as a direct spot) passing through a sample is taken as a symmetry center, a certain spot and other spots are observed at a point-symmetrical position.

When the crystal region is observed from the above specific direction, the lattice arrangement in the crystal region is basically a hexagonal lattice, but the unit cell is not limited to a regular hexagon, and may be a non-regular hexagon. In addition, the distortion may have a lattice arrangement such as pentagonal or heptagonal. In addition, no clear grain boundaries (grainbounding) were observed near the distortion of CAAC-OS. That is, distortion of the lattice arrangement suppresses the formation of grain boundaries. This is probably because CAAC-OS can accommodate distortion due to low density of arrangement of oxygen atoms in the a-b face direction or change in bonding distance between atoms due to substitution of metal atoms, or the like.

In addition, the crystal structure of the definite grain boundary is confirmed to be called poly crystal (polycrystalline). Since the grain boundary serves as a recombination center and carriers are trapped, there is a possibility that on-state current of the transistor is lowered, field effect mobility is lowered, or the like. Therefore, CAAC-OS, in which no definite grain boundary is confirmed, is one of crystalline oxides that provide a semiconductor layer of a transistor with an excellent crystal structure. Note that, in order to constitute the CAAC-OS, a structure containing Zn is preferable. For example, in—zn oxide and in—ga—zn oxide are preferable because occurrence of grain boundaries can be further suppressed than In oxide.

CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundary is confirmed. Therefore, it can be said that in the CAAC-OS, a decrease in electron mobility due to grain boundaries does not easily occur. Further, since crystallinity of an oxide semiconductor is sometimes lowered by contamination of impurities, generation of defects, or the like, CAAC-OS is said to be an oxide semiconductor with few impurities or defects (oxygen vacancies, or the like). Therefore, the physical properties of the oxide semiconductor including CAAC-OS are stable. Therefore, an oxide semiconductor including CAAC-OS has high heat resistance and high reliability. In addition, CAAC-OS is also stable to high temperatures (so-called thermal budget) in the manufacturing process. Thus, by using the CAAC-OS for the OS transistor, the degree of freedom in the manufacturing process can be increased.

[nc-OS]

In nc-OS, atomic arrangements in minute regions (for example, regions of 1nm to 10nm, particularly, regions of 1nm to 3 nm) have periodicity. In other words, nc-OS has a minute crystal. For example, the size of the fine crystals is 1nm to 10nm, particularly 1nm to 3nm, and the fine crystals are called nanocrystals. Furthermore, the nc-OS did not observe regularity of crystal orientation between different nanocrystals. Therefore, the orientation was not observed in the whole film. Therefore, nc-OS is sometimes not different from a-like OS or amorphous oxide semiconductor in some analytical methods. For example, when the nc-OS film is subjected to structural analysis by using an XRD device, a peak showing crystallinity is not detected in the Out-of-plane XRD measurement using θ/2θ scanning. In addition, when an electron diffraction (also referred to as selective electron diffraction) using an electron beam having a beam diameter larger than that of nanocrystals (for example, 50nm or more) is performed on the nc-OS film, a diffraction pattern resembling a halo pattern is observed. On the other hand, when an electron diffraction (also referred to as a "nanobeam electron diffraction") using an electron beam having a beam diameter equal to or smaller than the size of a nanocrystal (for example, 1nm or more and 30nm or less) is performed on an nc-OS film, an electron diffraction pattern in which a plurality of spots are observed in an annular region centered on a direct spot may be obtained.

[a-like OS]

The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. The a-like OS contains holes or low density regions. That is, the crystallinity of the a-like OS is lower than that of nc-OS and CAAC-OS. The concentration of hydrogen in the film of a-like OS is higher than that in the films of nc-OS and CAAC-OS.

[ Structure of oxide semiconductor ]

Next, the details of the CAC-OS will be described. In addition, CAC-OS is related to material composition.

[CAC-OS]

The CAC-OS refers to, for example, a constitution in which elements contained in a metal oxide are unevenly distributed, wherein the size of a material containing unevenly distributed elements is 0.5nm or more and 10nm or less, preferably 1nm or more and 3nm or less or an approximate size. Note that a state in which one or more metal elements are unevenly distributed in a metal oxide and a region including the metal elements is mixed is also referred to as a mosaic shape or a patch shape hereinafter, and the size of the region is 0.5nm or more and 10nm or less, preferably 1nm or more and 3nm or less or an approximate size.

The CAC-OS is a structure in which a material is divided into a first region and a second region, and the first region is mosaic-shaped and distributed in a film (hereinafter also referred to as cloud-shaped). That is, CAC-OS refers to a composite metal oxide having a structure in which the first region and the second region are mixed.

Here, the atomic number ratios of In, ga and Zn with respect to the metal elements constituting the CAC-OS of the In-Ga-Zn oxide are each represented by [ In ], [ Ga ] and [ Zn ]. For example, in CAC-OS of In-Ga-Zn oxide, the first region is a region whose [ In ] is larger than that In the composition of the CAC-OS film. Further, the second region is a region whose [ Ga ] is larger than [ Ga ] in the composition of the CAC-OS film. Further, for example, the first region is a region whose [ In ] is larger than that In the second region and whose [ Ga ] is smaller than that In the second region. Further, the second region is a region whose [ Ga ] is larger than that In the first region and whose [ In ] is smaller than that In the first region.

Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, or the like. The second region is a region mainly composed of gallium oxide, gallium zinc oxide, or the like. In other words, the first region may be referred to as a region mainly composed of In. The second region may be referred to as a region containing Ga as a main component.

Note that a clear boundary between the first region and the second region may not be observed.

For example, in CAC-OS of In-Ga-Zn oxide, it was confirmed that the structure was mixed by unevenly distributing a region (first region) mainly composed of In and a region (second region) mainly composed of Ga based on an EDX-plane analysis (mapping) image obtained by an energy dispersive X-ray analysis method (EDX: energy Dispersive X-ray spectroscopy).

In the case of CAC-OSIn the case of a transistor, the CAC-OS can be provided with a switching function (a function of controlling on/off) by a complementary effect of the conductivity due to the first region and the insulation due to the second region. In other words, the CAC-OS material has a conductive function in one part and an insulating function in the other part, and has a semiconductor function in the whole material. By separating the conductive function from the insulating function, each function can be improved to the maximum extent. Thus, by using CAC-OS for the transistor, a high on-state current (I _on ) High field effect mobility (μ) and good switching operation.

Oxide semiconductors have various structures and various characteristics. The oxide semiconductor according to one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-likeOS, CAC-OS, nc-OS, and CAAC-OS.

< transistor with oxide semiconductor >

Here, a case where the above oxide semiconductor is used for a transistor will be described.

By using the oxide semiconductor described above for a transistor, a transistor with high field effect mobility can be realized. Further, a transistor with high reliability can be realized.

An oxide semiconductor having a low carrier concentration is preferably used for the transistor. For example, the carrier concentration in the oxide semiconductor may be 1×10 ¹⁷ cm ^-3 Hereinafter, it is preferably 1X 10 ¹⁵ cm ^-3 Hereinafter, more preferably 1X 10 ¹³ cm ^-3 Hereinafter, it is more preferable that 1×10 ¹¹ cm ^-3 Hereinafter, it is more preferably less than 1X 10 ¹⁰ cm ^-3 And 1×10 ^-9 cm ^-3 The above. In the case of aiming at reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In the present specification and the like, a state in which the impurity concentration is low and the defect state density is low is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". Further, an oxide semiconductor having a low carrier concentration is sometimes referred to as "high-purity intrinsic semiconductorAn "or" substantially high purity intrinsic "oxide semiconductor.

Since the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a low defect state density, it is possible to have a low trap state density.

Further, it takes a long time until the charge trapped by the trap level of the oxide semiconductor disappears, and the charge may act like a fixed charge. Therefore, the transistor in which the channel formation region is formed in the oxide semiconductor having a high trap state density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

< impurity >

Here, the influence of each impurity in the oxide semiconductor will be described.

When the oxide semiconductor contains silicon or carbon which is one of group 14 elements, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor or in the vicinity of the interface of the oxide semiconductor (concentration measured by secondary ion mass spectrometry (SIMS: secondary Ion Mass Spectrometry)) was set to 2X 10 ¹⁸ atoms/cm ³ Hereinafter, it is preferably 2X 10 ¹⁷ atoms/cm ³ The following is given.

In addition, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect level is sometimes formed to form a carrier. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal easily has normally-on characteristics. Thus, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor measured by SIMS was made 1X 10 ¹⁸ atoms/cm ³ Hereinafter, it is preferably 2X 10 ¹⁶ atoms/cm ³ The following is given.

When the oxide semiconductor contains nitrogen, electrons are easily generated as carriers, and the carrier concentration is increased, so that the oxide semiconductor is n-type. As a result, the package is packedA transistor in which a nitrogen-containing oxide semiconductor is used for a semiconductor is likely to have normally-on characteristics. Alternatively, when the oxide semiconductor contains nitrogen, a trap level may be formed. As a result, the electrical characteristics of the transistor may be unstable. Therefore, the nitrogen concentration in the oxide semiconductor measured by SIMS is set to be lower than 5X 10 ¹⁹ atoms/cm ³ Preferably 5X 10 ¹⁸ atoms/cm ³ Hereinafter, more preferably 1X 10 ¹⁸ atoms/cm ³ Hereinafter, it is more preferable that the ratio is 5X 10 ¹⁷ atoms/cm ³ The following is given.

Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to generate water, and thus oxygen vacancies are sometimes formed. When hydrogen enters the oxygen vacancy, electrons are sometimes generated as carriers. In addition, some of the hydrogen may be bonded to oxygen bonded to a metal atom, thereby generating electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen easily has normally-on characteristics. Thus, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration measured by SIMS is set to be lower than 1×10 ²⁰ atoms/cm ³ Preferably less than 1X 10 ¹⁹ atoms/cm ³ More preferably less than 5X 10 ¹⁸ atoms/cm ³ More preferably less than 1X 10 ¹⁸ atoms/cm ³ 。

By using an oxide semiconductor whose impurity is sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

At least a part of this embodiment can be implemented in combination with other embodiments described in this specification as appropriate.

Embodiment 5

In this embodiment mode, an integrated circuit (hereinafter also referred to as a display IC) and an electronic device including a display portion of a display device according to one embodiment of the present invention will be described.

Fig. 40A is a perspective view of a display IC100 including the display device 10 according to the embodiment of the present invention. The drawings show that the display IC100 includes a display device 10 and a plurality of pins 101. In addition to the pins 101, the display IC may also include a heat sink or the like for dissipating heat. Note that the pins 101 may also be FPCs.

The display IC100 may adopt a structure in which an image is seen by emitting light (arrows in the drawing) through the display portion 60 included in the display device 10.

Fig. 40B is a perspective view schematically showing the structures of the layers 20, 30, and the light emitting element 70 of the display device 10. As described in embodiment 1 and the like, the layer 30 provided with the OS transistor includes the backup circuit 82 in addition to the pixel circuits 62R, 62G, and 62B in the region of the pixel 61.

As shown in fig. 40B, a backup circuit 82 provided together with the pixel circuits 62R, 62G, 62B may be provided corresponding to the sub-pixels of RGB. The backup circuit 82 can hold data of a circuit provided in the layer 20 by using the OS transistor, the functional circuit 50, the CPU51, or the like. The memory circuits 82B provided in the layer 30 provided with the OS transistors can be uniformly arranged in the layer 30, and therefore, unlike the case where the backup circuits 82 are locally arranged, the backup circuits 82 can be easily electrically connected to the functional circuits 50 or the CPU 51.

Next, an electronic device including the display IC will be described.

Fig. 41A is an external view of the head mounted display 8200.

The head mount display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like. Further, a battery 8206 is incorporated in the mounting portion 8201.

Power is supplied from the battery 8206 to the main body 8203 via the cable 8205. The main body 8203 includes a wireless receiver or the like, and is capable of displaying an image corresponding to received image data or the like on the display unit 8204. Further, by capturing the movement of the eyeball or eyelid of the user with a camera provided in the main body 8203 and calculating the coordinates of the user's line of sight from this information, the user's line of sight can be used as an input method.

Further, a plurality of electrodes may be provided at positions of the mounting portion 8201 that are contacted by the user. The main body 8203 may have a function of detecting a current flowing through the electrode according to the movement of the eyeball of the user, and thereby recognizing the line of sight of the user. Further, the main body 8203 may have a function of monitoring a pulse of the user by detecting a current flowing through the electrode. The mounting unit 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, or may have a function of displaying biological information of the user on the display unit 8204. The main body 8203 may detect the movement of the head of the user and change the image displayed on the display unit 8204 in synchronization with the movement of the head of the user.

The display IC according to one embodiment of the present invention can be used for the display portion 8204. Accordingly, the power consumption of the head-mounted display 8200 can be reduced, and therefore the head-mounted display 8200 can be continuously used for a long period of time. Further, by reducing the power consumption of the head mounted display 8200, the battery 8206 can be reduced in size and weight, and thus the head mounted display 8200 can be reduced in size and weight. This reduces the burden on the user wearing the head mount display 8200, and makes the user less likely to feel tired.

Fig. 41B, 41C, and 41D are external views of the head mounted display 8300. The head mount display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixing tool 8304, and a pair of lenses 8305. Further, the battery 8306 is incorporated in the housing 8301, and electric power can be supplied from the battery 8306 to the display portion 8302 or the like.

The user can see the display on the display portion 8302 through the lens 8305. Preferably, the display portion 8302 is curved. By bending the display portion 8302, the user can feel a high sense of reality. Note that in the present embodiment, the configuration in which one display portion 8302 is provided is illustrated, but the present invention is not limited to this, and for example, a configuration in which two display portions 8302 are provided may be employed. In this case, when each display unit is arranged on each eye side of the user, three-dimensional display using parallax or the like can be performed.

The display IC may be used for the display portion 8302. Thus, the power consumption of the head mounted display 8300 can be reduced, so that the head mounted display 8300 can be continuously used for a long period of time. Further, by reducing the power consumption of the head mounted display 8300, the battery 8306 can be reduced in size and weight, and thus the head mounted display 8300 can be reduced in size and weight. This reduces the burden on the user of the head mount display 8300, and makes the user less likely to feel tired.

Next, fig. 42A and 42B show examples of electronic devices different from those shown in fig. 41A to 41D.

The electronic device shown in fig. 42A and 42B includes a housing 9000, a display portion 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (the sensor has a function of measuring a force, a displacement, a position, a speed, an acceleration, an angular velocity, a rotation speed, a distance, light, liquid, magnetism, temperature, a chemical substance, sound, time, hardness, an electric field, electric current, voltage, electric power, radiation, flow, humidity, inclination, vibration, smell, or infrared), a battery 9009, or the like.

The electronic device shown in fig. 42A and 42B has various functions. For example, it may have the following functions: a function of displaying various information (still image, moving image, character image, etc.) on the display section; a function of the touch panel; a function of displaying a calendar, date, time, or the like; functions of controlling processing by using various software (programs); a function of performing wireless communication; a function of connecting to various computer networks by using a wireless communication function; a function of transmitting or receiving various data by using a wireless communication function; a function of reading out a program or data stored in the storage medium and displaying the program or data on the display section; etc. Note that the functions that the electronic device shown in fig. 42A and 42B can have are not limited to the above-described functions, but may have various functions. Although not shown in fig. 42A and 42B, the electronic device may include a plurality of display portions. In addition, the electronic device may be provided with a camera or the like so as to have the following functions: a function of photographing a still image; a function of photographing a dynamic image; a function of storing the photographed image in a storage medium (an external storage medium or a storage medium built in a camera); a function of displaying the photographed image on a display section; etc.

Next, the electronic device shown in fig. 42A and 42B will be described in detail.

Fig. 42A is a perspective view showing the portable information terminal 9101. The portable information terminal 9101 has functions of one or more of a telephone, an electronic notebook, an information reading device, and the like, for example. In particular, it can be used as a smart phone. Further, the portable information terminal 9101 may display text or image information on a plurality of sides thereof. For example, three operation buttons 9050 (also referred to as operation icons or simply as icons) may be displayed on one surface of the display portion 9001. Further, information 9051 indicated by a dotted rectangle may be displayed on the other face of the display portion 9001. Further, as an example of the information 9051, a display prompting reception of information from an email, SNS (Social Networking Services: social network service), telephone, or the like may be given; a title of an email, SNS, or the like; sender name of email or SNS; a date; time; a battery balance; and display of the antenna received signal strength, etc. Alternatively, an operation button 9050 or the like may be displayed in place of the information 9051 at a position where the information 9051 is displayed.

The above display IC can be applied to the portable information terminal 9101. Thus, the power consumption of the portable information terminal 9101 can be reduced, so that the portable information terminal 9101 can be continuously used for a long period of time. Further, by reducing the power consumption of the portable information terminal 9101, the battery 9009 can be reduced in size and weight, and thus the portable information terminal 9101 can be reduced in size and weight. The portability of the portable information terminal 9101 can be improved.

Fig. 42B is a perspective view showing the wristwatch-type portable information terminal 9200. The portable information terminal 9200 can execute various application programs such as mobile phones, emails, reading and editing of articles, music playing, network communication, and computer games. The display surface of the display portion 9001 is curved, and can display on the curved display surface. Fig. 42B shows an example in which a time 9251, an operation button 9252 (operation icon or simply referred to as icon), and content 9253 are displayed on the display portion 9001. The content 9253 may be, for example, a moving image.

Further, the portable information terminal 9200 can perform short-range wireless communication standardized by communication. For example, hands-free conversation may be performed by communicating with a headset that is capable of wireless communication. The portable information terminal 9200 includes a connection terminal 9006, and can directly exchange data with another information terminal via a connector. Further, charging may be performed through the connection terminal 9006. In addition, the charging operation may be performed by wireless power supply, instead of through the connection terminal 9006.

The above display IC can be applied to the portable information terminal 9200. Thus, the power consumption of the portable information terminal 9200 can be reduced, and therefore the portable information terminal 9200 can be continuously used for a long period of time. Further, by reducing the power consumption of the portable information terminal 9200, the battery 9009 can be reduced in size and weight, and therefore, the portable information terminal 9200 can be reduced in size and weight. The portability of the portable information terminal 9200 can be improved.

At least a part of this embodiment can be implemented in combination with other embodiments described in this specification as appropriate.

< notes concerning the description of the present specification and the like >

Next, explanation will be given of the above embodiment and each structure in the embodiment.

The structure shown in each embodiment mode can be combined with the structure shown in other embodiment modes as appropriate to constitute one embodiment mode of the present invention. Further, when a plurality of structural examples are shown in one embodiment, these structural examples may be appropriately combined.

Furthermore, the content (or a part thereof) described in one embodiment may be applied/combined/replaced with other content (or a part thereof) described in the embodiment and/or content (or a part thereof) described in another embodiment or another embodiments.

The content described in the embodiments refers to the content described in the various drawings or the content described in the specification by the article.

Further, by combining the drawing (or a part thereof) shown in one embodiment with other parts of the drawing, other drawings (or a part thereof) shown in the embodiment, and/or drawings (or a part thereof) shown in another embodiment or embodiments, more drawings can be constituted.

In this specification and the like, constituent elements are classified according to functions and are represented by blocks independent of each other in a block diagram. However, it is difficult to classify constituent elements by function in an actual circuit or the like, and one circuit may involve a plurality of functions or a plurality of circuits may involve one function. Accordingly, the division of blocks in the block diagrams is not limited to the constituent elements described in the specification, and may be appropriately different according to circumstances.

In the drawings, the size, thickness of layers, or regions are sometimes exaggerated for clarity of illustration. Accordingly, the present invention is not limited to the dimensions in the drawings. The drawings are shown in any size for clarity, and are not limited to the shapes, values, etc. shown in the drawings. For example, unevenness in signal, voltage, or current due to noise, timing deviation, or the like may be included.

In this specification and the like, when describing a connection relation of a transistor, expressions of "one of a source and a drain" (a first electrode or a first terminal), "the other of the source and the drain" (a second electrode or a second terminal) are used. This is because the source and drain of the transistor are interchanged according to the structure, operating conditions, or the like of the transistor. Note that the source and the drain of the transistor may be appropriately replaced with a source (drain) terminal, a source (drain) electrode, or the like as appropriate.

In this specification and the like, the "electrode" or the "wiring" does not limit the functions of the constituent elements. For example, an "electrode" is sometimes used as part of a "wiring" and vice versa. Further, "electrode" or "wiring" includes a case where a plurality of "electrodes" or "wirings" are formed integrally, and the like.

In this specification and the like, the voltage and the potential can be appropriately changed. The voltage refers to a potential difference from a reference potential, and when the reference potential is, for example, a ground voltage (ground voltage), the voltage may be referred to as a potential. The ground potential does not necessarily mean 0V. Note that the potentials are opposite, and the potential supplied to the wiring or the like sometimes varies according to the reference potential.

In this specification and the like, words such as "film" and "layer" may be exchanged with each other according to the situation or state. For example, the "conductive layer" may be replaced with the "conductive film" in some cases. In addition, the "insulating film" may be replaced with an "insulating layer" in some cases.

In this specification and the like, a switch means an element having a function of controlling whether or not to flow a current by changing to a conductive state (on state) or a nonconductive state (off state). Alternatively, the switch refers to an element having a function of selecting and switching a current path.

In this specification and the like, for example, a channel length refers to a distance between a source and a drain in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is in an on state) and a gate overlap or a region where a channel is formed in a top view of the transistor.

In this specification and the like, for example, a channel width refers to a length of a region where a semiconductor (or a portion where a current flows in the semiconductor when a transistor is in an on state) and a gate electrode overlap, or a portion where a source and a drain oppose each other in a region where a channel is formed.

In this specification and the like, "a and B connected" includes a case where a and B are electrically connected in addition to a case where a and B are directly connected. The description of "electrically connecting a and B" refers to a case where an object having a certain electric action is present between a and B, and the transmission and reception of electric signals of a and B are enabled.

[ description of the symbols ]

10: display device, 20: layer, 30: layer, 40: drive circuit, 50: functional circuit, 60: display unit, 61: pixels, 62R, 62G, 62B: pixel circuit, 80: trigger, 82: backup circuit, BD: backup data

Claims (9)

1. A display device, comprising:

A pixel circuit;

a driving circuit; and

the functional circuitry is configured to provide a functional circuit,

wherein the driving circuit has a function of outputting a signal for display at the pixel circuit,

the functional circuit includes a CPU including a CPU core having a trigger electrically connected to a backup circuit,

the display device further includes:

a first layer; and

the second layer of the material is formed by a first layer,

the first layer includes the driving circuit and the CPU,

the second layer includes the pixel circuit and the backup circuit,

and, the first layer and the second layer are disposed in different layers.

2. A display device, comprising:

a pixel circuit;

a driving circuit; and

the functional circuitry is configured to provide a functional circuit,

wherein the driving circuit has a function of outputting an image signal for display at the pixel circuit,

the functional circuit includes a CPU including a CPU core having a trigger electrically connected to a backup circuit,

the display device further includes:

a first layer; and

the second layer of the material is formed by a first layer,

the first layer includes the driving circuit and the CPU,

the second layer includes the pixel circuit and the backup circuit,

the first layer and the second layer are arranged in different layers,

And, the CPU has a function of correcting the image signal according to the amount of current flowing through the pixel circuit.

3. A display device, comprising:

a pixel circuit;

a driving circuit; and

the functional circuitry is configured to provide a functional circuit,

wherein the driving circuit has a function of outputting an image signal for display at the pixel circuit,

the functional circuit includes a CPU including a CPU core having a trigger electrically connected to a backup circuit,

the display device further includes:

a first layer; and

the second layer of the material is formed by a first layer,

the first layer includes the driving circuit and the CPU,

the second layer includes the pixel circuit and the backup circuit,

the first layer includes a first transistor having a semiconductor layer including silicon in a channel formation region,

the second layer includes a second transistor having a semiconductor layer including a metal oxide in a channel formation region,

and, the CPU has a function of correcting the image signal according to the amount of current flowing through the pixel circuit.

4. A display device according to claim 3,

wherein the metal oxide comprises In, the element M (M is Al, ga, Y or Sn) and Zn.

5. The display device according to any one of claim 1 to 4,

Wherein the backup circuit has a function of holding data held by the flip-flop in a state in which supply of the power supply voltage is stopped when the CPU is not in operation.

6. The display device according to any one of claims 1 to 5,

wherein the functional circuit comprises an accelerator,

and the accelerator is a circuit that performs a product-sum operation.

7. The display device according to any one of claims 1 to 6,

wherein the pixel circuit includes an organic EL device,

and the organic EL device is a light emitting device processed using photolithography.

8. The display device according to any one of claims 1 to 7,

wherein the backup circuit includes the first transistor provided in the first layer and a capacitor electrically connected to the first transistor,

and the capacitor is disposed in the first layer.

9. A display correction system, comprising:

a pixel circuit;

a driving circuit; and

the functional circuitry is configured to provide a functional circuit,

wherein the driving circuit has a function of outputting an image signal for display at the pixel circuit,

the functional circuit includes a CPU including a CPU core having a trigger electrically connected to a backup circuit,

The display correction system further includes:

a first layer; and

the second layer of the material is formed by a first layer,

the first layer includes the driving circuit and the CPU,

the second layer includes the pixel circuit and the backup circuit,

the backup circuit has a function of holding data in the flip-flop by turning off a first transistor including a semiconductor layer including silicon in a channel formation region when the CPU is not operating,

the CPU has a function of correcting the image signal by estimating defective pixels according to the amount of current flowing through the pixel circuit,

in the correction, the amount of current flowing through the pixel circuit of the pixel adjacent to the defective pixel is corrected.