CN116828972A - Phase change memory, manufacturing method and memory system - Google Patents
Phase change memory, manufacturing method and memory system Download PDFInfo
- Publication number
- CN116828972A CN116828972A CN202310863863.0A CN202310863863A CN116828972A CN 116828972 A CN116828972 A CN 116828972A CN 202310863863 A CN202310863863 A CN 202310863863A CN 116828972 A CN116828972 A CN 116828972A
- Authority
- CN
- China
- Prior art keywords
- layer
- change memory
- phase change
- electrode layer
- conductive line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 title claims abstract description 268
- 230000008859 change Effects 0.000 title claims abstract description 216
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 230000004888 barrier function Effects 0.000 claims abstract description 158
- 230000001052 transient effect Effects 0.000 claims abstract description 25
- 238000003860 storage Methods 0.000 claims abstract description 11
- 238000002955 isolation Methods 0.000 claims description 56
- 239000000463 material Substances 0.000 claims description 52
- 239000004065 semiconductor Substances 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 19
- 230000008569 process Effects 0.000 claims description 18
- 239000000470 constituent Substances 0.000 claims description 9
- 230000007547 defect Effects 0.000 claims description 6
- 239000000376 reactant Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 11
- 150000004767 nitrides Chemical class 0.000 description 11
- 239000000969 carrier Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000001276 controlling effect Effects 0.000 description 4
- 239000012782 phase change material Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 230000004941 influx Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000012864 cross contamination Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 239000005387 chalcogenide glass Substances 0.000 description 1
- 150000004770 chalcogenides Chemical class 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003090 exacerbative effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000010791 quenching Methods 0.000 description 1
- 230000000171 quenching effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
Abstract
The embodiment of the application discloses a phase change memory, a manufacturing method and a memory system. The phase change memory comprises a first phase change memory cell, a second phase change memory cell and a first storage element, wherein the first phase change memory cell is arranged between the first conductive wire and the second conductive wire; the first conductive wire and the second conductive wire are parallel to the same plane and are perpendicular to each other; the first phase change memory cell is perpendicular to both the first conductive line and the second conductive line and includes: a first electrode layer, a first gate layer, a second electrode layer, a first phase change memory layer, and a third electrode layer which are sequentially stacked; the first phase change memory cell further includes at least one of: a first drain barrier layer laminated in front of the first electrode layer, a second drain barrier layer laminated between the second electrode layer and the first phase change memory layer, and a third drain barrier layer laminated behind the third electrode layer; the first drain barrier layer, the second drain barrier layer and the third drain barrier layer are used for reducing transient in-rush current formed when the first gating layer is opened.
Description
Technical Field
The present application relates to the field of memory technologies, and in particular, to a phase change memory, a manufacturing method thereof, and a memory system.
Background
Phase change memories are memory elements that use conductivity or resistance differential characteristics between crystalline and amorphous states of a particular phase change material to store information. In providing for the operation of phase change material of a phase change memory to switch between crystalline and amorphous states, different pulses may be used to control the heating of the phase change material. At present, when programming or reading the phase-change memory, a large surge current is generated due to a large switching ratio of the gating device, so that the service life of the phase-change memory is seriously influenced, and read disturbs and write disturbs are caused, so that the reliability of the device is greatly reduced.
Disclosure of Invention
The embodiment of the application provides a phase change memory, a manufacturing method and a memory system.
In a first aspect, an embodiment of the present application provides a phase change memory, including: a first phase change memory cell between a first conductive line, a second conductive line, and the first conductive line and the second conductive line; wherein the first conductive line and the second conductive line are parallel to the same plane and perpendicular to each other; the first phase change memory cell is perpendicular to the first conductive line and the second conductive line; and the first phase change memory cell includes: a first electrode layer, a first gate layer, a second electrode layer, a first phase change memory layer, and a third electrode layer which are sequentially stacked; wherein,
The first phase change memory cell further includes at least one of: a first drain barrier layer laminated in front of the first electrode layer, a second drain barrier layer laminated between the second electrode layer and the first phase change memory layer, and a third drain barrier layer laminated behind the third electrode layer; the first drain barrier layer, the second drain barrier layer and the third drain barrier layer are used for reducing transient in-rush current formed when the first gating layer is opened.
In the above scheme, the forbidden bandwidths of the first leakage barrier layer, the second leakage barrier layer and the third leakage barrier layer are larger than the forbidden bandwidth of the first gating layer, and the thicknesses of the first leakage barrier layer, the second leakage barrier layer and the third leakage barrier layer are smaller than the thickness of the first gating layer.
In the above scheme, the constituent materials of the first drain barrier layer, the second drain barrier layer and the third drain barrier layer include a wide band gap semiconductor material.
In the above aspect, the wide bandgap semiconductor material includes at least one of:
silicon oxide;
silicon nitride;
silicon carbide;
Carbonitride.
In the above scheme, the thickness of the wide bandgap semiconductor material and the defects contained in the wide bandgap semiconductor material should be such that the bandgap of the wide bandgap semiconductor material can reduce the transient in-rush current formed when the gate layer is turned on and the leakage current of the wide bandgap semiconductor material can meet the driving requirement of the first phase change memory layer.
In the above scheme, the wide bandgap semiconductor material is formed by controlling the time and/or reactants of the process.
In the above aspect, the phase change memory further includes: a third conductive line and a second phase change memory cell between the second conductive line and the third conductive line; wherein the third conductive line and the second conductive line are parallel to the same plane and are perpendicular to each other; the second phase change memory unit is perpendicular to the second conductive line and the third conductive line; and the second phase change memory cell includes: a fourth electrode layer, a second gate layer, a fifth electrode layer, a second phase-change memory layer, and a sixth electrode layer, which are sequentially stacked; wherein,
the second phase change memory cell further includes at least one of: a fourth drain barrier layer laminated in front of the fourth electrode layer, a fifth drain barrier layer laminated between the fifth electrode layer and the second phase change memory layer, and a sixth drain barrier layer laminated behind the sixth electrode layer; the fourth drain barrier layer, the fifth drain barrier layer and the sixth drain barrier layer are configured to reduce transient in-rush current formed when the second gate layer is turned on.
In the above aspect, the phase change memory further includes:
a substrate;
the first isolation structure is alternately arranged on the surface of the substrate along a first direction in parallel with the first conductive wires and the first phase change memory cells which are stacked; wherein the first direction is parallel to the substrate surface;
the second isolation structure is alternately arranged on the surface of the substrate in parallel with the first phase change memory cells and the second conductive wires which are stacked along a second direction; wherein the second direction is parallel to the substrate and the second direction is perpendicular to the first direction.
In the above aspect, the first isolation structure includes: a first isolation layer arranged along a direction perpendicular to the first direction and covering the side wall of the third electrode layer and the side wall of the first phase change memory layer;
and the second isolation layer is arranged along the direction perpendicular to the first direction and covers the second electrode layer side wall, the first gating layer side wall, the first electrode layer side wall and the first conductive wire side wall.
In the above aspect, the second isolation structure includes:
a third isolation layer arranged along a direction perpendicular to the second direction and covering the side wall of the third electrode layer and the side wall of the first phase-change storage layer;
And a fourth isolation layer arranged along a direction perpendicular to the second direction and covering the second electrode layer side wall, the first gating layer side wall, the first electrode layer side wall and the second conductive wire side wall.
In the above aspect, the phase change memory further includes:
the first phase change memory layer has a first width and the second electrode layer has a second width along an extending direction parallel to the first conductive line; wherein the second width is greater than the first width;
and/or the number of the groups of groups,
the first phase change memory layer has a third width and the second electrode layer has a fourth width along an extending direction parallel to the second conductive line; wherein the fourth width is greater than the third width.
In a second aspect, an embodiment of the present application further provides a method for manufacturing a phase change memory, including: forming a first conductive line;
forming a first phase change memory cell;
forming a second conductive line;
wherein the first phase change memory cell formed comprises: a first electrode layer, a first gate layer, a second electrode layer, a first phase change memory layer, and a third electrode layer which are sequentially stacked; and the first phase change memory cell further comprises and at least one of: a first drain barrier layer laminated in front of the first electrode layer, a second drain barrier layer laminated between the second electrode layer and the first phase change memory layer, and a third drain barrier layer laminated behind the third electrode layer; the first drain barrier layer, the second drain barrier layer and the third drain barrier layer are used for reducing transient in-rush current formed when the first gating layer is opened.
In the above scheme, the method further comprises:
forming a second phase change memory cell;
forming a third conductive line;
wherein the second phase change memory cell formed comprises: a fourth electrode layer, a second gate layer, a fifth electrode layer, a second phase-change memory layer, and a sixth electrode layer, which are sequentially stacked; and the second phase change memory cell further comprises at least one of: a fourth drain barrier layer laminated in front of the fourth electrode layer, a fifth drain barrier layer laminated between the fifth electrode layer and the second phase change memory layer, and a sixth drain barrier layer laminated behind the sixth electrode layer; the fourth drain barrier layer, the fifth drain barrier layer and the sixth drain barrier layer are configured to reduce transient in-rush current formed when the second gate layer is turned on. In a third aspect, embodiments of the present application further provide a memory system, including: the memory of any of the above, and a memory controller coupled to the phase change memory.
The embodiment of the application provides a phase change memory, a manufacturing method and a memory system. Wherein the phase change memory comprises
A first phase change memory cell between a first conductive line, a second conductive line, and the first conductive line and the second conductive line; wherein the first conductive line and the second conductive line are parallel to the same plane and perpendicular to each other; the first phase change memory cell is perpendicular to the first conductive line and the second conductive line; and the first phase change memory cell includes: a first electrode layer, a first gate layer, a second electrode layer, a first phase change memory layer, and a third electrode layer which are sequentially stacked; wherein,
The first phase change memory cell further includes at least one of: a first drain barrier layer laminated in front of the first electrode layer, a second drain barrier layer laminated between the second electrode layer and the first phase change memory layer, and a third drain barrier layer laminated behind the third electrode layer; the first drain barrier layer, the second drain barrier layer and the third drain barrier layer are used for reducing transient in-rush current formed when the first gating layer is opened. According to the phase change memory provided by the embodiment of the application, at least one of the first leakage barrier layer, the second leakage barrier layer and the third leakage barrier layer is arranged in the first phase change memory layer, so that the transient inrush current formed when the first gating layer is started is reduced by the limited leakage current.
Drawings
In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. The same numbers with different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example and not by way of limitation, the various embodiments discussed in the present document.
FIG. 1 is a schematic diagram of a phase change memory according to aspects of the present application;
FIG. 2 is a partial equivalent circuit diagram of a phase change memory provided in accordance with aspects of the present application;
FIG. 3 is a graph of voltage versus current characteristics of a phase change memory provided in accordance with aspects of the present application;
FIG. 4 is a voltage-current characteristic diagram of a gating layer of a phase change memory provided in accordance with aspects of the present application;
FIG. 5 is a schematic diagram of the energy bands of the phase change memory of FIG. 1 provided in accordance with aspects of the present application;
FIG. 6 is a schematic diagram of another phase change memory provided in accordance with aspects of the present application;
FIG. 7 is a schematic diagram of the energy bands of the phase change memory of FIG. 4 provided in accordance with aspects of the present application;
FIG. 8 is a schematic diagram of a further phase change memory provided in accordance with aspects of the present application;
FIG. 9 is a flow chart of a method of fabricating a phase change memory according to aspects of the present application;
FIG. 10 is a flow chart of another method of fabricating a phase change memory according to aspects of the present application.
Detailed Description
Various embodiments of the present application are described in more detail below with reference to the accompanying drawings. Elements and features of embodiments of the application may be variously configured or arranged to form other embodiments, which may be a variation of any of the disclosed embodiments. Accordingly, embodiments of the application are not limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art to which the embodiments pertain. It should be noted that references to "an embodiment," "another embodiment," etc., do not necessarily refer to only one embodiment, and different references to any such phrases are not necessarily referring to the same embodiment. It will be understood that, although the terms "first," "second," "third," etc. may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element having the same or similar designation. Thus, a first element could also be termed a second or third element in one embodiment without departing from the spirit and scope of embodiments of the present application.
The figures are not necessarily to scale and in some instances, the proportions may be exaggerated to clearly illustrate the features of the embodiments. When an element is referred to as being connected or coupled to another element, it should be understood that the former may be directly connected or coupled to the latter or may be electrically connected or coupled to the latter via one or more intervening elements therebetween. Furthermore, it will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements or one or more intervening elements may also be present.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The articles "a" and/or "an" as used in embodiments of the application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. It will be further understood that the terms "comprises," "comprising," "includes," and "including" when used in this specification, specify the presence of stated elements and do not preclude the presence or addition of one or more other elements. The term "and/or" as used in embodiments of the present application includes any and all combinations of one or more of the associated listed items. Unless defined otherwise, all terms including technical and scientific techniques used by embodiments of the application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs in view of the embodiments of the application. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the embodiments and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the application, and the application may be practiced without some or all of these specific details. In other instances, well known process structures and/or processes have not been described in detail in order to not unnecessarily obscure the present application. It is also to be understood that in some cases, unless otherwise specified, features or elements described with respect to one embodiment may be used alone or in combination with other features or elements of another embodiment as would be apparent to one of ordinary skill in the relevant arts. Hereinafter, various embodiments of the present application are described in detail with reference to the accompanying drawings. The following description focuses on details to facilitate an understanding of embodiments of the application. Well-known technical details may be omitted so as not to obscure the features and aspects of the embodiments of the application.
The technical schemes described in the embodiments of the present application may be arbitrarily combined without any collision.
Fig. 1 is a partial schematic diagram of a phase change memory (PCM, phase Change Memory) 1000 provided in accordance with some aspects of the application. Referring to fig. 1, the PCM1000 may include: the first conductive line 1100, the phase change memory cell 1200, and the second conductive line 1300 are sequentially stacked, wherein the phase change memory cell 1200 may include: electrode layer 1210, gate layer 1220, electrode layer 1230, phase change memory layer 1240, and electrode layer 1250. The PCM may be based on heating and quenching by the phase change memory layer such that the phase change memory layer 1240 is transformed between amorphous and crystalline states, thereby storing data using the difference in resistivity of the phase change memory layer 1240 in the amorphous state and the crystalline state.
Fig. 2 is a partial equivalent circuit diagram of a phase change memory provided in accordance with some aspects of the present application. As shown in fig. 2, the phase change memory 1000 includes a memory array of 9 phase change memory cells; three first conductive lines 1100u1, 1100u2, 1100u3 extending in parallel to the y direction; and three second conductive lines 1300u1, 1200u2, 1300u3 extending in the parallel x direction. In each phase change memory cell, the gate layer 1220 may be equivalent to one gate element, and the phase change memory layer 1240 may be equivalent to one variable resistor, that is, each phase change memory cell may be equivalent to a series connection of one variable resistor and one gate element. The phase change memory cell may be electrically connected to a first conductive line 1100 through one end of the gate element and to a second conductive line 1300 through one end of the variable resistor. Based on such an equivalence, when a program operation is required for the phase change memory cell S, the phase change memory cells a, b, c, i.e., the selected memory cell, are not required for the program operation, the phase change memory cells S, b, c, i.e., the unselected memory cells. At this time, a first bit line voltage (-Vll) may be applied to the phase-change memory cell S through the first conductive line 1100S, and a first word line voltage (Vhh) may be applied to the phase-change memory cell S through the second conductive line 1300S such that the voltage (vhh+ Vll) applied to the phase-change memory cell S is sufficiently large to perform a program operation on the phase-change memory cell S. Meanwhile, a second bit line voltage (Vub) is applied to the phase change memory cell a and the phase change memory cell c through the first conductive line 1100u1 or 1100u2, and a second word line voltage (Vuw) is applied to the phase change memory cell b and the phase change memory cell c through the second conductive line 1300u1 or 1300u 2. Wherein the absolute value of the second bit line voltage is less than the absolute value of the first bit line voltage, and the absolute value of the second word line voltage is less than the absolute value of the first word line voltage. It should be noted that, the first bit line voltage (-Vll) is applied to the selected phase-change memory cell S through the first conductive line 1100S, and the first bit line voltage (-Vll) is also applied to the phase-change memory cell b connected in series with the first conductive line 1100S. Similarly, the first word line voltage (Vhh) is applied to the phase change memory cell a in series with the second conductive line 2300S at the same time as the first word line voltage (Vhh) is applied to the selected phase change memory cell S through the second conductive line 1300S.
Thus, for the memory array shown in FIG. 2a, the voltages of phase change memory cells S, a, b, and c are, respectively, in order:
VS＝Vhh+Vll (1)
Va＝Vhh-Vub (2)
Vb＝Vuw+Vll (3)
Vc＝Vuw-Vub (4)
wherein VS is the voltage of the phase change memory cell S; va is the voltage of the phase change memory cell a; vb is the voltage of the phase change memory cell b; vc is the voltage of phase change memory cell c.
Fig. 3 is a voltage-current characteristic diagram of a phase change memory provided in accordance with some aspects of the present application. Referring to fig. 3, when a write (set) operation (or a program operation) is performed on a phase-change memory cell, when a voltage on the phase-change memory cell increases to be greater than a first threshold voltage (Vt 1) and less than a second threshold voltage (Vt 2), a phase-change memory layer in the phase-change memory cell is changed from an amorphous state to a crystalline state, and a resistance of the phase-change memory layer in the crystalline state is smaller than a resistance of the phase-change memory layer in the amorphous state. When the phase change memory cell is read, the voltage applied to the memory cell is a read voltage (Vsense), and the read voltage is greater than the first threshold voltage and less than the second threshold voltage. When the voltage on the phase-change memory cell is increased to be greater than the second threshold voltage, the phase-change memory layer in the phase-change memory cell is changed from the crystalline state to the amorphous state, and the resistance of the phase-change memory layer in the crystalline state is smaller than the resistance of the phase-change memory layer in the amorphous state.
Fig. 4 is a voltage-current characteristic diagram of a gating layer of a phase change memory provided in accordance with some aspects of the present application. It should be appreciated that when performing a program or read operation for a selected phase change memory cell, it is preferable to turn on the gate layer corresponding to the gate element, and then apply a voltage to the phase change memory layer (PCM element) of the selected phase change memory cell to perform a data writing or reading operation. The current-voltage characteristics of the gating element are shown in fig. 4, since the gating element needs to have a large switching ratio to satisfy the demands of low leakage current and strong driving current. It is also a gating element that has a large switching ratio, and when the voltage across the gating element reaches a certain value, the gating element will generate a large inrush current at the moment of opening. The large inrush current can seriously affect the endurance of the individual hardware elements contained in the phase change memory and even directly lead to breakdown failure of the hardware elements. Meanwhile, a large inrush current also causes read disturbs (read disturbs) and write disturbs (write disturbs), which greatly reduce the device reliability. Currently, the inrush current has become a commonality problem for high-fast-switching-ratio gating elements.
In particular, see the band structure of the phase change memory shown in fig. 1 shown in fig. 5. From the band angle analysis, inrush current results from the instantaneous band change of the gating element on, the band barrier disappearing, and a large number of unbalanced carriers are rushed from the metal, as shown in fig. 5. These unbalanced carrier formed inrush currents will quickly relax to a steady state under the influence of the RLC circuitry. The unbalanced carrier itself resembles the carrier behavior at the moment of breakdown, and the excessive inrush current causes intense heat, further exacerbating the thermally excited carrier, and the two mutually strengthen. The influx of unbalanced carriers causes damage to the conductive path to be formed in the gating element, and soft failure occurs; even worse, individual hardware elements contained in the memory are destroyed, resulting in hard failures.
In order to solve the above problems, an embodiment of the present application provides another phase change memory. Specifically, as shown in fig. 6. The phase change memory 2000 may include:
a first phase change memory cell 2200 between a first conductive line 2100, a second conductive line 2300, and the first conductive line and the second conductive line; wherein the first conductive line and the second conductive line are parallel to the same plane and perpendicular to each other; the first phase change memory cell is perpendicular to the first conductive line and the second conductive line; and the first phase change memory cell 2200 includes: a first electrode layer 2210, a first gate layer 2220, a second electrode layer 2230, a first phase-change memory layer 2240, and a third electrode layer 2250, which are sequentially stacked; wherein,
The first phase change memory cell further includes at least one of: a first drain barrier layer 2260 stacked before the first electrode layer, a second drain barrier layer 2270 stacked between the second electrode layer and the first phase change memory layer, and a third drain barrier layer 2280 stacked after the third electrode layer; the first drain barrier layer, the second drain barrier layer and the third drain barrier layer are used for reducing transient in-rush current formed when the first gating layer is opened.
Here, constituent materials of the first conductive line 2100 and the second conductive line 2300 may include conductive materials. The conductive material may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or polysilicon, etc. The constituent materials of the first electrode layer, the second electrode layer and the third electrode layer may include, but are not limited to, W, co, cu, al, carbon, polysilicon, doped silicon, silicide or any combination thereof. For example, the constituent materials of the first electrode layer, the second electrode layer and the third electrode layer may be amorphous carbon, such as α -phase carbon. The first electrode layer, the second electrode layer and the third electrode layer are used for conducting electric signals. The constituent materials of the first gate layer 2220 may include: threshold selection switch (OTS, ovonic threshold switching) material, such as ZnaTeb, geaTeb, nbaOb or SiaAsbTec, etc. The material of the first phase-change memory layer may include: chalcogenide-based alloys (chalcogenide glass), such as GST (Ge-Sb-Te) alloys, or include any other suitable phase change material.
Referring to fig. 6, a first electrode layer, a first gate layer, a second electrode layer, and a first phase change memory level third electrode layer are sequentially stacked. The first plane on which the first conductive line is provided and the second plane on which the second conductive line is provided are parallel to each other, and the first plane overlaps the second plane. The phase change memory cell 2200 is located between and perpendicular to both the first plane and the second plane.
In order to solve the above-mentioned problems, referring to fig. 6, the first phase-change memory cell of the phase-change memory according to the embodiment of the present application further includes at least one of the following: a first drain barrier layer 2260 stacked before the first electrode layer, a second drain barrier layer 2270 stacked between the second electrode layer and the first phase change memory layer, and a third drain barrier layer 2280 stacked after the third electrode layer. The first drain barrier layer, the second drain barrier layer and the third drain barrier layer are used for reducing transient in-rush current formed when the first gating layer is opened.
It should be noted that, according to the design, the first leakage barrier layer, the second leakage barrier layer and the third leakage barrier layer have enough leakage currents, so that the first gate layer can not only slow down the speed of a large amount of influx of unbalanced carriers from metal when being opened, but also reduce the magnitude of the formed transient influx current, and can ensure the driving current required by the phase change memory cell to execute the programming or reading operation. That is, the first leakage barrier layer, the second leakage barrier layer and the third leakage barrier provided in the embodiments of the present application will not be turned off and on during the whole operation process of the phase change memory (OTS is turned on, performs programming or reading operations), but have sufficient leakage current during the whole process. Since the leakage current is still large, it is also limited, and is much smaller than the transient in-rush current. Therefore, after at least one of the first leakage barrier layer, the second leakage barrier layer and the third leakage barrier is added, the first leakage barrier layer, the second leakage barrier layer and the third leakage barrier are equivalent to a valve, and the valve can pass current, but the current flowing through the valve is limited (only the leakage current is large), so that the speed of a large amount of unbalanced carriers from metal is slowed down, and the size of the formed transient in-rush current is reduced; meanwhile, when programming or reading operation is performed, the magnitude of the leakage current can be ensured to be capable of driving current required, so that the subsequent programming or reading operation is not affected. In other words, the first, second and third leakage barriers solve the technical problem of the present application by: although the thicknesses of the first leakage barrier layer, the second leakage barrier layer and the third leakage barrier are very thin, the energy bands of the first leakage barrier layer, the second leakage barrier layer and the third leakage barrier are not bent very severely due to the large leakage current, and carriers are mainly transported in a jumping manner through defect energy levels rather than in a tunneling manner. And because the leakage current is still limited and is much smaller than the transient in-rush current, the speed of a large amount of in-rush unbalanced carriers from metal is slowed down, and the size of the formed transient in-rush current is reduced.
Based on the above-described requirements for the first, second, and third drain barrier layers, in some embodiments, the forbidden bandwidths of the first, second, and third drain barrier layers are greater than the forbidden bandwidths of the first gate layer, and the thicknesses of the first, second, and third drain barrier layers are less than the thickness of the first gate layer.
The forbidden bandwidths of the first leakage barrier layer, the second leakage barrier layer and the third leakage barrier layer should be far larger than the forbidden bandwidth when the first gate layer is turned off, and at least close to the forbidden bandwidth when the first phase change memory layer is in the crystalline state (for example, the forbidden bandwidth when the first phase change memory layer is in the crystalline state is about 0.5 electron volt (eV)).
In the practical application process, the mode of increasing the forbidden bandwidths of the first leakage barrier layer, the second leakage barrier layer and the third leakage barrier layer comprises at least one of the following steps: the method includes reducing thicknesses of the first, second, and third drain barrier layers, increasing numbers of defects contained in the first, second, and third drain barrier layers, and using a wide forbidden band material.
Based on this, in some embodiments, constituent materials of the first, second, and third drain barrier layers include a wide bandgap semiconductor material.
Here, the thickness of the wide bandgap semiconductor material and the defects included therein should satisfy that a bandgap of the wide bandgap semiconductor material can reduce a transient in-rush current formed when the gate layer is turned on and that a leakage current of the wide bandgap semiconductor material can satisfy a driving requirement for the first phase change memory layer.
In some embodiments, the wide bandgap semiconductor material may include at least one of: silicon oxide; silicon nitride; silicon carbide; carbonitride. And the wide bandgap semiconductor material may be formed by controlling the time of the process and/or the reactants.
It is to be noted that, based on the above description of the requirements to be satisfied for the first drain barrier layer, the second drain barrier layer, and the third drain barrier layer, a wide band gap semiconductor material is used for the first drain barrier layer, the second drain barrier layer, and the third drain barrier layer. The thickness of the wide bandgap semiconductor material and the defects contained in the wide bandgap semiconductor material should be such that the bandgap of the wide bandgap semiconductor material can reduce transient inrush current formed when the gate layer is turned on and the leakage current of the wide bandgap semiconductor material can meet the driving requirement of the first phase change memory layer. In some embodiments, the wide bandgap semiconductor material is on the order of nanometers thick.
In practice, the formation of wide bandgap semiconductor materials may be by controlling the time of the process and/or the reactant formation due to their relatively small thickness. In other words, since the thickness of the wide bandgap semiconductor material is relatively small, the thickness of the thin film purposely dedicated to growing the wide bandgap semiconductor material is often not required, and thus the thin film of the wide bandgap semiconductor material is not dedicated to manufacturing, but is formed in a process by controlling the duration and/or reactants thereof.
In addition, when the thin film of the wide band gap semiconductor material is formed, the thin film is mainly matched with the deposition and etching processes of other film materials in the unit according to the matching process, and meanwhile, the cross contamination limit of a production line is met, so that the wide band gap semiconductor material can be formed by adopting the semiconductor process. And the wide forbidden band semiconductor material can be made of silicon/oxygen/carbon/nitrogen and other elements, and the films formed by the materials have different etching selectivity ratios with film layers formed by other materials, so that the controllability of an etching process is improved, the structure is more stable, element diffusion and element universality are not easy to occur, the risk of cross contamination is reduced, and the stress regulating capability is stronger.
In particular, see the band structure of the phase change memory of fig. 6 shown in fig. 7. In the communication structure of Metal-OTS-Metal, a wide forbidden band material with small thickness is added to serve as a stable potential barrier to block/limit inrush current formed by non-equilibrium carrier inrush, so that the formation of inrush current is controlled.
The first drain barrier layer, the second drain barrier layer, and the third drain barrier layer may be provided with drain barrier layers at a plurality of positions. However, in the practical application process, the arrangement of the leakage barrier layers at a plurality of positions increases additional resistance, so that the resistance window and the detection sensitivity of the memory cell are reduced; raising the detection range of the whole voltage signal, and causing interference to the design of a logic circuit; and because the operation current of the phase change memory unit is higher, the barrier layer resistance can easily generate heat, on one hand, the power consumption of the memory chip is greatly improved, and on the other hand, the thermal crosstalk can be enhanced, so that the reliability of the chip is influenced. Therefore, the leakage barrier layer is preferably provided at a selected position within a reasonable range. According to experimental effects, the first leakage barrier layer has a smaller effect on the inrush current than the second and third leakage barrier layers.
In some embodiments, phase change memory 2000 further comprises:
a substrate;
the first isolation structure is alternately arranged on the surface of the substrate along a first direction in parallel with the first conductive wires and the first phase change memory cells which are stacked; wherein the first direction is parallel to the substrate surface;
the second isolation structure is alternately arranged on the surface of the substrate in parallel with the first phase change memory cells and the second conductive wires which are stacked along a second direction; wherein the second direction is parallel to the substrate and the second direction is perpendicular to the first direction.
Illustratively, the substrate refers to a material to which subsequent layers of material are added. The substrate may comprise a semiconductor material, such as silicon, germanium, or gallium arsenide, or the like.
Here, the first isolation structure serves to electrically isolate adjacent first phase change memory cells 2200 in a first direction. The first isolation structure also serves to electrically isolate adjacent first conductive lines 2100 in a first direction. It is noted that a larger amount of heat is generated during the phase change of the first phase change memory layer 2250, and thus, the first isolation structure is also used for thermal isolation in order to reduce crosstalk between adjacent first phase change memory cells 2200. In connection with the phase change memory shown in fig. 6, the first direction is parallel to the x-axis direction and the second direction is parallel to the y-axis (not shown) direction. Wherein the y-axis is perpendicular to the zox plane.
In some embodiments, the first isolation structure comprises: a first isolation layer arranged along a direction perpendicular to the first direction and covering the side wall of the third electrode layer and the side wall of the first phase change memory layer;
and the second isolation layer is arranged along the direction perpendicular to the first direction and covers the second electrode layer side wall, the first gating layer side wall, the first electrode layer side wall and the first conductive wire side wall.
Illustratively, the first isolation layer is located between the second isolation layer and the third electrode layer 2260 layer, and the first isolation layer is located between the second isolation layer and the phase change memory layer 2250. The first isolation layer may be used to encapsulate sidewalls of the first phase change memory cell 2200 parallel to the second direction. Illustratively, the first isolation layer may include a first insulating nitride layer and a first oxide layer, wherein the first insulating nitride is located between the first oxide layer and the third electrode layer 2260 layer, and the first insulating nitride is located between the first insulating oxide layer and the first phase change memory layer 2250. The second isolation layer may be used to thermally isolate adjacent first phase change memory cells 2200. Illustratively, the second isolation layer may include a second insulating nitride layer and a second oxide layer having a lower thermal conductivity, wherein the second insulating nitride layer is located between the second oxide layer and the first isolation layer, and the second insulating nitride layer is located between the second oxide layer and the second electrode layer 2240, the first gate layer 2230, the first electrode layer 2220, and the first conductive line 2100, respectively.
Here, the second isolation structure serves to electrically isolate adjacent memory cells 1200 in the second direction. The second isolation structure also serves to electrically isolate adjacent second conductive lines 1300 in a second direction. It should be noted that during the phase change of phase change memory layer 1250, a larger amount of heat is generated, and therefore, the second isolation structure is also used for thermal isolation in order to reduce crosstalk between adjacent memory cells 1200. It should also be noted that the second isolation structure and the first isolation structure may comprise the same constituent materials. The constituent materials of the second isolation structure and the first isolation structure may include a material having a low thermal conductivity.
In some embodiments, the second isolation structure may include:
a third isolation layer arranged along a direction perpendicular to the second direction and covering the side wall of the third electrode layer and the side wall of the first phase-change storage layer;
and a fourth isolation layer arranged along a direction perpendicular to the second direction and covering the second electrode layer side wall, the first gating layer side wall, the first electrode layer side wall and the second conductive wire side wall.
Here, the third isolation layer may be used to encapsulate the sidewalls of the first phase change memory cell 2200 parallel to the first direction. Illustratively, the third isolation layer may include a third insulating nitride layer and a third oxide layer, wherein the third insulating nitride layer is located between the third oxide layer and the second conductive line 2300, the third electrode layer 2260 layer, and the first phase-change memory layer 2250, respectively. The fourth isolation layer may be used to thermally isolate adjacent first phase change memory cells 2200. Illustratively, the fourth isolation layer may include a fourth insulating nitride layer and a fourth oxide layer having a lower thermal conductivity, wherein the fourth insulating nitride layer is located between the fourth oxide layer and the third isolation layer, and the fourth insulating nitride layer is located between the fourth oxide layer and the second electrode layer 2240, the first gate layer 2230, and the first electrode layer 2220, respectively.
The first leakage barrier layer, the second leakage barrier layer, and the third leakage barrier layer are also one layer stacked in the phase change memory cell, and therefore the first isolation structure includes a first isolation layer and a second isolation layer; and the third isolation layer and the fourth isolation layer contained in the second isolation structure also cover the side walls of the first leakage barrier layer, the second leakage barrier layer and the third leakage barrier layer.
In some embodiments, the phase change memory further comprises:
the first phase change memory layer has a first width and the second electrode layer has a second width along an extending direction parallel to the first conductive line; wherein the second width is greater than the first width;
and/or the number of the groups of groups,
the first phase change memory layer has a third width and the second electrode layer has a fourth width along an extending direction parallel to the second conductive line; wherein the fourth width is greater than the third width.
Illustratively, the first conductive line extends in a direction parallel to the second direction, and the second conductive line extends in a direction parallel to the first direction. The bottom of the phase change memory layer is in contact with the top of the second electrode layer. It will be appreciated that for each phase change memory cell, the bottom area of the phase change memory layer is smaller than the top area of the second electrode layer in a direction parallel to the substrate surface. For the phase-change storage layer with the same thickness, compared with the phase-change storage layer with the bottom area larger than or equal to the top area of the second electrode layer, the phase-change storage unit provided by the embodiment of the disclosure reduces the bottom area of the phase-change storage layer, so that the volume of the phase-change storage layer is reduced, and further, the energy required by the phase-change storage layer to generate the phase change is reduced, and the power consumption of the phase-change storage is reduced.
In some embodiments, phase change memory 2000 includes at least two phase change memory arrays disposed in a stack, each phase change memory array including a plurality of phase change memory cells; wherein the first conductive line or the second conductive line is disposed between two adjacent phase change memory arrays.
Therefore, in order to solve the technical problems provided by the embodiment of the application. In some embodiments, a further phase change memory is shown in FIG. 8. The phase change memory 2000 may further include: a third conductive line 2500 and a second phase change memory cell 2400 between the second conductive line and the third conductive line; wherein the third conductive line and the second conductive line are parallel to the same plane and are perpendicular to each other; the second phase change memory unit is perpendicular to the second conductive line and the third conductive line; and the second phase change memory unit 2400 includes: a fourth electrode layer 2410, a second gate layer 2420, a fifth electrode layer 2430, a second phase-change memory layer 2440, and a sixth electrode layer 2450, which are sequentially stacked; wherein,
the second phase change memory cell further includes at least one of: a fourth drain barrier layer 2460 stacked before the fourth electrode layer, a fifth drain barrier layer 2470 stacked between the fifth electrode layer and the second phase-change memory layer, and a sixth drain barrier layer 2480 stacked after the sixth electrode layer; the fourth drain barrier layer, the fifth drain barrier layer and the sixth drain barrier layer are configured to reduce transient in-rush current formed when the second gate layer is turned on.
Here, the second phase change memory cell shown in fig. 8 has the same structure and similar functions as the first phase change memory cell of fig. 6, and thus, the second phase change memory cell can be understood with reference to the first phase change memory cell described above, and the specific functions and structures thereof are not repeated herein.
Based on the same inventive concept, the embodiment of the application further provides a method for manufacturing a phase change memory, and specifically as shown in fig. 9, the method may include:
s901: forming a first conductive line;
s902: forming a first phase change memory cell; wherein the first phase change memory cell formed comprises: a first electrode layer, a first gate layer, a second electrode layer, a first phase change memory layer, and a third electrode layer which are sequentially stacked; and the first phase change memory cell further comprises and at least one of: a first drain barrier layer laminated in front of the first electrode layer, a second drain barrier layer laminated between the second electrode layer and the first phase change memory layer, and a third drain barrier layer laminated behind the third electrode layer; the first leakage barrier layer, the second leakage barrier layer and the third leakage barrier layer are used for reducing transient in-rush current formed when the first gating layer is opened;
S903: forming a second conductive line.
It should be noted that the number of the substrates,
in some embodiments, as shown in fig. 10, the manufacturing method may further include:
s904: forming a second phase change memory cell; wherein the second phase change memory cell formed includes: a fourth electrode layer, a second gate layer, a fifth electrode layer, a second phase-change memory layer, and a sixth electrode layer, which are sequentially stacked; and the second phase change memory cell further comprises at least one of: a fourth drain barrier layer laminated in front of the fourth electrode layer, a fifth drain barrier layer laminated between the fifth electrode layer and the second phase change memory layer, and a sixth drain barrier layer laminated behind the sixth electrode layer; the fourth leakage barrier layer, the fifth leakage barrier layer and the sixth leakage barrier layer are used for reducing transient in-rush current formed when the second gating layer is opened;
s905: forming a third conductive line.
The manufacturing method is based on the foregoing structure, and any process can be used to achieve the above technical effects. The semiconductor process is prioritized according to the foregoing description. Specifically, parameters of the process, such as duration, reactants, etc., can be regulated according to actual conditions.
Based on the same inventive concept, an embodiment of the present application also provides a memory system including: comprising the following steps: the phase change memory of any one or more of the preceding claims and a memory controller coupled to the phase change memory.
The memory system and the manufacturing method and the phase change memory described above belong to the same inventive concept, and the terms and operations appearing herein are described in detail and are not repeated here.
The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as would be used by one of ordinary skill in the art upon reading the above description. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, various features may be grouped together to simplify the present application. This should not be construed to mean that the disclosed features are not essential to any of the claims. Rather, the disclosed subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment, and it is contemplated that these embodiments may be combined with each other in various combinations or permutations. The scope of the application should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Claims (14)
1. A phase change memory, comprising:
a first phase change memory cell between a first conductive line, a second conductive line, and the first conductive line and the second conductive line; wherein the first conductive line and the second conductive line are parallel to the same plane and perpendicular to each other; the first phase change memory cell is perpendicular to the first conductive line and the second conductive line; and the first phase change memory cell includes: a first electrode layer, a first gate layer, a second electrode layer, a first phase change memory layer, and a third electrode layer which are sequentially stacked; wherein,
the first phase change memory cell further includes at least one of: a first drain barrier layer laminated in front of the first electrode layer, a second drain barrier layer laminated between the second electrode layer and the first phase change memory layer, and a third drain barrier layer laminated behind the third electrode layer; the first drain barrier layer, the second drain barrier layer and the third drain barrier layer are used for reducing transient in-rush current formed when the first gating layer is opened.
2. The phase change memory according to claim 1, wherein a forbidden band width of the first, second, and third drain barrier layers is greater than a forbidden band width of the first gate layer, and thicknesses of the first, second, and third drain barrier layers are less than a thickness of the first gate layer.
3. The phase change memory according to claim 1 or 2, wherein constituent materials of the first, second and third drain barrier layers include a wide bandgap semiconductor material.
4. The phase change memory of claim 3, wherein the wide bandgap semiconductor material comprises at least one of:
silicon oxide;
silicon nitride;
silicon carbide;
carbonitride.
5. The phase change memory according to claim 3, wherein the wide bandgap semiconductor material has a thickness and contains defects such that a bandgap of the wide bandgap semiconductor material is capable of reducing a transient in-rush current formed when the gate layer is turned on and such that a leakage current of the wide bandgap semiconductor material is capable of satisfying a driving requirement of the first phase change memory layer.
6. The phase change memory according to claim 5, wherein the wide bandgap semiconductor material is formed by controlling the time and/or reactants of a process.
7. The phase change memory of claim 1, further comprising: a third conductive line and a second phase change memory cell between the second conductive line and the third conductive line; wherein the third conductive line and the second conductive line are parallel to the same plane and are perpendicular to each other; the second phase change memory unit is perpendicular to the second conductive line and the third conductive line; and the second phase change memory cell includes: a fourth electrode layer, a second gate layer, a fifth electrode layer, a second phase-change memory layer, and a sixth electrode layer, which are sequentially stacked; wherein,
The second phase change memory cell further includes at least one of: a fourth drain barrier layer laminated in front of the fourth electrode layer, a fifth drain barrier layer laminated between the fifth electrode layer and the second phase change memory layer, and a sixth drain barrier layer laminated behind the sixth electrode layer; the fourth drain barrier layer, the fifth drain barrier layer and the sixth drain barrier layer are configured to reduce transient in-rush current formed when the second gate layer is turned on.
8. The phase change memory of claim 1, further comprising:
a substrate;
the first isolation structure is alternately arranged on the surface of the substrate along a first direction in parallel with the first conductive wires and the first phase change memory cells which are stacked; wherein the first direction is parallel to the substrate surface;
the second isolation structure is alternately arranged on the surface of the substrate in parallel with the first phase change memory cells and the second conductive wires which are stacked along a second direction; wherein the second direction is parallel to the substrate and the second direction is perpendicular to the first direction.
9. The phase change memory of claim 8, wherein the first isolation structure comprises: a first isolation layer arranged along a direction perpendicular to the first direction and covering the side wall of the third electrode layer and the side wall of the first phase change memory layer;
And the second isolation layer is arranged along the direction perpendicular to the first direction and covers the second electrode layer side wall, the first gating layer side wall, the first electrode layer side wall and the first conductive wire side wall.
10. The phase change memory of claim 8, wherein the second isolation structure comprises:
a third isolation layer arranged along a direction perpendicular to the second direction and covering the side wall of the third electrode layer and the side wall of the first phase-change storage layer;
and a fourth isolation layer arranged along a direction perpendicular to the second direction and covering the second electrode layer side wall, the first gating layer side wall, the first electrode layer side wall and the second conductive wire side wall.
11. The phase change memory of claim 1, further comprising:
the first phase change memory layer has a first width and the second electrode layer has a second width along an extending direction parallel to the first conductive line; wherein the second width is greater than the first width;
and/or the number of the groups of groups,
the first phase change memory layer has a third width and the second electrode layer has a fourth width along an extending direction parallel to the second conductive line; wherein the fourth width is greater than the third width.
12. A method of fabricating a phase change memory, comprising:
forming a first conductive line;
forming a first phase change memory cell;
forming a second conductive line;
wherein the first phase change memory cell formed comprises: a first electrode layer, a first gate layer, a second electrode layer, a first phase change memory layer, and a third electrode layer which are sequentially stacked; and the first phase change memory cell further comprises and at least one of: a first drain barrier layer laminated in front of the first electrode layer, a second drain barrier layer laminated between the second electrode layer and the first phase change memory layer, and a third drain barrier layer laminated behind the third electrode layer; the first drain barrier layer, the second drain barrier layer and the third drain barrier layer are used for reducing transient in-rush current formed when the first gating layer is opened.
13. The method of manufacturing of claim 12, further comprising:
forming a second phase change memory cell;
forming a third conductive line;
wherein the second phase change memory cell formed comprises: a fourth electrode layer, a second gate layer, a fifth electrode layer, a second phase-change memory layer, and a sixth electrode layer, which are sequentially stacked; and the second phase change memory cell further comprises at least one of: a fourth drain barrier layer laminated in front of the fourth electrode layer, a fifth drain barrier layer laminated between the fifth electrode layer and the second phase change memory layer, and a sixth drain barrier layer laminated behind the sixth electrode layer; the fourth drain barrier layer, the fifth drain barrier layer and the sixth drain barrier layer are configured to reduce transient in-rush current formed when the second gate layer is turned on.
14. A memory system, comprising: the phase change memory of any one or more of claims 1-11 and a memory controller coupled to the phase change memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310863863.0A CN116828972A (en) | 2023-07-13 | 2023-07-13 | Phase change memory, manufacturing method and memory system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310863863.0A CN116828972A (en) | 2023-07-13 | 2023-07-13 | Phase change memory, manufacturing method and memory system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116828972A true CN116828972A (en) | 2023-09-29 |
Family
ID=88125773
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310863863.0A Pending CN116828972A (en) | 2023-07-13 | 2023-07-13 | Phase change memory, manufacturing method and memory system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116828972A (en) |
-
2023
- 2023-07-13 CN CN202310863863.0A patent/CN116828972A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102132408B (en) | Storage element and storage device | |
| US8227783B2 (en) | Non-volatile resistive sense memory with praseodymium calcium manganese oxide | |
| US20170098683A1 (en) | Switch device and storage unit | |
| JP5439420B2 (en) | Storage device | |
| KR100782482B1 (en) | Phase change memory cell employing a GeBiTe layer as a phase change material layer, phase change memory device including the same, electronic device including the same and method of fabricating the same | |
| CN100550462C (en) | Resistor random access memory cell with L type electrode | |
| US20100084625A1 (en) | Memory Device | |
| WO2022021014A1 (en) | New cell structure with reduced programming current and thermal cross talk for 3d x-point memory | |
| US8957399B2 (en) | Nonvolatile memory element and nonvolatile memory device | |
| US11004902B2 (en) | Circuit element, storage device, electronic equipment, method of writing information into circuit element, and method of reading information from circuit element | |
| US9172037B2 (en) | Combined conductive plug/conductive line memory arrays and methods of forming the same | |
| WO2022104591A1 (en) | Vertical 3d pcm memory cell and program read scheme | |
| KR20170098673A (en) | Memory device | |
| US20150137062A1 (en) | Mimcaps with quantum wells as selector elements for crossbar memory arrays | |
| CN111384238B (en) | Gate tube material, gate tube unit and memory device structure | |
| KR20190088196A (en) | Switching device, method of fabricating the same, and non-volatile memory device having the same | |
| US20080112207A1 (en) | Solid electrolyte memory device | |
| US20090146131A1 (en) | Integrated Circuit, and Method for Manufacturing an Integrated Circuit | |
| KR20190065980A (en) | Next Generation Non-Volatile Mott Memory Device using Characteristic of Transition Metal Oxides | |
| US12040014B2 (en) | Configurable resistivity for lines in a memory device | |
| CN116828972A (en) | Phase change memory, manufacturing method and memory system | |
| WO2022115985A1 (en) | A novel liner confined cell structure and fabrication method with reduced programming current and thermal cross talk for 3d x-point memory | |
| WO2022115986A1 (en) | New liner electrode cell structure and fabrication method with reduced programming current and thermal cross talk for 3d x-point memory | |
| WO2022032490A1 (en) | New cell stack with reduced wl and bl resistance for 3d x-point memory to improve program and increase array size | |
| US11830816B2 (en) | Reduced resistivity for access lines in a memory array |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |