CN116827339A - Direct digital frequency synthesizer based on Taylor polynomial approximation and method thereof - Google Patents
Direct digital frequency synthesizer based on Taylor polynomial approximation and method thereof Download PDFInfo
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
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- G06F1/0321—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers
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Abstract
The invention provides a direct digital frequency synthesizer based on a Taylor polynomial approximation and a method thereof, comprising a phase accumulation module, a phase interceptor and a phase amplitude conversion module based on the Taylor polynomial approximation, wherein the output end of the phase accumulation module is connected with the input end of the phase interceptor, and the output end of the phase interceptor is connected with the input end of the phase amplitude conversion module based on the Taylor polynomial approximation; the phase accumulation module, the phase interceptor and the phase amplitude conversion module based on the Taylor polynomial approximation are respectively connected with a system clock, the phase accumulation module consists of an adder and a register which are sequentially connected, and the phase amplitude conversion module based on the Taylor polynomial approximation consists of a pi/4 multiplier, a logarithmic converter, a polynomial generating module, an adder-subtractor and a section selecting module which are sequentially connected. The invention effectively solves the problem of output spurious of the direct digital frequency synthesizer, greatly reduces the power consumption of the direct digital frequency synthesizer and ensures that the direct digital frequency synthesizer has better dynamic performance.
Description
Technical Field
The invention belongs to the technical field of digital frequency synthesis, and particularly relates to a direct digital frequency synthesizer based on taylor polynomial approximation and a method thereof.
Background
In recent years, a direct digital frequency synthesizer (Direct Digital Frequency Synthesizer, abbreviated as DDS) has the outstanding advantages of small volume, low production cost, high frequency resolution, easy intelligent control and the like, and is widely applied to a plurality of technical fields such as digital signal processing, digital integrated circuit design, radar measurement, satellite navigation and the like, and patent technical literature and non-patent technical literature closely related to the direct digital frequency synthesizer are layered endlessly.
For example, the invention patent application with application publication number CN104113333A discloses a direct digital frequency synthesizer, which comprises a clock frequency dividing module, a phase accumulating module, a phase splitting module, a phase amplitude converting module, a first interleaving sampling module, a digital-to-analog converting module and a second interleaving sampling module, wherein the clock frequency dividing module divides the frequency of the system clock and then provides sampling clocks for other 6 functional modules; the phase accumulation module carries out linear phase addition on an input frequency control word under the control of an input frequency division clock to output a phase value of a synthesized signal; the phase branching module branches and outputs the phase value output by the phase accumulating module to the phase amplitude conversion module under the control of the input frequency division clock; the phase-amplitude conversion module converts an input phase value into a corresponding amplitude value under the control of an input frequency division clock; the first interleaving sampling module interleaves and samples the amplitude value under the control of an input frequency division clock to output a digital signal; the digital-to-analog conversion module converts the digital signal into an analog signal under the control of the input frequency division clock, and then the analog signal is interleaved and sampled by the second interleaving sampling module to output a signal with the same frequency as the system clock.
As another example, the invention of the publication CN106774630B discloses a compensated direct digital frequency synthesizer, which comprises the following components in addition to a phase accumulator, a sine lookup table ROM, a digital-to-analog converter DAC and a low pass filter LPF in a conventional direct digital frequency synthesizer:
the phase accumulation register is used for generating a first data stream, namely a standard signal X [ n ] of an nth clock before phase truncation and an error signal e [ n ] of the nth clock after phase truncation, wherein n is an integer greater than or equal to 0;
a phase cut compensation coefficient calculator that calculates a phase cut compensation coefficient Ck [ n ] (k=1, 2,3,4, 5) of an nth clock from the first data stream;
a delay alignment unit 1, configured to align the phase truncation compensation coefficient Ck [ n ] of the nth clock with a second data stream generated by a sinusoidal lookup table ROM;
the phase cut-off compensator is used for carrying out linear and nonlinear compensation on the second data stream after delay alignment according to the phase cut-off compensation coefficient Ck [ n ] of the nth clock;
the working frequency and the storage capacity of the sine lookup error table ROM are identical to those of the sine lookup error table ROM, but each storage unit stores a quantization error e' n of an nth clock of a corresponding amplitude value;
an adder for accumulating the data of the same address unit of the sine lookup table ROM and the sine lookup error table ROM to obtain a third data stream;
a delay alignment unit 2 for aligning the quantization error e' n of the nth clock of the amplitude value with the third data stream;
an amplitude quantization error compensation coefficient calculator for calculating an amplitude quantization error compensation coefficient according to the third data stream X 'n and the quantization error e' n after time delay alignment;
a delay alignment unit 3 for aligning the data stream generated by the phase truncation compensator with the amplitude quantization error compensation coefficient;
and the amplitude quantization error compensator further performs linear and nonlinear compensation on the data output by the phase truncation compensator according to the amplitude quantization error compensation coefficient C' k [ n ] (k=1, 2,3,4, 5) of the nth clock after delay alignment, and finally transmits the compensated data to the digital-to-analog converter.
For another example, the basic structure, the working principle and the research and development direction of the direct digital frequency synthesizer are systematically generalized and analyzed in the university of Beijing transportation research institute Song Yan 'research method and implementation of the direct digital frequency synthesizer'. It is particularly worth mentioning that the thesis systematically describing the application of taylor series approximation algorithm in the data conversion of direct digital frequency synthesizer has important reference function for the design of direct digital frequency synthesizer.
In general, the technical solutions disclosed in the above patent technical literature or non-patent technical literature show a technical trend in the field of direct digital frequency synthesizers to a certain extent, but the above prior art also has certain technical drawbacks. Taking the technical scheme disclosed in the patent application of CN104113333a as an example, the invention can obtain a high-speed sampling frequency by using a low-speed actual sampling clock, and meanwhile, the invention improves the frequency of an output signal and reduces the power consumption of a system, which is a remarkable advantage, however, the invention also has the defects of complex system and unreasonable algorithm adopted by data conversion. Taking the technical scheme disclosed in the patent of CN106774630B as an example, the invention better solves the problem of output spurious in a direct digital frequency synthesizer, but the phase-amplitude conversion in the invention is mainly realized based on the storage of a sine lookup table ROM, and the occupied area of the sine lookup table ROM is greatly increased and the power consumption is increased when the high-order output or higher frequency precision is expanded; in addition, the error design of the sine lookup table ROM also has the problem of inconsistent error bit width, if the maximum bit width is used, the consumption of resources is greatly increased, and the invention cannot work under the high-frequency condition due to the influence of address bits in the process of checking values. Taking the technical scheme disclosed in the 'direct digital frequency synthesizer' of the 'Shuoshi thesis as an example, the' Shuoshi thesis 'panoramas' shows the design method and the development trend of the 'direct digital frequency synthesizer' of the 'Shuoshi thesis, and systematically researches the application problem of the Taylor series approximation algorithm in the' direct digital frequency synthesizer ', however, the Taylor expansion in the's thesis is realized by fitting a sine lookup table ROM to look up a table, so that the technical defects of the 'CN 106774630B patent are also in the technical scheme disclosed in the's paper.
It should be noted that, the patent application of publication number CN 115001485A filed by the applicant before discloses a direct digital frequency synthesizer based on taylor polynomial approximation, which is superior to the above prior art in terms of technical principle, but has a disadvantage in terms of technical means for embodying the technical principle.
Disclosure of Invention
The present invention aims to reduce the output spurious of a direct digital frequency synthesizer, reduce the power consumption of the direct digital frequency synthesizer and obtain better dynamic performance, thereby overcoming the defects of the prior art.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
the direct digital frequency synthesizer based on the Taylor polynomial approximation comprises a phase accumulation module (also called a phase accumulator module), a phase interceptor (also called a phase interceptor module or a phase interceptor) and a phase amplitude conversion module based on the Taylor polynomial approximation, wherein the output end of the phase accumulation module is connected with the input end of the phase interceptor, and the output end of the phase interceptor is connected with the input end of the phase amplitude conversion module based on the Taylor polynomial approximation; the phase accumulation module, the phase interceptor and the phase amplitude conversion module based on the Taylor polynomial approximation are respectively connected with a system clock, the phase accumulation module is composed of an adder and a register which are sequentially connected (the sequential connection refers to the connection relation of each device from front to back in the flow direction of the digital code, and the following is the same), the phase amplitude conversion module based on the Taylor polynomial approximation is composed of a pi/4 multiplier, a logarithmic converter, a polynomial generating module, an adder-subtractor and a section selecting module which are sequentially connected, wherein the total number of the polynomial generating modules is 4, and the 4 polynomial generating modules are respectively connected with the logarithmic converter at the front end of the polynomial generating module and the adder-subtractor at the rear end of the polynomial generating module in a parallel connection mode.
On the basis of the technical scheme, the invention can be added with the following technical means so as to better realize the purpose of the invention:
the pi/4 multiplier is composed of a first adder, a second adder and a third adder which are sequentially connected.
Further, the logarithmic converter consists of a first "1" detector, a shifter and an adder.
Further, the 4-block polynomial generating module is composed of a multiplier, an anti-logarithmic converter and an adder which are sequentially connected.
Further, the anti-logarithmic converter consists of a first '1' converter, a shifter and an adder which are connected in sequence.
Based on the direct digital frequency synthesizer based on the taylor polynomial approximation corresponding to the technical scheme, the invention further provides a digital code processing method, which comprises the following steps:
step 1, when a digital code representing a phase increment is input to a phase accumulation module, the phase accumulation module outputs the phase digital code represented by the increment to a phase interceptor under the drive of a system clock;
step 2, after the phase interceptor intercepts the phase digital code, the phase digital code with the bit width of 18 bits is transmitted to a phase amplitude conversion module based on Taylor polynomial approximation;
and step 3, processing the phase digital code with the width of 18 bits by a phase amplitude conversion module based on the Taylor polynomial approximation, and outputting a sine and cosine amplitude digital code corresponding to the phase digital code.
Further, when executing step 1, the digital code representing the phase increment is added with the last phase digital code stored in the register through the adder, and then is output to the register to update the stored phase digital code;
further, step 3 comprises the sub-steps of:
step 3-1, after the pi/4 multiplier processes the phase digital code output by the phase accumulator, outputting the radian value digital code x corresponding to the phase digital code to the logarithmic converter;
step 3-2, after the logarithmic converter processes the radian value digital code x output by the pi/4 multiplier, outputting the logarithmic value log of the radian value digital code x to the four polynomial generating modules 2 x；
Step 3-3, the four polynomial generating modules process log values respectively 2 x, the logarithmic value is first passed through multiplier and preset coefficient b i Multiplying to obtain b i log 2 x, then log with a predetermined coefficient 2 a i Multiplying to obtain log 2 a i +b i log 2 x, then input to an anti-logarithmic converter to obtainFitting the four polynomial generating modules to obtain the final product
Step 3-4, the adder-subtractor outputs four polynomial generating modules according to the Taylor polynomial conversion relationAdding or subtracting, wherein the taylor polynomial conversion relations of sine and cosine are respectivelyAnd->
And 3-5, judging by the interval selection module through the high 3 bits of the phase digital code, and then selecting and outputting according to a sin/cos correlation formula.
Further, the pi/4 multiplier is composed of a first adder, a second adder and a third adder, when the pi/4 multiplier processes the phase digital codes, the first adder adds the phase digital codes shifted to the right by 1 bit, the phase digital codes shifted to the right by 2 bits and the phase digital codes shifted to the right by 5 bits and outputs the added phase digital codes to the second adder, the second adder adds the output of the first adder and the phase digital codes shifted to the right by 8 bits and outputs the added phase digital codes to the third adder, and the third adder adds the output of the second adder and the phase digital codes shifted to the right by 12 bits and outputs the output of the third adder as the radian value digital codes corresponding to the phase.
Further, the logarithmic converter consists of a first 1 detector, a shifter and an adder, the input radian value digital code is connected with the input of the first 1 detector, the input of the shifter and the input of the adder, the first 1 detector outputs an integer part of the logarithmic value of the radian value digital code, the shifter input and the adder jointly act and output a decimal part of the shifter input and the adder, and the integer part is spliced with the decimal part to obtain the logarithmic value digital code corresponding to the radian value digital code;
the anti-logarithmic converter consists of a first 1 converter, a shifter and an adder, wherein the first 1 converter converts the integer part of the logarithmic digital code into a numerical value i, then the ith bit is represented by the shifter as a bit 1, and then the anti-logarithmic conversion can be realized by receiving the subsequent data of the bit with the binary value of the decimal part of the logarithmic digital code, and the anti-logarithmic digital code of the logarithmic digital code is output.
Compared with the prior art, the invention has the main beneficial effects that:
the invention provides a direct digital frequency synthesizer based on the Taylor polynomial approximation by utilizing the Taylor polynomial and the periodic characteristics of the sine/cosine function, and the conversion between a fixed-point system and a logarithmic system is completed by using a high-efficiency converter unit, so that the cost of the hardware realization of the sine/cosine function is reduced, and good trade-off between the precision and the hardware cost is realized. In addition, the Taylor polynomial approximation is effectively utilized, so that the occupied memory space of a relevant lookup table is reduced, and the performance of the whole system is improved. In a word, the invention not only effectively solves the problem of output spurious of the direct digital frequency synthesizer, but also greatly reduces the power consumption of the direct digital frequency synthesizer and enables the direct digital frequency synthesizer to obtain better dynamic performance.
Drawings
FIG. 1 is a schematic diagram of the structure of one embodiment of the present invention;
fig. 2 is a schematic structural diagram of a phase-amplitude conversion module based on taylor polynomial approximation in this embodiment;
FIG. 3 is a schematic diagram of the structure of the pi/4 multiplier in this embodiment;
fig. 4 is a schematic diagram of the structure of the logarithmic converter in this embodiment;
fig. 5 is a schematic diagram of the structure of the antilog converter in this embodiment;
fig. 6 is a diagram illustrating the symmetry of the sine/cosine diagrams in this embodiment.
Detailed Description
In order to facilitate a more complete understanding of the technical solution of the present invention by those skilled in the art, an embodiment of the present invention is described below with reference to the accompanying drawings.
As shown in fig. 1, a direct digital frequency synthesizer based on taylor polynomial approximation includes a phase accumulation module (also referred to as a phase accumulator module), a phase interceptor (also referred to as a phase interceptor module or a phase interceptor), and a phase amplitude conversion module based on taylor polynomial approximation, wherein the phase accumulator, the phase interceptor, and the phase amplitude converter are respectively connected with a system clock. The digital codes representing the phase increment are input to a phase accumulation module, the phase accumulation module outputs the phase digital codes represented by the increment under the drive of a clock, the output of the phase accumulation module is connected with the input of a phase truncation module, the output of the phase truncation module is connected with the input of a phase amplitude conversion module, and the phase amplitude conversion module outputs sine and cosine amplitude digital codes corresponding to the phase digital codes.
In this embodiment, the phase accumulator is composed of an adder and a register, the phase increment digital code is added to the last phase digital code stored in the register by the adder, and then the last phase digital code is output to the register to update the stored phase digital code, where the bit width of the phase increment digital code and the phase digital code is 32 bits. The phase truncator is used for truncating the low order bits of the phase digital code output by the phase accumulator, and the bit width of the truncated phase digital code is 18 bits.
As shown in fig. 2, in this embodiment, the phase-amplitude conversion module based on taylor polynomial approximation performs conversion based on taylor polynomial, and is composed of a pi/4 multiplier, a logarithmic converter, a four-way polynomial generation module, an adder-subtractor and a section selection module.
Since the phase words output by the phase accumulator are not angle values, but the actual angle values are required by using taylor polynomials, the phase words obtained by the phase accumulator need to be mapped with the actual angles. For this purpose, the present embodiment performs this conversion by using a pi/4 multiplier as shown in fig. 3, where the input is the phase digital code output by the phase accumulator, and multiplies it by pi/4 to obtain the radian value digital code x corresponding to the phase. Because pi/4 can be expressed as pi/4.apprxeq.2 -1 +2 -2 +2 -5 +2 -8 +2 -12 The pi/4 multiplier is composed of 3 adders (CS_Adder) with carry (namely, the pi/4 multiplier is composed of a first Adder, a second Adder and a third Adder which are sequentially connected), the input is a phase digital code output by the phase accumulator, the first Adder adds a phase digital code which is shifted to the right by 1 bit, a phase digital code which is shifted to the right by 2 bits and a phase digital code which is shifted to the right by 5 bits and then transmits the phase digital code to the second Adder, the second Adder adds the output of the first Adder 1 and the phase digital code which is shifted to the right by 8 bits and then transmits the phase digital code to the third Adder, and the third Adder adds the output of the second Adder and the phase digital code which is shifted to the right by 12 bits and then outputs the phase digital code; the output of the third adder 3 is the radian value digital code corresponding to the phase. The calculation speed can be increased since only shifting and addition are used.
After the actual angle x is obtained, a sine/cosine function can be obtained through taylor polynomial approximation, and the whole calculation process is mainly realized through logarithmic calculation. The input of the logarithmic converter is the radian value digital code output by the pi/4 multiplier, and the output is the logarithmic value log of the radian value digital code 2 x。
In this embodiment, the logarithmic converter comprises a first "1" detector, a shifter and an adder, the input radian value digital code is connected to the first "1" detector input, the shifter input and the adder input, and the first "1" is connected to the first "1" detector input and the shifter input and the adder input "The detector outputs an integer part of the logarithmic value of the radian digital code, the shifter input and the adder act together to output a decimal part of the shifter input and the adder, and the integer part and the decimal part are spliced to obtain the 15-bit logarithmic value digital code corresponding to the radian digital code. Specifically, when a logarithm is calculated for a binary number, the embodiment first observes the position of the first "1" of the binary number, where the position corresponds to a position weight of 2 i The positive part of the logarithmic value of the number is i, and the decimal of the binary digit value of the subsequent bit can quickly obtain the logarithmic value of the number. For example, when the value is 27, the binary value is 11011, the first "1" appears at the position of the weight 24, the integer part is 4, the binary value of the decimal part is 1011, the whole value is 100.1011 (4.6875), the logarithmic value can be obtained, and the structure of the whole logarithmic converter is shown in fig. 4. In addition, a first 1 detector (FirstOneDetector) is used to detect the first non-zero bit of the input signal, i.e., the position where the most significant bit is 1. It determines the position of the most significant bit by detecting the amplitude of the input signal, the output of which is the integer part of the logarithmic value of the radian value digital code. This information is used to control the output frequency of the frequency synthesizer.
In this embodiment, the four polynomial generating modules (also called polynomial fitting modules) are composed of multipliers, adders and anti-logarithmic converters, the inputs are all logarithmic values of the radian digital codes, and the logarithmic values pass through the multipliers and the preset coefficient b i Multiplying to obtain b i log 2 x, then log with a predetermined coefficient 2 a i Multiplying to obtain log 2 a i +b i log 2 x, then input to an anti-logarithmic converter to obtainFour polynomial fitting modules can obtain +.>
In this embodiment, the antilog converter is composed of a first "1" converter, a shifter and an adder, the first "1" converter converts the integer part of the digital code into a value i, then the shifter is used to represent the ith bit as bit 1, and then the bit is connected with the binary value of the decimal part of the digital code to the subsequent data of the bit to realize the antilog conversion, and the antilog digital code of the digital code is output, and the structure of the entire antilog converter is shown in fig. 5. In operation, the first 1 converter (First One Converter) converts the amplitude of the input signal to a control parameter of the digital frequency synthesizer based on the output of the first 1 detector. It converts the most significant bit position information into an appropriate control signal (into a value i based on the integer part of the digital code) for adjusting the output frequency of the frequency synthesizer.
In this embodiment, the adder-subtractor is configured to output the four-way polynomial fitting module according to the taylor polynomial conversion relationshipAdding or subtracting, wherein the taylor polynomial conversion relation of sine and cosine is +.>And->From the perspective of the taylor polynomial, the precision is higher and higher as the sine function and the cosine function approach the increase of the order of the taylor polynomial. Since the power term of the Taylor polynomial selected by the invention is 7, the error is not more than 3×10 -7 Thus, the whole phase-amplitude conversion process can be accurately completed by the four polynomials, i.e. the final completed conversion value can be obtained by the logarithmic converter, adder, pi/4 multiplier, anti-logarithmic converter and corresponding addition. In the calculation process, log 2 x can be reused by the same unit, coefficient log 2 a i The invention can greatly reduce the consumption of circuit resources because of a fixed value. .
In addition, as shown in FIG. 6, the sine/cosine function has the symmetry of the trigrams, soTo divide a complete cycle into eight parts, respectively In the phase-amplitude conversion process, the sine value and the cosine value in the interval are obtained by calculation, and the sine value and the cosine value in the whole period can be obtained by mirror image, inversion and other operations, so that the intermediate selection module in the embodiment judges through the high 3 bits of the phase digital code, divides the whole period into 8 intervals, and judges through the 3-bit digital code.
The above description is made of the structural features, the working principle and the method for processing digital codes according to an embodiment of the present invention with reference to the accompanying drawings, and the method includes the following steps:
step 1, when a digital code representing a phase increment is input to a phase accumulation module, the phase accumulation module outputs the phase digital code represented by the increment to a phase interceptor under the drive of a system clock;
step 2, after the phase interceptor intercepts the phase digital code, the phase digital code with the bit width of 18 bits is transmitted to a phase amplitude conversion module based on Taylor polynomial approximation;
and step 3, processing the phase digital code with the width of 18 bits by a phase amplitude conversion module based on the Taylor polynomial approximation, and outputting a sine and cosine amplitude digital code corresponding to the phase digital code.
When executing step 1, the digital code representing the phase increment is added with the last phase digital code stored in the register through the adder, and then is output to the register to update the stored phase digital code;
step 3 comprises the following sub-steps:
step 3-1, after the pi/4 multiplier processes the phase digital code output by the phase accumulator, outputting the radian value digital code x corresponding to the phase digital code to the logarithmic converter;
step 3-2, logarithmic converter pair piAfter the radian value digital code x output by the/4 multiplier is processed, the log value log of the radian value digital code x is output to four polynomial generating modules 2 x；
Step 3-3, the four polynomial generating modules process log values respectively 2 x, the logarithmic value is first passed through multiplier and preset coefficient b i Multiplying to obtain b i log 2 x, then log with a predetermined coefficient 2 a i Multiplying to obtain log 2 a i +b i log 2 x, then input to an anti-logarithmic converter to obtainFitting the four polynomial generating modules to obtain the final product
Step 3-4, the adder-subtractor outputs four polynomial generating modules according to the Taylor polynomial conversion relationAdding or subtracting, wherein the taylor polynomial conversion relations of sine and cosine are respectivelyAnd->
And 3-5, judging by the interval selection module through the high 3 bits of the phase digital code, and then selecting and outputting according to a sin/cos correlation formula.
The pi/4 multiplier is composed of a first adder, a second adder and a third adder, when the pi/4 multiplier processes the phase digital codes, the first adder adds the phase digital codes shifted to the right by 1 bit, the phase digital codes shifted to the right by 2 bits and the phase digital codes shifted to the right by 5 bits and outputs the added phase digital codes to the second adder, the second adder adds the output of the first adder and the phase digital codes shifted to the right by 8 bits and outputs the added phase digital codes to the third adder, and the third adder adds the output of the second adder and the phase digital codes shifted to the right by 12 bits and outputs the output radian value digital codes corresponding to the phase.
The logarithmic converter consists of a first 1 detector, a shifter and an adder, wherein the input radian value digital code is connected with the input of the first 1 detector, the input of the shifter and the input of the adder, the first 1 detector outputs an integer part of the logarithmic value of the radian value digital code, the shifter input and the adder jointly act and output a decimal part of the shifter input and the adder, and the integer part is spliced with the decimal part to obtain the logarithmic value digital code corresponding to the radian value digital code;
the anti-logarithmic converter consists of a first 1 converter, a shifter and an adder, wherein the first 1 converter converts the integer part of the logarithmic digital code into a numerical value i, then the ith bit is represented by the shifter as a bit 1, and then the anti-logarithmic conversion can be realized by receiving the subsequent data of the bit with the binary value of the decimal part of the logarithmic digital code, and the anti-logarithmic digital code of the logarithmic digital code is output.
Claims (10)
1. The direct digital frequency synthesizer based on the Taylor polynomial approximation comprises a phase accumulation module, a phase interceptor and a phase amplitude conversion module based on the Taylor polynomial approximation, wherein the output end of the phase accumulation module is connected with the input end of the phase interceptor, and the output end of the phase interceptor is connected with the input end of the phase amplitude conversion module based on the Taylor polynomial approximation; the phase accumulation module, the phase interceptor and the phase amplitude conversion module based on the taylor polynomial approximation are also respectively connected with a system clock, and the phase interceptor and the phase amplitude conversion module are characterized in that: the phase accumulation module consists of an adder and a register which are sequentially connected, and the phase amplitude conversion module based on the Taylor polynomial approximation consists of a pi/4 multiplier, a logarithmic converter, a polynomial generating module, an adder-subtractor and a section selecting module which are sequentially connected, wherein the polynomial generating module is totally 4 blocks, and the 4 blocks of polynomial generating modules are respectively connected with the logarithmic converter at the front end and the adder-subtractor at the rear end in a parallel connection mode.
2. The direct digital frequency synthesizer based on taylor polynomial approximation of claim 1, wherein: the pi/4 multiplier is composed of a first adder, a second adder and a third adder which are sequentially connected.
3. The direct digital frequency synthesizer based on taylor polynomial approximation of claim 1, wherein: the logarithmic converter consists of a first '1' detector, a shifter and an adder.
4. The direct digital frequency synthesizer based on taylor polynomial approximation of claim 1, wherein: the 4-block polynomial generating module consists of a multiplier, an anti-logarithmic converter and an adder which are sequentially connected.
5. The direct digital frequency synthesizer based on taylor polynomial approximation of claim 4, wherein: the anti-logarithmic converter consists of a first '1' converter, a shifter and an adder which are connected in sequence.
6. A digital code processing method, characterized in that a direct digital frequency synthesizer based on taylor polynomial approximation according to any one of claims 1 to 5 is used, comprising the steps of:
step 1, when a digital code representing a phase increment is input to a phase accumulation module, the phase accumulation module outputs the phase digital code represented by the increment to a phase interceptor under the drive of a system clock;
step 2, after the phase interceptor intercepts the phase digital code, the phase digital code with the bit width of 18 bits is transmitted to a phase amplitude conversion module based on Taylor polynomial approximation;
and step 3, processing the phase digital code with the width of 18 bits by a phase amplitude conversion module based on the Taylor polynomial approximation, and outputting a sine and cosine amplitude digital code corresponding to the phase digital code.
7. The digital code processing method as claimed in claim 6, wherein:
when executing step 1, the digital code representing the phase increment is added with the last phase digital code stored in the register through the adder, and then is output to the register to update the stored phase digital code.
8. The digital code processing method as claimed in claim 6, wherein: step 3 comprises the following sub-steps:
step 3-1, after the pi/4 multiplier processes the phase digital code output by the phase accumulator, outputting the radian value digital code x corresponding to the phase digital code to the logarithmic converter;
step 3-2, after the logarithmic converter processes the radian value digital code x output by the pi/4 multiplier, outputting the logarithmic value log of the radian value digital code x to the four polynomial generating modules 2 x；
Step 3-3, the four polynomial generating modules process log values respectively 2 x, the logarithmic value is first passed through multiplier and preset coefficient b i Multiplying to obtain b i log 2 x, then log with a predetermined coefficient 2 a i Multiplying to obtain log 2 a i +b i log 2 x, then input to an anti-logarithmic converter to obtainFitting the four polynomial generating modules to obtain the final product
Step 3-4, the adder-subtractor outputs four polynomial generating modules according to the Taylor polynomial conversion relationAdding or subtracting, wherein the taylor polynomial conversion relations of sine and cosine are respectivelyAnd->
And 3-5, judging by the interval selection module through the high 3 bits of the phase digital code, and then selecting and outputting according to a sin/cos correlation formula.
9. The digital code processing method as claimed in claim 8, wherein: the pi/4 multiplier is composed of a first adder, a second adder and a third adder, when the pi/4 multiplier processes the phase digital codes, the first adder adds the phase digital codes shifted to the right by 1 bit, the phase digital codes shifted to the right by 2 bits and the phase digital codes shifted to the right by 5 bits and outputs the added phase digital codes to the second adder, the second adder adds the output of the first adder and the phase digital codes shifted to the right by 8 bits and outputs the added phase digital codes to the third adder, and the third adder adds the output of the second adder and the phase digital codes shifted to the right by 12 bits and outputs the output radian value digital codes corresponding to the phase.
10. The digital code processing method as claimed in claim 8, wherein: the logarithmic converter consists of a first 1 detector, a shifter and an adder, wherein the input radian value digital code is connected with the input of the first 1 detector, the input of the shifter and the input of the adder, the first 1 detector outputs an integer part of the logarithmic value of the radian value digital code, the shifter input and the adder jointly act and output a decimal part of the shifter input and the adder, and the integer part is spliced with the decimal part to obtain the logarithmic value digital code corresponding to the radian value digital code;
the anti-logarithmic converter consists of a first 1 converter, a shifter and an adder, wherein the first 1 converter converts the integer part of the logarithmic digital code into a numerical value i, then the ith bit is represented by the shifter as a bit 1, and then the anti-logarithmic conversion can be realized by receiving the subsequent data of the bit with the binary value of the decimal part of the logarithmic digital code, and the anti-logarithmic digital code of the logarithmic digital code is output.
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