CN101082858A - Device for realizing CORDIC algorithm - Google Patents
Device for realizing CORDIC algorithm Download PDFInfo
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- CN101082858A CN101082858A CN 200710118697 CN200710118697A CN101082858A CN 101082858 A CN101082858 A CN 101082858A CN 200710118697 CN200710118697 CN 200710118697 CN 200710118697 A CN200710118697 A CN 200710118697A CN 101082858 A CN101082858 A CN 101082858A
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Abstract
The invention discloses a realizing device of CORDIC algorism with input plural executing angle at thita (0<=thita<2pi), which comprises the following parts: control unit, m1 graded direction vector generating unit, m1 graded angle rotary unit, m2 graded mode correcting unit and output unit, wherein each direction vector generating element continuously generates n direction vectors in one data period, which deflects n times for angle rotary unit; each graded mode correcting unit does n iterating calculations. the parameter m1, m2 and n can be allocated according to calculating precision and time delay, which is natural number (3<=m1<=6, 2<=m2<=4, 2<=n<=8); the multi-grade CORDIC calculating structure saves more energy than traditional CORDIC stream line by over one third, which reduces time delay.
Description
Technical field
The present invention relates to a kind of implement device of cordic algorithm, belong to digital processing field.
Background technology
CORDIC (CORDIC) algorithm is proposed in nineteen fifty-nine by J.E.Volder, its thought is approached the required anglec of rotation by the continuous beat of a series of fixing, relevant with computing radix angles, with simply displacement, additive operation have replaced complicated multiplying.This algorithm is applied to navigational system the earliest, makes that vector rotation and directed computing need no longer to do that trigonometric function is tabled look-up, complex process such as multiplication, evolution and inverse trigonometric function.1971, Walther was generalized to cordic algorithm in the unified calculation of various elementary functions, and along with the development of VLSI (VLSI (very large scale integrated circuit)) technology, cordic algorithm has obtained using widely.Because cordic algorithm comprises repeatedly iterative process, for reducing clock request, its circuit is realized having abandoned single step arrangement, generally adopts the streamline form.For example, patent of invention 200410013670.3 discloses a kind of based on CORDIC cellular array formula restructural DSP engine chip structure, by using modular structure to realize the compatibility that the wide CORDIC of different words is calculated, but basic structure still is traditional streamline; Patent of invention 200580003296.1 discloses a kind of compound realization of the cordic algorithm of rotation mutually that is used for, though adopt compound phase vector rotation to realize that cordic algorithm has reduced pipeline series, but can not use simple " displacement-Jia " to realize that hardware resource consumption is still very big owing to calculate.The CORDIC of pipeline organization has advantages such as speed is fast, the circuit realization is simple, but,, cause time delay and resource consumption also considerable because pipeline series is many, therefore be necessary to seek a kind of new cordic algorithm implementation structure, on speed and chip area, obtain preferably and optimize.
Summary of the invention
The implement device that the purpose of this invention is to provide a kind of cordic algorithm is used to shorten the CORDIC time delay of streamline form, and economizes on resources.
A kind of cordic algorithm implement device of the present invention comprises: control module, m
1Level direction vector generating unit, m
1Level angle rotary unit, m
2Level mould correcting unit and output unit.This device can be the rotation of θ (0≤θ＜2 π) to importing plural number enforcement angle.The input clock of this device comprises data clock clk1 and iteration clock clk2, and wherein, clk2 is the n frequency multiplication of clk1.According to output data precision, clock request, can be to the progression m of direction vector generating unit, angle rotary unit
1Progression m with the mould correcting unit
2And parameter n is configured, here m
1, m
2, n is natural number, generally gets 2≤n≤8,3≤m
1≤ 6,2≤m
2≤ 4.
Above-mentioned control module comprises one along detecting device and a counter.Detect along the rising edge of detecting device, realize the synchronous of clk1 and clk2, produce and select control signal clk1.Counter is counted clk2, and iterative process is carried out synchronously and control, produces the iteration count signal.
Above-mentioned m
1Level direction vector generating unit, unit at different levels include a MUX, a storer, an arithmetical unit and a d type flip flop.MUX is selected the outside input angle degree θ (or output of prime d type flip flop) and the output of d type flip flop at the corresponding levels, then the sign bit of output is exported as direction vector δ.Storer is used to store deviation angle γ
i(1≤i≤m
1N), when 1≤i≤6, γ
i=π/4; When 6＜i≤mn, γ
i=arctan (2
6-i).K (1≤k≤m wherein
1) a deviation angle in the level direction vector generating unit storer is γ
i((k-1) n+1≤i≤kn), the iteration count signal that storer sends according to control module, the output of selecting corresponding deviation angle to send into arithmetical unit and MUX is calculated, and account form is determined by direction vector.Result of calculation is deposited in the d type flip flop.
Above-mentioned m
1Level angle rotary unit, unit at different levels include a MUX, a shift unit, an arithmetical unit and a d type flip flop.The angle rotary unit is corresponding one by one with the unit at different levels of direction vector generating unit, and working method is similar, MUX is used for input to be selected, and the account form of arithmetical unit determines that by the direction vector that k level direction vector generating unit produces d type flip flop is used to deposit result of calculation.Difference is that the position of angle rotary unit storer in the direction vector generating unit replaces shift unit.The iteration count signal that shift unit sends according to control module carries out dextroposition to the output of MUX and handles, with deviation angle γ
iCorrespondence, the figure place that moves to right s
i(1≤i≤m
1N) be: when 1≤i≤6, s
i=0; When 6＜i≤mn, s
i=i-6.Wherein, the figure place that moves to right of shift unit is s in the k level angle rotary unit
i((k-1) n+1≤i≤kn).The output of MUX and shift unit will be fed through in the arithmetical unit and calculate.
Above-mentioned m
2Level mould correcting unit, unit at different levels include a MUX, a shift unit, an arithmetical unit and a d type flip flop.The mould correcting unit is used to finish the multiply operation of output of afterbody angle rotary unit and mould correction coefficient (0.075906617).Well known in the art, the constant multiplication can calculate with " displacement-Jia " and realize that the mould correcting unit promptly adopts this mode to carry out.The working method of mould correcting units at different levels and angle rotary unit are similar, and difference is that the figure place that moves to right of shift unit is determined by the mould correction coefficient in the iterative process, only carries out subtraction in the arithmetical unit, does not need to provide direction vector.
Above-mentioned output unit receives the result of calculation of afterbody mould correcting unit, and it is outputed to the device outside.
Above-mentioned m
1Between the level direction vector generating unit, m
1Between the level angle rotary unit, m
2Between the level mould correcting unit and m
1All adopt cascade system to be connected between level angle rotary unit and the 1st grade of mould correcting unit, under the control of iteration count signal, each clk1 is in the cycle, and units synchronization at different levels are finished iteration n time.
In sum, cordic algorithm implement device provided by the invention and traditional pipelined cordic only carry out an iterative computation and compare in every grade of unit in the cycle at a clk1, this device is by carrying out repeatedly iteration every grade of unit inter-sync, reduce CORDIC and calculated progression, thereby reduced resource consumption.This device can be widely used in digital processing field.
Description of drawings
Fig. 1 is 4 grades of CORDIC computing structural representations.
Fig. 2 is the control module synoptic diagram.
Fig. 3 is a direction vector generating unit synoptic diagram.
Fig. 4 is an angle rotary unit synoptic diagram.
Fig. 5 is a mould correcting unit synoptic diagram.
Wherein 10 is control module CU, the 20th, m
1Level direction vector generating unit DGU, the 30th, m
1Level angle rotary unit ARU, the 40th, m
2Level mould correcting unit MRU, the 50th, output unit OU, the 101st, CU be along monitor, the 102nd, CU counter, the 201st, DGU MUX, the 202nd, DGU storer, the 203rd, DGU arithmetical unit, the 204th, the d type flip flop of DGU, the 301st, ARU MUX, the 302nd, ARU shift unit, the 303rd, ARU arithmetical unit, the 304th, the d type flip flop of ARU, the 401st, MRU MUX, the 402nd, MRU shift unit, the 403rd, MRU arithmetical unit, the 404th, the d type flip flop of MRU.
Embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.
Embodiment 1: with 4 grades of CORDIC computing structure (m
1=4, m
2=2, n=4) be example.
4 grades of CORDIC computing structures as shown in Figure 1, this arithmetic unit is made of control module CU10,4 grades of direction vector generating unit DGU20,4 grades of angle rotary unit ARU30,2 grades of mould correcting unit MRU 40 and output unit OU 50.Clk2 is 4 frequencys multiplication of clk1, and in the cycle, direction vector generating unit DGU at different levels, angle rotary unit ARU and mould correcting unit MRU carry out iterative computation 4 times at a clk1.
Control module CU10 is by forming (as shown in Figure 2) along detecting device 101 and counter 102.The 2nd clk2 after the clk1 rising edge arrives is in the cycle, to select control signal sc to draw high along detecting device 101, all the other times then put low, counter is counted clk2, when sc begins zero clearing during for high level, the output ic maximal value of counter is 3, and signal sc and ic are input in direction vector generating unit DGU, angle rotary unit ARU and the mould correcting unit MRU unit, is used for the control of iterative computation process with synchronously.
(as shown in Figure 3) formed by a MUX 201, storer 202, an arithmetical unit 203 and a d type flip flop 204 in every grade of unit of level Four direction vector generating unit DGU 20.Getting the sign bit of MUX 201 outputs exports as direction vector δ.Work as ic=3, during sc=1, arithmetical unit 203 is sent in the output (for the 2nd～4 grade of DGU Unit 20) that MUX 201 is imported angle θ (for first order DGU Unit 20) or prime d type flip flop 204 with the outside, enters the 1st deviation angle in the storer 202 of also having of arithmetical unit 203 simultaneously.When δ=0, arithmetical unit 203 is carried out subtractions; When δ=1, arithmetical unit 203 is carried out additive operations, and operation result is deposited in the d type flip flop 204.Work as ic=0, at 1,2 o'clock, sc=0, MUX 201 is sent the output of d type flip flop 204 at the corresponding levels into arithmetical unit 203, enters the the 2nd, the 3rd or the 4th deviation angle in the storer 202 of also having of arithmetical unit 203 simultaneously, and operation result is deposited in the d type flip flop 204 equally.In cycle, the unit at different levels of DGU 20 produce 4 direction vectors at a clk1.
(as shown in Figure 4) formed by a MUX 301, shift unit 302, an arithmetical unit 303 and a d type flip flop 304 in every grade of anglec of rotation unit of level Four angle rotary unit ARU 30.When ic=3, sc=1, MUX 301 is sent the output (for the 2nd～4 grade of ARU Unit 30) of outside input plural number (for first order ARU Unit 30) or prime d type flip flop 304 into arithmetical unit 303, and the output of MUX 301 also enters in the arithmetical unit 303 after handling through dextroposition.When δ=0, arithmetical unit 303 obtains the real part result by subtraction, obtains the imaginary part result by additive operation; When δ=1, real part and imaginary part obtain by addition and subtraction respectively.Work as ic=0,1,2 o'clock, sc=0, MUX 301 is sent the output of d type flip flop 304 at the corresponding levels and one of the output of shift unit 302 into arithmetical unit 303, and operation result is deposited in the d type flip flop 304 equally.The figure place that moves to right in the shifting process is controlled by ic.
(as shown in Figure 5) formed by a MUX 401, shift unit 402, an arithmetical unit 403 and a d type flip flop 404 in every grade of unit of two-stage mould correcting unit MRU 40.When ic=3, sc=1, MUX 401 is sent the output (for first order MRU40 unit) of d type flip flop 304 in fourth stage ARU Unit 30 or the output (for second level MRU Unit 40) of prime d type flip flop 404 into arithmetical unit 403, the output of MUX 401 also enters in the arithmetical unit 403 after handling through dextroposition, and 403 of arithmetical unit are carried out subtraction.Work as ic=0,1,2 o'clock, sc=0, MUX 401 is sent the output of d type flip flop 404 at the corresponding levels and one of the output of shift unit 402 into arithmetical unit 403, and operation result is deposited in the d type flip flop 404 equally.The figure place that moves to right in the shifting process is controlled by ic.
In output unit OU50, when sc=1, the output of d type flip flop 404 in the MRU40 unit, the second level is received and deposits, output net result (promptly the input plural number is the postrotational result of θ through over-angle).
Above-mentioned CORDIC computing structure adopts 4 grades of direction vector generating units, 4 grades of angle rotary units to realize iterative computation 16 times, adopt 2 grades of mould correcting units to realize iterative computation 8 times, finish same iterative computation number of times if adopt pipeline organization, then need 16 grades of direction vector generating units, 16 grades of angle rotary units and 8 grades of mould correcting units respectively, compare with traditional CORDIC pipeline organization, 4 grades of CORDIC computing structures have reduced hardware resource consumption largely.
Claims (8)
1, a kind of implement device of cordic algorithm is characterized in that this device comprises:
Control module carries out synchronously data clock clk1 and iteration clock clk2, control iterative computation process, and clk2 is n (n is a natural number, generally the gets 2≤n≤8) frequency multiplication of clk1;
m
1Level direction vector generating unit, (m
1Be natural number, generally get 3≤m
1≤ 6), the deviation angle according to input angle θ and storage produces direction vector;
m
1Level angle rotary unit carries out " displacement-Jia " calculating according to direction vector to importing plural number;
m
2Level mould correcting unit, (m
2Be natural number, generally get 2≤m
2≤ 4), the mould correction coefficient is multiply by in postrotational output to angle, also adopts " displacement-Jia " to calculate and realizes;
Output unit receives and exports the result of calculation that mould is proofreaied and correct;
Above-mentioned m
1Between the level direction vector generating unit, m
1Between the level angle rotary unit, m
2Between the level mould correcting unit and m
1All adopt cascade system to be connected between level angle rotary unit and the 1st grade of mould correcting unit.
2, the implement device of a kind of cordic algorithm as claimed in claim 1, it is characterized in that: described control module is by constituting along detecting device and counter, realize that along detecting device clk1 and clk2's is synchronous, produce and select control signal, counter produces the iteration count signal, and iterative process is carried out synchronously and control.
3, the implement device of a kind of cordic algorithm as claimed in claim 1 is characterized in that: described m
1Level direction vector generating unit, unit at different levels are made of a MUX, a storer, an arithmetical unit and a d type flip flop respectively, the sign bit of MUX output is exported as direction vector, storer is used to store deviation angle, select also a corresponding deviation angle of selecting to be sent into arithmetical unit according to the iteration count signal that control module sends, calculate with the output of MUX, account form is determined by direction vector.
4, the implement device of a kind of cordic algorithm as claimed in claim 1 is characterized in that: described m
1Level angle rotary unit, unit at different levels are made of a MUX, a shift unit, an arithmetical unit and a d type flip flop respectively, angle rotary units at different levels are corresponding with the direction vector generating unit, and working method is similar, the iteration count signal that sends according to control module, shift unit carries out dextroposition to the output of MUX to be handled, the output of MUX and shift unit will be fed through in the arithmetical unit and calculate, and account form is determined by the direction vector that the direction vector generating unit produces.
5, the implement device of a kind of cordic algorithm as claimed in claim 1, it is characterized in that: described m2 level mould correcting unit, unit at different levels are made of a MUX, a shift unit, an arithmetical unit and a d type flip flop respectively, the working method of mould correcting units at different levels and angle rotary unit is similar, use " displacement-Jia " iterative computation to realize the multiply operation of afterbody angle rotation output and mould correction coefficient, the figure place that moves to right of shift unit is determined by the mould correction coefficient in the iterative process, only carries out subtraction in the arithmetical unit.
6, as the implement device of claim 1 or 2 or 3 or 4 or 5 described a kind of cordic algorithms, it is characterized in that: under the control of the iteration count signal that control module produces, each clk1 is in the cycle, and direction vector generating units at different levels, angle rotary unit, mould correcting unit are finished n time iteration respectively synchronously.
7, as the implement device of claim 1 or 3 or 4 or 5 described a kind of cordic algorithms, it is characterized in that:
Described MUX when selecting control signal to be high level, is selected the output of outer input data or prime d type flip flop, when selecting control signal to be low level, selects the output to d type flip flop at the corresponding levels.
8, as the implement device of claim 1 or 3 or 4 or 5 described a kind of cordic algorithms, it is characterized in that:
Described d type flip flop, the output that is used to deposit arithmetical unit.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101908123A (en) * | 2010-06-01 | 2010-12-08 | 福建新大陆电脑股份有限公司 | Hardware logic implementation device for Hough operation |
| CN101930351A (en) * | 2009-06-26 | 2010-12-29 | 深圳迈瑞生物医疗电子股份有限公司 | Transform operation method, transform operation device, coordinate rotation digital computation method and coordinate rotation digital computation device |
| CN101997533A (en) * | 2009-08-17 | 2011-03-30 | 炬力集成电路设计有限公司 | Arithmetical logic circuit and operation method thereof |
| CN102323878A (en) * | 2011-05-31 | 2012-01-18 | 电子科技大学 | Circuit device and method for norm correction of CORDIC (Coordinated Rotation Digital Computer) algorithm |
| CN103488459A (en) * | 2013-09-13 | 2014-01-01 | 复旦大学 | Complex multiplication unit based on modified high-radix CORDIC algorithm |
| CN105978570A (en) * | 2016-06-30 | 2016-09-28 | 中工科安科技有限公司 | High-precision signal processing system of sine and cosine encoder |
| CN110659014A (en) * | 2018-06-29 | 2020-01-07 | 赛灵思公司 | Multiplier and neural network computing platform |
| CN111666064A (en) * | 2020-06-03 | 2020-09-15 | 合肥工业大学 | Trigonometric function loop iteration solving method and device based on CORDIC |
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2007
- 2007-07-12 CN CNB2007101186972A patent/CN100511125C/en not_active Expired - Fee Related
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101930351A (en) * | 2009-06-26 | 2010-12-29 | 深圳迈瑞生物医疗电子股份有限公司 | Transform operation method, transform operation device, coordinate rotation digital computation method and coordinate rotation digital computation device |
| CN101997533B (en) * | 2009-08-17 | 2014-07-16 | 炬力集成电路设计有限公司 | Arithmetical logic circuit and operation method thereof |
| CN101997533A (en) * | 2009-08-17 | 2011-03-30 | 炬力集成电路设计有限公司 | Arithmetical logic circuit and operation method thereof |
| CN101908123A (en) * | 2010-06-01 | 2010-12-08 | 福建新大陆电脑股份有限公司 | Hardware logic implementation device for Hough operation |
| CN101908123B (en) * | 2010-06-01 | 2012-06-27 | 福建新大陆电脑股份有限公司 | Hardware logic implementation device for Hough operation |
| CN102323878A (en) * | 2011-05-31 | 2012-01-18 | 电子科技大学 | Circuit device and method for norm correction of CORDIC (Coordinated Rotation Digital Computer) algorithm |
| CN102323878B (en) * | 2011-05-31 | 2014-10-15 | 电子科技大学 | Circuit device and method for norm correction of CORDIC (Coordinated Rotation Digital Computer) algorithm |
| CN103488459A (en) * | 2013-09-13 | 2014-01-01 | 复旦大学 | Complex multiplication unit based on modified high-radix CORDIC algorithm |
| CN103488459B (en) * | 2013-09-13 | 2017-01-25 | 复旦大学 | Modified high-radix CORDIC method and complex multiplication unit based on modified high-radix CORDIC method |
| CN105978570A (en) * | 2016-06-30 | 2016-09-28 | 中工科安科技有限公司 | High-precision signal processing system of sine and cosine encoder |
| CN105978570B (en) * | 2016-06-30 | 2023-04-25 | 中工科安科技有限公司 | High-precision signal processing system of sine and cosine encoder |
| CN110659014A (en) * | 2018-06-29 | 2020-01-07 | 赛灵思公司 | Multiplier and neural network computing platform |
| CN110659014B (en) * | 2018-06-29 | 2022-01-14 | 赛灵思公司 | Multiplier and neural network computing platform |
| CN111666064A (en) * | 2020-06-03 | 2020-09-15 | 合肥工业大学 | Trigonometric function loop iteration solving method and device based on CORDIC |
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