CN105978570B - High-precision signal processing system of sine and cosine encoder - Google Patents

High-precision signal processing system of sine and cosine encoder Download PDF

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CN105978570B
CN105978570B CN201610517319.0A CN201610517319A CN105978570B CN 105978570 B CN105978570 B CN 105978570B CN 201610517319 A CN201610517319 A CN 201610517319A CN 105978570 B CN105978570 B CN 105978570B
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文长明
文可
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
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    • H03M1/12—Analogue/digital converters
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
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Abstract

The invention discloses a high-precision signal processing system of a sine and cosine encoder, which comprises two gain circuits, two AD conversion subsystems, a quadruple frequency subsystem, a multiplier I, a CORDIC algorithm subsystem, a precision code calculation subsystem, a speed calculation subsystem, a multiplier II and two CRC check subsystems. The two gain circuits respectively receive Asinα and Bcosα with 90 degrees phase difference, and the outputs are respectively connected with the two AD conversion subsystems and the quadruple frequency subsystem. The first multiplier and the CORDIC algorithm subsystem are respectively connected with the fine code computing subsystem. And the output signal of the frequency doubling subsystem is overlapped with the output signal of the fine code computing subsystem and then is connected with the CRC subsystem and the speed computing subsystem through the multiplier II. The speed computing subsystem is connected with the CRC subsystem II, and the output ends of the two CRC subsystems are respectively used as two output ends of the whole system.

Description

High-precision signal processing system of sine and cosine encoder
Technical Field
The present invention relates to signal processing systems, and more particularly, to a high-precision signal processing system for a sine and cosine encoder.
Background
The incremental sine and cosine encoder is a precise sensor for measuring angular displacement and angular velocity. The sine and cosine encoder has the advantages of high resolution, high precision, non-contact measurement, reliable use and the like, and is widely used in the scientific fields of precise measurement, real-time control and the like.
With the increasing precision requirements of numerical control systems and modern industrial control systems, encoders with higher resolution and precision are required. However, the high precision requirements of the market on signals such as the position and the speed of the motor cannot be met only by means of improvement of hardware performance, so that the encoder output sine and cosine signals are further required to be electronically subdivided, and the precision of the encoder signals is improved. Common electronic subdivision methods include arctangent direct method, CORDIC algorithm, table look-up method, maxwell series method, closed-loop tracking method, signal injection method, etc. The output signal is a TTL square wave encoder, the signal can only be subjected to 4 times frequency multiplication, and the requirement of carrying out more subdivision difference on the original signal can not be met.
Disclosure of Invention
The invention aims to provide a high-precision signal processing system of a sine and cosine encoder, which solves the technical problem of subdivision of an original signal by any multiple, and can be arbitrarily subdivided theoretically, so that a rotor real-time angle value (rad) and a rotor real-time speed value (rad/s) which are higher than the resolution of the original signal can be obtained through calculation.
The invention is realized by the following technical scheme: a high-precision signal processing system of sine and cosine encoder; the method is used for processing Asin alpha and Bco alpha which are 90 degrees different in phase between two paths of phases output by the incremental rotary encoder; the sine and cosine encoder high-precision signal processing system comprises a differential amplifier I, a differential amplifier II, an AD conversion subsystem I, an AD conversion subsystem II, a quadruple frequency subsystem, a multiplier I, a CORDIC algorithm subsystem, a precision code computing subsystem, a speed computing subsystem, a multiplier II, a CRC checking subsystem I and a CRC checking subsystem II; the input end of the differential amplifier I receives Asinα, and the output end of the differential amplifier I is simultaneously connected with the input end of the AD conversion subsystem and the input end of the quadruple frequency subsystem; the input end of the second differential amplifier receives Bcosa, and the output end of the second differential amplifier is simultaneously connected with the input end of the second AD conversion subsystem and the input end of the second quadruple frequency subsystem; two paths of output signals of the two AD conversion subsystems are connected with two input ends of the CORDIC algorithm subsystem, the other two paths of output signals of the two AD conversion subsystems are connected with two input ends of the first multiplier, and the output end of the first multiplier and the output end of the CORDIC algorithm subsystem are respectively connected with two input ends of the fine code calculation subsystem; the output signal of the quadruple frequency subsystem is overlapped with the output signal of the fine code computing subsystem and then is sent to the first input end of the second multiplier, and the output end of the second multiplier is simultaneously connected with the first input end of the CRC subsystem and the input end of the speed computing subsystem; the output end of the CRC subsystem is used as the output end I of the high-precision signal processing system of the whole sine and cosine encoder, the output end of the speed calculation subsystem is connected with the input end II of the CRC subsystem, and the output end II of the CRC subsystem is used as the output end II of the high-precision signal processing system of the whole sine and cosine encoder.
As a further improvement of the scheme, one end of the limiter is used as an input end of the AD conversion subsystem, the other end of the limiter is sequentially connected in series to obtain an absolute value I, a differential amplifier III and a quantizer I, the output end of the quantizer I is used as an output end I of the AD conversion subsystem, and the other end of the limiter is also connected with an input contact of the switch I; the other two input contacts of the switch I respectively receive two constants which are respectively 1 and-1, and the output end of the switch I is used as the output end II of the AD conversion subsystem.
As a further improvement of the above scheme, the CORDIC algorithm subsystem includes an absolute value two, an absolute value three, and a CORDIC trigonometric function algorithm; one end of the second absolute value and one end of the third absolute value are respectively used as two input ends of the CORDIC algorithm subsystem, the other end of the second absolute value and the other end of the third absolute value are respectively connected with two input ends of the CORDIC trigonometric function algorithm, and the output end of the CORDIC trigonometric function algorithm is used as the output end of the CORDIC algorithm subsystem.
As a further improvement of the scheme, the fine code computing subsystem comprises a switch II and a multiplier III; the two input contacts of the second switch are respectively used as two input ends of the fine code computing subsystem, and the input signal of one input contact is negatively fed back with a constant signal and then is connected into the remaining input contact of the second switch; and the output contact of the second switch is connected with the input end of the third multiplier, and the output end of the third multiplier is used as the output end of the refined code computing subsystem.
As a further improvement of the above scheme, the quadruple frequency subsystem comprises a first comparison amplifier, a second comparison amplifier, a data type converter, a D flip-flop, a first counter, a second counter and an adder; the input end of the first comparison amplifier is used as the input end I of the quadruple frequency subsystem, the output end of the first comparison amplifier is connected with the control end of the first counter on one hand, and the output end I of the D trigger is connected with the data type converter on the other hand; the input end of the second comparison amplifier is used as the input end II of the quadruple frequency subsystem, and the output end of the second comparison amplifier is connected with the control end of the second counter on the one hand and the output end II of the D trigger on the other hand; the in-phase output end of the D trigger is connected with the up-counting digits of the two counters, and the reverse-phase output end of the D trigger is connected with the down-counting digits of the two counters; the output ends of the two counters are used as the output ends of the quadruple frequency subsystem after being operated by the adder.
As a further improvement of the above, the speed calculation subsystem includes: 0-n sample hold, subtracter and divider; the delay is the time length DeltaT of one system clock at a time, the number of times of delay is arbitrary, V_cal_in is the input of the speed calculation subsystem, V_cal_in=Pro 2_out, pro2_out is the output of a multiplier II, and a subtracter samples and holds Pro2_out at m time to obtain V_cal_in by a plurality of system clocks, and records as lambda m At the same time, collect Pro2_out at the current moment, record as lambda m+n Where n is the number of sample-and-hold system clocks, the result of the calculation is output to a divider, the result of the calculation (lambda m+n -λ m ) /(n×Δt) as the speed calculation subsystem output v_cal_out.
As a further improvement of the above scheme, each CRC check subsystem includes a multiplier four, a quantizer two, a shaping digital-to-bit converter, and a CRC check generator; one input end of the multiplier IV is used as an input end of the CRC checking subsystem, the other input end of the multiplier IV receives a constant, and the output end of the multiplier IV is sequentially connected with the quantizer II, the shaping digital-to-analog converter and the CRC checking generator in series, and the output end of the CRC checking generator is used as an output end of the CRC checking subsystem.
As a further improvement of the above scheme, the CORDIC algorithm subsystem uses a coordinate rotation formula to continuously rotate the specific angle of the encoder by an iterative method when the inverse trigonometric function is evaluated, and the angle β=atan (1/2 of each rotation i ) So that the sum of the angles of the cumulative rotation approaches a certain set angle infinitely, 2 i Representing the angle accumulated value after i iterations of the CORDIC algorithm, i representing the number of iterations.
As a further improvement of the above solution, the fine interpolation method of the fine code computation subsystem includes: firstly, obtaining quantized values of Asin alpha and Bco alpha after AD conversion, and judging signs of the quantized values; calculating an (|asinα/bcosα|); judging whether Asinα is equal to or greater than 0; if so, α=atan (|asinα/Bcos α|), otherwise, α=90° -ATAN (|asinα/Bcos α|).
In order to realize higher multiple encoder subdivision frequency multiplication, the invention performs AD sampling on the sine and cosine encoder signals to calculate real-time fine interpolation position values on the basis of quadruple frequency counting. The invention provides a method for calculating the electrical angle value of less than one period by adopting a small-range method, and reduces the angle range of each measurement to 0-90 degrees, and the Matlab/Simulink simulation result shows that the method has better feasibility. Experiments the 2048 line encoder output electrical signal at 100kHz was subdivided 40 times per electrical angle period with a resolution of 15.82 ". In terms of speed measurement, an improved M/T speed measurement method (M/T speed measurement method is a well-known algorithm) is adopted, and an electric angle change value of 90 sampling periods is calculated to obtain a motor speed value, and experiments show that the speed error value is within +/-0.000115 rad/s.
Drawings
Fig. 1 is a schematic diagram of a simulation structure of a high-precision signal processing system of a sine and cosine encoder according to the present invention.
Fig. 2 is a schematic diagram of an AD conversion subsystem of the high-precision signal processing system of the sine and cosine encoder shown in fig. 1.
Fig. 3 is a schematic diagram of a CORDIC algorithm subsystem of the high-precision signal processing system of the sine and cosine encoder of fig. 1.
Fig. 4 is a schematic diagram of a fine code computing subsystem of the high-precision signal processing system of the sine and cosine encoder in fig. 1.
Fig. 5 is a schematic diagram of a quadruple frequency subsystem of the high-precision signal processing system of the sine and cosine encoder of fig. 1.
Fig. 6 is a schematic diagram of a speed calculation subsystem of the high-precision signal processing system of the sine and cosine encoder in fig. 1.
Fig. 7 is a schematic diagram of a CRC check subsystem of the high precision signal processing system of the sin-cos encoder of fig. 1.
Fig. 8 is a waveform diagram of the encoder forward rotation output signal.
Fig. 9 is a functional block diagram of a rotary encoder signal processing system.
Fig. 10 is a signal conditioning and interface circuit.
FIG. 11 is a schematic diagram of an encoder interface unit coarse position count.
Fig. 12 is a state change information diagram of an encoder.
Fig. 13 is a schematic diagram of CORDIC coordinate plane rotation.
Fig. 14 is a flowchart of the fine interpolation calculation procedure.
Fig. 15 is a waveform diagram of the output of the differential signal after passing through the signal conditioning circuit.
Fig. 16 is a schematic diagram of the quantized values of the signals |a|, |b|, and the fine interpolation value α.
Fig. 17 is a graph of simulated measured velocity error for different sampling periods.
Detailed Description
The present invention will be described in further detail with reference to examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The sine and cosine encoder high-precision signal processing system is used for processing Asinα and Bcosα which are 90 degrees different in phase between two paths of output signals of an incremental rotary encoder. Referring to fig. 1, the high-precision signal processing system of the sine and cosine encoder includes a first differential amplifier (Gain 1), a second differential amplifier (Gain 2), a first AD conversion subsystem, a second AD conversion subsystem, a quadruple frequency subsystem, a first multiplier (product 1), a CORDIC algorithm subsystem, a precision code calculation subsystem, a speed calculation subsystem, a second multiplier (product 2), a first CRC check subsystem, and a second CRC check subsystem.
The input end of the differential amplifier I (Gain 1) receives Asin alpha, and the output end of the differential amplifier I (Gain 1) is simultaneously connected with the input end of the AD conversion subsystem and the input end of the quadruple frequency subsystem. The input end of the differential amplifier II (Gain 2) receives Bcosa, and the output end of the differential amplifier II (Gain 2) is simultaneously connected with the input end of the AD conversion subsystem II and the input end of the quadruple frequency subsystem II. Two paths of output signals of the two AD conversion subsystems are connected with two input ends of the CORDIC algorithm subsystem, the other two paths of output signals of the two AD conversion subsystems are connected with two input ends of the multiplier I, and the output end of the multiplier I and the output end of the CORDIC algorithm subsystem are respectively connected with two input ends of the fine code calculation subsystem. The output signal of the quadruple frequency subsystem is overlapped with the output signal of the fine code computing subsystem and then is sent to the first input end of the second multiplier, the second input end of the second multiplier receives pi/4096 signals, pi is the circumference ratio, the value is obtained by a mechanical rotation angle lambda computing formula, and the output end of the second multiplier is simultaneously connected with the first input end of the CRC subsystem and the input end of the speed computing subsystem. The output end of the CRC subsystem is used as the output end I of the high-precision signal processing system of the whole sine and cosine encoder, the output end of the speed calculation subsystem is connected with the input end II of the CRC subsystem, and the output end II of the CRC subsystem is used as the output end II of the high-precision signal processing system of the whole sine and cosine encoder.
Therefore, the input of the differential amplifier I is Asinα, and the output end of the differential amplifier I is connected with the input end of the AD conversion subsystem and the input end of the quadruple frequency subsystem at the same time. The input of the second differential amplifier is Bcosα, and the output end of the second differential amplifier is connected with the input end of the second AD conversion subsystem and the input end of the second quadruple frequency subsystem at the same time. Two paths of output signals of the two AD conversion subsystems are connected with two input ends of the CORDIC algorithm subsystem, the other two paths of output signals of the two AD conversion subsystems are connected with two input ends of a first multiplier which is used as a symbol judgment unit, and the output end of the first multiplier and the output end of the CORDIC algorithm subsystem are respectively connected with two input ends of the fine code calculation subsystem.
Referring to fig. 2, each AD conversion subsystem includes a slicer (original signal), an absolute value of one (Abs 1), a differential amplifier of three (Gain 3), a Quantizer of one (Quantizer 1), and a Switch of one (Switch 1). One end of the limiter is used as an input end of the AD conversion subsystem, the other end of the limiter is sequentially connected in series with an absolute value I, a differential amplifier III and a quantizer I, and an output end of the quantizer I is used as an output end I of the AD conversion subsystem. The input ad_in of the limiter is derived from differential amplifier one and differential amplifier two (gain1_out, gain2_out, and AD 1_in=gain1_out, AD 2_in=gain2_out), and limits the input signal to a prescribed amplitude, on the one hand, the output of the limiter is sequentially subjected to absolute value determination, 2-by-2 16 The digital value is taken as the output ad_out1 of the AD conversion subsystem by the amplification of the differential amplifier three and the quantization of the quantizer one=65535 (here, a 16-bit AD converter is taken as an example); on the other hand, the output of the limiter is given to the switch one, which determines whether the received signal is positive or negative, and if the received signal is greater than zero, the switch one outputs 1 as the output ad_out2=1 of the AD conversion subsystem, and if the received signal is less than zero, the switch one outputs-1 as the output ad_out2= -1 of the AD conversion subsystem.
The other end of the limiter I is also connected with one input contact of the switch I, the other two input contacts of the switch I are respectively connected with two constants which are respectively 1 and-1, and the output end of the switch I is used as the output end II of the AD conversion subsystem. The ad_out1 (AD 1_out1, AD 2_out1) of the AD conversion subsystem is used as input of the CORDIC algorithm subsystem, respectively. The first and second ad_out2 (AD 1_out1 and AD 2_out1) of the AD conversion subsystem are used as the input of the first multiplier, respectively, for symbol discrimination, and for judging which quadrant of the coordinate plane the real-time position of the motor rotor is located. The output of multiplier one is Pro1 out.
Referring to fig. 3, the CORDIC algorithm subsystem includes an absolute value two (Abs 2), an absolute value three (Abs 3), and a CORDIC trigonometric function algorithm (Trigonometric Function). One end of Abs2, abs3 are respectively used as two input ends of the CORDIC algorithm subsystem, the other end of Abs2, abs3 is respectively connected with two input ends of the CORDIC trigonometric function algorithm (Trigonometric Function), and the output end of the CORDIC trigonometric function algorithm (Trigonometric Function) is used as the output end of the CORDIC algorithm subsystem. Cor_in1, cor_in2 are inputs to the CORDIC algorithm subsystem, and cor_in1=ard1_out1, cor_in2=ard2_out1, calculated by the CORDIC trigonometric function algorithm, is used as the output cor_out of the CORDIC algorithm subsystem.
Referring to fig. 4, the fine code computing subsystem, i.e., the fine interpolation computing unit, includes a switch 2 and a multiplier 3. The two input contacts of the switch II are respectively used as the two input ends of the fine code computing subsystem, and the input signal of one input contact is negatively fed back to the signal pi/2 and then is connected to the remaining input contact of the switch II. And an output contact of the second switch is connected with the first input end of the product3, the second input end of the product3 receives a constant of 2/pi, and the output end of the product3 is used as the output end of the fine code computing subsystem. Fine_in1, fine_in2 are inputs to the refinement code calculation subsystem, and fine_in1=cor_out, fine_in2=pro1_out. The second switch determines whether the input fine_intwo is positive or negative, and if fine_intwo is greater than zero, the output of the second switch= (Pi/2-fine_in1), and if fine_intwo is less than zero, the output of the second switch = fine_in1. The output of the second switch is multiplied by a constant 2/Pi to be used as the output fine_out of the Fine code computing subsystem.
Referring to fig. 5, the quad frequency subsystem includes a first comparison amplifier (sign 1), a second comparison amplifier (sign 2), a data type converter (converter), a D flip-flop (D Latch), a first counter (count 1), a second counter (count 2), and an Adder (ADD). The input of sign1 is used as the input I of the quadruple frequency subsystem, and the output of sign1 is connected with the control end of the counter I on the one hand and the output I of the D Latch via a data type converter on the other hand. The input end of sign2 is used as the input end II of the quadruple frequency subsystem, and the output end of sign2 is connected with the control end of the counter II on the one hand and the output end II of the D Latch on the other hand. The in-phase output end of the D Latch is connected with the up-counting digits of the two counters, and the reverse-phase output end of the D Latch is connected with the down-counting digits of the two counters; the output ends of the two counters are used as the output ends of the quadruple frequency subsystem after being operated by the adder.
Muti4_in1, muti4_in2 are inputs to the quad frequency subsystem, and muti4_in1=gain1_out, muti4_in2=gain2_out. The muti4_in1 is transmitted to the D end of the D trigger after data type conversion, the muti4_in2 is transmitted to the CP end of the D trigger, the output Q, Q' of the D trigger is respectively transmitted to the counter I and the counter II, the counter I and the counter II are up-down counters, the rising edge and the falling edge of the input pulse are counted by +1, and the output of the counter I and the output of the counter II are summed by an adder to be used as the output muti4_out of the frequency-quadrupling subsystem.
Referring to fig. 6, the velocity calculation subsystem includes n sample-and-hold (delay) 0～n ) Subtracter, divider (divider). In this embodiment, 10 sample-and-hold delay are used 0～9 . The output end of the speed calculation subsystem is sequentially connected with 10 sample-hold delay units in series 0～9 And then negatively feeding back to the input of the speed calculation subsystem, adopting subtracter operation, then transmitting to the first input end of the speed, and receiving a constant by the second input end of the speed, for example, 0.00001, wherein the output of the speed is used as the output end of the whole speed calculation subsystem.
The delay is the time length DeltaT of one system clock, the number of delays is arbitrary, in the invention, 10 times is taken as an example, namely delay 0～9 V_cal_in is the input of the speed calculation subsystem, and v_cal_in=pro 2_out (output of multiplier two), the subtractor samples and holds Pro2_out at m time instant for 10 system clocks to obtain v_cal_in, recorded as λ m At the same time, collect Pro2_out at the current moment, record as lambda m+n Where n is the number of sample-and-hold system clocks, the result of the calculation is output to a divider, the result of the calculation (lambda m+n -λ m ) As the speed calculation subsystem output v_cal_out,/(n×Δt) =0.00001 in the present invention.
Referring to fig. 7, each CRC check subsystem includes a multiplier four (Product 4), a Quantizer two (Quantizer 2), a shaping digital-to-bit converter (Integer to Bit Converter), and a CRC check generator (General CRC Generator). One input end of the Product4 is used as an input end of the CRC checking subsystem, the other input end of the Product4 receives a constant, and the output end of the Product4 is sequentially connected with a quantizer II, a shaping digital-to-bit converter and a CRC checking generator in series, and the output end of the CRC checking generator is used as an output end of the CRC checking subsystem. Crc_in is an input to the CRC check subsystem, and crc1_in=pro 2_out, crc2_in=v_cal_out. The CRC_in and the check code constant are multiplied by the multiplier 4, the operation result is quantized by the quantizer2, the quantization result is converted into a bit value, and finally, the CRC operation is performed in the CRC check generator, and the result is used as the output CRC_out of the CRC check subsystem. The CRC subsystem is used for calculating CRC of the real-time position value of the precision code, and the CRC subsystem is used for calculating CRC of the real-time speed value.
Example 1
1. Incremental rotary encoder signal processing principle
Under ideal conditions, the incremental rotary encoder outputs A, B sine and cosine signals with 90 degrees phase difference. When the encoder rotates in the positive direction, the phase of the output signal B lags the phase of the signal A by 90 degrees; conversely, when the encoder rotates in the opposite direction, the A output signal phase lags the B signal by 90 degrees. The encoder outputs a signal waveform when rotating in the forward direction, as shown in fig. 8, and fig. 8 is a waveform diagram of the encoder output signal when rotating in the forward direction.
The encoder initial signal needs to be converted to obtain information such as the angle position of the motor. In terms of signal processing, the encoder output signal is split into two paths, as shown in fig. 9, fig. 9 is a schematic block diagram of a rotary encoder signal processing system. One path of signals is converted into TTL pulse signals through a differential amplifier, a proportional amplifier and a filter treatment, the TTL signals are connected to a EIU (Encoder Interface Unit) encoder interface unit of an ADSP-CM408 mixed signal control processor, and 4 times of frequency multiplication is carried out to obtain encoder coarse code information; the other path of signals Asin alpha and Bcon alpha are transmitted to an analog multiplexer of the ADSP-CM408 through a high-speed operational amplifier and an RC filter circuit, are processed through a sample-hold amplifier and then are transmitted to an AD conversion unit to obtain digital signals with sixteen-bit sampling precision, and the obtained digital signals are subjected to fine code error correction. Then adopting an electronic subdivision algorithm to directly calculate an inverse tangent value to obtain an electric angle alpha of the encoder, and obtaining an encoder precise code signal through the electric angle alpha. And finally, adding the coarse code information and the fine interpolation information together to obtain accurate motor angular position, angular speed and other information.
The signal conditioning circuit adopts an ADA4899 high-speed operational amplifier of ADI company to amplify and reshape sine and cosine signals in two stages to obtain conditioned sine and cosine analog signals; and then the TTL level signal with the high level of 3.3V and the low level of 0V is output through the comparison amplifier, the signal conditioning circuit is shown in fig. 10, and fig. 10 is a signal conditioning and interface circuit.
EIU coarse position count
The encoder interface unit adopts a quadruple frequency counting mode and judges the rotation direction of the encoder. For the whole period sine and cosine signals output by the encoder, the whole period sine and cosine signals are converted into TTL pulse signals with equal periods through a comparator, the TTL pulse signals are input into an EIU unit for pulse counting, as shown in FIG. 11, and FIG. 11 is a schematic diagram of coarse position counting of an interface unit of the encoder. Two paths of pulse signals Ti1 and Ti2 (figure 12) are input to the ports of the CND0_UD and the CND0_DG (figure 10) of the EIU unit, and two-bit changed Gray code information is formed according to the difference of the high level and the low level of the pulse signals. Before coarse position counting, the pulse signal needs to be subjected to double-D trigger filtering processing.
When the encoder rotates forward, the change rule of the two-bit Gray code signal is 10, 11, 01, 00 and 10 circularly; when the encoder is reversed, the two-bit Gray code signal changes circularly with the rules of 01, 11, 10, 00 and 01. The up-or down-count corresponds to one up-or down-count for each state change. Thus, one signal period is counted four times, i.e., four times frequency. When a disturbance or fault occurs, such as jitter, other states may occur, and the encoder does not count at this time, and its state change information is shown in fig. 12.
3. High resolution subdivision location information
When the electrical angle is less than one period, in order to feed back real-time information more accurately, an electronic subdivision algorithm is required to be adopted for frequency multiplication so as to obtain the angular position and the angular speed of the motor with higher accuracy. ADSP-CM408MCU carries 240MHz ARM Cortex-M4 kernel, has floating point operation function, improves operation speed, can also carry out binary channels AD sampling simultaneously to two paths of sine and cosine signals of encoder output, and sampling time is 150ns, conversion time 380ns.
3.1CORDIC algorithm inverse tangent
The electronic subdivision algorithm mainly uses the arctangent direct evaluation method. The calculation formula of the electrical angle alpha is as follows:
Figure BDA0001037316530000113
in order to implement the inverse trigonometric function evaluation faster, J.Volder proposed a fast algorithm in 1959, called the CORDIC (Cordinate Rotation Digital Computer) algorithm. Under the condition of ensuring the operation precision, the algorithm greatly reduces the operation time. CORDIC algorithm as shown in fig. 13, fig. 13 is a schematic diagram of CORDIC plane coordinate rotation. The X, Y axis coordinate is rotated by a certain degree, and through N times of iterative operation, when the ordinate is rotated to 0, the degree of rotation is beta. Let (x, y) be the original coordinate point, and the coordinates after rotating clockwise by β with the origin as the center are denoted as (x ', y').
Then there is the following counter-clockwise coordinate rotation formula:
Figure BDA0001037316530000111
however, the above formula has four multiplication operations during operation, the operation amount is larger, and the algorithm is further improved. At this time, a multiplication factor is extractedThe sub cos alpha is found from the matrix operation formula, the distance from the new coordinate point after each rotation to the original point is prolonged, and the growth factor is 1/cos alpha. However, the α value is not affected. Thus, the operation amount becomes two multiplication operations. The following coordinate rotation formula is then obtained:
Figure BDA0001037316530000112
by iterative method, the rotation is carried out continuously by a specific angle, and the angle beta=atan (1/2 of the rotation i ) So that the sum of the angles of cumulative rotation approaches a certain set angle infinitely. This is a continuous correction process, in order to make the y value approach zero infinitely, when a certain rotation is performed by a certain angle to obtain that the y value is negative, the next rotation needs to be corrected to be the opposite rotation. Then, the iterative formula of the CORDIC algorithm is:
Figure BDA0001037316530000121
the angle accumulation formula is: z i+1 ＝z i +d i α i ；d i = ±1, wherein Z i Representing an angle accumulated value after i times of iteration of the CORDIC algorithm; symbol d i Is a decision factor, determines the rotation direction, and the positive and negative of the rotation direction depend on y obtained after iteration i It is worth positive and negative. The result of the angle accumulation formula is the value of the electric angle alpha.
3.2 real-time Fine interpolation position values
Because the requirement cannot be met by simply relying on quadrupling frequency, higher-precision subdivision is also needed, and the real-time fine interpolation position value can be obtained by the sine and cosine signal subdivision technology.
When 0-360 degrees are selected for electronic subdivision, if the angle value is larger when approximation is performed by adopting the CORDIC algorithm, the approximation frequency is larger, the operation amount is indirectly increased, the operation time is increased, and the real-time performance of the system is not facilitated. Therefore, the electrical angle is calculated by adopting a small-range method of 0-90 degrees, and because four-time frequency counting is adopted in coarse code counting, the angle of less than one quarter period can be calculated each time when the value of the electrical angle is calculated, and the measuring range is reduced to 0-90 degrees, so that the iteration times are reduced when the inverse tangent value is calculated by the CORDIC algorithm, and the operation time is further reduced. Moreover, the method can achieve subdivision accuracy of more than tens times, and the upper limit of the method is limited by AD sampling time, conversion time and operation speed of the MCU in theory. The arctangent value is obtained by a CORDIC algorithm, and then the real-time fine interpolation position value is obtained by a formula.
Figure BDA0001037316530000122
The software algorithm implementation flow chart is shown in fig. 14, fig. 14 is a flow chart of a fine interpolation calculation program, and the fine interpolation method of the fine code calculation subsystem comprises the following steps: firstly, obtaining quantized values of Asin alpha and Bco alpha after AD conversion, and judging signs of the quantized values; calculating an (|asinα/bcosα|); judging whether Asinα is equal to or greater than 0; if so, α=atan (|asinα/Bcos α|), otherwise, α=90° -ATAN (|asinα/Bcos α|).
3.3 Motor position information
The high-precision motor rotation angle value consists of two parts, and the obtained coarse code signal and the fine code signal, namely the real-time fine interpolation position value, are combined to obtain the mechanical rotation angle lambda of the encoder. The calculation formula of the mechanical rotation angle lambda is as follows:
Figure BDA0001037316530000131
wherein N represents the number of signal cycles generated by one rotation of the motor rotor; z represents the number of signal cycles generated by the actual rotation of the motor; lambda (lambda) 0 Indicating the initial position of the motor rotor.
When the rotating speed of the motor is measured, the M/T speed measuring method is improved, the angle change value of 10 sampling periods is measured by adopting the change based on the sampling angle, so that the problems of less pulse number in unit time of the M method and short time between two pulses of the T method are solved, the defect of the real-time performance of the M/T method is overcome, and the measuring precision is higher. Transmitting the mechanical angle lambda to ADSThe P-CM408 controls the processor to perform an arithmetic process to obtain data information such as the rotational speed, the position, and the steering of the motor. The motor rotation speed algorithm is as follows:
Figure BDA0001037316530000132
wherein lambda is m+n M+n mechanical rotation angles; lambda (lambda) m Is the mth mechanical rotation angle; Δt is the sampling time.
4. Experimental simulation analysis
The signal conditioning circuit is first simulated in Multisim circuit simulation software. Fig. 15 shows an output waveform of the differential signal after passing through the signal conditioning circuit.
After the original signal is conditioned, a more ideal signal waveform is obtained. Taking the conditioned signal as a signal source of Simulink simulation, obtaining fine interpolation information through 16-bit AD conversion and CORDIC algorithm, obtaining coarse code information after source signals are counted by an amplifier, a comparator and four times of frequency, obtaining complete position value information by adding the coarse code information and the coarse code information, and outputting the complete position value information to CRC1_out through 32-bit CRC; after the 32-bit CRC check, the speed value is output to CRC2_out. The Simulink simulation model is shown in fig. 1. During simulation, the simulation step length is set to be 0.1s, the input signal frequency is 100kHz, and the sampling time is 0.25us. As can be seen from simulation analysis, as shown in FIG. 16, FIG. 16 is a schematic diagram of the quantized values of the signals of |A|, |B|, and the fine interpolation value α. After the A, B signals, namely Asinα and Bcosα, are sampled and quantized by an AD converter, absolute value operation is taken to obtain a quantized value, after CORDIC operation, the arctangent value α is obtained, and the value is reproduced in a period ranging from 0 degrees to 90 degrees, so that the algorithm of the formula can better realize subdivision frequency multiplication of the sine and cosine signals of the encoder.
In the experiment, a Hildenhe 2048-line sine and cosine encoder is adopted, the rotating speed is 3000rpm, and the frequency of the sine and cosine signal output by the encoder is 102.4kHz. The theoretical mechanical angle is 30.679616rad within 0.1s, the actual rotor angle value is 30.678849rad, and the error is 0.000767rad; and the theoretical speed is 306.796158rad/s. Fig. 17 is a graph of simulated measured speed error for different sampling periods, and the difference between the measured speed and the theoretical value for different sampling periods is 10, 30, 50, 70, and 90 sampling periods, respectively, and the measured speed error data is obtained for one speed. When 10 sampling periods are taken as the speed measuring period, the error is larger, and as the sampling period increases, the error is reduced, and the error value is shown in table 1.
Table 1 measuring speed error values for different sampling periods
Figure BDA0001037316530000141
5. Conclusion(s)
In order to realize higher multiple encoder subdivision frequency multiplication, AD sampling is carried out on the sine and cosine encoder signals on the basis of quadruple frequency counting to obtain real-time fine interpolation position values. The method is provided for calculating the electrical angle value of less than one period by adopting a small-range method, and the angle measuring range is reduced to 0-90 degrees each time, and the Matlab/Simulink simulation result shows that the method has better feasibility. Experiments the 2048 line encoder output electrical signal at 100kHz was subdivided 40 times per electrical angle period with a resolution of 15.82 ". In terms of speed measurement, an improved M/T speed measurement method is adopted, and an electrical angle change value of 90 sampling periods is calculated to obtain a motor speed value, and experiments show that the speed error value is within +/-0.000115 rad/s.
For other information, refer to patent documents CN201510465550.5, CN201520574867.8, CN201510467898.8, CN201610029229.7, CN201610029321.3, CN201510465547.3, CN201520570360.5.
Example 2
Assuming actual application:
1. the resolution of the encoder is 2048 lines;
2. the motor speed is 3000rpm;
3. the feed rate of the screw rod is 5mm, namely 5mm/r, when the motor rotates for one circle;
4. the resolution of the feeding amount reaches 0.0001mm, and the corresponding mechanical angle is 360/(5/0.0001) =0.0072° =25.92'.
Let the encoder subdivision multiple be N, then:
Figure BDA0001037316530000151
obtaining N>24.4, i.e. minimum 25 frequency doubling. And (3) injection: since the frequency of the encoder interface unit is multiplied, 7 times of the frequency is needed to achieve the ideal resolution, and the overall subdivision multiple reaches 28 times.
When the rotation speed is 3000rpm, as shown in fig. 8, the frequency of the sine and cosine signals output by the encoder is:
Figure BDA0001037316530000155
the fine interpolation calculation formula:
Figure BDA0001037316530000152
mechanical rotation angle calculation formula:
Figure BDA0001037316530000153
the speed calculation formula:
Figure BDA0001037316530000154
/>
the foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims (8)

1. A high-precision signal processing system of a sine and cosine encoder is used for processing Asinα and Bcosα which are 90 degrees different in phase between two paths of output signals of an incremental rotary encoder; the method is characterized in that: the sine and cosine encoder high-precision signal processing system comprises a differential amplifier I, a differential amplifier II, an AD conversion subsystem I, an AD conversion subsystem II, a quadruple frequency subsystem, a multiplier I, a CORDIC algorithm subsystem, a precision code computing subsystem, a speed computing subsystem, a multiplier II, a CRC checking subsystem I and a CRC checking subsystem II; the input end of the differential amplifier I receives Asinα, and the output end of the differential amplifier I is simultaneously connected with the input end of the AD conversion subsystem and the input end of the quadruple frequency subsystem; the input end of the second differential amplifier receives Bcosa, and the output end of the second differential amplifier is simultaneously connected with the input end of the second AD conversion subsystem and the input end of the second quadruple frequency subsystem; two paths of output signals of the two AD conversion subsystems are connected with two input ends of the CORDIC algorithm subsystem, the other two paths of output signals of the two AD conversion subsystems are connected with two input ends of the first multiplier, and the output end of the first multiplier and the output end of the CORDIC algorithm subsystem are respectively connected with two input ends of the fine code calculation subsystem; the output signal of the quadruple frequency subsystem is overlapped with the output signal of the fine code computing subsystem and then is sent to the first input end of the second multiplier, and the output end of the second multiplier is simultaneously connected with the first input end of the CRC subsystem and the input end of the speed computing subsystem; the output end of the CRC subsystem is used as the output end I of the high-precision signal processing system of the whole sine and cosine encoder, the output end of the speed calculation subsystem is connected with the input end II of the CRC subsystem, and the output end II of the CRC subsystem is used as the output end II of the high-precision signal processing system of the whole sine and cosine encoder;
the fine code computing subsystem comprises a switch II and a multiplier III; the two input contacts of the second switch are respectively used as two input ends of the fine code computing subsystem, and the input signal of one input contact is negatively fed back with a constant signal and then is connected into the remaining input contact of the second switch; and the output contact of the second switch is connected with the input end of the third multiplier, and the output end of the third multiplier is used as the output end of the refined code computing subsystem.
2. The sine and cosine encoder high precision signal processing system as claimed in claim 1, wherein: each AD conversion subsystem comprises a limiter, an absolute value first, a differential amplifier third, a quantizer first and a switch first; one end of the limiter is used as an input end of the AD conversion subsystem, the other end of the limiter is sequentially connected in series with an absolute value I, a differential amplifier III and a quantizer I, the output end of the quantizer I is used as an output end I of the AD conversion subsystem, and the other end of the limiter is also connected with an input contact of the switch I; the other two input contacts of the switch I respectively receive two constants which are respectively 1 and-1, and the output end of the switch I is used as the output end II of the AD conversion subsystem.
3. The sine and cosine encoder high precision signal processing system as claimed in claim 1, wherein: the CORDIC algorithm subsystem comprises an absolute value two, an absolute value three and a CORDIC trigonometric function algorithm; one end of the second absolute value and one end of the third absolute value are respectively used as two input ends of the CORDIC algorithm subsystem, the other end of the second absolute value and the other end of the third absolute value are respectively connected with two input ends of the CORDIC trigonometric function algorithm, and the output end of the CORDIC trigonometric function algorithm is used as the output end of the CORDIC algorithm subsystem.
4. The sine and cosine encoder high precision signal processing system as claimed in claim 1, wherein: the quadruple frequency subsystem comprises a first comparison amplifier, a second comparison amplifier, a data type converter, a D trigger, a first counter, a second counter and an adder; the input end of the first comparison amplifier is used as the input end I of the quadruple frequency subsystem, the output end of the first comparison amplifier is connected with the control end of the first counter on one hand, and the output end I of the D trigger is connected with the data type converter on the other hand; the input end of the second comparison amplifier is used as the input end II of the quadruple frequency subsystem, and the output end of the second comparison amplifier is connected with the control end of the second counter on the one hand and the output end II of the D trigger on the other hand; the in-phase output end of the D trigger is connected with the up-counting digits of the two counters, and the reverse-phase output end of the D trigger is connected with the down-counting digits of the two counters; the output ends of the two counters are used as the output ends of the quadruple frequency subsystem after being operated by the adder.
5. The sine and cosine encoder high precision signal processing system as claimed in claim 1, wherein: speed calculation sub-unitThe system comprises: 0-n sample hold, subtracter and divider; the delay is the time length DeltaT of one system clock at a time, the number of times of delay is arbitrary, V_cal_in is the input of the speed calculation subsystem, V_cal_in=Pro 2_out, pro2_out is the output of a multiplier II, and a subtracter samples and holds Pro2_out at m time to obtain V_cal_in by a plurality of system clocks, and records as lambda m At the same time, collect Pro2_out at the current moment, record as lambda m+n Where n is the number of sample-and-hold system clocks, the result of the calculation is output to a divider, the result of the calculation (lambda m+n -λ m ) /(n×Δt) as the speed calculation subsystem output v_cal_out.
6. The sine and cosine encoder high precision signal processing system as claimed in claim 1, wherein: each CRC subsystem comprises a multiplier IV, a quantizer II, a shaping digital-to-bit converter and a CRC generator; one input end of the multiplier IV is used as an input end of the CRC checking subsystem, the other input end of the multiplier IV receives a constant, and the output end of the multiplier IV is sequentially connected with the quantizer II, the shaping digital-to-analog converter and the CRC checking generator in series, and the output end of the CRC checking generator is used as an output end of the CRC checking subsystem.
7. The sine and cosine encoder high precision signal processing system as claimed in claim 1, wherein: when the CORDIC algorithm subsystem evaluates the inverse trigonometric function, a coordinate rotation formula is adopted, the specific angle of the encoder is continuously rotated by an iterative method, and the angle beta=ATAN (1/2) of each rotation i ) So that the sum of the angles of the cumulative rotation approaches a certain set angle infinitely, 2 i Representing the angle accumulated value after i iterations of the CORDIC algorithm, i representing the number of iterations.
8. The sine and cosine encoder high precision signal processing system as claimed in claim 1, wherein: the fine interpolation method of the fine code computation subsystem comprises the following steps: firstly, obtaining quantized values of Asin alpha and Bco alpha after AD conversion, and judging signs of the quantized values; calculating an (|asinα/bcosα|); judging whether Asinα is equal to or greater than 0; if so, α=atan (|asinα/Bcos α|), otherwise, α=90° -ATAN (|asinα/Bcos α|).
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