CN105978570A - High-precision signal processing system of sine and cosine encoder - Google Patents
High-precision signal processing system of sine and cosine encoder Download PDFInfo
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- CN105978570A CN105978570A CN201610517319.0A CN201610517319A CN105978570A CN 105978570 A CN105978570 A CN 105978570A CN 201610517319 A CN201610517319 A CN 201610517319A CN 105978570 A CN105978570 A CN 105978570A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
- G01D21/00—Measuring or testing not otherwise provided for
- G01D21/02—Measuring two or more variables by means not covered by a single other subclass
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
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Abstract
The invention discloses a high-precision signal processing system of a sine and cosine encoder. The system comprises two gain circuits, two AD conversion subsystems, a frequency quadrupling subsystem, a first product, a CORDIC algorithm subsystem, a precise code calculation subsystem, a speed calculation subsystem, a second product and two CRC checking subsystems. The two gain circuits receive Asin alpha ad Bcos alpha of which phase difference is 90 degrees. The output ends of the two gain circuits are connected with the two AD conversion subsystems and the frequency quadrupling subsystem. The first product and the CORDIC algorithm subsystem are connected with the precise code calculation subsystem. The output signal of the frequency quadrupling subsystem and the output signal of the precise code calculation subsystem are overlapped and then are connected to a first CRC checking subsystem and the speed calculation subsystem through the second product. The speed calculation subsystem is connected with a second CRC checking subsystem. The output ends of the two CRC checking subsystems are taken as the two output ends of the whole system.
Description
Technical field
The present invention relates to a kind of signal processing system, particularly relate to a kind of sine and cosine encoder high-precision signal and process system
System.
Background technology
Increment type sine and cosine encoder is a kind of sophisticated sensor measuring angular displacement and angular velocity.Sine and cosine encoder with
The advantages such as its resolution height, precision height, noncontacting measurement, use are reliable, are widely used in the section such as accurate measurement and real-time control
Skill field.
Along with the required precision of digital control system and modern industrial control system is more and more higher, need higher resolution and essence
The encoder of degree.But the lifting relying solely on hardware performance also cannot meet market to signals such as the position of motor and speed
High-precision requirement, therefore, it is also desirable to carry out electronics segmentation, to promote encoder to encoder output cosine and sine signal further
The precision of signal.Conventional electronics divided method has arc tangent directly to ask for method, cordic algorithm, look-up table, Maclaurin
Series Method, Closed loop track method, signal injection method etc..Output signal is the encoder of TTL square wave, and signal can only carry out 4 frequencys multiplication, nothing
Method meets the requirement that primary signal carries out more segmentation difference.
Summary of the invention
It is an object of the invention to provide a kind of sine and cosine encoder high-precision signal processing system, which solve original
Signal carries out the technical barrier of the segmentation of any multiple, can arbitrarily segment in theory, such that it is able to former by calculating acquisition ratio
Beginning signal resolution higher rotor real-time angular value (rad) and rotor real-time speed value (rad/s).
The present invention is achieved through the following technical solutions: a kind of sine and cosine encoder high-precision signal processing system；It is used for
Process the Asin α and Bcos α of the two-way phase 90 degree of incremental rotary encoder output；Described sine and cosine encoder is high-precision
Degree signal processing system includes the unification of difference amplifier one, difference amplifier two, AD conversion subsystem, AD conversion subsystem two, four
Frequency multiplication subsystem, multiplier one, cordic algorithm subsystem, essence yardage Operator Systems, speed calculation subsystem, multiplier two,
CRC check subsystem is unified, CRC check subsystem two；Wherein, the input of described difference amplifier one receives Asin α, described difference
The outfan dividing amplifier one is simultaneously connected with the unified input of described AD conversion subsystem and the input of described quadruple subsystem
End one；The input of described difference amplifier two receives Bcos α, and the outfan of described difference amplifier two is simultaneously connected with described AD
The input of conversion subsystem two and the input two of described quadruple subsystem；The two-way output letter of two AD conversion subsystems
Number connecting two inputs of described cordic algorithm subsystem, the another two-way output signal of two AD conversion subsystems connects institute
State two inputs of multiplier one, the outfan of described multiplier one, the outfan difference of described cordic algorithm subsystem
Connect two inputs of described essence yardage Operator Systems；The output signal of described quadruple subsystem and described essence yardage operator
The output signal of system delivers to the input one of described multiplier two after being overlapped, the outfan of described multiplier two connects simultaneously
Connect the unified input of described CRC check subsystem, the input of described speed calculation subsystem；Described CRC check subsystem is unified
Outfan as the outfan one of whole sine and cosine encoder high-precision signal processing system, described speed calculation subsystem
Outfan connects the input of described CRC check subsystem two, and the outfan of described CRC check subsystem two is as whole just remaining
The outfan two of string encoder high-precision signal processing system.
As the further improvement of such scheme, one end of described amplitude limiter is as the input of AD conversion subsystem, institute
State the other end of amplitude limiter to be sequentially connected in series and ask absolute value one, difference amplifier three, quantizer one, the outfan of described quantizer one
As the outfan one of AD conversion subsystem, the other end of described amplitude limiter is also connected with an input contact of described switch one；
Remaining two input contacts of described switch one receive two constants being respectively 1 and-1, the outfan of described switch one respectively
Outfan two as AD conversion subsystem.
As the further improvement of such scheme, described cordic algorithm subsystem includes seeking absolute value two, seeking absolute value
Three, CORDIC trigonometric function algorithm；Seek absolute value two, ask one end of absolute value three respectively as described cordic algorithm subsystem
Two inputs, seek absolute value two, to ask the other end of absolute value three to connect two of CORDIC trigonometric function algorithm respectively defeated
Entering end, the outfan of CORDIC trigonometric function algorithm is as the outfan of described cordic algorithm subsystem.
As the further improvement of such scheme, described essence yardage Operator Systems includes switching two, multiplier three；Described open
Two that close two input the contacts two inputs respectively as described essence yardage Operator Systems, and one of them inputs contact
The surplus next input contact of described switch two is accessed again after one constant signal of input signal negative feedback；Described switch two defeated
Going out contact and connect the input of multiplier three, the outfan of multiplier three is as the outfan of described essence yardage Operator Systems.
As the further improvement of such scheme, described quadruple subsystem includes comparison amplifier one, comparison amplifier
Two, data type converter, d type flip flop, enumerator one, enumerator two, adder；The input of comparison amplifier one is as institute
State the input one of quadruple subsystem, the control end of the outfan of comparison amplifier one on the one hand linkage counter one, another
Aspect connects the outfan one of d type flip flop via data type converter；The input of comparison amplifier two is as described four times
Frequently the input two of subsystem, the control end of the outfan of comparison amplifier two on the one hand linkage counter two, on the other hand connect
Connect the outfan two of d type flip flop；The in-phase output end of d type flip flop connects the increasing counting number position of two enumerators, d type flip flop anti-
Phase output terminal connects the subtrahend meter digital of two enumerators；The outfan of two enumerators after adder computing as described four
The outfan of frequency multiplication subsystem.
As the further improvement of such scheme, speed calculation subsystem includes: 0～n sample holding, subtractor, remove
Musical instruments used in a Buddhist or Taoist mass；Delay is once the time span Δ T of a system clock, and the number of times of delay is arbitrary, and V_cal_in is velometer
The input of Operator Systems, and V_cal_in=Pro2_out, Pro2_out is the output of multiplier two, and subtractor is in the m moment
Pro2_out sampling keeps multiple system clocks to obtain V_cal_in, is recorded as λm, gather the Pro2_out of current time simultaneously,
It is recorded as λm+n, n therein is the number of the system clock that sampling keeps, and result of calculation exports to divider, result of calculation
(λm+n-λm)/(n × Δ T) export V_cal_out as speed calculation subsystem.
As the further improvement of such scheme, each CRC check subsystem includes multiplier four, quantizer two, shaping
Number indexing transducer, CRC check generator；One input of multiplier four is as the input of CRC check subsystem, multiplication
Another input admiralty constant of device four, the outfan of multiplier four be sequentially connected in series quantizer two, shaping number indexing transducer,
CRC check generator, the outfan of CRC check generator is as the outfan of CRC check subsystem.
As the further improvement of such scheme, cordic algorithm subsystem, when antitrigonometric function evaluation, uses coordinate
Rotation formula, by the method for iteration, the special angle of continuous rotary encoder, the angle beta=ATAN (1/2 rotated every timei),
Make the angle of the angle a certain setting of sum infinite approach of accumulative rotation, 2iRepresent the angle after cordic algorithm iteration i time
Degree accumulated value, i represents iterations.
As the further improvement of such scheme, the Fine interpolation method of described essence yardage Operator Systems includes: first obtain AD
The quantized value of the Asin α after conversion and Bcos α, and judge its symbol；Calculate ATAN (| Asin α/Bcos α |)；Judge Asin α *
Whether Bcos α is more than or equal to 0；It is then α=ATAN (| Asin α/Bcos α |), otherwise, α=90 °-ATAN (| Asin α/Bcos α
|)。
The present invention segments frequency multiplication for the encoder realizing higher multiple, on the basis of quadruple counting, aligns remaining
String code device signal carries out Fine interpolation positional value when AD samples realistic.The present invention proposes the little area method of employing and calculates less than one
The electric angle angle value in cycle, is contracted to 0～90 ° by measuring angular range every time, and Matlab/Simulink simulation result shows, this
Method has preferable feasibility.Test the 2048 line encoder output signals of telecommunication to 100kHz and carry out each electrical angle cycle
40 times of segmentations, resolution has reached 15.82 ".At the aspect that tests the speed, (M/T velocimetry is a kind of to have employed the M/T velocimetry of improvement
Known algorithm), calculate the electrical angle changing value in 90 sampling periods, in the hope of motor speed value, experiment display, velocity error
It is worth within ± 0.000115rad/s.
Accompanying drawing explanation
Fig. 1 is the simulation architecture schematic diagram of the sine and cosine encoder high-precision signal processing system of the present invention.
Fig. 2 is the structural representation of the AD conversion subsystem of sine and cosine encoder high-precision signal processing system in Fig. 1.
Fig. 3 is the structural representation of the cordic algorithm subsystem of sine and cosine encoder high-precision signal processing system in Fig. 1
Figure.
Fig. 4 is the structural representation of the smart yardage Operator Systems of sine and cosine encoder high-precision signal processing system in Fig. 1.
Fig. 5 is the structural representation of the quadruple subsystem of sine and cosine encoder high-precision signal processing system in Fig. 1.
Fig. 6 is the structural representation of the speed calculation subsystem of sine and cosine encoder high-precision signal processing system in Fig. 1.
Fig. 7 is the structural representation of the CRC check subsystem of sine and cosine encoder high-precision signal processing system in Fig. 1.
Fig. 8 is that encoder rotates forward signal output waveform figure.
Fig. 9 is rotary encoder through signals processing system theory diagram.
Figure 10 is signal condition and interface circuit.
Figure 11 is that encoder interfaces unit coarse position counts schematic diagram.
Figure 12 is the state change information figure of encoder.
Figure 13 is that CORDIC coordinate plane rotates schematic diagram.
Figure 14 is Fine interpolation calculation procedure flow chart.
Figure 15 is differential signal output waveform figure after signal conditioning circuit.
Figure 16 is | A |, the schematic diagram of | B | signal quantization value and Fine interpolation value α.
When Figure 17 is Different sampling period number, emulation records speed-error curve figure.
Detailed description of the invention
Below in conjunction with embodiment, the present invention is further elaborated.Should be appreciated that concrete reality described herein
Execute example only in order to explain the present invention, do not limit the present invention.
The sine and cosine encoder high-precision signal processing system of the present invention is for processing incremental rotary encoder output
The Asin α and Bcos α of two-way phase 90 degree.Refer to Fig. 1, described sine and cosine encoder high-precision signal processing system bag
Include difference amplifier one (Gain1), difference amplifier two (Gain2), the unification of AD conversion subsystem, AD conversion subsystem two, four times
Frequently subsystem, multiplier one (product 1), cordic algorithm subsystem, essence yardage Operator Systems, speed calculation subsystem,
Multiplier two (product 2), CRC check subsystem are unified, CRC check subsystem two.
The input of described difference amplifier one (Gain1) receives Asin α, described difference amplifier one (Gain1) defeated
Go out end and be simultaneously connected with the unified input of described AD conversion subsystem and the input one of described quadruple subsystem.Described difference is put
The input of big device two (Gain2) receives Bcos α, and the outfan of described difference amplifier two (Gain2) is simultaneously connected with described AD
The input of conversion subsystem two and the input two of described quadruple subsystem.The two-way output letter of two AD conversion subsystems
Number connecting two inputs of described cordic algorithm subsystem, the another two-way output signal of two AD conversion subsystems connects institute
Stating two inputs of multiplier one, the outfan of described multiplier one, the outfan of cordic algorithm subsystem connect respectively
Two inputs of described essence yardage Operator Systems.The output signal of described quadruple subsystem and described essence yardage Operator Systems
Output signal be overlapped after deliver to the input one of described multiplier two, the input two of described multiplier two receives pi/
4096 signals, pi is pi, and this numerical value is obtained by machinery anglec of rotation λ computing formula, and the outfan of described multiplier two is same
Time connect the unified input of described CRC check subsystem, the input of described speed calculation subsystem.Described CRC check subsystem
Unified outfan is as the outfan one of whole sine and cosine encoder high-precision signal processing system, described speed calculation subsystem
The outfan of system connects the input of described CRC check subsystem two, and the outfan of described CRC check subsystem two is as whole
The outfan two of sine and cosine encoder high-precision signal processing system.
Therefore, the input of described difference amplifier one is Asin α, and the outfan of described difference amplifier one is simultaneously connected with described
Input that AD conversion subsystem is unified and the input one of described quadruple subsystem.The input of described difference amplifier two is
Bcos α, the outfan of described difference amplifier two is simultaneously connected with the input of described AD conversion subsystem two and described quadruple
The input two of subsystem.The two-way output signal of two AD conversion subsystems connects two of described cordic algorithm subsystem
Input, the another two-way output signal of two AD conversion subsystems connects two inputs of multiplier one, multiplier one conduct
Symbol decision unit, the outfan of described multiplier one, the outfan of described cordic algorithm subsystem connect described essence respectively
Two inputs of yardage Operator Systems.
Referring to Fig. 2, each AD conversion subsystem includes amplitude limiter (original signal), seeks absolute value one
(Abs1), difference amplifier three (Gain3), quantizer one (Quantizer1), switch one (Switch1).Described amplitude limiter
One end is as the input of AD conversion subsystem, and the other end of described amplitude limiter is sequentially connected in series asks absolute value one, difference amplifier
Three, quantizer one, the outfan of described quantizer one is as the outfan one of AD conversion subsystem.The input AD_in of amplitude limiter
From difference amplifier one and difference amplifier two (gain1_out, gain2_out, and AD1_in=gain1_out, AD2_in
=gain2_out), and input signal is limited in the amplitude of regulation, on the one hand, the output of amplitude limiter sequentially passes through asks absolute
It is worth, by 216=65535 (being here as a example by 16 bit A/D converters) amplification of difference amplifier three, the quantization of quantizer one, for
Digital value is as the output AD_out1 of AD conversion subsystem；On the other hand, the output of amplitude limiter is to switch one, switch one judgement
The signal received is just or to bear, if the signal received is more than zero, then switch one output 1, as AD conversion subsystem
Output AD_out2=1, if the signal received is less than zero, then switch one output-1, as the output of AD conversion subsystem
AD_out2=-1.
The other end of amplitude limiter one is also connected with switching an input contact of, and remaining two input contacts of switch one are divided
Not Lian Jie two be respectively 1 and-1 constants, the outfan of described switch one is as the outfan two of AD conversion subsystem.AD turns
Change that subsystem is unified, the AD_out1 (AD1_out1, AD2_out1) of two is respectively as the input of cordic algorithm subsystem.AD turns
Change that subsystem is unified, the AD_out2 (AD1_out1, AD2_out1) of two respectively as the input of multiplier one, differentiate for symbol,
Judge rotor real time position is in which quadrant of coordinate plane.Multiplier one is output as Pro1_out.
Refer to Fig. 3, described cordic algorithm subsystem include asking absolute value two (Abs2), ask absolute value three (Abs3),
CORDIC trigonometric function algorithm (Trigonometric Function).One end of Abs2, Abs3 is respectively as described CORDIC
Two inputs of algorithm subsystem, the other end of Abs2, Abs3 connects CORDIC trigonometric function algorithm respectively
Two inputs of (Trigonometric Function), CORDIC trigonometric function algorithm (Trigonometric
Function) outfan is as the outfan of described cordic algorithm subsystem.COR_in1, COR_in2 are cordic algorithms
The input of subsystem, and COR_in1=AD1_out1, COR_in2=AD2_out1, calculate through CORDIC trigonometric function algorithm
After, as the output COR_out of cordic algorithm subsystem.
Referring to Fig. 4, described essence yardage Operator Systems i.e. Fine interpolation computing unit includes switching two (switch 2), multiplication
Device three (product3).Two input contacts of described switch two are respectively as two inputs of described essence yardage Operator Systems
Hold, and input signal negative feedback of one of them input contact accesses the surplus next one of described switch two after the signal of pi/2 again
Input contact.The output contact of described switch two connects the input one of product3, and the input two of product3 receives 2/
The constant of pi, the outfan of product3 is as the outfan of described essence yardage Operator Systems.Fine_in1, Fine_in2 are essences
The input of yardage Operator Systems, and Fine_in1=COR_out, Fine_in2=Pro1_out.Switch two judgement input
Fine_in bis-is just or to bear, if Fine_in bis-is more than zero, then and output=(Pi/2-Fine_in1) of switch two, if
Fine_in bis-less than zero, then switchs the output=Fine_in1 of two.The output of switch two wants multiplication by constants 2/Pi as essence yardage
The output Fine_out of Operator Systems.
Referring to Fig. 5, described quadruple subsystem includes comparison amplifier one (sign1), comparison amplifier two
(sign2), data type converter (convert), d type flip flop (D Latch), enumerator one (count1), enumerator two
(count2), adder (ADD).The input of sign1 is as the input one of described quadruple subsystem, the output of sign1
The control end of end on the one hand linkage counter one, on the other hand connects the outfan one of D Latch via data type converter.
The input of sign2 as the input two of described quadruple subsystem, the outfan of sign2 on the one hand linkage counter two
Control end, on the other hand connect the outfan two of D Latch.The in-phase output end of D Latch connects the increasing number of two enumerators
Meter digital, the reversed-phase output of D Latch connects the subtrahend meter digital of two enumerators；The outfan of two enumerators is through addition
As the outfan of described quadruple subsystem after device computing.
Muti4_in1, Muti4_in2 are the inputs of quadruple subsystem, and Muti4_in1=gain1_out, Muti4_
In2=gain2_out.Muti4_in1 flowed to the D end of d type flip flop after entering data type conversion, Muti4_in2 flows to D
The CP end of trigger, output Q, the Q ' of d type flip flop flows to enumerator one sum counter two, enumerator one sum counter two respectively
Being up-down counter, rising edge and trailing edge to input pulse all do+1 counting, the output warp of enumerator one sum counter two
As the output Muti4_out of quadruple subsystem after adder summation.
Referring to Fig. 6, speed calculation subsystem includes that n sampling keeps (delay0～n), subtractor, divider
(Divide).10 samplings are used to keep delay in the present embodiment0～9.The outfan of speed calculation subsystem is through going here and there successively
10 samplings connect keep delay0～9Negative feedback inputs to it again, uses subtractor computing, then passes to the defeated of Divide
Entering end one, input two admiralty constant of Divide, such as 0.00001, the output of Divide is as whole speed calculation subsystem
Outfan.
Delay is once the time span Δ T of a system clock, and the number of times of delay is arbitrary, with 10 times in the present invention
As a example by, i.e. delay0～9, V_cal_in is the input of speed calculation subsystem, and V_cal_in=Pro2_out (multiplier two
Output), subtractor is sampled the Pro2_out in m moment and is kept 10 system clocks to obtain V_cal_in, is recorded as λm, adopt simultaneously
The Pro2_out of collection current time, is recorded as λm+n, n therein is the number of the system clock that sampling keeps, and result of calculation exports
To divider, result of calculation (λm+n-λm)/(n × Δ T) as speed calculation subsystem export V_cal_out, in the present invention with
As a example by (n × Δ T)=0.00001.
Referring to Fig. 7, each CRC check subsystem includes multiplier four (Product4), quantizer two
(Quantizer2), shaping number indexing transducer (Integer to Bit Converter), CRC check generator (General
CRC Generator).One input of Product4 as the input of CRC check subsystem, another of Product4
Input admiralty constant, the outfan of Product4 is sequentially connected in series quantizer two, shaping number indexing transducer, CRC check generation
Device, the outfan of CRC check generator is as the outfan of CRC check subsystem.CRC_in is the defeated of CRC check subsystem
Enter, and CRC1_in=Pro2_out, CRC2_in=V_Cal_out.CRC_in does multiplication fortune with check code constant through multiplier 4
Calculating, the quantified device of operation result 2 quantifies, and quantized result reconvert becomes bit value, finally does CRC fortune in CRC check generator
Calculating, its result is as the output CRC_out of CRC check subsystem.CRC check subsystem is unified to essence code real time position value
CRC calculates, and CRC check subsystem two is that the CRC to real-time speed value calculates.
Embodiment 1
1. incremental rotary encoder principles of signal processing
In an ideal case, the cosine and sine signal of incremental rotary encoder output A, B two-way phase 90 degree.Work as volume
Code device positive direction is rotary, B output signal delayed phase a-signal 90 degree；Otherwise, when encoder opposite direction rotates, A exports letter
Number delayed phase B signal 90 degree.Signal output waveform when encoder rotates forward, as shown in Figure 8, Fig. 8 is the rotation of encoder forward
Transfer out signal waveforms.
The initial signal demand of encoder, after conversion process, just can draw the information such as motor angle position.At signal
Process aspect, is divided into two-way by encoder output, as it is shown in figure 9, Fig. 9 is rotary encoder through signals processing system principle frame
Figure.One road signal through difference amplifier, proportional amplifier, be converted to TTL pulse signal, filtered process is by TTL signal even
Receive ADSP-CM408 mixed signal and control EIU (Encoder Interface Unit) the encoder interfaces unit of processor,
Carry out 4 frequency multiplication countings, obtain encoder thick code information；Another road signal Asin α and Bcos α through high speed operation amplifier and
RC filter circuit is transferred to the analog multiplexer of ADSP-CM408, after being then passed through sample/hold amplifier process, and transmission
To AD conversion unit, obtain the digital signal of sixteen bit sampling precision, the digital signal obtained is carried out essence code error correction.Connect
Employing electronics algorithm of subdivision, tangent value of directly negating, draw encoder electrical angle α, can be encoded by electrical angle α
Device essence code signal.Finally, thick code information and Fine interpolation information are added together, have just drawn accurate motor Angle Position angular velocity
Etc. information.
Signal conditioning circuit uses the ADA4899 high speed operation amplifier of ADI company, is amplified through two-stage by cosine and sine signal
Sine and cosine analogue signal after being nursed one's health after shaping；The most again through comparison amplifier, output high level is 3.3V, low level
For the Transistor-Transistor Logic level signal of 0V, as shown in Figure 10, Figure 10 is signal condition and interface circuit to signal conditioning circuit.
2.EIU coarse position counts
Encoder interfaces unit uses quadruple counting mode, and judges encoder direction of rotation.Encoder is exported
Cosine and sine signal complete cycle, be converted into, through comparator, the TTL pulse signal that periodicity is equal, by TTL pulse signal
Input EIU unit, carries out step-by-step counting, and as shown in figure 11, Figure 11 is that encoder interfaces unit coarse position counts schematic diagram.EIU
CNT0_UD, CNT0_DG (Figure 10) port input two-way Ti1, Ti2 (Figure 12) pulse signal of unit, according to its low and high level
Difference, forms the Gray code information of two changes.Before carrying out coarse position counting, need first pulse signals to carry out double D and touch
Send out device Filtering Processing.
When encoder rotates forward, two gray code signal Changing Patterns are 10,11,01,00,10 circulation change；Work as coding
During device reversion, two gray code signal Changing Patterns are 01,11,10,00,01 circulation change.State change, reversible meter each time
Number device all correspondences once increase or subtract counting.Therefore, a signal period carries out four countings, i.e. quadruple counting.When there being interference
Or during fault generation, such as shake, the generation of other states can be caused, now encoder does not counts, its state change letter
Breath is as shown in figure 12.
3. high-resolution segmentation positional information
When electrical angle is less than a cycle, in order to feed back real time information more accurately, need to use electronics segmentation to calculate
Method carries out frequency multiplication, to obtain motor Angle Position and the angular velocity of higher precision.ADSP-CM408MCU carries the ARM of 240MHz
Cortex-M4 kernel, has floating-point operation function, improves arithmetic speed, also can be same to encoder output two-way cosine and sine signal
Shi Jinhang double channel A/D is sampled, and the sampling time is 150ns, changes time 380ns.
3.1CORDIC algorithm is negated tangent
Electronics algorithm of subdivision mainly uses the direct evaluation method of arc tangent.The computing formula of electrical angle α is:
In order to realize antitrigonometric function evaluation faster, J.Volder proposes a kind of fast algorithm in nineteen fifty-nine, is referred to as
For CORDIC (Cordinate Rotation Digital Computer) algorithm.This algorithm is ensureing the situation of operational precision
Under, make operation time greatly reduce.As shown in figure 13, Figure 13 is that CORDIC plane coordinates rotates schematic diagram to cordic algorithm.Will
X, Y-axis coordinate rotate certain number of degrees, by n times interative computation, when vertical coordinate rotates to be 0, then the number of degrees of rotation are exactly
β.If (x, is y) original coordinates point, and by it centered by initial point, the coordinate after the β that turns clockwise is designated as (x ', y ').
Then there is a following coordinate rotation formula counterclockwise:
But, above-mentioned formula has four multiplyings computing when, and operand is the biggest, improves calculation further
Method.Now extract a multiplication factor cos α, from matrix operations formula, remove cos α, each postrotational new seat
Punctuate is elongated to the distance of initial point, and growth factor is 1/cos α.But, for the not impact of required α value.So computing
Amount just becomes twice multiplying.The most just obtain following coordinate rotation formula:
By the method for iteration, constantly rotate specific angle, the angle beta=ATAN (1/2 every time rotatedi) so that
The angle of the accumulative angle a certain setting of sum infinite approach rotated.This is the process of a continuous correction, in order to make y value unlimited
Approach zero, when certain rotates to an angle and draws y value for negative value, then rotate next time and need to be modified to opposite direction rotation.Then,
Cordic algorithm iterative formula is:
Then angle totalization formula is: zi+1=zi+diαi；di=± 1, wherein, ZiAfter expression cordic algorithm iteration i time
Angle accumulated value；Symbol diBeing the judgement factor, determine direction of rotation, it is positive and negative depends on gained y after iterationiIt is worth positive and negative.Angle
Result required by degree totalization formula is the value of electrical angle α.
3.2 real-time Fine interpolation positional values
Owing to simple dependence quadruple cannot meet requirement, in addition it is also necessary to the segmentation of higher precision, and sine and cosine letter
Number segmentation technology can obtain real-time Fine interpolation positional value.
When selecting 0～360 ° to carry out electronics segmentation, the when of approaching according to cordic algorithm, if angle
Value is relatively big, needs the number of times approached relatively big, indirectly adds operand so that operation time increases, thus is unfavorable for system
Real-time.Therefore, use 0～90 ° of little area method to calculate electrical angle herein, during due to thick yardage number, have employed quadruple meter
Number, just can only calculate the angular dimension in not 1/4th cycles of foot every time, will measure range shorter when calculating the value of electrical angle
To 0～90 degree, so with cordic algorithm negate tangent value time just decrease iterations, and then decrease operation time.
And, the method can reach the subdivision accuracy of more than tens times, when its upper limit is limited to AD sampling time and conversion in theory
Between and the computing speed of MCU.Drawn arc-tangent value by cordic algorithm, more (1) tried to achieve real-time Fine interpolation positional value by formula.
As shown in figure 14, Figure 14 is Fine interpolation calculation procedure flow chart to its software algorithm flowchart, described essence yardage
The Fine interpolation method of Operator Systems includes: first obtains the quantized value of Asin α and the Bcos α after AD conversion, and judges its symbol；Meter
Calculate ATAN (| Asin α/Bcos α |)；Judge that whether Asin α * Bcos α is more than or equal to 0；Be then α=ATAN (| Asin α/Bcos α
|), otherwise, α=90 °-ATAN (| Asin α/Bcos α |).
3.3 motor position information
High-precision motor rotation angle value is made up of two parts, by the thick code signal obtained and essence code signal essence the most in real time
Interpolation position value is combined, and obtains mechanical anglec of rotation λ of encoder.The computing formula of machinery anglec of rotation λ is:
Wherein, N represent rotor rotate a circle produce signal period number；Z represents that motor is actual and rotates the letter produced
Number periodicity；λ0Represent the initial position of rotor.
When measuring motor speed, improve M/T speed-measuring method, use change based on sampling angle, measure 10 and adopt
The angle changing value in sample cycle, thus eliminating the need the problem that in the M method unit interval, umber of pulse is few and T method two inter pulse time is short,
The real-time simultaneously also overcoming M/T method is not enough, and certainty of measurement is higher.Mechanical angle λ is passed to ADSP-CM408 and controls processor
Carry out calculation process, to obtain the rotating speed of motor, position and the data message such as to turn to.Motor speed algorithm is:
Wherein, λm+nIt is the m+n machinery anglec of rotation；λmFor the m-th machinery anglec of rotation；Δ T is the sampling time.
4. experiment simulation analysis
First signal conditioning circuit emulates at Multisim circuit simulating software.It is differential signal warp as shown in figure 15
Output waveform figure after signal conditioning circuit.
After primary signal is conditioned, obtain ideal signal waveform.By the signal after conditioning as Simulink
The signal source of emulation, obtains Fine interpolation information through 16 AD conversion, cordic algorithm, and the amplified device of source signal, comparator
And obtaining thick code information after quadruple counting, both additions obtain full location value information, then the CRC school through 32
Test, output to CRC1_out；Velocity amplitude is after 32 CRC checks, and CRC2_out is arrived in output.Its Simulink phantom
As shown in Figure 1.During emulation, simulation step length is set to 0.1s, and frequency input signal is 100kHz, and the sampling time is 0.25us.Warp
Simulation analysis understands, and as shown in figure 16, Figure 16 is | A |, the schematic diagram of | B | signal quantization value and Fine interpolation value α.A, B are being believed
Number i.e. Asin α, Bcos α is after a/d converter sample quantization, and take absolute value computing, obtains quantized value, transports through CORDIC
After calculation, obtaining arc-tangent value α, its value reappeared 0～90 ° of scope cycle, and therefore, it is right that formula algorithm (1) preferably achieves
The segmentation frequency multiplication of encoder cosine and sine signal.
When experiment, use Heidenhain 2048 line sine and cosine encoder, rotating speed 3000rpm, encoder output sine and cosine letter
Number frequency be 102.4kHz.In 0.1s, theoretical mechanical angle is 30.679616rad, and actual rotor angle value is
30.678849rad, error is 0.000767rad；And rate theory value is 306.796158rad/s.Figure 17 is different sampling weeks
During issue, emulation records speed-error curve figure, Different sampling period record the difference of speed and theoretical value be respectively 10,30,
50,70,90 sampling periods record velocity error data when surveying a speed.When using 10 sampling periods as the cycle of testing the speed
Time, error is relatively big, and along with the sampling period increases, error has reduced, and its error value is as shown in table 1.
Table 1 Different sampling period number records speed error value
5. conclusion
Segment frequency multiplication to realize the encoder of higher multiple, on the basis of quadruple counting, sine and cosine is encoded
Device signal carries out Fine interpolation positional value when AD samples realistic.Literary composition proposes and uses little area method to calculate the electricity less than a cycle
Angle value, is contracted to 0～90 ° by measuring angular range every time, and Matlab/Simulink simulation result shows, the method has
Preferably feasibility.Test the 2048 line encoder output signals of telecommunication to 100kHz and carry out each electrical angle cycle 40 times carefully
Point, resolution has reached 15.82 ".At the aspect that tests the speed, have employed improvement M/T velocimetry, calculate the electrical angle in 90 sampling periods
Changing value, in the hope of motor speed value, experiment display, speed error value is within ± 0.000115rad/s.
Other refer to for information about our company patent documentation CN201510465550.5, CN201520574867.8,
CN201510467898.8、CN201610029229.7、CN201610029321.3、CN201510465547.3、
CN201520570360.5。
Embodiment 2
When assuming actual application:
1. encoder resolution is 2048 lines；
2. motor speed is 3000rpm；
3. motor often revolves the screw mandrel amount of feeding that turns around is 5mm, i.e. 5mm/r；
4. amount of feeding resolution reaches 0.0001mm, corresponding mechanical angle be 360/ (5/0.0001)=0.0072 °=
25.92″。
If encoder segmentation multiple is N, then:Draw N > 24.4, the most minimum 25 frequencys multiplication.Note: by
In in encoder interfaces unit quadruple, therefore want to reach desired resolution, in addition it is also necessary to carry out 7 frequencys multiplication again, the most whole
Body segmentation multiple reaches 28 frequencys multiplication.
When rotating speed is 3000rpm, as shown in Figure 8, the frequency of encoder output cosine and sine signal is:
Fine interpolation computing formula:
Machinery anglec of rotation computing formula:
Speed calculation formula:
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all essences in the present invention
Any amendment, equivalent and the improvement etc. made within god and principle, should be included within the scope of the present invention.
Claims (9)
1. a sine and cosine encoder high-precision signal processing system, it is for processing the two-way of incremental rotary encoder output
The Asin α and Bcos α of phase 90 degree；It is characterized in that: described sine and cosine encoder high-precision signal processing system includes
The unification of difference amplifier one, difference amplifier two, AD conversion subsystem, AD conversion subsystem two, quadruple subsystem, multiplier
One, cordic algorithm subsystem, essence yardage Operator Systems, speed calculation subsystem, multiplier two, CRC check subsystem unified,
CRC check subsystem two；Wherein, the input of described difference amplifier one receives Asin α, the output of described difference amplifier one
End is simultaneously connected with the unified input of described AD conversion subsystem and the input one of described quadruple subsystem；Described differential amplification
The input of device two receives Bcos α, and the outfan of described difference amplifier two is simultaneously connected with the defeated of described AD conversion subsystem two
Enter the input two of end and described quadruple subsystem；The two-way output signal of two AD conversion subsystems connects described CORDIC
Two inputs of algorithm subsystem, the another two-way output signal of two AD conversion subsystems connects two of described multiplier one
Input, the outfan of described multiplier one, the outfan of described cordic algorithm subsystem connect described essence yardage respectively and calculate
Two inputs of subsystem；The output signal of described quadruple subsystem with described essence yardage Operator Systems output signal enter
Delivering to the input one of described multiplier two after row superposition, the outfan of described multiplier two is simultaneously connected with described CRC check
The input of system one, the input of described speed calculation subsystem；The unified outfan of described CRC check subsystem is as whole
The outfan one of sine and cosine encoder high-precision signal processing system, the outfan of described speed calculation subsystem connects described
The input of CRC check subsystem two, the outfan of described CRC check subsystem two is as whole sine and cosine encoder high accuracy
The outfan two of signal processing system.
2. sine and cosine encoder high-precision signal processing system as claimed in claim 1, it is characterised in that: described amplitude limiter
One end is as the input of AD conversion subsystem, and the other end of described amplitude limiter is sequentially connected in series asks absolute value one, difference amplifier
Three, quantizer one, the outfan of described quantizer one is as the outfan one of AD conversion subsystem, the other end of described amplitude limiter
It is also connected with an input contact of described switch one；Remaining two input contacts of described switch one receive two respectively and are respectively
The constant of 1 and-1, the outfan of described switch one is as the outfan two of AD conversion subsystem.
3. sine and cosine encoder high-precision signal processing system as claimed in claim 1, it is characterised in that: described CORDIC calculates
Method subsystem includes seeking absolute value two, asking absolute value three, CORDIC trigonometric function algorithm；Seek absolute value two, seek absolute value three
One end, respectively as two inputs of described cordic algorithm subsystem, is sought absolute value two, is asked the other end of absolute value three to divide
Not Lian Jie two inputs of CORDIC trigonometric function algorithm, the outfan of CORDIC trigonometric function algorithm is as described CORDIC
The outfan of algorithm subsystem.
4. sine and cosine encoder high-precision signal processing system as claimed in claim 1, it is characterised in that: described essence yardage is calculated
Subsystem includes switching two, multiplier three；Two input contacts of described switch two are respectively as described essence yardage Operator Systems
Two inputs, and one of them input contact one constant signal of input signal negative feedback after access described switch two again
Surplus next input contact；The output contact of described switch two connects the input of multiplier three, the outfan of multiplier three
Outfan as described essence yardage Operator Systems.
5. sine and cosine encoder high-precision signal processing system as claimed in claim 1, it is characterised in that: described quadruple
System includes comparison amplifier one, comparison amplifier two, data type converter, d type flip flop, enumerator one, enumerator two, adds
Musical instruments used in a Buddhist or Taoist mass；The input of comparison amplifier one is as the input one of described quadruple subsystem, the outfan of comparison amplifier one
On the one hand the control end of linkage counter one, on the other hand connects the outfan one of d type flip flop via data type converter；Ratio
On the one hand the relatively input of amplifier two connects as the input two of described quadruple subsystem, the outfan of comparison amplifier two
Connect the control end of enumerator two, on the other hand connect the outfan two of d type flip flop；The in-phase output end of d type flip flop connects two
The increasing counting number position of enumerator, the reversed-phase output of d type flip flop connects the subtrahend meter digital of two enumerators；Two enumerators
Outfan after adder computing as the outfan of described quadruple subsystem.
6. sine and cosine encoder high-precision signal processing system as claimed in claim 1, it is characterised in that: speed calculation subsystem
System includes: 0～n sampling holding, subtractor, divider；Delay is once the time span Δ T of a system clock, postpones
Number of times be arbitrary, V_cal_in is the input of speed calculation subsystem, and V_cal_in=Pro2_out, Pro2_out are
The output of multiplier two, subtractor is sampled the Pro2_out in m moment and is kept multiple system clocks to obtain V_cal_in, is recorded as
λm, gather the Pro2_out of current time simultaneously, be recorded as λm+n, n therein is the number of the system clock that sampling keeps, meter
Calculate result to export to divider, result of calculation (λm+n-λm)/(n × Δ T) export V_cal_out as speed calculation subsystem.
7. sine and cosine encoder high-precision signal processing system as claimed in claim 1, it is characterised in that: each CRC check
Subsystem includes multiplier four, quantizer two, shaping number indexing transducer, CRC check generator；One input of multiplier four
Holding the input as CRC check subsystem, another input admiralty constant of multiplier four, the outfan of multiplier four depends on
Secondary tandem quantization device two, shaping number indexing transducer, CRC check generator, the outfan of CRC check generator is as CRC school
Test the outfan of subsystem.
8. sine and cosine encoder high-precision signal processing system as claimed in claim 1, it is characterised in that: cordic algorithm
System, when antitrigonometric function evaluation, uses coordinate rotation formula, by the method for iteration, the specific angle of continuous rotary encoder
Degree, the angle beta=ATAN (1/2 every time rotatedi) so that the angle of the accumulative angle a certain setting of sum infinite approach rotated, 2i
Representing the angle accumulated value after cordic algorithm iteration i time, i represents iterations.
9. sine and cosine encoder high-precision signal processing system as claimed in claim 1, it is characterised in that: described essence yardage is calculated
The Fine interpolation method of subsystem includes: first obtains the quantized value of Asin α and the Bcos α after AD conversion, and judges its symbol；Calculate
ATAN(|Asinα/Bcosα|)；Judge that whether Asin α * Bcos α is more than or equal to 0；It is then α=ATAN (| Asin α/Bcos α |),
Otherwise, α=90 °-ATAN (| Asin α/Bcos α |).
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