CN101854172A - Numerical control oscillator parallel design method based on two-dimensional sine table - Google Patents

Abstract

The invention discloses a numerical control oscillator parallel design method based on a two-dimensional sine table, which comprises the following steps that: step 1: a group of two-dimensional sine table which comprises a plurality of rows and a plurality of lines of data is established; step 2: a phase accumulator is driven by a working lock to produce a digital phase accumulated valve according to a frequency control word, and outputs the same to a phase truncation device; step 3: the phase truncation device truncates the digital phase accumulated valve, converts the phase accumulated value into the address of a lookup table, and outputs the value to the two-dimensional sine table; step 4: the address of the lookup table serves a line number to search the two-dimensional sine table, searches and outputs a line of data of the sine table every time, is driven by the working clock, and continuously outputs and obtains M circuits of parallel digital sequences; comprised the traditional parallel numerical control oscillators, the novel parallel numerical control oscillator design method has higher delay resolution, better phase continuity and less hardware resource consumption.

Description

A kind of numerical control oscillator parallel design method based on two-dimensional sine table

Technical field

The present invention relates generally to a kind of method for designing of digital controlled oscillator, relates in particular to a kind of numerical control oscillator parallel design method based on two-dimensional sine table.

Background technology

In recent years, along with Direct Digital frequency synthesis (DDS, Direct Digital Synthesis) development of technology, digital controlled oscillator (NCO, Numberically Controlled Oscillator) as the core of DDS, because advantages such as its output signal frequency precision height, switching time is short, control is simple have obtained using widely in many aspects such as radar, communication, radio and television, instrument and meters.

Digital controlled oscillator mainly comprises phase accumulator and function generator two large divisions.Phase accumulator adds up to the frequency control word of input, obtain the digit phase of each clock cycle correspondence, again with in this digit phase input function generator, table look-up or after a series of phase-magnitude changes, just can obtain the sin cos functions value corresponding with input phase.

When utilizing hardware to realize digital controlled oscillator, be subject to the working clock frequency of hardware platform, often need to adopt parallel structure.Fig. 1 shows the structured flowchart of existing four tunnel parallel digital controlled oscillators, existing parallel digital controlled oscillator comprises a phase accumulator 101, four phase regulators 102,103,104,105, four identical phase truncation devices 106,107,108,109, and four identical sine tables 110,111,112,113.Four phase regulators are responsible for adjusting the phase difference between four road parallel signals, make four way word signals of final output can realize the splicing of frequency and phase place, obtain one road sinusoidal digital signal continuous, Quad Data Rate.

Though this implementation structure has reduced clock frequency, the hardware resource of digital controlled oscillator consumption is doubled, computation complexity increases, and the strict phase relation between each road parallel signal is difficult to guarantee.

Summary of the invention

The invention provides a kind of numerical control oscillator parallel design method, can reduce of the consumption of parallel digital controlled oscillator, improve the phase continuity of output Serial No. hardware resource based on two-dimensional sine table.

Described numerical control oscillator parallel design method based on two-dimensional sine table comprises the steps:

The first step: set up one group of two-dimensional sine table, comprise several rows, some columns certificates; The data member of every row is represented the some sampled points of every road parallel signal in the sinusoidal wave monocycle, and the data member of every row is represented each sinusoidal sampled point of each road parallel signal constantly, and each phase difference of going between two adjacent data members is

Each phase difference that is listed as between two adjacent data members is

Wherein, f _CLKBe working clock frequency, f ₀Be the centre frequency of digital controlled oscillator, M is the number of parallel signal, and H is the columns of two-dimensional sine table, i.e. sampling number in each sinusoidal wave monocycle;

Second step: phase accumulator produces the digit phase accumulated value according to frequency control word, and exports to the phase truncation device under the driving of work clock;

The 3rd step: the phase truncation device blocks the phase-accumulated value of numeral, and phase-accumulated value is converted to the look-up table address, and exports two-dimensional sine table to;

The 4th step: the look-up table address number is used for searching two-dimensional sine table as row, searches a columns certificate of output sine table at every turn, and under work clock drove, output obtained the parallel Serial No. in M road continuously, and the sample rate of Serial No. is f _CLK, centre frequency is f ₀

Beneficial effect of the present invention:

This new parallel digital controlled oscillator method for designing of the present invention, more existing parallel digital controlled oscillator time delay resolution is higher, and phase continuity is better, less hardware resource consumption.

Description of drawings

Fig. 1 is the block diagram that existing four tunnel parallel digital controlled oscillators are shown;

Fig. 2 is the block diagram based on four tunnel parallel digital controlled oscillators of two-dimensional sine table that illustrates according to exemplary embodiment of the present invention;

Fig. 3 is the block diagram that illustrates according to the two-dimensional sine table in the parallel digital controlled oscillator of exemplary embodiment of the present invention;

Embodiment

Reference is below in conjunction with the detailed description of accompanying drawing to exemplary embodiment, and the method for advantage of the present invention and characteristics and realization can more easily be understood.

Fig. 2 is the block diagram based on four tunnel parallel digital controlled oscillators of two-dimensional sine table according to exemplary embodiment of the present invention.Digital controlled oscillator according to exemplary embodiment of the present invention comprises: phase accumulator 202, phase truncation device 203 and two-dimensional sine table 204.

Accumulator 202 is with frequency control word f _DDSBe step-length, under the driving of clock, produce phase-accumulated value φ _Acc, and the phase-accumulated value φ that will produce _AccOutput to phase truncation device 203.

Frequency control word f _DDSCan determine by following formula:

$f_{\mathrm{DDS}}=\frac{f_0}{f_{\mathrm{CLK}}}\·2^N$

Wherein, f _CLKBe working clock frequency, f ₀Be the centre frequency of digital controlled oscillator, N is phase-accumulated value φ _AccNumber of bits.

Then, the phase-accumulated value φ of 203 pairs of generations of phase truncation device _AccBlock, be about to phase-accumulated value φ _AccW the binary digit that move to right, what obtain sine table searches address φ _Tab, the figure place that moves to right W can calculate by following formula:

W＝N-log ₂H

Wherein, N is phase-accumulated value φ _AccNumber of bits, H is the length of two-dimensional sine table 204, it is the sampling number in each sinusoidal wave monocycle, in the present embodiment, it is any positive integer of 2 time power that H can be chosen for as required, it only can influence the signal to noise ratio of digital controlled oscillator output sequence and spuious, can not influence the basic function of digital controlled oscillator.

Fig. 3 illustrates the block diagram according to the two-dimensional sine table in the parallel digital controlled oscillator shown in Figure 2 of exemplary embodiment of the present invention.

The one-dimension array structure that is different from traditional sine table, two-dimensional sine table are a kind of two-dimensional array structures, have 4 row, H row.Data member is considered to generate from the angle of phase place: each phase difference of going between two adjacent data members is

Each phase difference that is listed as between two adjacent data members is

The numerical value of the data member of sine table calculates by following formula:

Wherein, A is the quantization amplitude of sine table; M is the row number of sine table, and value gets 0,1,2,3; N is the row number of sine table, and value gets 0,1 ..., H-1.

Sine table lookup address φ _TabNumber be used to search two-dimensional sine table as row.Once search output one columns certificate, promptly four sampled points under work clock drives, are exported continuously and are obtained four way word sequence S _OSC1, S _OSC2, S _OSC3And S _OSC4Four way word sequence S _OSC1, S _OSC2, S _OSC3And S _OSC4Centre frequency be f ₀, initial phase is followed successively by 0,

Two-dimensional sine table can design in mathematical softwares such as Matlab in advance and finish, and the double-precision floating point computing among the Matlab is higher than the fixed-point calculation precision in the hardware, and is beneficial to the processing that rounds up, and reduces the error of calculation.

Claims (1)

1. the numerical control oscillator parallel design method based on two-dimensional sine table is characterized in that: comprise the steps:

The first step: set up one group of two-dimensional sine table, comprise several rows, some columns certificates; The data member of every row is represented the some sampled points of every road parallel signal in the sinusoidal wave monocycle, and the data member of every row is represented each sinusoidal sampled point of each road parallel signal constantly, and each phase difference of going between two adjacent data members is Each phase difference that is listed as between two adjacent data members is

Wherein, f _CLKBe working clock frequency, f ₀Be the centre frequency of digital controlled oscillator, M is the number of parallel signal, and H is the columns of two-dimensional sine table, i.e. sampling number in each sinusoidal wave monocycle;

Second step: phase accumulator produces the digit phase accumulated value according to frequency control word, and exports to the phase truncation device under the driving of work clock;

The 3rd step: the phase truncation device blocks the phase-accumulated value of numeral, and phase-accumulated value is converted to the look-up table address, and exports two-dimensional sine table to;

The 4th step: the look-up table address number is used for searching two-dimensional sine table as row, searches a columns certificate of output sine table at every turn, and under work clock drove, output obtained the parallel Serial No. in M road continuously, and the sample rate of Serial No. is f _CLK, centre frequency is f ₀

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