CN116827122A

CN116827122A - Current detection circuit and method of DC-DC converter, power conversion system and power supply

Info

Publication number: CN116827122A
Application number: CN202310773184.4A
Authority: CN
Inventors: 黄顺煜; 黄威仁; 李思颖
Original assignee: Agco Microelectronics Shenzhen Co ltd
Current assignee: Agco Microelectronics Shenzhen Co ltd
Priority date: 2023-06-27
Filing date: 2023-06-27
Publication date: 2023-09-29

Abstract

The present disclosure provides a current detection circuit, a method, a power conversion system and a power supply of a DC-DC converter, relating to the field of electronics, the current detection circuit comprising a processing circuit configured to, in each of at least one set of switching cycles: detecting a current based on a terminal voltage output period of the other end of the capacitor having one end grounded; in a first period, increasing a terminal voltage of the capacitor with a constant current; in a second period, using the low side detection current to enable the terminal voltage of the capacitor to change along with the low side detection current; each set of switching cycles comprises a first switching cycle and a second switching cycle which are consecutive, and in each set of switching cycles, the intensity of the constant current in the second switching cycle is determined based on the intensity of the terminal voltage of the capacitor at least two moments during which the low-side power transistor is on in the second period of the first switching cycle. Thus, the accuracy of inductor current detection can be improved.

Description

Current detection circuit and method of DC-DC converter, power conversion system and power supply

Technical Field

The present disclosure relates to the field of electronics, and in particular, to a current detection circuit, a method, a power conversion system, and a power supply for a direct current-direct current (DC-DC) converter.

Background

A DC-DC converter includes two power transistors connected in series between an input terminal and a ground terminal. The switching node between the two power transistors is connected to the inductor, and one of the two power transistors is configured to be turned off during the other on.

In the related art, for the purpose of overcurrent protection, current feedback, and the like, it is necessary to detect an inductor current flowing through an inductor.

Disclosure of Invention

According to an aspect of the disclosed embodiments, there is provided a current detection circuit of a DC-DC converter, the DC-DC converter including a high-side power transistor and a low-side power transistor connected in series between an input terminal and a ground terminal, a switching node between the high-side power transistor and the low-side power transistor being connected to an inductance; the current detection circuit includes: a first detection circuit configured to detect a current supplied to the inductor by the low-side power transistor during an on period of the low-side power transistor to output a low-side detection current; and processing circuitry including a first capacitor having a first terminal connected to ground, the processing circuitry configured to perform operations in each of at least one set of switching cycles, the operations comprising: and detecting a current based on a terminal voltage output period of a second terminal of the first capacitor, increasing the terminal voltage of the first capacitor by using a constant current in a first period, wherein the first period is one of a period in which the high-side power transistor is turned on and a period in which the low-side power transistor is turned off, the terminal voltage of the first capacitor is changed following the change of the low-side detection current by using the low-side detection current in a second period, and the second period and the first period constitute one switching period of the DC-DC converter, wherein each group of switching periods comprises a first switching period and a second switching period which are sequentially continuous to the DC-DC converter, and the intensity of the constant current in the second switching period is determined based on the intensity of the terminal voltage of the first capacitor in at least two moments in the first switching period, the at least two moments belonging to the period in which the low-side power transistor is turned on in the second period of the first switching period.

In some embodiments, the magnitude of the constant current in the second switching period is determined based on a magnitude of a terminal voltage of the first capacitor in a duration of the first switching period, the duration belonging to a period during which the low-side power transistor is on in a second period of the first switching period.

In some embodiments, the first period is a period in which the high-side power transistor is on.

In some embodiments, the processing circuitry is configured to: determining the intensity of the constant current in the second switching period according to the low-side voltage slope of the intensity of the terminal voltage of the first capacitor, which changes in the at least two moments.

In some embodiments, the processing circuitry is configured to: determining the intensity of the constant current in the second switching period according to the low-side voltage slope, the input voltage of the DC-DC converter and the output voltage of the DC-DC converter.

In some embodiments, the constant current strength in the second switching period is positively correlated with a product of the low side voltage slope and a ratio between the difference between the input voltage and the output voltage.

In some embodiments, the processing circuit includes: a current-voltage conversion circuit configured to convert the low-side detection current output from the first detection circuit into a first voltage; a first switch connected between a second terminal of the first capacitor and the current-voltage conversion circuit and configured to be turned off for a first period and turned on for a second period; and a sub-processing circuit configured to provide the constant current; a second switch is connected between the sub-processing circuit and the second terminal of the first capacitor and is configured to be turned on for a first period of time and turned off for a second period of time.

In some embodiments, the sub-processing circuit comprises: a second period slope circuit including a second capacitor having a first terminal connected to ground and configured to control a terminal voltage of a second terminal of the second capacitor to be maintained at a second voltage positively correlated to the low-side voltage slope in accordance with the first voltage; wherein the processing circuit is configured to determine the intensity of the constant current in the second switching period from the second voltage, the input voltage and the output voltage.

In some embodiments, the second period slope circuit includes: a differentiating circuit configured to output a third voltage positively correlated to a low-side voltage slope of the first voltage variation; a third switch connected between the differentiating circuit and the second terminal of the second capacitor and configured to be turned off for a first period and turned on for a second period.

In some embodiments, the sub-processing circuit further comprises: a duration circuit configured to output a pulse signal in which a duration of a pulse is positively correlated with a ratio of the second voltage and the output voltage, based on the second voltage and the output voltage; a first period pseudo-current circuit including a third capacitor and a fourth capacitor having a first terminal connected to ground and configured to increase a terminal voltage at a second terminal of the third capacitor with a first current positively correlated with a difference between the input voltage and the output voltage during a pulse duration in the pulse signal; sampling the terminal voltage of the third capacitor at the end of the pulse so that the terminal voltage of the second terminal of the fourth capacitor is kept at the sampled fourth voltage; the constant current in the second switching period is converted based on a terminal voltage of the fourth capacitor.

In some embodiments, the duration circuit comprises: a second voltage-to-current conversion circuit configured to convert the output voltage into a second current; the first end of the fifth capacitor is grounded, and the second end of the fifth capacitor is connected with the second voltage-current conversion circuit; a pulse generating circuit configured to output pulses in the pulse signal during an increase in a terminal voltage of a second terminal of the fifth capacitor from 0 to the second voltage; and a fourth switch having one end connected to an intermediate node between the second voltage-to-current conversion circuit and the fifth capacitor and the other end grounded, the fourth switch being configured to start turning on a first discharge period from the end of the sampling.

In some embodiments, the first period pseudo-current circuit comprises: a subtractor configured to output a fifth voltage positively correlated with a difference between the input voltage and the output voltage; a third voltage-current conversion circuit configured to obtain the first current based on the fifth voltage conversion; a fifth switch connected between the third voltage-to-current conversion circuit and the second terminal of the third capacitor and configured to be turned on during the pulse duration; a sample-and-hold circuit comprising the fourth capacitor and configured to sample a terminal voltage of the third capacitor at the end of the pulse such that the terminal voltage of the fourth capacitor is held at the fourth voltage; a sixth switch having one end connected to an intermediate node between the fifth switch and the third capacitor and the other end grounded, the sixth switch being configured to start turning on a second discharge period from the end of sampling by the sample-and-hold circuit; a fourth voltage-to-current conversion circuit configured to convert the constant current in the second switching period based on a terminal voltage of the fourth capacitor.

In some embodiments, the processing circuit includes: and a first voltage-current conversion circuit connected with the second end of the first capacitor and configured to obtain the period detection current based on the terminal voltage conversion of the first capacitor.

In some embodiments, the processing circuit is configured to perform the operation in each of a plurality of sets of switching cycles.

According to another aspect of the embodiments of the present disclosure, there is provided a current detection method of a DC-DC converter, the DC-DC converter including a high-side power transistor and a low-side power transistor connected in series between an input terminal and a ground terminal, a switching node between the high-side power transistor and the low-side power transistor being connected to an inductor; the method includes, in each of at least one set of switching cycles: detecting a current based on a terminal voltage output period of a second terminal of the first capacitor, the first terminal being grounded; detecting a current provided by the low-side power transistor to the inductor during the on period of the low-side power transistor so as to obtain a low-side detection current; increasing a terminal voltage of the first capacitor with a constant current in a first period, the first period being one of a period in which the high-side power transistor is turned on and a period in which the low-side power transistor is turned off; and in a second period, changing a terminal voltage of the first capacitor with the low-side detection current, the second period and the first period constituting one switching cycle of the DC-DC converter, wherein each group of switching cycles includes a first switching cycle and a second switching cycle that are consecutive in succession of the DC-DC converter, and in each group of switching cycles, an intensity of the constant current in the second switching cycle is determined based on an intensity of the terminal voltage of the first capacitor at least two times in the first switching cycle, the at least two times belonging to a period during which the low-side power transistor is turned on in the second period of the first switching cycle.

In some embodiments, the method further comprises: determining the intensity of the constant current in the second switching period according to the low-side voltage slope of the intensity of the terminal voltage of the first capacitor, which changes in the at least two moments.

In some embodiments, the intensity of the constant current in the second switching period is determined from the low-side voltage slope, the input voltage of the DC-DC converter, and the output voltage of the DC-DC converter.

According to still another aspect of the embodiments of the present disclosure, there is provided a power conversion system including: the current detection circuit of the DC-DC converter according to any one of the above embodiments; and the DC-DC converter.

According to still another aspect of the embodiments of the present disclosure, there is provided a power supply including: the power conversion system according to any one of the above embodiments.

In the current detection circuit of the DC-DC converter provided by the embodiments of the present disclosure, the processing circuit increases the terminal voltage of the first capacitor with a constant current in a first period in the switching cycle of the DC-DC converter, and changes the terminal voltage of the first capacitor with a low-side detection current in a second period to follow the low-side detection current change, so as to detect the current based on the terminal voltage output cycle of the first capacitor in the switching cycle of the DC-DC converter. In this way, the processing circuit can output a periodic sense current that increases with a constant slope as the real inductor current during the high-side power transistor on period, and output a periodic sense current that coincides with the accurate low-side sense current output by the first sense circuit during the low-side power transistor on period. Further, the intensity of the constant current in the latter switching period is determined based on the intensity of the terminal voltage of the first capacitor at least two times during the on period of the low-side power transistor in the former switching period. In this way, the rising slope of the period detection current in the second switching period can be made close to the rising slope of the real inductor current in the second switching period. Thus, the accuracy of inductor current detection can be improved.

Other features, aspects, and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the disclosure, which is to be read in connection with the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The disclosure may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic diagram of a power conversion system according to some embodiments of the present disclosure;

FIG. 2 is a signal waveform diagram according to some embodiments of the present disclosure;

FIG. 3 is a schematic diagram of a processing circuit according to some embodiments of the present disclosure;

FIG. 4 is a schematic diagram of sub-processing circuitry according to some embodiments of the present disclosure;

FIG. 5 is a schematic diagram of a second period slope circuit according to some embodiments of the present disclosure;

FIG. 6 is a schematic diagram of a time duration circuit according to some embodiments of the present disclosure;

FIG. 7 is a schematic diagram of a first period pseudo-current circuit according to some embodiments of the present disclosure;

FIG. 8 is a signal waveform diagram according to further embodiments of the present disclosure;

fig. 9 is a flow chart of a method of current detection of a DC-DC converter according to some embodiments of the present disclosure.

It should be understood that the dimensions of the various elements shown in the figures are not necessarily drawn to actual scale. Further, the same or similar reference numerals denote the same or similar members.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative, and is in no way intended to limit the disclosure, its application, or uses. The present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that: the relative arrangement of parts and steps, the composition of materials, numerical expressions and numerical values set forth in these embodiments should be construed as exemplary only and not limiting unless otherwise specifically stated.

The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises" and the like means that elements preceding the word encompass the elements recited after the word, and not exclude the possibility of also encompassing other elements. "upper", "lower", etc. are used merely to denote relative positional relationships, which may also change accordingly when the absolute position of the object to be described changes.

In this disclosure, when a particular element is described as being located between a first element and a second element, there may or may not be intervening elements between the particular element and the first element or the second element. When it is described that a specific component is connected to other components, the specific component may be directly connected to the other components without intervening components, or may be directly connected to the other components without intervening components.

All terms (including technical or scientific terms) used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs, unless specifically defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.

In the related art, one way to detect the inductor current is to detect the current passing through the power transistors with a detection circuit including a detection transistor and an operational amplifier, respectively, for each of the two power transistors.

The detected inductive current can be obtained by adding the detected currents output by the two detection circuits corresponding to the two power transistors at the same time, or the detected current output by the detection circuit corresponding to the on power transistor is used as the detected inductive current, and the detected current output by the detection circuit corresponding to the off power transistor is ignored.

However, in one switching cycle of the DC-DC converter, the duration of the high-side power transistor turned on is relatively short, and the short on time also includes a time that the detection circuit cannot accurately detect due to Ringing (SW Ringing) of the switching node, and the detection circuit can accurately detect after the Ringing of the switching node stops.

In other words, the proportion of time that the detection circuit accurately detects during the turn-on period of the high-side power transistor is small, which results in inaccuracy of the current that the detection circuit detects during the turn-on period of the high-side power transistor, and thus in inaccuracy of the inductor current detection.

By analysis, unlike the high-side power transistor, the low-side power transistor is turned on for a relatively long period of time, and the detection circuit detects a relatively accurate current during the period in which the low-side power transistor is turned on.

In view of this, the present disclosure proposes embodiments that use only the detection circuit to detect the current during the on period of the low-side power transistor, and no longer use the detection circuit to detect the current during the on period of the high-side power transistor, thereby improving the accuracy of inductor current detection.

Fig. 1 is a schematic diagram of a power conversion system according to some embodiments of the present disclosure.

As shown in fig. 1, the power conversion system includes a DC-DC converter and a current detection circuit of the DC-DC converter.

The DC-DC converter is configured to receive an input voltage Vin from an input terminal Vin and convert the input voltage Vin to an output voltage VOUT to be output from an output terminal VOUT. The DC-DC converter comprises a high side power transistor 11 and a low side power transistor 12 connected in series between an input terminal Vin and ground.

One of the high-side power transistor 11 and the low-side power transistor 12 is configured to be turned off during the other on. That is, the high-side power transistor 11 is configured to be turned off during the on period of the low-side power transistor 12, and the low-side power transistor 12 is configured to be turned off during the on period of the high-side power transistor 11.

Referring to fig. 1, the high side power transistor 11 may be controlled using a control signal dUG and the low side power transistor 12 may be controlled using a control signal dLG such that one of the high side power transistor 11 and the low side power transistor 12 is turned off during the other is turned on.

In some embodiments, high-side power transistor 11 and low-side power transistor 12 are metal-oxide semiconductor field effect transistors (MOSFETs), such as N-type MOSFETs or P-type MOSFETs.

The switching node SW between the high-side power transistor 11 and the low-side power transistor 12 is connected to the inductance L. In some embodiments, referring to fig. 1, the DC-DC converter further comprises a capacitor C having one end grounded and the other end connected to the inductance L.

The current detection circuit of the DC-DC converter comprises a first detection circuit 110 as shown in fig. 1. The first detection circuit 110 is configured to detect a current supplied to the inductor L by the low-side power transistor 12 during an on period of the low-side power transistor 12 to output a low-side detection current Isen1.

As some implementations, referring to fig. 1, the first detection circuit 110 includes an operational amplifier 111 and a detection transistor 112.

The detection transistor 112 is, for example, of the same type as the low-side power transistor 12 and has an on-resistance K times that of the low-side power transistor 12. K may be an integer of 2 or more, for example.

In some embodiments, the sense transistor 112 is fabricated on the same die (die) as the low-side power transistor 12 and the two are located adjacent. In this way, the main difference between the detection transistor 112 and the low-side power transistor 12 is only the channel width to length ratio (channel W/Lratio), while the other semiconductor process parameters are about the same, and this may also allow the detection transistor 112 and the low-side power transistor 12 to have close temperatures when the DC-DC converter is operating.

For example, the gate of the sense transistor 112 receives the same control signal dLG as the gate of the low-side power transistor 12. One terminal (e.g., source) of the sense transistor 112 is connected to one terminal (e.g., source) of the low-side power transistor 12.

The positive input of the operational amplifier 111 is connected to the other end (e.g., drain) of the low-side power transistor 12, and the negative input of the operational amplifier 111 is connected to the other end (e.g., drain) of the detection transistor 112. The negative input of the operational amplifier 111 is also connected to the output of the operational amplifier 111. The low side detection current Isen1 is output via the output terminal of the operational amplifier 111.

The current detection circuit of the DC-DC converter further comprises a processing circuit 120 as shown in fig. 1. As shown in fig. 3, the processing circuit 120 includes a first capacitor Cs1 having a first end grounded and a second end ungrounded.

The processing circuit 120 is configured to perform operations in each of at least one set of switching cycles. The following is a description with reference to fig. 2. Fig. 2 is a signal waveform diagram according to some embodiments of the present disclosure.

As shown in fig. 2, each switching cycle of the DC-DC converter is constituted by a first period p1 and a second period p 2. The first period p1 is one of a period in which the high-side power transistor 11 is on and a period in which the low-side power transistor 12 is off.

For example, the first period p1 is a period in which the high-side power transistor 11 is turned on, and the second period p2 is a period in which the high-side power transistor 11 is turned off. For another example, the first period p1 is a period in which the low-side power transistor 12 is turned off, and the second period p2 is a period in which the low-side power transistor 12 is turned on.

In other words, the first period p1 always includes a period in which the high-side power transistor 11 is turned on, and the second period p2 always includes a period in which the low-side power transistor 12 is turned on.

Fig. 2 schematically shows that the first period p1 is a period in which the high-side power transistor 11 is turned on. When the control signal dUG of the high-side power transistor 11 is high, the high-side power transistor 11 is turned on; in the case where the control signal dUG of the high-side power transistor 11 is low, the high-side power transistor 11 is turned off.

Although the control signal dLG of the low-side power transistor 11 is not shown in fig. 2, it is understood that the control signal dLG is high only during the second period p2 of each switching cycle.

The operation performed by the processing circuit 120 in each of at least one set of switching cycles is described below.

The operation performed by the processing circuit 120 in each switching cycle includes outputting the cycle detection current Isen based on the terminal voltage Vc1 of the second terminal of the first capacitor Cs1 that is not grounded. That is, the waveform of the period detection current Isen output by the processing circuit 120 in each switching period is desirably substantially identical to the waveform of the terminal voltage Vc1 of the first capacitor Cs1 shown in fig. 2.

The operation performed by the processing circuit 120 in each of the at least one set of switching cycles further includes increasing the terminal voltage Vc1 of the first capacitor Cs1 with the constant current Isr during the first period p 1.

It is understood that the constant current Isr refers to a current of constant intensity during the first period p1 of a certain switching cycle. In the first period p1 of the different switching periods, the intensities of the constant currents Isr may be the same or different.

When the terminal voltage Vc1 of the first capacitor Cs1 is increased by the constant-intensity current Isr in the first period p1, the terminal voltage Vc1 of the first capacitor Cs1 increases with a constant slope in the first period p1, and the processing circuit 120 also increases with a constant slope in the first period p1 based on the period detection current Isen output by the terminal voltage Vc 1.

That is, in the first period p1 in which the high-side power transistor 11 is turned on, the period detection current Isen output by the processing circuit 120 also increases with a constant slope. This is consistent with the true inductor current which increases with a constant slope during the turn-on of the high side power transistor 11.

In other words, by increasing the terminal voltage Vc1 of the first capacitor Cs1 with the constant current Isr in the first period p1 and outputting the period detection current Isen based on the terminal voltage Vc1 of the first capacitor Cs1, the processing circuit 120 can output the period detection current Isen that increases with a constant slope as the true inductor current during the high-side power transistor 11 is on.

It can be seen that during the on period of the high-side power transistor 11, the processing circuit 120 does not output a current based on the detection circuit, but outputs a pseudo current based on the terminal voltage Vc1 that increases with a constant slope.

In some embodiments, the first period p1 is a period in which the high-side power transistor 11 is turned on. The processing circuit 120 increases the terminal voltage Vc1 of the first capacitor Cs1 with the constant current Isr only in the period in which the high-side power transistor 11 is on, so that the detection current increased with a constant slope can be output only in the period in which the high-side power transistor 11 is on. This is more suitable for the case where the true inductor current increases with a constant slope only during the turn-on of the high-side power transistor 11, so that the accuracy of inductor current detection can be improved.

The operation performed by the processing circuit 120 in each of the at least one set of switching cycles further includes a second period p2, the terminal voltage Vc1 of the first capacitor Cs1 being varied following the variation of the low-side detection current Isen1 by the low-side detection current Isen1 outputted by the first detection circuit 110.

In this way, neglecting losses due to circuit transmission or the like, the period detection current Isen output by the processing circuit 120 during the on period of the low-side power transistor 12 in the second period p2 is the same as the low-side detection current Isen1 output by the first detection circuit 110 during the on period of the low-side power transistor 12 in the second period p 2.

That is, during the on period of the low-side power transistor 12, the processing circuit 120 outputs the low-side detection current Isen1 based on the detection of the first detection circuit 110.

In an embodiment provided by the present disclosure, each of the at least one set of switching cycles includes a first switching cycle and a second switching cycle that are consecutive in succession of the DC-DC converter.

In each set of switching periods, the intensity of the constant current Isr in the second switching period is determined based on the intensity of the terminal voltage Vc1 of the first capacitor Cs1 in at least two times in the first switching period, which belong to the period during which the low-side power transistor 12 is turned on in the second period p2 of the first switching period. That is, during the on period of the low-side power transistor 12 in the second period p2 of the previous switching cycle, at least two timings are selected, and the terminal voltage Vc1 of the first capacitor Cs1 at the at least two timings is measured, so that the intensity of the constant current Isr in the second switching cycle can be determined.

It is to be understood that the intensity of the constant current Isr in the second switching period determines the high-side voltage slope at which the terminal voltage Vc1 of the first capacitor Cs1 increases in the first period p1 of the second switching period (i.e., the slope at which the period detection current Isen increases in the first period p1 of the second switching period, hereinafter referred to as the rising slope), and the intensity of the terminal voltage Vc1 of the first capacitor Cs1 at each time instant within the second period p2 of the first switching period determines the intensity of the period detection current Isen output by the processing circuit 120 at that time instant.

The intensity of the constant current Isr in the second switching period is determined based on the intensity of the terminal voltage Vc1 of the first capacitor Cs1 at least two times during which the low-side power transistor 12 is turned on in the second period p2 of the first switching period, that is, the rising slope of the period detection current Isen in the first period p1 of the second switching period is determined based on the intensity of the period detection current Isen output from the processing circuit 120 at least two times during which the low-side power transistor 12 is turned on in the first switching period.

Since the real inductor current has continuity, according to the intensity of the period detection current Isen at least two times during which the low-side power transistor 12 is turned on in the previous switching period (i.e., the first switching period), the rising slope of the period detection current Isen in the subsequent switching period (i.e., the second switching period) based on the pseudo current output can be made to be close to the rising slope of the real inductor current in the second switching period, so that the accuracy of the inductor current detection can be improved.

Further, at least two times belong to the period during which the low-side power transistor 12 is turned on in the second period p2, that is, the rising slope of the period detection current Isen in the first period p1 of the second switching period is determined according to the intensities of the period detection current Isen at least two times during which the low-side power transistor 12 is turned on in the second period p2 in the first switching period.

Since the intensity of the period detection current Isen during the on period of the low-side power transistor 12 in the first switching period is an accurate value actually detected by the first detection circuit 110, the rising slope of the period detection current Isen in the second switching period can be made closer to the rising slope of the real inductor current in the second switching period according to the intensity of the period detection current Isen during at least two times during the on period of the low-side power transistor 12 in the first switching period, so that the accuracy of the inductor current detection can be further improved.

Therefore, the rising slope of the period detection current Isen in the second switching period is more similar to the rising slope of the real inductor current in the second switching period, so that the accuracy of inductor current detection can be further improved.

In the above-described embodiment, the processing circuit 120 increases the terminal voltage Vc1 of the first capacitor Cs1 with the constant current Isr in the first period p1 in the switching cycle of the DC-DC converter, and changes the terminal voltage Vc1 of the first capacitor Cs1 with the low side detection current Isen1 in the second period p2 following the change of the low side detection current Isen1 to output the cycle detection current Isen based on the terminal voltage Vc1 of the first capacitor Cs1 in the switching cycle of the DC-DC converter. In this way, the processing circuit 120 can output the periodic sense current Isen that increases with a constant slope as the true inductor current during the turn-on of the high-side power transistor 11, and output the periodic sense current Isen that coincides with the accurate low-side sense current Isen1 output by the first sense circuit 110 during the turn-on of the low-side power transistor 12. Further, the intensity of the constant current Isr in the latter switching period is determined based on the intensity of the terminal voltage Vc1 of the first capacitor Cs1 at least two times during the on period of the low-side power transistor 12 in the second period p2 in the former switching period. In this way, the rising slope of the period detection current Isen in the second switching period can be made close to the rising slope of the real inductor current in the second switching period. Thus, the accuracy of inductor current detection can be improved.

As some implementations, the intensity of the constant current Isr in the second switching period is determined based on the intensity of the terminal voltage Vc1 of the first capacitor Cs1 for a duration in the first switching period. This duration belongs to the period during which the low-side power transistor 12 is turned on during the second period p2 of the first switching cycle. It should be appreciated that this duration includes at least two of the aforementioned moments.

In some embodiments, processing circuitry 120 is configured to perform the above-described operations in each of the multiple sets of switching cycles. Thus, the accuracy of inductor current detection can be further improved.

In other embodiments, the processing circuit 120 is configured to perform the above operation in each set of successive first switching cycles and second switching cycles, so that the accuracy of inductor current detection can be further improved.

In some embodiments, the processing circuit 120 is configured to determine the intensity of the constant current Isr in the second switching period from the slope of the intensity of the terminal voltage Vc1 of the first capacitor Cs1 that varies during at least two moments during the turn-on of the low-side power transistor 12 (i.e., the low-side voltage slope).

In this manner, the processing circuit 120 may autonomously determine the intensity of the constant current Isr in the second switching period such that the rising slope of the period detection current Isen in the second switching period is close to the rising slope of the real inductor current in the second switching period without relying on an external circuit.

As some implementations, the processing circuit 120 is configured to determine the strength of the constant current Isr in the second switching period from the low-side voltage slope, the input voltage VIN of the DC-DC converter, and the output voltage VOUT of the DC-DC converter.

The rising slope delta' IUG of the real inductor current during the turn-on of the high-side power transistor 11 is related to the input voltage VIN and the output voltage VOUT of the DC-DC converter. Specifically, the relationship between them can be expressed as formula (1): Δ IUG = (VIN-VOUT)/L, where L is the inductance value of the inductance L.

The falling slope Δ' ILG of the real inductor current during the on-time of the low side power transistor 12 is related to the output voltage VOUT of the DC-DC converter. Specifically, the relationship between them can be expressed as formula (2): ΔILG=VOUT/l.

It can be seen that the rising slope delta 'IUG of the real inductor current is related to both the falling slope delta' ILG and the input voltage VIN and the output voltage VOUT of the DC-DC converter.

In other words, it is desirable that the rising slope of the period detection current Isen in the second switching period is related to both the falling slope of the period detection current Isen in the first switching period and the input voltage VIN and the output voltage VOUT of the DC-DC converter.

In the above implementation, the processing circuit 120 determines the intensity of the constant current Isr in the second switching period according to the low-side voltage slope determining the falling slope of the period detection current Isen, the input voltage VIN and the output voltage VOUT of the DC-DC converter. Therefore, the rising slope of the period detection current Isen in the second switching period is more similar to the rising slope of the real inductor current in the second switching period, so that the accuracy of inductor current detection is further improved.

As some implementations, the strength of the constant current Isr in the second switching period is positively correlated with the product of the low-side voltage slope and the ratio of the terminal voltage Vc1 that varies at least two times during the turn-on of the low-side power transistor 12 in the first switching period. The ratio is the ratio between the difference between the input voltage VIN and the output voltage VOUT, i.e., (VIN-VOUT)/VOUT.

Based on the above-mentioned formulas (1) and (2) representing the relationship between the rising slope Δ 'IUG, the falling slope Δ' ILG, and the input voltage VIN and the output voltage VOUT of the DC-DC converter, the relationship between the rising slope Δ 'IUG and the falling slope Δ' ILG of the real inductor current is: Δ IUG =Δilg· (VIN-VOUT)/VOUT.

That is, in order to make the period detection current Isen closer to the true inductor current, the relationship between the high side voltage slope Δ 'VUG of the terminal voltage Vc1 of the first capacitor Cs1 in the first period p1 of the second switching period and the low side voltage slope Δ' VLG in the second period p2 of the first switching period should be: ΔVUG=ΔVLG· (VIN-VOUT)/VOUT.

It will be appreciated that Δvlg=Δvlg/Δt, where Δt may be a time difference between any two times (i.e., any two times of the above at least two times) during which the low-side power transistor is turned on in the second period p2 of the first switching cycle, and Δvlg may be a voltage difference between the terminal voltages Vc1 of the first capacitor Cs1 at these two times. For example, the two moments may be a start moment and an end moment of the turning on of the low-side power transistor in the second period p2 of the first switching cycle, in which case Δt is the duration of the turning on of the low-side power transistor in the first switching cycle.

In the above implementation, in the first period p1, the terminal voltage Vc1 of the first capacitor Cs1 is increased by the constant current Isr, which is a positive correlation of the product of the intensity and the low-side voltage slope Δ' VLG and the above ratio. This can make the high side voltage slope Δ 'VUG of the terminal voltage Vc1 of the first capacitor Cs1 in the second switching period equal to the product of the low side voltage slope Δ' VLG of the terminal voltage Vc1 in the first switching period and the above ratio, so that the rising slope of the period detection current Isen in the second switching period can be made closer to the rising slope of the real inductor current in the second switching period. Thus, the accuracy of inductor current detection can be further improved.

Some implementations of processing circuit 120 are described below in connection with fig. 3. Fig. 3 is a schematic diagram of a processing circuit according to some embodiments of the present disclosure.

In some embodiments, as shown in fig. 3, the processing circuit 120 includes a current-to-voltage conversion circuit 1210 and a first switch S1.

The current-voltage conversion circuit 1210 is configured to convert the low-side detection current Isen1 output from the first detection circuit 110 into a first voltage V1.

The first switch S1 is connected between the second end of the first capacitor Cs1, which is not grounded, and the current-voltage conversion circuit 1210. The first switch S1 is configured to be turned off for a first period p1 and turned on for a second period p 2. With the first switch S1 turned on, the first voltage V1 is transmitted to the first capacitor Cs1.

For example, referring to fig. 3, the first period p1 is a period in which the high-side power transistor 11 is turned on,And the second period p2 is a period in which the high-side power transistor 11 is turned off, the control signal of the first switch S1As opposed to the control signal dUG of the high-side power transistor 11.

Based on the current-voltage conversion circuit 1210 and the first switch S1, the processing circuit 120 may vary the terminal voltage Vc1 of the first capacitor Cs1 with the low-side detection current Isen1 in the second period p2 following the low-side detection current Isen 1.

As some implementations, the current-to-voltage conversion circuit 1210 includes a resistor Rs1, an operational amplifier OP1, and a transistor TR1 as shown in fig. 3.

One end of the resistor Rs1 is used for receiving the low-side detection current Isen1 output by the first detection circuit 110, and the other end is grounded.

The positive input of the operational amplifier OP1 is connected to one end of the resistor Rs1 for receiving the low side detection current Isen 1. The negative input terminal of the operational amplifier OP1 is connected to the first terminal of the transistor TR1. The output terminal of the operational amplifier OP1 is connected to the second terminal of the transistor TR1.

The third terminal of the transistor TR1 is connected to a power supply terminal. The first voltage V1 is output from the first terminal of the transistor TR1 and is transferred to the first capacitor Cs1 when the first switch S1 is turned on.

In this way, the operational amplifier OP1 and the transistor TR1 in the current-voltage conversion circuit 1210 are connected as a voltage buffer circuit between the resistor Rs1 and the first capacitor Cs1. In this way, the reliability of the first capacitor Cs1 can be improved while converting the low-side detection current Isen1 into the first voltage V1, thereby improving the reliability of the current detection circuit.

In some embodiments, as shown in fig. 3, the processing circuit 120 includes a sub-processing circuit 1220 and a second switch S2.

The sub-processing circuit 1220 is configured to provide a constant current Isr. The sub-processing circuit 1220 may include, for example, a variable current source for providing a constant current Isr.

The second switch S2 is connected between the sub-processing circuit 1220 and a second terminal of the first capacitor Cs1 that is not grounded. The second switch S2 is configured to be turned on for a first period p1 and turned off for a second period p 2. With the second switch S2 turned on, the constant current Isr supplied from the sub-processing circuit 1220 is supplied to the first capacitor Cs1 so that the terminal voltage Vc1 of the first capacitor Cs1 increases.

For example, referring to fig. 3, in the case where the first period p1 is a period in which the high-side power transistor 11 is turned on and the second period p2 is a period in which the high-side power transistor 11 is turned off, the control signal of the second switch S2 may be the control signal dUG of the high-side power transistor 11.

Based on the sub-processing circuit 1220 and the second switch S2, the processing circuit 120 may increase the terminal voltage Vc1 of the first capacitor Cs1 with the constant current Isr in the first period p 1.

In some embodiments, as shown in fig. 3, the processing circuit 120 further includes a first voltage to current conversion circuit 1230.

The first voltage-to-current conversion circuit 1230 is connected to a second terminal of the first capacitor Cs1 that is not grounded. The first voltage-current conversion circuit 1230 is configured to convert the period detection current Isen based on the terminal voltage Vc1 of the first capacitor Cs 1.

As some implementations, the first voltage-to-current conversion circuit 1230 includes an operational amplifier OP2, a transistor TR2, a resistor Rs2, and a current mirror MR1 as shown in fig. 3.

The positive input of the operational amplifier OP2 is connected to the second end of the first capacitor Cs1 which is not grounded. The negative input terminal of the operational amplifier OP2 is connected to the first terminal of the transistor TR 2. The output terminal of the operational amplifier OP2 is connected to the second terminal of the transistor TR 2.

The first terminal of the transistor TR2 is grounded via a resistor Rs 2. A third terminal of the transistor TR2 is connected to an input terminal of the current mirror MR1. The period detection current Isen is output from the output terminal of the current mirror MR1. The structure of the current mirror MR1 is not described in detail here.

As some implementations, the resistance Rs2 is the same as the resistance Rs 1. In this way, it is ensured that the period detection current Isen output by the processing circuit 120 during the on period of the low-side power transistor 12 is the same as the low-side detection current Isen1 output by the first detection circuit 110 during the on period of the low-side power transistor 12.

The processing circuit 120 shown in fig. 3 may increase the terminal voltage Vc1 of the first capacitor Cs1 with the constant current Isr in the first period p1, or may change the terminal voltage Vc1 of the first capacitor Cs1 with the low side detection current Isen1 in the second period p2 so as to follow the change of the low side detection current Isen1, so that the cycle detection current Isen with high accuracy may be output based on the terminal voltage Vc1 of the second terminal of the first capacitor Cs 1.

Some implementations of sub-processing circuits 1220 are described below in connection with fig. 4. Fig. 4 is a schematic diagram of sub-processing circuits according to some embodiments of the present disclosure.

In some embodiments, as shown in fig. 4, the sub-processing circuit 1220 includes a second period slope circuit 1221, the second period slope circuit 1221 including a second capacitor C2 having a first terminal connected to ground and a second terminal connected to no ground as shown in fig. 5.

The second period slope circuit 1221 is configured to control the terminal voltage of the second terminal of the second capacitor C2 to be maintained at the second voltage Vsl positively correlated with the low-side voltage slope Δ' VLG according to the first voltage V1 output from the current-voltage conversion circuit 1210. The first voltage V1 is positively correlated with the low side detection current Isen 1.

It can be understood that the first voltage V1 output by the current-voltage conversion circuit 1210 is substantially equal to the terminal voltage Vc1 of the first capacitor Cs1 during the period in which the low-side power transistor 12 is turned on in the second period p 2.

In these embodiments, the processing circuit 120 is configured to determine the strength of the constant current Isr in the second switching period from the second voltage Vsl, the input voltage VIN and the output voltage VOUT of the DC-DC converter, so that the strength of the constant current Isr in the second switching period can be determined from the low-side voltage slope Δ' VLG, the input voltage VIN and the output voltage VOUT.

In some embodiments, as shown in fig. 4, the sub-processing circuit 1220 further includes a duration circuit 1222 and a first period pseudo-current circuit 1223.

As shown in fig. 6, the duration circuit 1222 may include a comparator COMP. The positive input terminal of the comparator COMP receives a terminal voltage of a terminal of the capacitor Ck1 that is not grounded, which is positively correlated with the output voltage VOUT. The negative input terminal of the comparator COMP receives the second voltage Vsl. As such, the duration circuit 1222 is configured to determine the duration of the pulse in the output pulse signal Tsample according to the second voltage Vsl representing the low-side voltage slope, which is held by the second capacitor C2, and the output voltage VOUT of the DC-DC converter. The duration of the pulse in the pulse signal Tsample is positively correlated with the second voltage Vsl, but negatively correlated with the output voltage VOUT.

The second voltage Vsl is positively correlated with the low side voltage slope, and the duration of the pulse in the pulse signal Tsample is positively correlated with the ratio of the second voltage Vsl to the output voltage VOUT (i.e., vsl/VOUT). In this case, the duration of the pulse is positively correlated with the ratio of the low side voltage slope to the output voltage VOUT (i.e., Δvlg/VOUT).

As shown in fig. 7, the first period pseudo-current circuit 1223 includes a third capacitor Ck2 and a fourth capacitor C4, the third capacitor Ck2 having a first end grounded and a second end ungrounded, and the fourth capacitor C4 having a first end grounded and a second end ungrounded.

The first period pseudo-current circuit 1223 is configured to control the fifth switch S5 to be turned on during a pulse duration in the pulse signal Tsample to increase the terminal voltage of the second terminal of the third capacitor Ck2 with the first current Idiff. Here, the first current Idiff is positively correlated with the difference between the input voltage VIN and the output voltage VOUT of the DC-DC converter.

The first period pseudo-current circuit 1223 is further configured to sample the terminal voltage of the third capacitor Ck2 at the end of the pulse signal Tsample, so that the terminal voltage of the second terminal of the fourth capacitor C4, which is not grounded, is maintained at the sampled fourth voltage Vsh, and to convert the constant current Isr in the second switching period based on the terminal voltage of the fourth capacitor C4 (i.e., the fourth voltage Vsh).

During the pulse duration, the first period pseudo-current circuit 1223 increases the terminal voltage of the second terminal of the third capacitor Ck2 with the first current Idiff. In this way, the terminal voltage of the third capacitor Ck2 at the end of the pulse (i.e., the fourth voltage Vsh) is positively correlated with the duration of the pulse and with the first current Idiff.

As described above, the pulse duration is positively correlated with the ratio of the low side voltage slope Δ 'VLG to the output voltage VOUT (i.e., Δ' VLG/VOUT), and the first current Idiff is positively correlated with the difference between the input voltage VIN and the output voltage VOUT. In this case, the fourth voltage Vsh is positively correlated with the ratio of the low-side voltage slope Δ 'VLG and the output voltage VOUT (i.e., Δ' VLG/VOUT), and is positively correlated with the difference between the input voltage VIN and the output voltage VOUT.

The sub-processing circuit 1220 converts the constant current Isr in the second switching period based on the fourth voltage Vsh. In this way, the constant current Isr in the second switching period can be positively correlated to the ratio of the low-side voltage slope Δ 'VLG to the output voltage VOUT (i.e., Δ' VLG/VOUT) and to the difference between the input voltage VIN and the output voltage VOUT.

In other words, the sub-processing circuit 1220 shown in fig. 4 can positively correlate the intensity of the constant current Isr in the second switching period with the product of the low-side voltage slope Δ' VLG and the ratio (VIN-VOUT)/VOUT, so that the rising slope of the period detection current Isen in the second switching period is closer to the rising slope of the real inductor current in the second switching period, and the accuracy of the inductor current detection can be further improved.

Some implementations of the second period slope circuit 1221 in the sub-processing circuit 1220 are described below in connection with fig. 5. Fig. 5 is a schematic diagram of a second period slope circuit according to some embodiments of the present disclosure.

As shown in fig. 5, the second period slope circuit 1221 includes a differentiating circuit 12211.

The differentiating circuit 12211 is configured to output a third voltage Vsl 'positively correlated with a low-side voltage slope Δ' VLG of the first voltage V1 output from the current-voltage converting circuit 1210 that varies at least two times during the on period of the low-side power transistor 12 in the first switching period.

In some embodiments, referring to fig. 5, the differentiating circuit 12211 includes a differentiator D1, a current mirror MR2, and a resistor Rs3. The differentiator D1 includes a capacitor Cs2, an operational amplifier OP3, a transistor TR3, and a resistor R3.

One end of the capacitor Cs2 is connected to the negative input terminal of the operational amplifier OP3, and the other end of the capacitor Cs2 is connected to the output terminal of the current-voltage conversion circuit 1210 to acquire the first voltage V1, thereby enabling the differentiator D1 to differentiate the first voltage V1 to obtain the third voltage Vsl'.

The positive input of the operational amplifier OP3 is for receiving the reference voltage Vbias. The negative input terminal of the operational amplifier OP3 is connected to the first terminal of the transistor TR3 via a resistor R3. The output terminal of the operational amplifier OP3 is connected to the second terminal of the transistor TR 3. A third terminal of the transistor TR3 is connected to an input terminal of the current mirror MR 2. The structure of the current mirror MR2 is not described in detail here.

In this way, the current Islope output by the current mirror MR2 is positively correlated with the low-side voltage slope Δ' VLG at which the terminal voltage Vc1 of the first capacitor Cs1 varies at least two times during the on period of the low-side power transistor 12.

The output terminal of the current mirror MR2 is connected to one terminal of the resistor Rs3, and the other terminal of the resistor Rs3 is grounded. In this case, the third voltage Vsl' at the output of the current mirror MR2 is positively correlated with the low-side voltage slope Δvlg. That is, the differentiating circuit 12211 may output the third voltage Vsl' positively correlated with the low-side voltage slope at which the terminal voltage Vc1 of the first capacitor Cs1 varies at least two times during the on period of the low-side power transistor 12.

Specifically, in the configuration shown in fig. 5, the current islope=Δ' vlg·cs2 output by the current mirror MR2, where Cs2 is the capacitance value of the capacitor Cs 2. In this case, the third voltage Vsl' may be calculated using the following formula (3):

Vsl′＝Islope·rs3＝Δ′VLG·cs2·rs3 (3)

wherein Rs3 is the resistance of the resistor Rs3.

In some embodiments, the capacitance value Cs2 of the capacitor Cs2 is equal to the capacitance value Cs1 of the first capacitor Cs 1.

As shown in fig. 5, the second period slope circuit 1221 further includes a third switch S3.

The third switch S3 is connected between the differentiating circuit 12211 and the second terminal of the second capacitor C2, which is not grounded. The third switch S3 is configured to be turned off for the first period p1 and turned on for the second period p 2.

With the third switch S3 turned on, the third voltage Vsl ' positively correlated with the low-side voltage slope Δ ' VLG is transferred to the second capacitor C2 such that the terminal voltage of the second terminal of the second capacitor C2, which is not grounded, is maintained at the second voltage Vsl positively correlated with the low-side voltage slope Δ ' VLG.

For example, in an ideal state, the second voltage Vsl is equal to the third voltage Vsl'. In this case, the following formula (4) can be obtained according to the above formula (3): vsl=Δ' vlg·cs2·rs3.

For example, referring to fig. 5, in the case where the first period p1 is a period in which the high-side power transistor 11 is turned on, and the second period p2 is a period in which the high-side power transistor 11 is turned off, the control signal of the third switch S3 As opposed to the control signal dUG of the high-side power transistor 11.

In the above embodiment, the differentiating circuit 12211 may output the third voltage Vsl 'positively correlated with the low-side voltage slope Δ' VLG and transmit the third voltage Vsl 'to the second capacitor C2 through the third switch S3, thereby maintaining the terminal voltage of the second capacitor C2 at the second voltage Vsl positively correlated with the low-side voltage slope Δ' VLG.

As some implementations, as shown in fig. 5, the differentiating circuit 12211 further includes an operational amplifier OP4 and a transistor TR4.

The positive input terminal of the operational amplifier OP4 is connected to the output terminal of the current mirror MR2, the negative input terminal of the operational amplifier OP4 is connected to the first terminal of the transistor TR4, and the output terminal of the operational amplifier OP4 is connected to the second terminal of the transistor TR4. The third terminal of the transistor TR4 is connected to a power supply terminal. A third voltage Vsl' positively correlated with the low side voltage slope Δvlg may be output from the first terminal of the transistor TR4.

In these implementations, the operational amplifier OP4 and the transistor TR4 may be connected as a voltage buffer circuit between the resistor Rs3 and the second capacitor C2, so that the reliability of the second capacitor C2 may be improved, and thus the reliability of the current detection circuit may be improved.

Some implementations of the duration circuit 1222 in the sub-processing circuit 1220 are described below in connection with fig. 6. Fig. 6 is a schematic diagram of a time duration circuit according to some embodiments of the present disclosure.

As shown in fig. 6, the time period circuit 1222 includes a second voltage-to-current conversion circuit 12221, the second voltage-to-current conversion circuit 12221 being configured to convert the output voltage VOUT of the DC-DC converter into a second current Ivout.

As some implementations, the second voltage-to-current conversion circuit 12221 includes an operational amplifier OP5, a transistor TR5, a current mirror MR3, and a resistor Rs4 as shown in fig. 6.

The positive input of the operational amplifier OP5 is used for receiving the output voltage VOUT of the DC-DC converter. The negative input terminal of the operational amplifier OP5 is connected to the first terminal of the transistor TR 5.

The first terminal of the transistor TR5 is grounded via a resistor Rs4. A second terminal of the transistor TR5 is connected to an output terminal of the operational amplifier OP 5. A third terminal of the transistor TR5 is connected to an input terminal of the current mirror MR 3. The second current Ivout is output from the output terminal of the current mirror MR 3. The structure of the current mirror MR3 is not described in detail here.

In the configuration shown in fig. 6, the second current ivout=vout/Rs 4, where Rs4 is the resistance of the resistor Rs4.

The duration circuit 1222 also includes a fifth capacitor Ck1 and a fourth switch S4 as shown in fig. 6.

The first terminal of the fifth capacitor Ck1 is grounded, and the second terminal is connected to the second voltage-current conversion circuit 12221. For example, referring to fig. 6, the second terminal of the fifth capacitor Ck1 is connected to the output terminal of the current mirror MR 3.

One end of the fourth switch S4 is connected to an intermediate node between the second voltage-current conversion circuit 12221 and the fifth capacitor Ck1, and the other end of the fourth switch S4 is grounded.

The fourth switch S4 is configured to start turning on the first discharge period from the end of sampling the terminal voltage of the third capacitor Ck2 by the first period pseudo-current circuit 1223.

When the fourth switch S4 is turned off, the second current Ivout output from the second voltage-current conversion circuit 12221 charges the fifth capacitor Ck1, and the terminal voltage of the second terminal of the fifth capacitor Ck1 that is not grounded increases.

When the fourth switch S4 is turned on, the fifth capacitor Ck1 is discharged, and the second current Ivout output by the second voltage-current conversion circuit 12221 does not charge the fifth capacitor Ck 1. When the fourth switch S4 is turned on for the first discharge period, the terminal voltage of the fifth capacitor Ck1 drops to 0.

The duration circuit 1222 also includes a pulse generation circuit 12222, as shown in fig. 6. The pulse generating circuit 12222 is configured to output a pulse in the pulse signal Tsample during a period in which the terminal voltage of the second terminal of the fifth capacitor Ck1 increases from 0 to the second voltage Vsl.

In other words, the pulse duration in the pulse signal Tsample is the duration required to charge the fifth capacitor Ck1 with the second current Ivout such that the terminal voltage of the fifth capacitor Ck1 increases from 0 to the second voltage Vsl representing the low-side voltage slope.

In the structure shown in fig. 6, the pulse duration Ts in the pulse signal Tsample can be calculated by the following equation (5):

where Ck1 is the capacitance value of the fifth capacitor Ck 1.

As can be seen from the above equation (5), the pulse duration Ts is positively correlated with the ratio of the second voltage Vsl to the output voltage VOUT (i.e., vsl/VOUT). The second voltage Vsl is positively correlated with the low-side voltage slope Δ ' VLG, i.e., the pulse duration Ts is positively correlated with the ratio of the low-side voltage slope Δ ' VLG to the output voltage VOUT (i.e., Δ ' VLG/VOUT).

As some implementations, the pulse generating circuit 12222 includes a comparator COMP AND an AND circuit AND as shown in fig. 6.

The positive input terminal of the comparator COMP is connected to the second terminal of the fifth capacitor Ck1, which is not grounded, so as to obtain the terminal voltage of the second terminal of the fifth capacitor Ck 1. The negative input terminal of the comparator COMP is for receiving the second voltage Vsl. The output of comparator COMP sums withThe first input of the gate AND is connected. A second input terminal of AND gate circuit for receiving signal Signal->May be logically opposite to the control signal dRS of the fourth switch S4. The control signal dRS of the fourth switch S4 will be described later.

In this way, the pulse generating circuit 12222 may output the pulse in the pulse signal Tsample during the period in which the terminal voltage of the second terminal of the fifth capacitor Ck1 increases from 0 to the second voltage Vsl, so that the pulse duration Ts is positively correlated with the "ratio of the low-side voltage slope Δvlg and the output voltage VOUT".

Some implementations of the first period pseudo-current circuit 1223 in the sub-processing circuit 1220 are described below in connection with fig. 7. Fig. 7 is a schematic diagram of a first period pseudo-current circuit according to some embodiments of the present disclosure.

As shown in fig. 7, the first period pseudo-current circuit 1223 includes a subtractor 12231. The subtractor 12231 is configured to output a fifth voltage V5 positively correlated with a difference between the input voltage VIN and the output voltage VOUT of the DC-DC converter.

As some implementations, subtractor 12231 includes an operational amplifier OP6, a transistor TR6, and 4 resistors RxNa, rx1a, rxNb, and Rx1b as shown in fig. 7.

One end of the resistor RxNa is used for receiving the input voltage VIN of the DC-DC converter, and the other end is connected with the positive input terminal of the operational amplifier OP 6. One end of the resistor Rx1a is connected with the positive input end of the operational amplifier OP6, and the other end is grounded.

One end of the resistor RxNb is used for receiving the output voltage VOUT of the DC-DC converter, and the other end is connected to the negative input terminal of the operational amplifier OP 6. One end of the resistor Rx1b is connected to the negative input terminal of the operational amplifier OP6, and the other end is connected to the first end of the transistor TR 6.

A second terminal of the transistor TR6 is connected to an output terminal of the operational amplifier OP6, and a third terminal of the transistor TR6 is connected to a power supply terminal.

The resistance of the resistor RxNa may be N times the resistance of the resistor Rx1a, the resistance of the resistor RxNb may be N times the resistance of the resistor Rx1b, and the resistance of the resistor RxNa is equal to the resistance of the resistor RxNb. N may be an integer greater than or equal to 2.

In this case, the fifth voltage v5= (VIN-VOUT)/N output by the subtractor 12231. For example, in the case where n=10, the fifth voltage v5= (VIN-VOUT)/10.

In these implementations, the fifth voltage V5 output by the subtractor 12231 is positively correlated with and less than the difference between the input voltage VIN and the output voltage VOUT. In this way, the reliability of the circuit element that receives the fifth voltage V5 in the circuit can be improved, and the reliability of the current detection circuit can be improved.

As shown in fig. 7, the first period pseudo-current circuit 1223 further includes a third voltage-current conversion circuit 12232, a fifth switch S5, and a sixth switch S6.

The third voltage-current conversion circuit 12232 is configured to convert the first current Idiff based on the fifth voltage V5. In other words, the first current Idiff is positively correlated with the difference between the input voltage VIN and the output voltage VOUT.

As some implementations, the third voltage-to-current conversion circuit 12232 includes the operational amplifier OP7, the transistor TR7, the resistor Rs5, and the current mirror MR4 shown in fig. 7.

The positive input of the operational amplifier OP7 is connected to the output of the subtractor 12231 (e.g., the first terminal of the transistor TR6 shown in fig. 7). The negative input terminal of the operational amplifier OP7 is connected to the first terminal of the transistor TR7, and the output terminal of the operational amplifier OP7 is connected to the second terminal of the transistor TR 7.

A first terminal of the transistor TR7 is grounded via a resistor Rs5, and a third terminal of the transistor TR7 is connected to an input terminal of the current mirror MR4. The first current Idiff is output from the output terminal of the current mirror MR4. The structure of the current mirror MR4 is not described in detail here.

In the configuration shown in fig. 7, the first current Idiff can be calculated by the following formula (6):

wherein Rs5 is the resistance of the resistor Rs 5.

The fifth switch S5 is connected between the third voltage-current conversion circuit 12232 and the second terminal of the third capacitor Ck 2. The fifth switch S5 is configured to conduct for the duration of the pulse. For example, referring to fig. 7, the control signal of the fifth switch S5 may be a pulse signal Tsample output from the pulse generating circuit 12222.

One end of the sixth switch S6 is connected to an intermediate node between the fifth switch S5 and the third capacitor Ck2, and the other end of the sixth switch S6 is grounded. The sixth switch S6 is configured to start turning on the second discharge period from the end of sampling by the sample-and-hold circuit 12233.

In other words, during the pulse duration, the fifth switch S5 is on and the sixth switch S6 is off. In this case, the first current Idiff charges the third capacitor Ck2, thereby increasing the terminal voltage of the second terminal of the third capacitor Ck2, which is not grounded.

At the end of the pulse, the fifth switch S5 is opened and the first current Idiff is no longer transferred to the third capacitor Ck2. The sixth switch S6 starts to turn on for the second discharge period so that the terminal voltage of the third capacitor Ck2 drops. At the end of the second discharge period, the terminal voltage of the third capacitor Ck2 drops to 0.

In this way, the first period pseudo-current circuit 1223 may increase the terminal voltage at the second terminal of the third capacitor Ck2 from 0 with the first current Idiff positively correlated with the difference between the input voltage VIN and the output voltage VOUT during the pulse duration in the pulse signal Tsample.

As shown in fig. 7, the first period pseudo-current circuit 1223 further includes a sample-and-hold circuit 12233 and a fourth voltage-to-current conversion circuit 12234.

The sample-and-hold circuit 12233 includes a fourth capacitor C4 having a first terminal grounded and a second terminal ungrounded, and the sample-and-hold circuit 12233 is configured to sample the terminal voltage of the third capacitor Ck2 at the end of the pulse signal Tsample so that the terminal voltage of the fourth capacitor C4 is held at the fourth voltage Vsh.

As some implementations, the sample-and-hold circuit 12233 includes an operational amplifier OP8, a transistor TR8, and a seventh switch S7 as shown in fig. 7.

The positive input terminal of the operational amplifier OP8 is connected to the second terminal of the third capacitor Ck2, which is not grounded. The negative input terminal of the operational amplifier OP8 is connected to the first terminal of the transistor TR 8. The output terminal of the operational amplifier OP8 is connected to the second terminal of the transistor TR 8. A third terminal of the transistor TR8 is connected to a power supply terminal.

The seventh switch S7 is connected between the first terminal of the transistor TR8 and the second terminal of the fourth capacitor C4, which is not grounded. The seventh switch S7 may be configured to be turned on for a sampling time from the end of the pulse, for example, so that the terminal voltage of the second terminal of the fourth capacitor C4 is maintained at the fourth voltage Vsh. The sampling time may be, for example, a time required for the terminal voltage of the fourth capacitor C4 to become equal to the terminal voltage of the third capacitor Ck2 at the end of the pulse after the seventh switch S7 is turned on.

The fourth voltage-current conversion circuit 12234 is configured to convert to a constant current Isr in the second switching period based on the terminal voltage of the fourth capacitor C4.

As some implementations, the fourth voltage-to-current conversion circuit 12234 includes an operational amplifier OP9, a transistor TR9, a current mirror MR5, and a resistor Rs6 as shown in fig. 7.

The positive input terminal of the operational amplifier OP9 is connected to the second terminal of the fourth capacitor C4, which is not grounded. The negative input terminal of the operational amplifier OP9 is connected to the first terminal of the transistor TR 9. The output terminal of the operational amplifier OP9 is connected to the second terminal of the transistor TR 9.

The first terminal of the transistor TR9 is grounded via a resistor Rs6. A third terminal of the transistor TR9 is connected to an input terminal of the current mirror MR 5. A constant current Isr may flow from the output of the current mirror MR 5. The structure of the current mirror MR5 is not described in detail here.

The current mirror MR5 may be, for example, 1: a current mirror for the N output. In this case, the constant current Isr can be calculated based on the following formula (7): isr=n·vsh/Rs6, where Rs6 is the resistance value of the resistor Rs6.

During the pulse duration, the third capacitor Ck2 with an initial terminal voltage of 0 is charged with the first current drift. In this case, the terminal voltage of the third capacitor Ck2 at the end of the pulse is denoted by Vch.

With the configuration shown in fig. 7, the terminal voltage vch=idiff·ts/Ck2 of the third capacitor Ck2 at the end of the pulse, and the following equation (8) can be obtained by substituting the above equations (5) and (6) into this equation:

where Ck2 is the capacitance value of the third capacitor Ck2.

The terminal voltage of the fourth capacitor C4 holds the fourth voltage vsh=vch. In this case, the following formula (9) can be obtained by combining the above formulas (7) and (8):

as in the above mentioned equation (4), the second voltage Vsl is positively correlated with the low side voltage slope Δ' VLG. As can be seen by combining the above formulas (4) and (9), the first period pseudo-current circuit 1223 shown in fig. 7 can output a constant current Isr whose intensity is positively correlated with the product of the low-side voltage slopes Δ' VLG and (VIN-VOUT)/VOUT in the second switching period, so that the rising slope of the period detection current Isen in the second switching period can be made closer to the rising slope of the real inductor current in the second switching period.

Specifically, the above formula (4) is substituted into the above calculation formula (9) of the constant current Isr, so that the calculation formula (10) of the constant current Isr can be obtained:

in some embodiments, r3·r4=r5·r6, and ck 1=ck 2. For example, rs 3=rs 4=rs 5=rs 6, and the resistance values of the resistors Rs1 and Rs2 are also equal to Rs3. In this case, the formula (11) for calculating the constant current can be obtained by combining the above formula (10): isr=Δ' vlg·cs2· (VIN-VOUT)/VOUT. The capacitance value Cs2 of the capacitor Cs2 is equal to the capacitance value Cs1 of the first capacitor Cs 1.

In the first period p1 of the second switching period, the terminal voltage Vc1 of the first capacitor Cs1 is increased by the constant current Isr shown in the above formula (11). In this case, the high-side voltage slope Δvug=Δvlg· (VIN-VOUT)/VOUT of the terminal voltage Vc1 of the first capacitor Cs1 coincides with the relationship between the rising slope Δ IUG and the falling slope Δilg of the true inductor current.

In other words, with the circuits shown in fig. 5 to 7, the rising slope of the period detection current Isen in the second switching period can be made to coincide with the rising slope of the true inductor current, so that the accuracy of inductor current detection can be further improved.

The operation modes of the fourth switch S4 shown in fig. 6, the sixth switch S6 shown in fig. 7, and the seventh switch S7 will be described below with reference to fig. 8. Fig. 8 is a signal waveform diagram according to further embodiments of the present disclosure.

Fig. 8 shows the pulse signal Tsample and the control signal dSH of the seventh switch S7. In addition, fig. 8 also shows control signals dRS of the fourth switch S4 and the sixth switch S6.

As shown in fig. 8, during any one pulse duration of the pulse signal Tsample, the fifth switch S5 is turned on, but the fourth switch S4, the sixth switch S6, and the seventh switch S7 are all turned off. In this case, the second current Ivout increases the terminal voltage of the fifth capacitor Ck1, and the first current Idiff increases the terminal voltage of the third capacitor Ck 2.

At the end of the pulse, the fifth switch S5 is turned off, and the terminal voltage of the third capacitor Ck2 is held at Vch. At this time, the seventh switch S7 starts to turn on for the sampling time Tsh under the control of the control signal dSH.

At the end of the sampling time Tsh, the seventh switch S7 is turned off so that the terminal voltage of the fourth capacitor C4 is maintained at the fourth voltage Vsh equal to Vch. At this time, under the control of the control signal dRS, the fourth switch S4 starts to turn on for the first discharge period so that the terminal voltage of the second terminal of the fifth capacitor Ck1 that is not grounded falls, and the sixth switch S6 starts to turn on for the second discharge period so that the terminal voltage of the second terminal of the third capacitor Ck2 that is not grounded starts to fall.

In this way, before the second period p2 of the preceding switching cycle of the next group of switching cycles starts, the terminal voltages at the non-grounded ends of the fifth capacitor Ck1 and the third capacitor Ck2 are reset to 0. When the second period p2 of the previous switching period of the next group of switching periods starts, the duration of the pulse duration in the timing pulse signal Tsample is restarted to reacquire the terminal voltage Vch of the third capacitor Ck2 at the end of the pulse.

Fig. 8 schematically illustrates that both the first discharge duration and the second discharge duration are equal to Tds, but the embodiment of the present disclosure is not limited thereto. For example, the first discharge duration may be greater than the second discharge duration. For another example, the first discharge duration may be less than the second discharge duration.

At the end of the first discharge period, the fourth switch S4 is turned off, and the terminal voltage of the fifth capacitor Ck1 drops to 0. At the end of the second discharge period, the sixth switch S6 is turned off, and the terminal voltage of the third capacitor Ck2 drops to 0.

Thereafter, the seventh switch S7, the fourth switch S4 and the sixth switch S6 remain turned off until the end of the next pulse. The subsequent processes are similar to the previous ones and will not be repeated here.

It should be understood that the above embodiments are described by taking an example in which the switch/transistor is turned on when the control signal is at a high level and turned off when the control signal is at a low level, but the embodiments of the present disclosure are not limited thereto.

The DC-DC converter comprises a high side power transistor 11 and a low side power transistor 12 connected in series between an input terminal and a ground terminal. The switching node SW between the high-side power transistor 11 and the low-side power transistor 12 is connected to the inductance L.

In each of at least one set of switching cycles of the DC-DC converter, the current detection method comprises steps 902-908 as shown in fig. 9.

In step 902, during the on period of the low-side power transistor 12, the current provided by the low-side power transistor 12 to the inductor L is detected to obtain a low-side detection current Isen1.

In step 904, the terminal voltage Vc1 of the first capacitor Cs1 is increased with the constant current Isr in the first period p 1. The first period p1 is one of a period in which the high-side power transistor 11 is on and a period in which the low-side power transistor 12 is off.

In step 906, in the second period p2, the terminal voltage Vc1 of the first capacitor Cs1 is changed with the low side detection current Isen1 following the change in the low side detection current Isen 1. Here, the second period p2 and the first period p1 constitute one switching cycle of the DC-DC converter.

In step 908, the period detection current Isen is output based on the terminal voltage Vc1 of the second terminal of the first capacitor Cs1 whose first terminal is grounded.

It should be appreciated that step 902 is performed during the execution of step 904. Step 904 and step 906 are performed sequentially. Step 908 is performed throughout the switching cycle of the DC-DC converter.

Here, each set of switching cycles includes a first switching cycle and a second switching cycle, which are consecutive in succession, of the DC-DC converter.

In each set of switching periods, the intensity of the constant current Isr in the second switching period is determined based on the intensity of the terminal voltage Vc1 of the first capacitor Cs1 at least two times in the first switching period, both of which belong to the period during which the low-side power transistor 12 is turned on in the second period p2 of the first switching period.

By performing the current detection method shown in fig. 9, the accuracy of inductor current detection can be improved.

In some embodiments, the intensity of the constant current Isr in the second switching period is determined based on the intensity of the terminal voltage Vc1 of the first capacitor Cs1 for a duration in the first switching period. This duration belongs to the period during which the low-side power transistor 12 is turned on during the second period p2 of the first switching cycle.

In some embodiments, the intensity of the constant current Isr in the second switching period may also be determined according to a low-side voltage slope in which the intensity of the terminal voltage Vc1 of the first capacitor Cs1 varies in at least two times.

As some implementations, the strength of the constant current Isr in the second switching period may be determined from the low-side voltage slope, the input voltage VIN of the DC-DC converter, and the output voltage VOUT of the DC-DC converter.

As some implementations, the magnitude of the constant current Isr in the second switching period is positively correlated with the product of the low-side voltage slope and (VIN-VOUT)/VOUT.

The current detection method shown in fig. 9 may be performed by the current detection circuit of the DC-DC converter according to any of the above embodiments, and the related embodiments of the method may be referred to the foregoing description of the current detection circuit, which is not repeated herein.

The embodiment of the disclosure also provides a power conversion system, including the current detection circuit of the DC-DC converter and the DC-DC converter of any one of the embodiments.

The embodiment of the disclosure also provides a power supply, which comprises the power conversion system of any one embodiment. The power supply may be, for example, a power supply of an electronic device such as a mobile phone or a computer.

Thus, various embodiments of the present disclosure have been described in detail. In order to avoid obscuring the concepts of the present disclosure, some details known in the art are not described. How to implement the solutions disclosed herein will be fully apparent to those skilled in the art from the above description.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. It will be understood by those skilled in the art that the foregoing embodiments may be modified and equivalents substituted for elements thereof without departing from the scope and spirit of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A current detection circuit of a DC-DC converter comprising a high-side power transistor (11) and a low-side power transistor (12) connected in series between an input terminal and a ground terminal, a switching node (SW) between the high-side power transistor (11) and the low-side power transistor (12) being connected with an inductance (L);

The current detection circuit includes:

a first detection circuit (110) configured to detect a current supplied to the inductor (L) by the low-side power transistor (12) during an on period of the low-side power transistor (12) to output a low-side detection current (Isen 1); and

a processing circuit (120) comprising a first capacitor (Cs 1) with a first terminal connected to ground, the processing circuit (120) being configured to perform operations in each of at least one set of switching cycles, the operations comprising:

a period detection current (Isen) is outputted based on a terminal voltage (Vc 1) of a second terminal of the first capacitor (Cs 1),

in a first period (p 1), a terminal voltage (Vc 1) of the first capacitor (Cs 1) is increased by a constant current (Isr), the first period (p 1) is one of a period in which the high-side power transistor (11) is turned on and a period in which the low-side power transistor (12) is turned off,

in a second period (p 2), the terminal voltage (Vc 1) of the first capacitor (Cs 1) is changed along with the change of the low-side detection current (Isen 1) by using the low-side detection current (Isen 1), the second period (p 2) and the first period (p 1) form one switching cycle of the DC-DC converter,

wherein each group of switching periods comprises a first switching period and a second switching period which are sequentially continuous in the DC-DC converter, and

In each set of switching cycles, the intensity of the constant current (Isr) in the second switching cycle is determined based on the intensity of the terminal voltage (Vc 1) of the first capacitor (Cs 1) in at least two moments in the first switching cycle, the at least two moments belonging to a period during which the low-side power transistor (12) is turned on within a second period (p 2) of the first switching cycle.

2. The current detection circuit according to claim 1, wherein the intensity of the constant current (Isr) in the second switching period is determined based on the intensity of the terminal voltage (Vc 1) of the first capacitor (Cs 1) in a duration in the first switching period, the duration belonging to a period during which the low-side power transistor (12) is turned on in the second period (p 2) of the first switching period.

3. The current detection circuit according to claim 1, wherein the first period (p 1) is a period in which the high-side power transistor (11) is on.

4. A current detection circuit according to any of claims 1-3, wherein the processing circuit (120) is configured to:

the intensity of the constant current (Isr) in the second switching period is determined according to a low-side voltage slope in which the intensity of the terminal voltage (Vc 1) of the first capacitor (Cs 1) varies in the at least two moments.

5. The current detection circuit of claim 4, wherein the processing circuit (120) is configured to:

the strength of the constant current (Isr) in the second switching period is determined according to the low side voltage slope, the input Voltage (VIN) of the DC-DC converter and the output Voltage (VOUT) of the DC-DC converter.

6. The current detection circuit of claim 5, wherein the strength of the constant current (Isr) in the second switching period is positively correlated with a product of the low-side voltage slope and a ratio between a difference between the input Voltage (VIN) and the output Voltage (VOUT).

7. The current detection circuit of claim 4, wherein the processing circuit (120) comprises:

a current-voltage conversion circuit (1210) configured to convert the low-side detection current (Isen 1) output from the first detection circuit (110) into a first voltage (V1);

a first switch (S1) connected between a second end of the first capacitor (Cs 1) and the current-voltage conversion circuit (1210), and configured to be turned off for a first period (p 1) and turned on for a second period (p 2); and

-a sub-processing circuit (1220) configured to provide said constant current (Isr);

A second switch (S2) connected between the sub-processing circuit (1220) and the second end of the first capacitor (Cs 1) and configured to be turned on for a first period (p 1) and turned off for a second period (p 2).

8. The current detection circuit of claim 7, wherein the sub-processing circuit (1220) comprises:

a second period slope circuit (1221) including a second capacitor (C2) having a first terminal connected to ground and configured to control a terminal voltage of a second terminal of the second capacitor (C2) to be maintained at a second voltage (Vsl) positively correlated with the low-side voltage slope in accordance with the first voltage (V1);

wherein the processing circuit (120) is configured to determine the intensity of the constant current (Isr) in the second switching period from the second voltage (Vsl), the input Voltage (VIN) and the output Voltage (VOUT).

9. The current detection circuit of claim 8, wherein the second period slope circuit (1221) comprises:

-a differentiating circuit (12211) configured to output a third voltage (Vsl') positively correlated to the low-side voltage slope of the first voltage (V1) variation;

a third switch (S3) connected between the differentiating circuit (12211) and the second end of the second capacitor (C2) and configured to be turned off for a first period (p 1) and turned on for a second period (p 2).

10. The current detection circuit of claim 7, wherein the sub-processing circuit (1220) further comprises:

-a duration circuit (1222) configured to output a pulse signal (Tsample) according to the second voltage (Vsl) and the output Voltage (VOUT), the duration of the pulse in the pulse signal (Tsample) being positively correlated with the ratio of the second voltage (Vsl) and the output Voltage (VOUT);

-a first period pseudo-current circuit (1223) comprising a third capacitor (Ck 2) and a fourth capacitor (C4) connected to a first ground and configured to increase a terminal voltage at a second terminal of the third capacitor (Ck 2) with a first current (aliff) during a pulse duration in the pulse signal (Tsample), the first current (aliff) being positively correlated with a difference between the input Voltage (VIN) and the output Voltage (VOUT); sampling the terminal voltage of the third capacitor (Ck 2) at the end of the pulse so that the terminal voltage of the second terminal of the fourth capacitor (C4) is maintained at the sampled fourth voltage (Vsh); -deriving the constant current (Isr) in the second switching period based on a terminal voltage conversion of the fourth capacitor (C4).

11. The current detection circuit of claim 10, wherein the duration circuit (1222) comprises:

A second voltage-to-current conversion circuit (12221) configured to convert the output Voltage (VOUT) into a second current (Ivout);

a fifth capacitor (Ck 1) having a first terminal grounded and a second terminal connected to the second voltage-to-current conversion circuit (12221);

a pulse generating circuit (12222) configured to output pulses in the pulse signal (Tsample) during an increase of a terminal voltage of the second terminal of the fifth capacitor (Ck 1) from 0 to the second voltage (Vsl); and

a fourth switch (S4) having one end connected to an intermediate node between the second voltage-to-current conversion circuit (12221) and the fifth capacitor (Ck 1) and the other end grounded, the fourth switch (S4) being configured to start turning on a first discharge period from the end of the sampling.

12. The current detection circuit of claim 10, wherein the first period pseudo-current circuit (1223) comprises:

a subtractor (12231) configured to output a fifth voltage (V5) positively correlated with a difference between the input Voltage (VIN) and the output Voltage (VOUT);

a third voltage-current conversion circuit (12232) configured to obtain the first current (Idiff) based on the conversion of the fifth voltage (V5);

a fifth switch (S5) connected between the third voltage-to-current conversion circuit (12232) and the second terminal of the third capacitor (Ck 2) and configured to be turned on during the pulse duration;

-a sample-and-hold circuit (12233) comprising the fourth capacitor (C4) and configured to sample the terminal voltage of the third capacitor (Ck 2) at the end of the pulse, such that the terminal voltage of the fourth capacitor (C4) is held at the fourth voltage (Vsh);

a sixth switch (S6) having one end connected to an intermediate node between the fifth switch (S5) and the third capacitor (Ck 2) and the other end grounded, the sixth switch (S6) being configured to start turning on a second discharge period from the end of sampling by the sample-and-hold circuit (12233);

a fourth voltage-to-current conversion circuit (12234) configured to convert the constant current (Isr) in the second switching period based on a terminal voltage of the fourth capacitor (C4).

13. The current detection circuit of claim 4, wherein the processing circuit (120) comprises:

a first voltage-current conversion circuit (1230), connected to the second terminal of the first capacitor (Cs 1), configured to convert the period detection current (Isen) based on the terminal voltage (Vc 1) of the first capacitor (Cs 1).

14. The current detection circuit of claim 1, wherein the processing circuit (120) is configured to perform the operation in each of a plurality of sets of switching cycles.

15. A current detection method of a DC-DC converter comprising a high-side power transistor (11) and a low-side power transistor (12) connected in series between an input terminal and a ground terminal, a switching node (SW) between the high-side power transistor (11) and the low-side power transistor (12) being connected with an inductance (L);

the method includes, in each of at least one set of switching cycles:

outputting a period detection current (Isen) based on a terminal voltage (Vc 1) of a second terminal of a first capacitor (Cs 1) having a first terminal grounded;

detecting a current provided by the low-side power transistor (12) to the inductor (L) during the turn-on of the low-side power transistor (12) to obtain a low-side detection current (Isen 1);

-increasing the terminal voltage (Vc 1) of the first capacitor (Cs 1) with a constant current (Isr) in a first period (p 1), the first period (p 1) being one of a period in which the high-side power transistor (11) is on and a period in which the low-side power transistor (12) is off; and

16. The method of claim 15, wherein the intensity of the constant current (Isr) in the second switching period is determined based on the intensity of the terminal voltage (Vc 1) of the first capacitor (Cs 1) in a duration in the first switching period, the duration belonging to a period during which the low-side power transistor (12) is turned on in a second period (p 2) of the first switching period.

17. The method of claim 15 or 16, further comprising:

18. The method according to claim 17, wherein:

19. The method of claim 18, wherein the strength of the constant current (Isr) in the second switching period is positively correlated with the product of the low-side voltage slope and a ratio between the difference between the input Voltage (VIN) and the output Voltage (VOUT).

20. A power conversion system, comprising:

a current detection circuit of a DC-DC converter as claimed in any one of claims 1 to 14; and

the DC-DC converter.

21. A power supply, comprising:

the power conversion system of claim 20.