CN116825831A - Semiconductor device, preparation method thereof and electronic device - Google Patents

Semiconductor device, preparation method thereof and electronic device Download PDF

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Publication number
CN116825831A
CN116825831A CN202310871235.7A CN202310871235A CN116825831A CN 116825831 A CN116825831 A CN 116825831A CN 202310871235 A CN202310871235 A CN 202310871235A CN 116825831 A CN116825831 A CN 116825831A
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Prior art keywords
base layer
layer
doping concentration
base
sub
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Inventor
李峰柱
项少华
梁程程
王冲
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Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
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Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
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Priority to CN202310871235.7A priority Critical patent/CN116825831A/en
Publication of CN116825831A publication Critical patent/CN116825831A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42304—Base electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66242—Heterojunction transistors [HBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H01L29/7373—Vertical transistors having a two-dimensional base, e.g. modulation-doped base, inversion layer base, delta-doped base

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

The invention provides a semiconductor device, a preparation method thereof and an electronic device, wherein the semiconductor device comprises: a substrate; the base layer comprises a first base layer and a second base layer positioned outside the first base layer, and the resistance of the second base layer is larger than that of the first base layer. The second base layer is formed to serve as the base ballast resistor to compensate the voltage drop of the emitter and the base, so that thermal runaway caused by a current concentration effect can be avoided, the resistance value of the base ballast resistor is convenient to control, and the reduction of the output power and the power additional efficiency of the semiconductor device can be avoided due to smaller base current.

Description

Semiconductor device, preparation method thereof and electronic device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a preparation method thereof and an electronic device.
Background
Heterojunction bipolar transistors (Heterojunction Bipolar Transistor, HBTs) have the advantages of high frequency, high efficiency, high linearity, high power density, single power supply operation and the like, and are widely applied to the fields of wireless communication, satellites, radars and the like. In the heterojunction bipolar transistor, if the temperature of the element increases, the on-voltage between the base and the emitter decreases and the collector current increases. The current distribution inside the transistor is uneven, so that the current is concentrated in a certain tiny area, filiform large current is formed, the temperature is increased, the current in the tiny area is further increased, the vicious circle is entered, the transistor is easily caused to be out of control, and the transistor is further damaged.
In the related art, an emitter cap layer is generally used as a ballast resistor to inhibit thermal runaway of a transistor, and a plurality of emitter ballast resistors are used to form negative feedback so as to improve emitter bias stability and solve a current concentration effect, but an excessive emitter ballast resistor can cause reduction of output power and reduction of power addition efficiency.
Disclosure of Invention
In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In view of the problems existing at present, an aspect of the present invention provides a semiconductor device including:
a substrate;
the base layer comprises a first base layer and a second base layer positioned outside the first base layer, and the resistance of the second base layer is larger than that of the first base layer.
In one embodiment, the second base layer comprises at least two sub base layers arranged in a stacked manner, different ones of the sub base layers having different doping concentrations;
alternatively, the doping concentration of the second base layer gradually decreases from top to bottom.
In one embodiment, the second base layer includes a first sub-base layer and a second sub-base layer stacked from bottom to top, wherein:
the first sub-base layer has a first thickness and a first doping concentration;
the second sub-base layer has a second thickness and a second doping concentration;
the first doping concentration is different from the second doping concentration, and a sum of the first thickness and the second thickness is equal to a thickness of the first base layer.
In one embodiment, the first doping concentration is less than the second doping concentration, and the first doping concentration and/or the second doping concentration is less than the doping concentration of the first base layer.
In another aspect, the embodiment of the invention provides a method for preparing a semiconductor device, which includes:
providing a substrate;
and forming a subcollector layer, a collector layer, a base layer and an emitter layer on the substrate in sequence from bottom to top, wherein the base layer comprises a first base layer and a second base layer positioned outside the first base layer, and the resistance of the second base layer is larger than that of the first base layer.
In one embodiment, the step of forming the base layer comprises:
forming a first base layer on the collector layer, the first base layer including a first region and a second region located outside the first region;
removing the first base layer in the second region to expose the collector layer;
and forming a second base layer on the collector layer exposed by the second region.
In one embodiment, the second base layer comprises at least two sub-base layers arranged in a stack, different ones of the sub-base layers having different doping concentrations.
In one embodiment, forming the second base layer includes:
forming a first sub-base layer on the collector layer, the first sub-base layer having a first thickness and a first doping concentration;
forming a second sub-base layer on the first sub-base layer, the second sub-base layer having a second thickness and a second doping concentration, a sum of the first thickness and the second thickness being equal to a thickness of the first base layer, the first doping concentration being different from the second doping concentration; the method further comprises the steps of:
the second base layer has a target resistance by adjusting the first thickness and the second thickness.
In one embodiment, the first doping concentration is less than the second doping concentration, and the first doping concentration and/or the second doping concentration is less than the doping concentration of the first base layer.
The invention also provides an electronic device comprising the semiconductor device.
According to the semiconductor device, the manufacturing method thereof and the electronic device, the second base layer is formed to serve as the base ballast resistor to compensate the voltage drop of the emitter and the base, thermal runaway caused by a current concentration effect can be avoided, on one hand, the resistance value of the base ballast resistor can be conveniently controlled, and on the other hand, the reduction of the output power and the power additional efficiency of the semiconductor device can be avoided due to the fact that the base current is smaller.
Drawings
The following drawings are included to provide an understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and their description to explain the principles of the invention.
In the accompanying drawings:
FIGS. 1A-1B are schematic cross-sectional views showing devices obtained by performing a method for manufacturing a semiconductor device according to the related art;
fig. 1C shows a schematic circuit diagram of a semiconductor device of the related art;
fig. 2 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention;
FIGS. 3A-3F are schematic cross-sectional views of a semiconductor device according to an embodiment of the present invention;
FIG. 3G illustrates a schematic cross-sectional view of a second base layer including a first sub-base layer and a second sub-base layer according to an embodiment of the present invention;
fig. 3H shows a schematic circuit diagram of a semiconductor device according to an embodiment of the present invention;
fig. 4 shows a schematic diagram of an electronic device according to an embodiment of the invention.
Detailed Description
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In order to provide a thorough understanding of the present invention, detailed steps and structures will be presented in the following description in order to illustrate the technical solution presented by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.
As shown in fig. 1A, 1B and 1C, fig. 1A to 1B show schematic cross-sectional views of a device obtained by implementing a related art semiconductor device manufacturing method, and fig. 1C shows a schematic circuit diagram of a related art semiconductor device. First, as shown in fig. 1A, a subcollector layer 101, a collector layer 102, a base layer 103, an emitter layer 104, an emitter cap layer 105, and an ohmic contact layer 106 are sequentially formed on a substrate 100 from bottom to top. Next, as shown in fig. 1B, a first mesa structure including the emitter layer 104, the emitter cap layer 105, and the ohmic contact layer 106, and a second mesa structure including the collector layer 102 and the base layer 103 are formed through patterning or the like, and the collector electrode 107 is formed on the sub-collector layer 101, the base electrode 108 is formed on the base layer 103, and the emitter electrode 109 is formed on the ohmic contact layer 106. Among them, the emitter cap layer 105 serves as an emitter ballast resistor, i.e., a ballast resistor as shown in fig. 1C, to suppress thermal runaway of the transistor and to improve emitter junction bias stability, but an excessive emitter ballast resistor may cause a decrease in output power and power added efficiency.
Accordingly, in view of the foregoing technical problems, the present invention proposes a semiconductor device and a method for manufacturing the same, the semiconductor device comprising: a substrate; the base layer comprises a first base layer and a second base layer positioned outside the first base layer, and the resistance of the second base layer is larger than that of the first base layer.
As shown in fig. 2, the method for manufacturing the semiconductor device mainly comprises the following steps:
step S1, providing a substrate;
and S2, sequentially forming a subcollector layer, a collector layer, a base layer and an emitter layer on the substrate from bottom to top, wherein the base layer comprises a first base layer and a second base layer positioned outside the first base layer, and the resistance of the second base layer is larger than that of the first base layer.
According to the semiconductor device, the manufacturing method thereof and the electronic device, the second base layer is formed to serve as the base ballast resistor, so that the emitter-base voltage drop is compensated for instead of the emitter ballast resistor in the existing scheme, thermal runaway caused by a current concentration effect is avoided, on one hand, the resistance value of the base ballast resistor can be conveniently controlled, and on the other hand, the reduction of output power and power additional efficiency of the semiconductor device can be avoided due to the fact that the base current is smaller.
Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to fig. 2 to 3H, wherein fig. 2 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention, fig. 3A to 3F are schematic cross-sectional views illustrating a device obtained by performing the method for manufacturing a semiconductor device according to an embodiment of the present invention, fig. 3G is a schematic cross-sectional view illustrating a second base layer including a first sub-base layer and a second sub-base layer according to an embodiment of the present invention, and fig. 3H is a schematic circuit diagram illustrating a semiconductor device according to an embodiment of the present invention.
The semiconductor device according to the embodiments of the present invention may be any suitable device known to those skilled in the art, and in this embodiment, the technical solution of the present invention is mainly explained and illustrated by taking a case where the semiconductor device is a heterojunction bipolar transistor as an example.
As illustrated in fig. 3A to 3G, the method of manufacturing a semiconductor device of the present invention includes the steps of:
first, a substrate is provided. Specifically, as shown in fig. 3A, the substrate 300 is a semi-insulating substrate, such as a GaAs semi-insulating substrate; the substrate 300 may also be at least one of the following mentioned materials: si, ge, siGe, siC, siGeC, inAs, inP, inGaAs or other III/V compound semiconductors, and also include multilayer structures of these semiconductors, or are silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like. In other embodiments, substrate 300 may be any other suitable substrate.
Subsequently, a subcollector layer, a collector layer, a base layer, and an emitter layer are sequentially formed on the substrate from bottom to top, the base layer including a first base layer and a second base layer located outside the first base layer, the second base layer having a resistance greater than a resistance of the first base layer.
In some embodiments, with continued reference to fig. 3A, subcollector layer 301 is formed on a substrate 300. The subcollector layer is a highly doped layer for ohmic contact to the collector layer. By way of example, subcollector layer 301 may be formed using an epitaxial growth process or a suitable technique. In this embodiment, subcollector layer 301 may be formed using any of several methods in an epitaxial growth process, non-limiting examples of which include Low Pressure Chemical Vapor Deposition (LPCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermalizationChemical Vapor Deposition (RTCVD) and Molecular Beam Epitaxy (MBE). Exemplary subcollector layer 301 is gallium arsenide, has a thickness in the range of 400 nanometers to 800 nanometers, is of the N-type conductivity, is of the silicon doping element, and is of the Si doping source 2 H 6 The doping concentration range is 5E18cm -3 To 5E19cm -3 The pressure of the epitaxy process is in the range of 50mbar to 200mbar, the temperature of the epitaxy process is in the range of 500 ℃ to 800 ℃ and the V/III ratio (i.e. the molar ratio of group V element to group III element) is in the range of 0.5 to 100, but it should be understood that the above process conditions are merely examples and that the relevant process parameters can be adapted accordingly by a person skilled in the art according to the actual needs.
Next, a collector layer 302 is formed on the subcollector layer 301. By way of example, collector layer 302 may be formed using an epitaxial growth process or a suitable technique. In this embodiment, collector layer 302 can be formed using any of several methods in an epitaxial growth process, non-limiting examples of which include Low Pressure Chemical Vapor Deposition (LPCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid Thermal Chemical Vapor Deposition (RTCVD), and Molecular Beam Epitaxy (MBE). The collector layer 302 is illustratively gallium arsenide, has a thickness in the range of 300 nm to 1000 nm, is of the N-type conductivity, is of the silicon doping element, and is of the Si doping source 2 H 6 The doping concentration range is 5E15cm -3 To 2E16cm -3 The pressure of the epitaxy process is in the range of 50mbar to 200mbar, the temperature of the epitaxy process is in the range of 500 ℃ to 800 ℃ and the V/III ratio is in the range of 0.5 to 100, but it should be understood that the above process conditions are only examples and that the relevant process parameters can be adjusted accordingly by a person skilled in the art according to the actual need.
Next, as shown in fig. 3A to 3C, a base layer is formed on the collector layer 302, the base layer including a first base layer 303 and a second base layer 304, the second base layer 304 being located outside the first base layer 303, the thickness of the second base layer 304 being equal to the thickness of the first base layer 303. The resistance value of the second base layer 304 is different from the resistance value of the first base layer 304, and the resistance value of the second base layer 304 is larger than the resistance value of the first base layer 303, so that the second base layer 304 forms a base ballast resistor to compensate the emitter-base voltage drop, and thermal runaway caused by the current concentration effect is avoided. Because the base ballast resistor is not on the output path, compared with the adoption of the emitter ballast resistor, the semiconductor device provided by the embodiment of the invention has better thermal stability and higher output power and power additional efficiency.
Specifically, as shown in FIG. 3F, the emitter current I E Base current I B Collector current I C The method comprises the following steps of: i E ＝I nE +I PE ，I B ＝I PE +I pr ，I C ＝I E -I B ＝I E -I PE -I pr The method comprises the steps of carrying out a first treatment on the surface of the Wherein I is PE Representing hole diffusion current formed by holes injected into the emitter region from the base region; i nE Representing electron diffusion current formed by electrons injected from the base region into the emitter region; i pr Representing the current formed by holes injected into the base region to replenish holes lost in recombination with electrons injected into the base region. Since the current transmission efficiency of the semiconductor device is I C /I b Therefore, to improve the current transmission efficiency of the semiconductor device, I should be reduced as much as possible PE And I pr . Increasing the resistance of the second base layer 304 may reduce I pr Thereby improving the current transmission efficiency of the semiconductor device.
The first base layer 303 and the second base layer 304 may be formed using an epitaxial growth process or a suitable technique, for example. In this embodiment, the first base layer 303 and the second base layer 304 may be formed using any of several methods in an epitaxial growth process, non-limiting examples including Low Pressure Chemical Vapor Deposition (LPCVD), plasma Enhanced Chemical Vapor Deposition (PECVD), ultra High Vacuum Chemical Vapor Deposition (UHVCVD), rapid Thermal Chemical Vapor Deposition (RTCVD), and Molecular Beam Epitaxy (MBE). Illustratively, the material of the first base layer 303 is In x Ga 1-x As (x is 0 or more and 0.1 or less), the thickness is 40 nm to 100nm, the conductivity type is P type, the doping element is carbon, the doping concentration is in the range of1E19cm -3 To 5E19cm -3 The pressure of the epitaxy process is 50mbar to 200mbar, the temperature of the epitaxy process is 500 ℃ to 800 ℃ and the V/III ratio is 0.5 to 100. The second base layer 304 is made of gallium arsenide, carbon tetrachloride or carbon tetrabromide, and has a doping concentration of 1E18cm -3 To 5E19cm -3 The pressure of the epitaxy process is 50mbar to 200mbar, the temperature of the epitaxy process is 500 ℃ to 800 ℃ and the V/III ratio is 0.5 to 100.
Illustratively, since the resistance value of the film layer is correlated with the doping concentration of the film layer, the second base layer 304 can be made to have a specific resistance value by varying the doping concentration of the second base layer 304.
In some embodiments, the step of forming the base layer includes: first, as shown in fig. 3A, a first base layer 303 is formed on a collector layer 302, the first base layer 303 including a first region and a second region located outside the first region; next, as shown in fig. 3B, the first base layer 303 in the second region is removed to expose the collector layer 302; finally, as shown in fig. 3C, a second base layer 304 is formed on the collector layer 302 exposed in the second region. In other embodiments, the second base layer 304 may also be formed on the collector layer 302, the second base layer 304 may be patterned, and the first base layer 303 may be formed on the collector layer 302.
In some embodiments, the thickness of the first base layer 303 is H 303 The method comprises the steps of carrying out a first treatment on the surface of the The second base layer 304 is divided into a plurality of second sub-base layers, wherein the thickness and doping concentration of each layer are Hi and Ti, i=1, 2, …; and h1+h2+ … … +hi=h 303 I is more than or equal to 2. Since the resistance of the thin film is proportional to the doping concentration and inversely proportional to the thickness, hi and Ti can be adjusted such that the second base layer 304 reaches a target resistance. Illustratively T1<T2<……<The doping concentration of Ti, namely each sub-base layer, gradually decreases from top to bottom.
In some embodiments, as shown in fig. 3G, the second base layer 304 includes a first sub-base layer 3041 and a second sub-base layer 3042 that are stacked. Illustratively, the first sub-base layer 3041 has a first thickness and a first doping concentration, and the second sub-base layer 3042 has a second thickness and a second doping concentration, the sum of the first thickness and the second thickness being equal to the thickness of the first base layer 303. At least one of the first doping concentration and the second doping concentration is less than the doping concentration of the first base layer 303 to ensure that the resistance of the second base layer 304 is greater than the resistance of the first base layer 303.
In some embodiments, the first doping concentration is different from the second doping concentration, and the resistance value of the film layer is related to the thickness of the film layer, so that the first sub-base layer 3041 and the second sub-base layer 3042 can have specific resistance values by adjusting the first thickness and the second thickness under the condition that the sum of the first thickness and the second thickness is unchanged, and further the second base layer 304 can have a target resistance value, and the adjustment manner is more flexible; the target resistance is a resistance preset based on actual requirements. For example, the first sub-base layer 3041 is an undoped insulating layer, and the second sub-base layer 3042 is a lightly doped layer, and the second base layer 304 with different resistance values can be obtained by balancing the thicknesses of the first sub-base layer 3041 and the second sub-base layer 3042. Further, providing the first sub-base layer 3041 as an insulating layer can also avoid current leakage at the interface of the first sub-base layer 3041 and the collector layer 302.
In some embodiments, the resistance of the film layer is also related to the doping concentration of the film layer, so the first sub-base layer 3041 and the second sub-base layer 3042 can have specific resistance values by adjusting the first doping concentration and the second doping concentration, and further the second base layer 304 can have a target resistance value, which is a preset resistance value based on actual requirements.
In some embodiments, the doping concentration of the second base layer 304 gradually decreases from top to bottom, and in particular, the doping concentration may be gradually increased during the growth of the second base layer by using an epitaxial process, so that the doping concentration of the second base layer gradually increases during the growth. Because the doping concentration is lower near the collector layer, current leakage at the interface of the second base layer 304 and the collector layer 302 can be avoided.
Subsequently, as shown in fig. 3C, an emitter layer 305 covering the first and second base layers 303 and 304 and an ohmic contact layer 306 covering the emitter layer 305 are formed.
By way of example, the emitter layer 305 may be formed using an epitaxial growth process or a suitable technique. Illustratively, the emitter layer 305 is of material In y Ga 1-y P (y is greater than or equal to 0 and less than or equal to 0.5), thickness is in the range of 30-60 nanometers, conductivity type is N type, doping element is silicon, doping concentration is in the range of 1E17cm -3 To 2E16cm -3 The pressure of the epitaxy process is in the range of 50mbar to 200mbar, the temperature of the epitaxy process is in the range of 500 ℃ to 800 ℃ and the V/III ratio is in the range of 0.5 to 100.
Illustratively, the material of the ohmic contact layer 306 includes In z Ga 1-z As，0<z is less than or equal to 0.6, and the thickness is 50 nm-100 nm; the doping type is N type, the doping element is Si or Te, and the doping concentration is not lower than 5e19cm -3 The ohmic contact layer 306 is grown at a pressure of 50 to 200mbar and a growth temperature of 500 to 800 ℃ with a V/III ratio of 0.5 to 100.
Subsequently, as shown in fig. 3D, the emitter layer 305 and the ohmic contact layer 306 are patterned to form a first mesa structure including a first emitter layer 3051 on the first base layer 303 and a first ohmic contact layer 3061 on the first emitter layer 3051, and a second emitter layer 3052 on the second base layer 304 and a second ohmic contact layer 3062 on the second emitter layer 3052. Illustratively, the first emitter layer 3051 covers the first base layer 303, and the second emitter layer 3052 exposes a portion of the second base layer 304. For example, the ohmic contact layer 306 and the emitter layer 305 may be sequentially etched using the photoresist as a mask to form a first mesa structure, and the etching process may include a wet etching process or a dry etching process.
Next, as shown in fig. 3E, the second base layer 304 and the collector layer 302 are patterned to form a second mesa structure that exposes the subcollector layer 301 below the collector layer 302.
Illustratively, the area of the second mesa structure is greater than the area of the second mesa structure. By forming the first mesa structure and the second mesa structure, the withstand voltage performance of the semiconductor device can be improved.
In some embodiments, as shown in fig. 3F, after forming the second mesa structure, a collector electrode 307 is formed on the sub-collector layer 301 for extracting the collector layer 302 through the sub-collector layer 301, wherein the sub-collector layer 301 functions as an inflow path of current flowing in the collector layer 302; forming a base electrode 308 on the second base layer 304 for extracting the first base layer 303 through the second base layer 304; and forming an emitter electrode 309 on the emitter layer 305, specifically, forming the emitter electrode 309 on the first emitter layer 3051 for extracting the first emitter layer 3051. Illustratively, the base electrode 308 may also be formed on the second emitter layer 3052, with the metal penetrating through the second emitter layer 3052 to form an ohmic contact with the second base layer 304 through an alloying process; meanwhile, as the second emitter layer 3052 is used as a passivation layer, the surface recombination current can be reduced, and the device gain is increased.
The collector electrode 307 may be a multilayered metal structure composed of AuGe layers, ni layers, and Au layers that are stacked, for example. Illustratively, the base electrode 308 has a multi-layered metal structure composed of a Pt layer, a Ti layer, and an Au layer that are stacked. The emitter electrode 309 has a multilayer metal structure composed of Mo layers, ti layers, pt layers, and Au layers, which are stacked. Illustratively, the collector electrode 307, the base electrode 308, and the emitter electrode 309 may be formed using photolithography, evaporation, and lift-off processes.
The method for manufacturing a semiconductor device according to the present invention may further include other steps, which are not described in detail herein.
As shown in fig. 3H, in the embodiment of the present invention, the second base layer is used as a base ballast resistor, so as to compensate for the emitter-base voltage drop, avoid thermal runaway caused by the current concentration effect, and replace the emitter ballast resistor in the prior art with the base ballast resistor, so that on one hand, the resistance of the base ballast resistor can be conveniently controlled, and on the other hand, the base ballast resistor is arranged so as to avoid the reduction of the output power and the additional power efficiency of the semiconductor device due to the smaller base current.
The present invention also provides a semiconductor device that can be produced by the method in the foregoing embodiments.
Next, a semiconductor device of an embodiment of the present invention will be explained and explained with reference to fig. 3F, in which the same structure as in the previous embodiment is not described in detail here.
Specifically, as shown in fig. 3F, the semiconductor device of the present invention includes: a substrate 300; a subcollector layer 301, a collector layer 302, a base layer and an emitter layer 305 formed on a substrate 300 from bottom to top, the base layer comprising a first base layer 303 and a second base layer 304 located outside the first base layer 303, the second base layer 304 having a resistance greater than the resistance of the first base layer 303.
Illustratively, the substrate 300 is a semi-insulating substrate, which may be at least one of the following mentioned materials: si, ge, siGe, siC, siGeC, inAs, gaAs, inP, inGaAs or other III/V compound semiconductors, and also include multilayer structures of these semiconductors, or are silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like.
Subcollector layer 301 is formed on substrate 300 as a highly doped layer for ohmic contact to collector layer 302. Exemplary subcollector layer 301 is GaAs with a thickness in the range of 400 nm to 800 nm, an N-type conductivity, a doping element of silicon, and a doping concentration in the range of 5E18cm -3 To 5E19cm -3 The V/III ratio ranges from 0.5 to 100.
Collector layer 302 is located on subcollector layer 301 and has a width that is less than the width of subcollector layer 301. The collector layer 302 is made of gallium arsenide, has a thickness ranging from 300 nm to 1000 nm, has an N-type conductivity, has a doping element of silicon, and has a doping concentration ranging from 5E15cm -3 To 2E16cm -3 The V/III ratio ranges from 0.5 to 100.
A base layer is formed on the collector layer 302, the base layer comprising a first base layer 303 and a second base layer 304, the second base layer 304 being located outside the first base layer 303, the second base layer 304 having a resistance which is greater than the resistance of the first base layer 303. Illustratively, the material of the first base layer 303 is In x Ga 1-x As (x is greater than or equal to 0 and less than or equal to 0.1), the thickness is in the range of 40-100 nanometers, the conductivity type is P type, the doping element is carbon, and the doping concentration is in the range of 1E19cm -3 To 5E19cm -3 The V/III ratio ranges from 0.5 to 100. The second base layer 304 is made of gallium arsenide, carbon tetrachloride or carbon tetrabromide, and has a doping concentration of 1E18cm -3 To 5E19cm -3 The V/III ratio ranges from 0.5 to 100. The thickness of the second base layer 304 is equal to the thickness of the first base layer 303, and the doping concentration of the second base layer 304 is not higher than the doping concentration of the first base layer 303.
In some embodiments, the thickness of the first base layer 303 is H 303 The method comprises the steps of carrying out a first treatment on the surface of the The second base layer 304 is divided into a plurality of second sub-base layers, wherein the thickness and doping concentration of each layer are Hi and Ti, i=1, 2, …; and h1+h2+ … … +hi=h 303 I is more than or equal to 2. Since the resistance of the thin film is proportional to the doping concentration and inversely proportional to the thickness, hi and Ti can be adjusted such that the second base layer 304 reaches a target resistance. Illustratively T1<T2<……<The doping concentration of Ti, namely each sub-base layer, gradually decreases from top to bottom.
In some embodiments, as shown in fig. 3G, the second base layer 304 includes a first sub-base layer 3041 and a second sub-base layer 3042 that are stacked. The first sub-base layer 3041 has a first thickness H1 and a first doping concentration T1, and the second sub-base layer 3042 has a second thickness H2 and a second doping concentration T2, T1<T2. Illustratively, the sum of the first thickness H1 and the second thickness H2 is equal to the thickness H of the first base layer 303 303 . The first thickness is illustratively equal to the second thickness, or the first thickness is greater than the second thickness, or the first thickness is less than the second thickness. At least one of the first doping concentration and the second doping concentration is less than the doping concentration of the first base layer 303 to ensure the first doping concentrationThe resistance of the two base layers 304 is greater than the resistance of the first base layer 303.
Compared to a single-layer structure with uniform doping, when a double-layer structure is adopted, the resistance of the first and second sub-base layers 3041 and 3042 can be controlled by adjusting the first and second doping concentrations and the first and second thicknesses, so that the second base layer 304 has a target resistance, which enables the change of the resistance of the second base layer 304 to be more flexible and has a larger range, wherein the target resistance is a resistance preset based on practical requirements. Illustratively, the second base layer has a sheet resistance of about 50 to 1000 Ω/sq.
In one embodiment, the first sub-base layer 3041 is an undoped insulating layer, and the second sub-base layer 3042 is a lightly doped layer, and the second base layer 304 with different resistance values can be obtained by balancing the thicknesses of the first sub-base layer 3041 and the second sub-base layer 3042. Further, providing the first sub-base layer 3041 as an insulating layer can also avoid current leakage at the interface of the first sub-base layer 3041 and the collector layer 302.
In some embodiments, the doping concentration of the second base layer 304 gradually decreases from top to bottom, and current leakage at the interface of the second base layer 304 and the collector layer 302 can be avoided due to the lower doping concentration near the collector layer.
Further, the semiconductor device of the present invention further includes: a collector electrode 307 on the subcollector layer 301; a base electrode 308 on the second base layer 304; and an emitter electrode 309 on the ohmic contact layer 306. The collector electrode 307 has a multilayer metal structure composed of AuGe layers, ni layers, and Au layers, which are stacked, for example. Illustratively, the base electrode 308 has a multi-layered metal structure composed of a Pt layer, a Ti layer, and an Au layer that are stacked. The emitter electrode 309 has a multilayer metal structure composed of Mo layers, ti layers, pt layers, and Au layers, which are stacked.
Thus, the description of the structure of the semiconductor device of the present invention is completed, and other constituent structures may be included in the complete device, which will not be described in detail herein.
Since the semiconductor device is provided with the second base layer serving as the base ballast resistor to compensate the voltage drop of the emitter and the base, thermal runaway caused by the current concentration effect can be avoided, the resistance value of the base ballast resistor can be conveniently controlled on one hand, and on the other hand, the reduction of the output power and the power additional efficiency of the semiconductor device can be avoided by arranging the base ballast resistor due to smaller base current.
In another embodiment of the present invention, an electronic apparatus is provided, including the semiconductor device, where the semiconductor device is prepared according to the foregoing method.
The electronic device of the embodiment may be any electronic product or apparatus such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, MP3, MP4, PSP, and the like, and may also be any intermediate product including a circuit. The electronic device provided by the embodiment of the invention has better performance due to the use of the semiconductor device.
Wherein fig. 4 shows an example of a mobile phone. The mobile phone 400 is provided with a display portion 402, an operation button 403, an external connection port 404, a speaker 405, a microphone 406, and the like included in a housing 401.
Although a number of embodiments have been described herein, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various modifications and alterations may be made in the arrangement and/or component parts of the subject matter within the scope of the disclosure, the drawings, and the appended claims. In addition to modifications and variations in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.

Claims (10)

1. A semiconductor device, the semiconductor device comprising:
a substrate;
the base layer comprises a first base layer and a second base layer positioned outside the first base layer, and the resistance of the second base layer is larger than that of the first base layer.
2. The semiconductor device of claim 1, wherein the second base layer comprises at least two sub-base layers arranged in a stack, different ones of the sub-base layers having different doping concentrations;
alternatively, the doping concentration of the second base layer gradually decreases from top to bottom.
3. The semiconductor device of claim 2, wherein the second base layer comprises a first sub-base layer and a second sub-base layer disposed in a bottom-to-top stack, wherein:
the first sub-base layer has a first thickness and a first doping concentration;
the second sub-base layer has a second thickness and a second doping concentration;
the first doping concentration is different from the second doping concentration, and a sum of the first thickness and the second thickness is equal to a thickness of the first base layer.
4. The semiconductor device of claim 3, wherein the first doping concentration is less than the second doping concentration, the first doping concentration and/or the second doping concentration being less than a doping concentration of the first base layer.
5. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate;
and forming a subcollector layer, a collector layer, a base layer and an emitter layer on the substrate in sequence from bottom to top, wherein the base layer comprises a first base layer and a second base layer positioned outside the first base layer, and the resistance of the second base layer is larger than that of the first base layer.
6. The method of manufacturing of claim 5, wherein the step of forming the base layer comprises:
forming a first base layer on the collector layer, the first base layer including a first region and a second region located outside the first region;
removing the first base layer in the second region to expose the collector layer;
and forming a second base layer on the collector layer exposed by the second region.
7. The method of claim 5, wherein the second base layer comprises at least two sub-base layers arranged in a stack, different ones of the sub-base layers having different doping concentrations; alternatively, the doping concentration of the second base layer gradually decreases from top to bottom.
8. The method of manufacturing of claim 7, wherein forming the second base layer comprises:
forming a first sub-base layer on the collector layer, the first sub-base layer having a first thickness and a first doping concentration;
forming a second sub-base layer on the first sub-base layer, the second sub-base layer having a second thickness and a second doping concentration, a sum of the first thickness and the second thickness being equal to a thickness of the first base layer, the first doping concentration being different from the second doping concentration; the method further comprises the steps of:
the second base layer has a target resistance by adjusting the first thickness and the second thickness.
9. The method of manufacturing according to claim 8, characterized in that the first doping concentration is smaller than the second doping concentration, the first doping concentration and/or the second doping concentration being smaller than the doping concentration of the first base layer.
10. An electronic device, characterized in that it comprises the semiconductor device according to any one of claims 1 to 4.
CN202310871235.7A 2023-07-14 2023-07-14 Semiconductor device, preparation method thereof and electronic device Pending CN116825831A (en)

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