CN116825801A - Preparation method of micro LED chip and micro LED chip - Google Patents
Preparation method of micro LED chip and micro LED chip Download PDFInfo
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- CN116825801A CN116825801A CN202210546886.4A CN202210546886A CN116825801A CN 116825801 A CN116825801 A CN 116825801A CN 202210546886 A CN202210546886 A CN 202210546886A CN 116825801 A CN116825801 A CN 116825801A
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- 238000009792 diffusion process Methods 0.000 claims abstract description 71
- 238000000034 method Methods 0.000 claims abstract description 41
- 238000000151 deposition Methods 0.000 claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 239000007772 electrode material Substances 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 160
- 239000000463 material Substances 0.000 claims description 26
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- 238000000059 patterning Methods 0.000 claims description 14
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 12
- IAZDPXIOMUYVGZ-UHFFFAOYSA-N Dimethylsulphoxide Chemical compound CS(C)=O IAZDPXIOMUYVGZ-UHFFFAOYSA-N 0.000 claims description 12
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- RKTYLMNFRDHKIL-UHFFFAOYSA-N copper;5,10,15,20-tetraphenylporphyrin-22,24-diide Chemical group [Cu+2].C1=CC(C(=C2C=CC([N-]2)=C(C=2C=CC=CC=2)C=2C=CC(N=2)=C(C=2C=CC=CC=2)C2=CC=C3[N-]2)C=2C=CC=CC=2)=NC1=C3C1=CC=CC=C1 RKTYLMNFRDHKIL-UHFFFAOYSA-N 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
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- FDPIMTJIUBPUKL-UHFFFAOYSA-N dimethylacetone Natural products CCC(=O)CC FDPIMTJIUBPUKL-UHFFFAOYSA-N 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 10
- 229910002601 GaN Inorganic materials 0.000 description 22
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 22
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Abstract
The application provides a preparation method of a micro LED chip and the micro LED chip, wherein the preparation method comprises the following steps: preparing a first mask layer on the patterned epitaxial wafer; etching the epitaxial wafer according to the pattern of the first mask layer, and forming a mesa array on the surface of the epitaxial wafer, wherein the mesa array comprises a plurality of mesa units, and two adjacent mesa units are arranged at intervals; removing the first mask layer; depositing a current diffusion layer on the surface of the mesa array; electrode materials are deposited on the surface of the epitaxial wafer deposited with the current diffusion layer, a first electrode and a second electrode are formed, the first electrode is deposited on the surface of the current diffusion layer, and the second electrode is deposited on the surface of the epitaxial wafer between two adjacent mesa units. The manufacturing process of the Micro-LED chip is optimized and improved, the process steps are simplified, the process complexity of the preparation of the Micro-LED array is effectively reduced, the quality of products is controlled, and the production efficiency is improved.
Description
Technical Field
The application belongs to the technical field of Micro-LED chips, and particularly relates to a preparation method of a Micro-LED chip and the Micro-LED chip.
Background
The Micro-LED is a Micro-LED, namely a self-luminous micron-sized LED is used as a luminous pixel unit, and is a miniaturized, thin-film and array LED, and because the Micro-LED has the advantages of small size, high integration level, self-luminescence, high brightness, low energy consumption and the like, besides the huge prospect in the display field, the application of the Micro-LED is expanded to the fields of AR/VR/MR, optical communication/optical interconnection, medical detection and the like. The Micro-LED chip is a core element of the Micro-LED, and the quality of the Micro-LED chip directly influences the light-emitting effect of the Micro-LED.
The existing Micro-LED chip has the defects of complicated preparation process, unfavorable controllable product quality and low production efficiency.
Disclosure of Invention
Based on the above, the application aims to provide a preparation method of a micro LED chip, which aims to solve the technical problems of complicated preparation process, unfavorable controllable product quality and low production efficiency in the prior art.
Another object of the present application is to provide a micro led chip.
In order to achieve the above object, the present application has the following technical scheme:
a preparation method of a micro LED chip comprises the following steps:
preparing a first mask layer on the patterned epitaxial wafer;
etching the epitaxial wafer according to the pattern of the first mask layer, and forming a mesa array on the surface of the epitaxial wafer, wherein the mesa array comprises a plurality of mesa units, and two adjacent mesa units are arranged at intervals;
removing the first mask layer;
depositing a current diffusion layer on the surface of the mesa array;
electrode materials are deposited on the surface of the epitaxial wafer deposited with the current diffusion layer, a first electrode and a second electrode are formed, the first electrode is deposited on the surface of the current diffusion layer, and the second electrode is deposited on the surface of the epitaxial wafer between two adjacent mesa units.
Optionally, the method for preparing the first mask layer on the patterned epitaxial wafer and removing the first mask layer comprises the following steps:
coating photoresist on at least one surface of an epitaxial wafer, drying, and then carrying out patterning treatment on the photoresist to obtain a first photoresist layer, wherein part of the surface of the epitaxial wafer forms an exposure area through the pattern of the first photoresist layer;
depositing a mask material on one surface of the epitaxial wafer coated with the first photoresist layer to form a first mask layer, wherein the first mask layer covers the surface and the exposed area of the first photoresist layer;
and removing the first photoresist layer and the first mask layer positioned on the surface of the first photoresist layer by adopting an organic solvent to obtain a patterned first mask layer, wherein the patterned first mask layer comprises a plurality of mask units distributed in an array, so that the part of the epitaxial wafer corresponding to the first photoresist layer is exposed to the outside to form a region to be etched.
Optionally, the method for forming the mesa array on the surface of the epitaxial wafer by etching the epitaxial wafer according to the pattern of the first mask layer comprises the following steps:
etching a region to be etched of the epitaxial wafer to form a plurality of pits, wherein the pits are distributed in an array;
and removing the residual first mask layer to obtain the mesa array.
Optionally, the method for depositing and forming the current diffusion layer on the surface of the mesa array comprises the following steps:
forming a second photoresist layer between the mesa units, wherein the second photoresist layer protrudes out of the surface of the mesa units, and two sides of the second photoresist layer overlap the peripheral edges of the mesa units;
performing deposition treatment on the surfaces of the mesa unit and the second photoresist layer to form a current diffusion material film, wherein the current diffusion material film covers the surfaces of the mesa unit and the second photoresist layer;
and removing the second photoresist layer and the current diffusion material film covered on the surface of the second photoresist layer by adopting an organic solvent to obtain a current diffusion layer, wherein the current diffusion layer is attached to the surface of the mesa unit.
Optionally, depositing electrode materials on the surface of the epitaxial wafer where the current diffusion layer is located, and forming the first electrode and the second electrode comprises the following steps:
coating photoresist on the surface of the epitaxial wafer on which the current diffusion layer is deposited, drying, and then carrying out patterning treatment to obtain a third photoresist layer, wherein the third photoresist layer comprises a plurality of third photoresist units, two adjacent third photoresist units are arranged at intervals, each third photoresist unit covers the peripheral edge of the mesa unit and the peripheral edge of the current diffusion layer, the surface of the current diffusion layer between the two third photoresist units is exposed, and each third photoresist unit protrudes out of the surface of the current diffusion layer; the epitaxial wafer area between two adjacent mesa units is exposed outside;
depositing electrode materials on one surface of the epitaxial wafer where the third photoresist is located, forming a first electrode on the current diffusion layer, and forming a second electrode on the epitaxial wafer between two adjacent mesa units;
and removing the third photoresist layer by using an organic solvent.
Optionally, the mesa unit has a tetragonal structure, and the side length of the mesa unit is L, and L is more than or equal to 1 μm and less than or equal to 50 μm.
Optionally, the electrode material comprises a multi-layered metal structure of Ti/Al/Ti/Au.
Optionally, the mask material comprises silicon nitride, silicon oxide, or metal; and/or the current spreading layer comprises an ITO layer or a metal layer.
Alternatively, the organic solvent comprises dimethyl sulfoxide or acetone.
And a micro led chip manufactured by the manufacturing method of the micro led chip according to any one of the above.
1. According to the preparation method of the Micro LED chip, the epitaxial wafer is patterned, the patterned first mask layer is prepared, the mesa array is prepared by using the pattern of the first mask layer, and then the current diffusion layer, the first electrode and the second electrode are prepared, so that the process of the Micro LED chip is optimized and improved, the procedure of obtaining the mask layer through etching is eliminated, the process steps are simplified, the process complexity of the preparation of the Micro LED array is effectively reduced, the quality of products is controlled, and the production efficiency is improved;
2. the micro LED chip provided by the application can be widely applied to the fields of flat panel display, AR/VR/MR, optical communication/optical interconnection, medical detection and the like.
Drawings
The application will be further described with reference to the accompanying drawings and examples, in which:
fig. 1 is a flowchart of a method for manufacturing a micro led chip according to embodiment 1 of the present application;
fig. 2 is a schematic flow chart of steps S110 to S210 of the micro led chip provided in embodiment 1 of the present application;
fig. 3 is a flowchart of steps S310 to S330 of the micro led chip provided in embodiment 1 of the present application;
fig. 4 is a flowchart of steps S410 to S500 of the micro led chip provided in embodiment 1 of the present application.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
The embodiment of the application provides a preparation method of a micro LED chip, which comprises the following steps:
s100: and preparing a first mask layer on the patterned epitaxial wafer.
The epitaxial wafer in the embodiment of the application refers to a gallium nitride-based epitaxial wafer, and the gallium nitride-based epitaxial wafer comprises a substrate, a p-type gallium nitride layer and an n-type gallium nitride layer.
Optionally, the method for preparing the first mask layer on the patterned epitaxial wafer comprises the following steps:
s110: and coating photoresist on at least one surface of the epitaxial wafer, drying, and then carrying out patterning treatment on the photoresist to obtain a first photoresist layer, wherein part of the surface of the epitaxial wafer forms an exposed area through the pattern of the first photoresist layer.
It will be appreciated that the exposed area includes a plurality of exposed cells, the plurality of exposed cell arrays are distributed, and adjacent two exposed cells are spaced apart in preparation for subsequent patterning of the first mask layer.
The photoresist can be coated by a spin coating method, and the spin coating method can rapidly and uniformly coat the photoresist on the epitaxial wafer, thereby being beneficial to improving the working efficiency.
The photoresist can be a photoresist soluble in an organic solvent, so that the photoresist can be removed by adopting the organic solvent, and other structural layers are not lost.
Patterning the photoresist means exposing and developing the photoresist to obtain a predetermined pattern.
S120: and depositing a mask material on one surface of the epitaxial wafer coated with the first photoresist layer to form a first mask layer, wherein the first mask layer covers the surface and the exposed area of the first photoresist layer.
A masking material can be deposited on the epitaxial wafer by adopting a coating process, wherein the masking material comprises silicon nitride, silicon oxide or metal, and on one hand, the masking material can be deposited on the epitaxial wafer by adopting the coating process, is insoluble in an organic solvent and can be removed separately from the first photoresist layer; on the other hand, the method of removing silicon nitride, silicon oxide or metal does not damage the epitaxial wafer, so these mask materials are suitable as the material of the transition layer.
It will be appreciated that the first photoresist layer protrudes from the end surface of the first mask layer corresponding to the exposed region, so that when the organic solvent is used to dissolve the first photoresist layer subsequently, the organic solvent may contact the protruding portion of the first photoresist layer, and gradually dissolve the first photoresist layer.
S130: and removing the first photoresist layer and the first mask layer positioned on the surface of the first photoresist layer by adopting an organic solvent to obtain a patterned first mask layer, wherein the patterned first mask layer comprises a plurality of mask units distributed in an array, so that the part of the epitaxial wafer corresponding to the first photoresist layer is exposed.
It can be understood that the mask units are in one-to-one correspondence with the exposing units, and positions of the mask units distributed in the plurality of arrays corresponding to the epitaxial wafer are positions where the mesa units are formed subsequently.
The first photoresist layer and the first mask layer on the first photoresist layer are removed, namely the first mask layer is patterned, the pattern of the first mask layer corresponds to the array distribution design of the mesa array, and the part of the epitaxial wafer corresponding to the first photoresist layer is exposed to prepare a structure for etching in the next process.
Optionally, the organic solvent includes dimethyl sulfoxide or acetone, so that the first photoresist layer can be effectively dissolved, and after the first photoresist layer is dissolved and separated, the first mask layer on the first photoresist layer is separated along with the separation of the first photoresist layer.
S200: etching the epitaxial wafer according to the pattern of the first mask layer, removing the first mask layer, and forming a mesa array on the surface of the epitaxial wafer, wherein the mesa array comprises a plurality of mesa units, and two adjacent mesa units are arranged at intervals.
The mesa array is prepared on the epitaxial wafer to block the electrical paths of pixels between adjacent pixels, so that basic Micro-LED pixels are obtained, and the expected information such as images, videos and the like is displayed through the on-off combination of the pixels.
Optionally, the method for forming the mesa array on the surface of the epitaxial wafer by etching the epitaxial wafer according to the pattern of the first mask layer comprises the following steps:
s210: and etching the to-be-etched area of the epitaxial wafer to form a plurality of pits, wherein the pits are distributed in an array, and removing the residual first mask layer by adopting a wet etching method to obtain a mesa array.
It can be understood that the first photoresist layer and the first mask layer are both transition layers, so that in order to design patterns of the mesa array on the epitaxial wafer, a structure preparation is made for preparing the mesa array, and after the mesa array is prepared, the first photoresist layer and the first mask layer can be removed, and then the next process is performed.
Optionally, the mesa unit has a tetragonal structure, and the side length of the mesa unit is L, and L is more than or equal to 1 μm and less than or equal to 50 μm. The side length of the embodiment of the application refers to the side length of the table top unit in the horizontal direction, the table top unit is of a tetragonal structure, the side length L of the table top unit is the side length of a square section along the horizontal direction, and the square section can be rectangular or square. When the square is rectangular, the length of the long side of the square is in the range of 1 μm to 50 μm.
S300: and depositing a current diffusion layer on the surface of the mesa array.
In order to reduce the contact resistance of the epitaxial wafer and the electrode and to enable current to be spread from the p-electrode to the n-electrode without congestion, it is necessary to prepare a current spreading layer between the mesa unit of the epitaxial wafer and the electrode.
Optionally, the current diffusion layer includes an ITO layer or a metal layer, which can effectively reduce the contact resistance between the epitaxial wafer and the electrode.
Optionally, the method for depositing and forming the current diffusion layer on the surface of the mesa array comprises the following steps:
s310: forming a second photoresist layer between the mesa units, wherein the second photoresist layer protrudes out of the surface of the mesa units, and two sides of the second photoresist layer overlap the peripheral edges of the mesa units;
s320: performing deposition treatment on the surfaces of the mesa unit and the second photoresist layer to form a current diffusion material film, wherein the current diffusion material film covers the surfaces of the mesa unit and the second photoresist layer;
s330: and removing the second photoresist layer and the current diffusion material film covered on the surface of the second photoresist layer by adopting an organic solvent to obtain a current diffusion layer, wherein the current diffusion layer is attached to the surface of the mesa unit.
S400: electrode materials are deposited on the surface of the epitaxial wafer deposited with the current diffusion layer, a first electrode and a second electrode are formed, the first electrode is deposited on the surface of the current diffusion layer, and the second electrode is deposited on the surface of the epitaxial wafer between two adjacent mesa units.
It can be appreciated that the first electrode and the second electrode are arranged at intervals and are arranged in a non-electric connection mode, so that the problem of short circuit in the using process is avoided.
Optionally, depositing electrode materials on the surface of the epitaxial wafer where the current diffusion layer is located, and forming the first electrode and the second electrode comprises the following steps:
s410: coating photoresist on the surface of the epitaxial wafer deposited with the current diffusion layer, drying, and then carrying out patterning treatment to obtain a third photoresist layer, wherein the third photoresist layer comprises a plurality of third photoresist units, two adjacent third photoresist units are arranged at intervals, each third photoresist unit covers the peripheral edge of the mesa unit and the peripheral edge of the current diffusion layer, the surface of the current diffusion layer between the two third photoresist units is exposed outside, and each third photoresist unit protrudes out of the surface of the current diffusion layer; the epitaxial wafer area between two adjacent mesa units is exposed.
Optionally, the spacing distance between two adjacent third photoresist units is the same, which is beneficial to controlling the formation width of the first electrode and the second electrode.
S420: and depositing electrode materials on one surface of the epitaxial wafer where the third photoresist is located, forming a first electrode on the current diffusion layer, and forming a second electrode on the epitaxial wafer between two adjacent mesa units.
Optionally, the electrode material comprises a multi-layered metal structure of Ti/Al/Ti/Au.
S500: and removing the third photoresist layer by using an organic solvent.
Optionally, the first photoresist layer, the second photoresist layer and the third photoresist layer adopt the same photoresist and adopt the same organic solvent to remove the photoresist, so that the use condition can be simplified, and the problems that the process is possibly disordered and the process complexity is increased due to the adoption of a plurality of different photoresists and organic solvents are avoided.
And a micro led chip manufactured by the manufacturing method of the micro led chip according to any one of the above.
According to the preparation method of the Micro LED chip, the epitaxial wafer is patterned, the patterned first mask layer is prepared, the mesa array is prepared by using the pattern of the first mask layer, then the current diffusion layer, the first electrode and the second electrode are prepared, the process of the Micro-LED chip is optimized and improved, the procedure of obtaining the mask layer through etching is removed, the process steps are simplified, the process complexity of the preparation of the Micro-LED array is effectively reduced, the quality of products is controlled, and the production efficiency is improved.
The micro LED chip provided by the embodiment of the application can be widely applied to the fields of flat panel display, AR/VR/MR, optical communication/optical interconnection, medical detection and the like.
The following is illustrated by examples.
Example 1
The preparation method of the micro led chip of the embodiment, as shown in fig. 2 to 4, includes the following steps:
s110: spin-coating photoresist on at least one surface of the gallium nitride-based epitaxial wafer 1, drying, and then patterning the photoresist to obtain a first photoresist layer 31, wherein a part of the surface of the gallium nitride-based epitaxial wafer 1 forms an exposed region through the pattern of the first photoresist layer 31.
S120: a mask material silicon nitride is deposited on one surface of the gallium nitride-based epitaxial wafer 1 where the first photoresist layer 31 is located in a coating mode, a first mask layer 4 is formed, the first mask layer 4 covers the surface and the exposed area of the first photoresist layer 31, and the first photoresist layer 31 protrudes out of the end face of the first mask layer 4 corresponding to the exposed area.
S130: and removing the first photoresist layer 31 and the first mask layer 4 positioned on the surface of the first photoresist layer 31 by using dimethyl sulfoxide to obtain a patterned first mask layer 4, wherein the patterned first mask layer 4 comprises a plurality of mask units distributed in an array, and the part of the gallium nitride-based epitaxial wafer 1 corresponding to the first photoresist layer 31 is exposed.
S210: etching the to-be-etched area of the gallium nitride-based epitaxial wafer 1 to form a plurality of pits distributed in an array, removing the first mask layer 4 by adopting a wet etching method to obtain a mesa array, wherein the mesa array comprises a plurality of mesa units 5, the mesa units 5 are distributed at intervals, the horizontal section of the mesa units 5 is square, and the side length L of the mesa units 5 is 1.5 mu m.
S310: a second photoresist layer 32 is formed between the mesa units 5, the second photoresist layer 32 protrudes from the surface of the mesa units 5, and both sides of the second photoresist layer 32 overlap the peripheral side edges of the mesa units 5.
S320: a deposition process is performed on the surfaces of the mesa unit 5 and the second photoresist layer 32 to form a current diffusion material film that covers the surfaces of the mesa unit 5 and the second photoresist layer 32.
S330: and removing the second photoresist layer 32 and the current diffusion material film covered on the surface of the second photoresist layer 32 by using dimethyl sulfoxide to obtain a current diffusion layer 6, wherein the current diffusion layer 6 is attached to the surface of the mesa unit 5.
S410: coating photoresist on one surface of the gallium nitride-based epitaxial wafer 1 where the current diffusion layer 6 is located, drying, and then performing patterning treatment to obtain a third photoresist layer, wherein the third photoresist layer comprises a plurality of third photoresist units 33, two adjacent third photoresist units 33 are arranged at intervals, each third photoresist unit 33 covers the peripheral edge of the mesa unit 5 and the peripheral edge of the current diffusion layer 6, the surface of the current diffusion layer 6 between the two third photoresist units 33 is exposed outside, and each third photoresist unit 33 protrudes out of the surface of the current diffusion layer 6; the gallium nitride-based epitaxial wafer 1 region between two adjacent mesa units 5 is exposed.
S420: an electrode material is deposited on one surface of the gallium nitride-based epitaxial wafer 1 where the third photoresist layer is located, a first electrode 72 is formed on the current diffusion layer 6, a second electrode 71 is formed on the gallium nitride-based epitaxial wafer between two adjacent mesa units, and the first electrode 72 and the second electrode 71 each comprise a multi-layer metal structure of Ti/Al/Ti/Au.
S500: and removing the third photoresist layer by using dimethyl sulfoxide to obtain the micro LED chip.
Example 2
The preparation method of the micro LED chip of the embodiment comprises the following steps:
s110: spin-coating photoresist on at least one surface of a gallium nitride-based epitaxial wafer, drying, and then carrying out patterning treatment on the photoresist to obtain a first photoresist layer, wherein part of the surface of the gallium nitride-based epitaxial wafer forms an exposure area through the pattern of the first photoresist layer.
S120: and depositing mask material chromium on one surface of the gallium nitride-based epitaxial wafer where the first photoresist layer is located, forming a first mask layer, wherein the first mask layer covers the surface and the exposed area of the first photoresist layer, and the first photoresist layer protrudes out of the end face of the first mask layer corresponding to the exposed area.
S130: and removing the first photoresist layer and the first mask layer positioned on the surface of the first photoresist layer by adopting acetone to obtain a patterned first mask layer, wherein the patterned first mask layer comprises a plurality of mask units distributed in an array, and the part of the gallium nitride-based epitaxial wafer corresponding to the first photoresist layer is exposed.
S210: etching a region to be etched of the gallium nitride-based epitaxial wafer to form a plurality of pits distributed in an array, removing the first mask layer by adopting a wet etching method to obtain a mesa array, wherein the mesa array comprises a plurality of mesa units which are distributed at intervals, the horizontal section of each mesa unit is square, and the side length L of each mesa unit is 49 mu m.
S310: and forming a second photoresist layer between the mesa units, wherein the second photoresist layer protrudes out of the surface of the mesa units, and two sides of the second photoresist layer overlap the peripheral edges of the mesa units.
S320: and carrying out deposition treatment on the surfaces of the mesa unit and the second photoresist layer to form a current diffusion material film, wherein the current diffusion material film covers the surfaces of the mesa unit and the second photoresist layer.
S330: and removing the second photoresist layer and the current diffusion material film covered on the surface of the second photoresist layer by adopting acetone to obtain a current diffusion layer, wherein the current diffusion layer is attached to the surface of the mesa unit.
S410: coating photoresist on one surface of the gallium nitride-based epitaxial wafer where the current diffusion layer is located, drying, and then carrying out patterning treatment to obtain a third photoresist layer, wherein the third photoresist layer comprises a plurality of third photoresist units, two adjacent third photoresist units are arranged at intervals, each third photoresist unit covers the peripheral edge of the mesa unit and the peripheral edge of the current diffusion layer, the surface of the current diffusion layer between the two third photoresist units is exposed, and each third photoresist unit protrudes out of the surface of the current diffusion layer; the gallium nitride-based epitaxial wafer area between two adjacent mesa units is exposed.
S420: and depositing an electrode material on one surface of the gallium nitride-based epitaxial wafer where the third photoresist is located, forming a first electrode on the current diffusion layer, and forming a second electrode on the gallium nitride-based epitaxial wafer between two adjacent mesa units, wherein the first electrode and the second electrode both comprise a Ti/Al/Ti/Au multilayer metal structure.
S500: and removing the third photoresist layer by adopting acetone to obtain the micro LED chip.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the application.
Claims (10)
1. A preparation method of a micro LED chip is characterized by comprising the following steps: the method comprises the following steps:
preparing a first mask layer on the patterned epitaxial wafer;
etching the epitaxial wafer according to the pattern of the first mask layer, and forming a mesa array on the surface of the epitaxial wafer, wherein the mesa array comprises a plurality of mesa units, and two adjacent mesa units are arranged at intervals;
removing the first mask layer;
depositing a current diffusion layer on the surface of the mesa array;
and depositing electrode materials on the surface of the epitaxial wafer deposited with the current diffusion layer to form a first electrode and a second electrode, wherein the first electrode is deposited on the surface of the current diffusion layer, and the second electrode is deposited on the surface of the epitaxial wafer between two adjacent mesa units.
2. The method for manufacturing a micro led chip according to claim 1, wherein: the method for preparing the first mask layer on the patterned epitaxial wafer comprises the following steps of:
coating photoresist on at least one surface of the epitaxial wafer, drying, and then carrying out patterning treatment on the photoresist to obtain a first photoresist layer, wherein part of the surface of the epitaxial wafer forms an exposure area through the pattern of the first photoresist layer;
depositing a mask material on the surface of the epitaxial wafer coated with the first photoresist layer to form a first mask layer, wherein the first mask layer covers the surface of the first photoresist layer and the exposed area;
and removing the first photoresist layer and the first mask layer positioned on the surface of the first photoresist layer by adopting an organic solvent to obtain the first mask layer after patterning, wherein the first mask layer after patterning comprises a plurality of mask units distributed in an array, so that the part of the epitaxial wafer corresponding to the first photoresist layer is exposed outside to form a region to be etched.
3. The method for manufacturing a micro led chip according to claim 2, wherein: the method for forming the mesa array on the surface of the epitaxial wafer by etching the epitaxial wafer according to the pattern of the first mask layer comprises the following steps:
etching a region to be etched of the epitaxial wafer to form a plurality of pits, wherein the pits are distributed in an array;
and removing the residual first mask layer to obtain a mesa array.
4. The method for manufacturing a micro led chip according to claim 1, wherein: the method for depositing and forming the current diffusion layer on the surface of the mesa array comprises the following steps:
forming a second photoresist layer between the mesa units, wherein the second photoresist layer protrudes out of the surface of the mesa units, and two sides of the second photoresist layer overlap the peripheral edges of the mesa units;
performing deposition treatment on the surfaces of the mesa unit and the second photoresist layer to form a current diffusion material film, wherein the current diffusion material film covers the surfaces of the mesa unit and the second photoresist layer;
and removing the second photoresist layer and the current diffusion material film covered on the surface of the second photoresist layer by adopting an organic solvent to obtain a current diffusion layer, wherein the current diffusion layer is attached to the surface of the mesa unit.
5. The method for manufacturing a micro led chip according to claim 1, wherein: the method for forming the first electrode and the second electrode by depositing electrode materials on one surface of the epitaxial wafer where the current diffusion layer is located comprises the following steps:
coating photoresist on the surface of the epitaxial wafer on which the current diffusion layer is deposited, drying, and then carrying out patterning treatment to obtain a third photoresist layer, wherein the third photoresist layer comprises a plurality of third photoresist units, two adjacent third photoresist units are arranged at intervals, each third photoresist unit covers the peripheral edge of the mesa unit and the peripheral edge of the current diffusion layer, the surface of the current diffusion layer between the two third photoresist units is exposed, and each third photoresist unit protrudes out of the surface of the current diffusion layer; the epitaxial wafer area between two adjacent mesa units is exposed outside;
depositing electrode materials on one surface of the epitaxial wafer where the third photoresist is located, forming a first electrode on the current diffusion layer, and forming a second electrode on the epitaxial wafer between two adjacent mesa units;
and removing the third photoresist layer by adopting an organic solvent.
6. The method for manufacturing a micro led chip according to any one of claims 1 to 5, wherein: the table top unit is of a tetragonal structure, and the side length of the table top unit is L which is more than or equal to 1 mu m and less than or equal to 50 mu m.
7. The method for manufacturing a micro led chip according to any one of claims 1 to 5, wherein: the electrode material comprises a multi-layer metal structure of Ti/Al/Ti/Au.
8. The method for manufacturing a micro led chip according to any one of claims 2 to 5, wherein: the mask material comprises silicon nitride, silicon oxide or metal; and/or the number of the groups of groups,
the organic solvent comprises dimethyl sulfoxide or acetone.
9. The method for manufacturing a micro led chip according to any one of claims 2 to 5, wherein: the current diffusion layer includes an ITO layer or a metal layer.
10. A micro led chip manufactured by the manufacturing method of the micro led chip according to any one of claims 1 to 9.
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| CN202210546886.4A CN116825801A (en) | 2022-05-19 | 2022-05-19 | Preparation method of micro LED chip and micro LED chip |
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| CN202210546886.4A CN116825801A (en) | 2022-05-19 | 2022-05-19 | Preparation method of micro LED chip and micro LED chip |
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