CN116822453B - Method for comparing integrated circuits - Google Patents
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- CN116822453B CN116822453B CN202311075071.3A CN202311075071A CN116822453B CN 116822453 B CN116822453 B CN 116822453B CN 202311075071 A CN202311075071 A CN 202311075071A CN 116822453 B CN116822453 B CN 116822453B
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Abstract
The invention discloses an integrated circuit comparison method, which comprises the following steps: dividing the layouts of two integrated circuits to be compared into a plurality of blocks corresponding to each other; comparing the corresponding blocks in pairs; if the geometric data in the two blocks are consistent, the figures in the two blocks are considered to be identical; and if the geometric data in the two blocks are inconsistent, performing exclusive OR operation on the geometric figures in the two blocks, obtaining corresponding comparison results, and combining the comparison results of all the figures through Boolean OR operation. The invention can greatly improve the comparison efficiency of the layout.
Description
Technical Field
The invention relates to the technical field of physical verification of integrated circuits, in particular to a method for rapidly comparing ultra-large-scale integrated circuits.
Background
In the chip design production link, some minor modifications and adjustments are often made to the layout of the chip to meet the process requirements of the wafer foundry (foundry). At this time, the modified layout and the layout before modification are compared to determine whether the place where modification occurs accords with the expectation.
Since the actual chip layout is typically very large scale integrated circuit layout, the quick verification can only be performed by LVL (Layout VS Layout) software.
As shown in fig. 1, in the design and test flow, the LVL is also an important tool for verifying whether the front and rear layouts (the layout file 1 and the layout file 2) are consistent, and as a point tool, the LVL is commonly used for comparing two layouts which are the same in most of the areas, and outputs the result after exclusive-or is performed on the two layouts.
The layout file of the integrated circuit is usually in a GDS format, and based on the consideration of data compression, the OASIS format appears later, no matter which format is adopted, the layout file is a description of the layout, and the two formats are both public industry standards.
The process of layout analysis is a process of reading layout files, and when two layout files are read, LVL comparison is carried out on the two layout files.
The challenges of performing layout calibration and testing are also increasing while the chip layout is expanding increasingly, and the efficiency and accuracy are both very high.
Therefore, how to improve the comparison efficiency of two layouts before and after modification and ensure the accuracy at the same time is a technical problem to be solved urgently.
Disclosure of Invention
The invention provides an integrated circuit comparison method for solving the technical problem that the comparison efficiency of the layout of an ultra-large scale integrated circuit in the prior art is relatively low.
The invention provides an integrated circuit comparison method, which comprises the following steps:
dividing the layouts of two integrated circuits to be compared into a plurality of blocks corresponding to each other;
comparing the corresponding blocks in pairs;
if the geometric data in the two blocks are consistent, the figures in the two blocks are considered to be identical;
if the geometric data in the two blocks are inconsistent, performing exclusive OR operation on the geometric figures in the two blocks, and obtaining corresponding comparison results;
and merging the comparison results of all the graphs through Boolean OR operation.
Further, the dividing the layout of the two integrated circuits to be compared into a plurality of blocks corresponding to each other includes:
firstly, respectively dividing two integrated circuits into a corresponding number of dividing blocks according to the number of nodes of a distributed system for performing comparison;
dividing each divided block into a plurality of divided blocks according to the number of graphics on each divided block;
judging the type of the graph touched by the dividing line in the dividing process, if the type of the graph is an example graph, not dividing the example graph, so that the example graph can acquire a complete example graph in the divided corresponding blocks; if the pattern is a regular pattern, dividing the regular pattern according to the dividing line.
Further, comparing the corresponding blocks in pairs specifically includes:
if the layout data is in a flattening mode, traversing the graphics in the two blocks according to the same rule, and comparing vertex data of the same positions of the two traversed graphics in the two blocks; if the two patterns are different, judging that the two patterns are inconsistent; if the two patterns are the same, comparing other vertex data of the two patterns, if the other vertex data are the same, marking the two patterns as paired patterns, otherwise judging that the two patterns are inconsistent;
further, comparing the corresponding blocks in pairs specifically includes:
if the layout data is in a layering mode, traversing the graphics in each group of two blocks according to the same rule, judging whether the currently traversed graphics are example graphics or not, if so, calling the previous comparison result; if not, comparing the two instance graphs;
if the currently traversed graph is a conventional graph, comparing vertex data of the same positions of the two traversed graphs in each group of two blocks; if the two patterns are different, judging that the two patterns are inconsistent; if the two patterns are the same, the other vertex data of the two patterns are compared, if the other vertex data are the same, the two patterns are marked as paired patterns, otherwise, the two patterns are not consistent.
Further, comparing the two example graphs includes the steps of:
obtaining a layering structure diagram corresponding to an instance graph;
taking the top layer of the hierarchical structure chart as the current layer;
comparing all the graphs of the current layer in sequence; if the two graphs are found to be inconsistent, flattening the inconsistent graphs, and putting the graphs on the top layer for exclusive OR operation;
judging whether the current graph to be compared has a lower structure or not; if yes, traversing downwards, taking the next layer as the current layer and returning to the previous step; if not, ending the flow after all the graphs of the current layer are compared.
Further, before dividing the layouts of two integrated circuits to be compared into a plurality of blocks corresponding to each other, when the layouts of the integrated circuits are read, geometric data of the graphics on the layouts are stored by storing coordinate points of graphics vertices and types of the graphics on the layouts.
Further, when the layout of the integrated circuit is read, the conventional graph and the example graph in the layout are respectively processed.
According to the invention, under the condition that most of the two layouts are consistent, exclusive OR operation is not performed on each geometric figure of the two layouts to judge whether the geometric figures are consistent. By the data comparison strategy, completely consistent geometric data are excluded, and exclusive OR operation is carried out on two patterns which cannot be clearly judged, so that most of calculation time can be saved, and extremely fast Layout comparison operation (Layout VS Layout) is realized.
Drawings
The invention is described in detail below with reference to examples and figures, wherein:
FIG. 1 is a prior art layout comparison flow diagram;
FIG. 2 is a block schematic diagram of the present invention;
FIG. 3 is a graph of a matching demonstration of the binDiff algorithm of the present invention;
FIG. 4 is a schematic diagram of the present invention for the separate processing of an example graphic and a generic graphic;
fig. 5 is an overall flow chart of an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Thus, reference throughout this specification to one feature will be used in order to describe one embodiment of the invention, not to imply that each embodiment of the invention must be in the proper motion. Furthermore, it should be noted that the present specification describes a number of features. Although certain features may be combined together to illustrate a possible system design, such features may be used in other combinations not explicitly described. Thus, unless otherwise indicated, the illustrated combinations are not intended to be limiting.
The vast majority of comparison objects are identical for mass data, so the present invention aims to exclude identical objects at minimal cost and is suitable for distributed, and multithreaded parallel processing. The main principle of the comparison method of the integrated circuit is that the layout of the ultra-large scale integrated circuit is divided into small blocks, namely bin processing (containerization processing), then the patterns on the two blocks of the same area position of the integrated circuit layout to be compared are compared, and the blocks which are compared can be simultaneously processed in a parallel mode, so that the processing efficiency is greatly improved. In addition, the method adopts a vertex comparison mode when comparing the geometric figures on the two blocks, so that whether the two compared geometric figures are consistent or not can be quickly found, and the comparison efficiency is improved.
In one embodiment, the method of the present invention for alignment of integrated circuits includes the following steps.
Step 1, dividing the layouts of two integrated circuits to be compared into a plurality of blocks corresponding to each other;
step 2, comparing the corresponding blocks one by one;
step 3, if the geometric data in the two blocks are consistent, the figures in the two blocks are considered to be identical; if the geometric data in the two blocks are inconsistent, performing exclusive OR operation on the geometric figures in the two blocks, and obtaining corresponding comparison results;
and 4, merging the comparison results of all the graphs through Boolean OR operation.
The invention eliminates the obvious identical patterns, and only needs to exclusive or operate the patterns which cannot intuitively obtain whether the patterns are identical, thereby greatly reducing the comparison workload of the ultra-large scale integrated circuits.
In one embodiment, the step 1 includes the following steps.
Step 1.1, firstly, dividing two integrated circuits into a corresponding number of dividing blocks according to the number of nodes of a distributed system for performing comparison;
step 1.2, dividing each divided block into a plurality of blocks, namely a plurality of bins according to the number of graphics on each divided block;
step 1.3, judging the type of the graph touched by the dividing line in the dividing process, if the type of the graph is an example graph, not dividing the example graph, so that the example graph can acquire a complete example graph in the divided corresponding blocks; if the pattern is a regular pattern, dividing the regular pattern according to the dividing line. When the method is used for dividing, a dividing function is adopted for dividing, if an example graph is encountered by a dividing line in the dividing process, the example graph is not divided by the dividing function, and the geometric data of the example graph is maintained. If the dividing line touches the conventional graph, inputting the conventional graph into the dividing function to obtain the geometric data of the two divided graphs.
When the layout of the integrated circuit is read, the geometric data of the graphics on the layout are stored by storing the coordinate points of the graphics vertexes and the types of the graphics on the layout.
As shown in fig. 2, the present invention divides the layout of the integrated circuit according to the positions, and two blocks (the bin on the left side and the bin on the right side) corresponding to each other after the layout of the two integrated circuits to be compared is divided, belong to the corresponding regions with the same positions, so that the layout of the ultra-large scale integrated circuit is converted into the comparison of the blocks.
In one embodiment, the present invention compares the corresponding blocks one by one, specifically using the following steps.
If the layout data is in a flattening mode, traversing the graphics in the two blocks according to the same rule, and comparing vertex data of the same positions of the two traversed graphics in the two blocks; if the two patterns are different, judging that the two patterns are inconsistent; if the two patterns are the same, the other vertex data of the two patterns are compared, if the other vertex data are the same, the two patterns are marked as paired patterns, otherwise, the two patterns are not consistent.
The layout data is divided into a layout of a flattening mode (flat) and a layout of a layering mode (hierarchical), wherein the flattening mode is that only one top-level Cell (TOPCell) exists in the layout data, all geometric figures exist in the top-level Cell TOPCell, a plurality of sub-cells (sub-cells) are arranged in the layout data of the hierarchy mode to form the top-level Cell TOPCell besides the top-level Cell TOPCell, and the geometric figures can exist in the sub-cells or TOPCell.
Because all data are stored in hierarchical mode (hierarchy) in the actual chip layout, the invention also supports hierarchical comparison during layout comparison so as to realize good comparison speed.
The hierarchical structure of the layout is that in the chip layout, a plurality of electronic devices are stored in the form of units (cells), and when the layout is drawn, the complicated layout can be drawn quickly by repeatedly calling the cells. A Cell can be understood as a collection of geometric figures, which when called, is called an instance (instance graph), i.e., an instance graph contains one or more geometric figures.
The same is true when comparing, if a cell is compared to determine if it is consistent, then all instances called to that cell in the layout are not determined. If a cell is called ten millions of times in a hierarchical layout, we need to compare only once, and the remaining instance that also calls the cell need not be compared.
Thus, in one embodiment, comparing the mutually corresponding partitions in pairs specifically includes the following steps.
If the layout data is in a layering mode, traversing the graphics in each group of two blocks according to the same rule, judging whether the currently traversed graphics are example graphics or not, if so, calling the previous comparison result; if not, comparing the two instance graphs;
if the currently traversed graph is a conventional graph, comparing vertex data of the same positions of the two traversed graphs in each group of two blocks; if the two patterns are different, judging that the two patterns are inconsistent; if the two patterns are the same, the other vertex data of the two patterns are compared, if the other vertex data are the same, the two patterns are marked as paired patterns, otherwise, the two patterns are not consistent.
The comparison of the two example graphs in the technical scheme comprises the following steps.
Obtaining a layering structure diagram corresponding to an instance graph;
taking the top layer of the hierarchical structure chart as the current layer;
comparing all the graphs of the current layer in sequence; if the two graphs are found to be inconsistent, flattening the inconsistent graphs, and putting the graphs on the top layer for exclusive OR operation; if the two patterns are consistent, the two patterns are recorded as paired patterns.
Judging whether the current graph to be compared has a lower structure or not; if yes, traversing downwards, taking the next layer as the current layer and returning to the previous step; if not, ending the flow after all the graphs of the current layer are compared.
The algorithm related to the comparison is called as a binDiff algorithm, wherein the binDiff algorithm is an algorithm for quickly traversing all graphs, and after the layout file is read in through a layout analyzer to form internal geometric data, the graph data can be divided into small-block bins for search comparison and quick traversal. Each bin can be analogically to a small partition, and the number of graphics in a bin is approximately 10-100. When two layouts are compared through a binDiff algorithm, the comparison is equivalent to the comparison of the bins at corresponding positions in the two layouts, and the expected time complexity is of the order of O (N) because the number of patterns in one bin is about 10-100.
As shown in FIG. 3, each time a comparison is made, the lower left corner of each graph in each bin graph set is taken for comparison, i.e., lowerLeftPonit, abbreviated as LLP. And (3) rapidly judging whether the patterns are the same by comparing the LLPs, and judging that the patterns are different in two patterns when the patterns inconsistent with the LLPs are found after traversing the reference patterns and realizing the patterns and the LLPs in all the bins. When the LLP attributes are the same, it is then compared whether the other geometric features of the two LLP identical graphs are identical. If so, marking the pattern as the pattern with the found pairing.
If the LLP attributes are different, the two graphs participating in the comparison are directly considered to be inconsistent, and then the graphs are flattened into the top-level structure for exclusive OR operation.
If LLP is the same and other geometric features are consistent, a mark is made to avoid multiple comparisons of the pattern.
In a further embodiment, as shown in FIG. 4, the present invention processes conventional and example patterns in a layout separately when reading the layout of an integrated circuit. When comparing the geometric figures of the layouts, the present integrated circuit layout files are in a layering form, and the geometric figures are respectively stored into a general geometric figure (conventional figure) and an instance figure (instance figure) which can be called for multiple times in the layering storage form of the layouts, and when comparing the layouts, the geometric figures of the general geometric figure and the instance figure are respectively processed.
As shown in fig. 5, the overall flow of the present invention may be generally summarized as performing a bin process on layout files of two integrated circuits to be compared, i.e. dividing the layout into a plurality of blocks. And then adopting a binDiff algorithm to compare the two corresponding blocks. And performing exclusive OR processing on the screened obvious different patterns, and finally outputting corresponding results.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (6)
1. An integrated circuit alignment method, comprising:
dividing the layouts of two integrated circuits to be compared into a plurality of blocks corresponding to each other;
comparing the corresponding blocks in pairs, including: if the layout data is in a layering mode, traversing the graphics in each group of two blocks according to the same rule, judging whether the currently traversed graphics are example graphics or not, if so, calling the previous comparison result; if not, comparing the two instance graphs; if the currently traversed graph is a conventional graph, comparing vertex data of the same positions of the two traversed graphs in each group of two blocks; if the two patterns are different, judging that the two patterns are inconsistent; if the two patterns are the same, comparing other vertex data of the two patterns, if the other vertex data are the same, marking the two patterns as paired patterns, otherwise judging that the two patterns are inconsistent;
if the geometric data in the two blocks are consistent, the figures in the two blocks are considered to be identical; if the geometric data in the two blocks are inconsistent, performing exclusive OR operation on the geometric figures in the two blocks, and obtaining corresponding comparison results;
and merging the comparison results of all the graphs through Boolean OR operation.
2. The method for comparing integrated circuits according to claim 1, wherein dividing the layout of two integrated circuits to be compared into a plurality of blocks corresponding to each other includes:
firstly, respectively dividing two integrated circuits into a corresponding number of dividing blocks according to the number of nodes of a distributed system for performing comparison;
dividing each divided block into a plurality of divided blocks according to the number of graphics on each divided block;
judging the type of the graph touched by the dividing line in the dividing process, if the type of the graph is an example graph, not dividing the example graph, so that the example graph can acquire a complete example graph in the divided corresponding blocks; if the pattern is a regular pattern, dividing the regular pattern according to the dividing line.
3. The method of comparing integrated circuits of claim 1, wherein comparing the corresponding blocks in pairs comprises:
if the layout data is in a flattening mode, traversing the graphics in each group of two blocks according to the same rule, and comparing vertex data of the same positions of the two traversed graphics in each group of two blocks; if the two patterns are different, judging that the two patterns are inconsistent; if the two patterns are the same, the other vertex data of the two patterns are compared, if the other vertex data are the same, the two patterns are marked as paired patterns, otherwise, the two patterns are not consistent.
4. The method of alignment of integrated circuits of claim 1, wherein the comparing of the two instance patterns comprises the steps of:
obtaining a layering structure diagram corresponding to an instance graph;
taking the top layer of the hierarchical structure chart as the current layer;
comparing all the graphs of the current layer in sequence; if the two graphs are found to be inconsistent, flattening the inconsistent graphs, and putting the graphs on the top layer for exclusive OR operation;
judging whether the current graph to be compared has a lower structure or not; if yes, traversing downwards, taking the next layer as the current layer and returning to the previous step; if not, ending the flow after all the graphs of the current layer are compared.
5. The method according to claim 1, wherein the geometric data of the graphics on the layout is stored by storing coordinate points of graphics vertices and types of graphics on the layout when the layout of the integrated circuit is read before dividing the layout of two integrated circuits to be compared into a plurality of blocks corresponding to each other.
6. The method of comparing integrated circuits according to claim 5, wherein conventional patterns and instance patterns in a layout of the integrated circuits are processed separately when the layout is read.
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