CN118073222B

CN118073222B - Wafer testing method, device, computer equipment and storage medium

Info

Publication number: CN118073222B
Application number: CN202410466805.9A
Authority: CN
Inventors: 王家祺; 胡信伟
Original assignee: Nanjing Paige Measurement And Control Technology Co ltd
Current assignee: Nanjing Paige Measurement And Control Technology Co ltd
Filing date: 2024-04-17
Publication date: 2024-06-28
Anticipated expiration: 2044-04-17

Abstract

The invention relates to the technical field of wafer testing, and discloses a wafer testing method, a device, computer equipment and a storage medium, wherein the method comprises the following steps: acquiring coordinates of chips to be tested, wherein the wafer comprises a plurality of chips to be tested and a plurality of tested chips, and the tested chips are configured with state marks; determining at least one reference coordinate from a reference coordinate classification table according to the coordinates of the chip to be tested, wherein the reference coordinate classification table comprises a plurality of reference coordinates, the plurality of reference coordinates correspond to a plurality of coordinate sets one by one, the coordinate sets are sets of the coordinates of at least one tested chip, and the distance between the at least one reference coordinate and the coordinates of the chip to be tested is smaller than a preset distance; determining a state related chip of the chip to be tested according to at least one reference coordinate, wherein the state related chip is a tested chip corresponding to one of the reference coordinates; the method and the device for testing the wafer state of the semiconductor chip determine the state mark of the state-related chip as the state mark of the chip to be tested, and can improve the testing efficiency of the wafer.

Description

Wafer testing method, device, computer equipment and storage medium

Technical Field

The present invention relates to the field of wafer testing technologies, and in particular, to a wafer testing method, a device, a computer apparatus, and a storage medium.

Background

Chip testing is mainly divided into a wafer Probe test (CP) and a final test FT (FINAL TEST, FT), wherein the wafer test is positioned between wafer manufacture and packaging in the whole Chip manufacture process, and a Probe (Probe) which is made into fine hair by gold wires is arranged on a detection head and is contacted with a contact point (Pad) on a die, so that the electrical characteristics of the corresponding die are tested to determine whether the die is qualified or not.

In the wafer testing process, each chip on the wafer is generally tested, the wafer generally includes a large number of chips, for example, an 8-inch wafer may include about twenty-five thousand chips, in order to save testing cost, in the related art, a sampling test mode is selected to test, specifically, a chip at a fixed position in the wafer is selected to test, the tested chip will be subjected to status marking according to the testing result, then the relative distance between each chip to be tested and the tested chip on the wafer is calculated, one tested chip closest to the tested chip is selected, and the status marking of the tested chip is directly marked to the tested chip. The above method can save test cost, but the calculation amount for determining the relative distance is large, resulting in lower test efficiency.

Disclosure of Invention

In view of the above, the present invention provides a wafer testing method, apparatus, computer device and storage medium, so as to solve the problem of low wafer testing efficiency.

In a first aspect, the present invention provides a wafer testing method, including: acquiring coordinates of chips to be tested, wherein the wafer comprises a plurality of chips to be tested and a plurality of tested chips, and the tested chips are configured with state marks which are used for representing whether the chips are qualified or not; determining at least one reference coordinate from a reference coordinate classification table according to the coordinates of the chip to be tested, wherein the reference coordinate classification table comprises a plurality of reference coordinates, the reference coordinates correspond to a plurality of coordinate sets one by one, the coordinate sets are sets of the coordinates of at least one tested chip, the reference coordinates are the coordinates of one tested chip in the corresponding coordinate sets, and the distance between the at least one reference coordinate and the coordinates of the chip to be tested is smaller than a preset distance; determining a state related chip of the chip to be tested according to at least one reference coordinate, wherein the state related chip is a tested chip corresponding to one of the reference coordinates; and determining the state mark of the state-related chip as the state mark of the chip to be tested.

According to the wafer testing method provided by the embodiment, after the coordinates of the chips to be tested are obtained, at least one reference coordinate is determined from the reference coordinate classification table according to the coordinates of the chips to be tested, then the state related chips of the chips to be tested are determined based on the at least one reference coordinate, the state marks of the state related chips are determined to be the state marks of the chips to be tested, and the process is repeated to complete the state marks of all the chips to be tested on the wafer, so that the wafer testing is completed. According to the invention, at least one reference coordinate close to the chip to be tested is determined through the reference coordinate classification table, then the state-related chip is determined according to the at least one reference coordinate, and the relative distance between each tested chip and the chip to be tested is not required to be determined, so that the calculated amount of the state-related chip is greatly reduced, the efficiency of wafer testing is improved, and the testing cost is further reduced.

In an alternative embodiment, before determining at least one reference coordinate from the reference coordinate classification table according to the coordinates of the chip under test, the method further comprises: and creating a reference coordinate classification table according to the coordinates of the tested chips in the wafer.

In an alternative embodiment, the reference coordinates are configured with levels, and a reference coordinate classification table is created according to the coordinates of the chips tested in the wafer, including: determining a reference coordinate of a current level according to the coordinate values in a current coordinate set, wherein the current coordinate set is a set of coordinates of a tested chip; classifying the current coordinate set according to the reference coordinates of the current level to obtain a plurality of next coordinate sets; determining a reference coordinate of a next level according to the coordinate values in the next coordinate set, wherein the next level is smaller than the current level; and creating a reference coordinate classification table according to the reference coordinates of the current level and the reference coordinates of the next level.

In an alternative embodiment, determining at least one reference coordinate from the reference coordinate classification table according to the coordinates of the chip to be tested includes: sequentially comparing the reference coordinates with the coordinates of the chip to be tested according to the level sequence, and determining the reference coordinates meeting the requirements under each level; and determining the first N reference coordinates in the first order as the at least one reference coordinate, wherein the first order is an order in which the reference coordinates meeting the requirements are arranged from small to large according to corresponding grades, and N is an integer greater than or equal to 1.

In an alternative embodiment, determining a state-related chip of the chip to be tested according to at least one reference coordinate includes: determining the relative distance between the tested chip and the chip to be tested corresponding to each reference coordinate according to at least one reference coordinate and the coordinate of the chip to be tested; and determining the tested chip with the smallest relative distance as a state related chip of the chip to be tested.

In this embodiment, the test result of the chip to be tested is determined according to the test result of the tested chip closest to the chip to be tested, so that the accuracy of the test result of the wafer can be improved.

In an alternative embodiment, the status flag is also used to characterize the cause of the chip failure in the event of the chip failure.

In this embodiment, the reason that the chip is unqualified is represented by the status flag, so that a user can observe and understand the test result of the wafer more conveniently.

In an alternative embodiment, before acquiring the coordinates of the chip to be tested, the method further includes: under the condition that the errors of the sampling test result and the full-test result of the wafers in the same batch are smaller than the preset errors, determining the sampling size according to the test result of the wafers in the same batch; dividing a wafer into a plurality of sampling areas according to the sampling size; at least one chip in the sampling area is tested to determine a plurality of chips under test and status markers corresponding to the chips under test.

According to the wafer testing method provided by the embodiment, under the condition that errors of sampling test results and full-test results of wafers in the same batch are smaller than preset errors, the sampling size is determined according to the test results of the wafers in the same batch, the wafers are divided into a plurality of sampling areas according to the sampling size, at least one chip in the sampling areas is tested, and a plurality of tested chips and state marks corresponding to the tested chips are determined. By determining the position of the tested chip in the mode, the accuracy of the test result of the wafer to be tested, which is determined based on the tested chip, can be improved.

In a second aspect, the present invention provides a wafer testing apparatus, comprising: the wafer comprises a plurality of chips to be tested and a plurality of tested chips, wherein the tested chips are configured with state marks, and the state marks are used for representing whether the chips are qualified or not; the first determining module is used for determining at least one reference coordinate from the reference coordinate classification table according to the coordinates of the chip to be detected, wherein the reference coordinate classification table comprises a plurality of reference coordinates, the plurality of reference coordinates correspond to the plurality of coordinate sets one by one, the coordinate sets are sets of the coordinates of at least one detected chip, the reference coordinates are the coordinates of one detected chip in the corresponding coordinate sets, and the distance between the at least one reference coordinate and the coordinates of the chip to be detected is smaller than a preset distance; the second determining module is used for determining a state related chip of the chip to be tested according to at least one reference coordinate, wherein the state related chip is a tested chip corresponding to one of the reference coordinates; and the third determining module is used for determining the state mark of the state-related chip as the state mark of the chip to be tested.

In an alternative embodiment, the apparatus further comprises: and the creating module is used for creating a reference coordinate classification table according to the coordinates of the tested chips in the wafer.

In an alternative embodiment, the creation module includes: the first determining unit is used for determining the reference coordinate of the current level according to the coordinate value in the current coordinate set, wherein the current coordinate set is the set of the coordinates of the tested chip; the classifying unit is used for classifying the current coordinate set according to the reference coordinates of the current level to obtain a plurality of next coordinate sets; a second determining unit, configured to determine a reference coordinate of a next level according to a magnitude of the coordinate values in the next coordinate set, where the next level is smaller than the current level; and the first creating unit is used for creating a reference coordinate classification table according to the reference coordinate of the current level and the reference coordinate of the next level.

In an alternative embodiment, the first determining module includes: the third determining unit is used for sequentially comparing the plurality of reference coordinates with the coordinates of the chip to be tested according to the grade sequence and determining the reference coordinates meeting the requirements under each grade; and a fourth determining unit configured to determine the first N reference coordinates in the first order as at least one reference coordinate, where the first order is an order in which the reference coordinates satisfying the requirement are arranged in corresponding levels from small to large, and N is an integer greater than or equal to 1.

In an alternative embodiment, the second determining module includes: a fifth determining unit, configured to determine, according to at least one reference coordinate and the coordinates of the chip to be tested, a relative distance between the tested chip and the chip to be tested corresponding to each reference coordinate; and a sixth determining unit for determining the tested chip with the smallest relative distance as the state related chip of the chip to be tested.

In an alternative embodiment, the apparatus further comprises: a fourth determining module, configured to determine a sampling size according to the test result of the same lot of wafers when the error between the sampling test result of the same lot of wafers and the full test result is less than a preset error; the dividing module is used for dividing the wafer into a plurality of sampling areas according to the sampling size; and the test module is used for testing at least one chip in the sampling area to determine a plurality of tested chips and corresponding state marks of the tested chips.

In a third aspect, the present invention provides a computer device comprising: the wafer test device comprises a memory and a processor, wherein the memory and the processor are in communication connection, the memory stores computer instructions, and the processor executes the computer instructions so as to execute the wafer test method according to the first aspect or any implementation mode corresponding to the first aspect.

In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions for causing a computer to perform the wafer test method of the first aspect or any of its corresponding embodiments.

According to the wafer testing method provided by the invention, at least one reference coordinate close to the chip to be tested is determined through the reference coordinate classification table, then the state-related chip is determined according to the at least one reference coordinate, the relative distance between each tested chip and the chip to be tested is not required to be determined, the calculated amount of determining the state-related chip can be greatly reduced, the wafer testing efficiency is improved, and the testing cost is further reduced.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the related art, the drawings that are required to be used in the description of the embodiments or the related art will be briefly described, and it is apparent that the drawings in the description below are some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a flow chart of a wafer testing method according to an embodiment of the invention;

FIG. 2 is a schematic diagram of a wafer according to an embodiment of the present invention;

FIG. 3 is a flow chart of another wafer testing method according to an embodiment of the invention;

FIG. 4 is a flow chart of yet another wafer testing method according to an embodiment of the present invention;

FIG. 5 is a schematic view of another wafer structure according to an embodiment of the present invention;

FIG. 6 is a block diagram of a wafer test apparatus according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Chip testing is an important link for ensuring product yield and cost control, and whether the performance of the chip meets the design requirement can be determined through testing. As products enter the era of high-performance central processing units (Central Processing Unit, CPU), graphics processors (Graphics Processing Unit, GPU), neural network processors (Neural Processing Unit, NPU), digital signal processors (DIGITAL SIGNAL processors, DSP) and System on a Chip (SoC), there are more and more modules integrated inside a Chip, and failure modes in the manufacturing process are correspondingly increased, so that the importance of Chip testing is becoming more and more prominent.

In order to save test cost, in the related art, wafer test (CP) is performed by a pull test method, chips at fixed positions in a wafer are selected for testing, the tested chips are subjected to status marking according to test results, then the relative distance between each chip to be tested and the tested chip on the wafer is calculated, one tested chip closest to the chip to be tested is selected, and the status marking of the tested chip is directly marked to the chip to be tested.

For example, when testing a wafer with 10000 chips in the above manner, if the number of actually tested chips (i.e. tested chips) is 2500, the number of chips to be tested is 7500, and if the relative distance between each chip to be tested and the tested chip on the wafer is calculated, 7500×2500 times of calculation is needed, the calculation amount is huge, resulting in lower efficiency of wafer test.

In view of this, the invention provides a wafer testing method, which determines at least one reference coordinate close to a chip to be tested through a reference coordinate classification table, and further determines a state related chip of the chip to be tested according to the at least one reference coordinate, so that the calculated amount of determining the state related chip can be greatly reduced, the efficiency of wafer testing is improved, and the testing cost is further reduced.

The wafer testing method provided by the invention is described in detail below with reference to the accompanying drawings.

In accordance with an embodiment of the present invention, a wafer test method embodiment is provided, it being noted that the steps shown in the flowchart of the figures may be performed in a computer system, such as a set of computer executable instructions, and, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in an order other than that shown or described herein.

In this embodiment, a wafer testing method is provided, which may be used in a control device of a wafer testing apparatus, and the control device of the wafer testing apparatus may be a processor, a computer, a notebook computer, a server or other devices, and fig. 1 is a schematic flow chart of a wafer testing method according to an embodiment of the present invention, as shown in fig. 1, and the method includes the following steps:

step S101, obtaining coordinates of a chip to be tested.

The wafer comprises a plurality of chips to be tested and a plurality of tested chips, and the tested chips are provided with state marks which are used for representing whether the chips are qualified or not. Specifically, as shown in fig. 2, the wafer includes a plurality of chips 110 including a chip that has completed testing (i.e., a tested chip 111) and a chip that waits for testing (i.e., a chip under test 112). In this embodiment, the tested chip may be a chip that has been tested by a wafer tester (Wafer Prober) and configured with a flag that characterizes the status (pass or fail) of the chip.

It should be appreciated that the purpose of the wafer tester is to test the chips (dies) on the wafer at high speed and accurately to ensure that the electrical characteristics thereof meet the design requirements, thereby screening out the qualified products, reducing the defective products from entering the subsequent packaging and assembly process, and improving the reliability and yield of the whole chip manufacture.

By way of example, the application is not limited to a particular form of status indicia, e.g., status indicia may be numbers, letters, patterns, colors, etc. For example, when the status flag is a value of "1", it indicates that the status of the chip is acceptable, and when the status flag is a value of "2", it indicates that the status of the chip is unacceptable.

For example, the wafer testing device may use a certain chip in the wafer as an origin of coordinates, and establish a two-dimensional rectangular coordinate system, so as to determine the coordinates of each chip to be tested in the wafer.

Step S102, determining at least one reference coordinate from a reference coordinate classification table according to the coordinates of the chip to be tested.

The reference coordinate classification table comprises a plurality of reference coordinates, the reference coordinates correspond to the coordinate sets one by one, the coordinate sets are the coordinate sets of at least one measured chip, the reference coordinates are the coordinate of one measured chip in the corresponding coordinate sets, and the distance between the at least one reference coordinate and the coordinate of the chip to be measured is smaller than the preset distance.

Specifically, the coordinates of all the chips to be tested in the wafer are divided into a plurality of coordinate sets based on the reference coordinates, each coordinate set including the coordinates of at least one chip to be tested, the plurality of reference coordinates being configured with a rank (priority), the higher-rank coordinate set containing the lower-rank coordinate set. The reference coordinate with the lowest level corresponding to the chip to be detected can be determined by comparing the coordinates of the chip to be detected with the reference coordinates, and the reference coordinate with the lowest level corresponding to the chip to be detected is the reference coordinate which is closer to the chip to be detected (the distance is smaller than the preset distance).

Step S103, determining a state related chip of the chip to be tested according to at least one reference coordinate.

The state-related chip is a tested chip corresponding to one of the at least one reference coordinate.

For example, one reference coordinate may be randomly selected from at least one reference coordinate, and the measured chip corresponding to the reference coordinate may be determined as a state-related chip of the chip to be measured; the relative distance between the tested chip and the chip to be tested corresponding to the reference coordinates can be determined according to the reference coordinates and the coordinates of the chip to be tested, and then the tested chip with the minimum relative distance is determined as the state related chip of the chip to be tested.

Step S104, determining the state mark of the state-related chip as the state mark of the chip to be tested.

Specifically, the state of the chip to be tested is the same as the state of the state-related chip, for example, if the state of the state-related chip is marked with a value of "1", the state of the chip to be tested is also marked with a value of "1".

In this embodiment, a wafer testing method is provided, which can be used in a control device of a wafer testing apparatus, and fig. 3 is a schematic flow chart of another wafer testing method according to an embodiment of the invention, as shown in fig. 3, and the method includes the following steps:

step S301, obtain coordinates of the chip to be tested.

Please refer to step S101 in the embodiment shown in fig. 1 in detail, which is not described herein.

In step S302, a reference coordinate classification table is created according to the coordinates of the tested chips in the wafer.

Specifically, the step S302 includes:

In step S3021, the reference coordinates of the current level are determined according to the magnitudes of the coordinate values in the current coordinate set.

The current coordinate set is a set of coordinates of the tested chip. The invention does not limit the mode of determining the reference coordinates of the current level according to the coordinate values in the current coordinate set.

For example, the X values corresponding to the coordinates in the current coordinate set may be arranged in order from small to large, and then the coordinates corresponding to the X values at the most intermediate position may be regarded as the reference coordinates of the current level. For example, the current coordinate set is { (1, 2), (3, 4), (5, 2), (2, 6), (5, 5) }, and at this time, the arrangement order of the X values is 1,2, 3, 5, and the reference coordinate is (3, 4).

If the two X values are at the most intermediate position (i.e., the number of coordinates in the set is even), the coordinate corresponding to the larger value of the two X values is selected as the reference coordinate, and if the two X values are at the most intermediate position and the two X values are equal, the coordinate corresponding to the larger value of the Y value of the two X values is selected as the reference coordinate.

For example, the Y values corresponding to the coordinates in the current coordinate set may be arranged in order from small to large, and then the coordinates corresponding to the Y value at the most intermediate position may be regarded as the reference coordinates. For example, the current coordinate set is { (1, 2), (3, 4), (5, 2), (2, 6), (5, 5) }, and at this time, the arrangement order of the Y values is 2, 4, 5, 6, and the reference coordinate is (3, 4).

If the two Y values are at the most intermediate position (i.e., the number of coordinates in the set is even), the coordinate corresponding to the larger value of the two Y values is selected as the reference coordinate, and if the two Y values are at the most intermediate position and the two Y values are equal, the coordinate corresponding to the larger value of the X value of the two Y values is selected as the reference coordinate.

For example, an average value of X values corresponding to coordinates in the current coordinate set may be determined, and then a coordinate corresponding to one X value nearest to the average value may be taken as a reference coordinate. For example, the current coordinate set is { (1, 2), (3, 4), (5, 2), (2, 6), (5, 5) }, and at this time, the average value of X values is 3.2= (1+2+3+5+5)/5, and the reference coordinate is (3, 4).

For example, an average value of Y values corresponding to coordinates in the current coordinate set may be determined, and then a coordinate corresponding to one Y value closest to the average value may be taken as a reference coordinate. For example, the current coordinate set is { (1, 2), (3, 4), (5, 2), (2, 6), (5, 5) }, and at this time, the average value of Y values is 3.8= (2+2+4+5+6)/5, and the reference coordinate is (3, 4).

The level of the reference coordinate is determined according to the number of times the coordinate set is classified, for example, if the current coordinate set is an initial coordinate set (i.e., the set of coordinates of all the chips tested), the current level is 1, and if the current coordinate set is an initial coordinate set after the first classification, the current level is 11.

In step S3022, the current coordinate set is classified according to the reference coordinates of the current level, to obtain a plurality of next coordinate sets.

Illustratively, in the case where the reference coordinate of the current level is determined based on the X value of the coordinates in the current coordinate set, all coordinates of which the X value of the coordinates in the current coordinate set is smaller than the X value of the reference coordinate are classified into one set (i.e., the first next coordinate set), and all coordinates of which the X value of the coordinates in the current coordinate set is larger than the X value of the reference coordinate are classified into one set (i.e., the second next coordinate set). For example, the current coordinate set is { (1, 2), (3, 4), (5, 2), (2, 6), (5, 5) }, the reference coordinate determined with the X value is (3, 4), and the next coordinate set is the set { (1, 2), (2, 6) } and the set { (3, 4), (5, 2), (5, 5) }.

Illustratively, in the case where the reference coordinate of the current level is determined based on the Y value of the coordinate in the current coordinate set, all coordinates of which the Y value of the coordinate in the current coordinate set is smaller than the Y value of the reference coordinate are classified into one set (i.e., the first next coordinate set), and all coordinates of which the Y value of the coordinate in the current coordinate set is larger than the Y value of the reference coordinate are classified into one set (i.e., the second next coordinate set). For example, the current coordinate set is { (1, 2), (3, 4), (5, 2), (2, 6), (5, 5) }, the reference coordinate determined with the Y value is (3, 4), and the next coordinate set is the set { (1, 2), (5, 2) } and the set { (3, 4), (2, 6), (5, 5) }.

Step S3023, determining the reference coordinates of the next level according to the magnitudes of the coordinate values in the next coordinate set.

Wherein the next level is less than the current level. Specifically, the process of determining the reference coordinate of the next level according to the magnitude of the coordinate value in the next coordinate set is similar to the above step S3021, that is, the next coordinate set may be used as the current coordinate set to determine the reference coordinate, which is not described in detail herein.

Step S3024, creating a reference coordinate classification table based on the reference coordinates of the current level and the reference coordinates of the next level.

Specifically, a plurality of reference coordinates can be obtained through the steps, and then a reference coordinate classification table is obtained. It should be noted that the coordinates may be micron coordinates, taking the shape of each chip on the wafer as a rectangle as an example, for example, the coordinates of a certain chip are (3, 4), the length of the chip of the wafer is 1600 microns, and the width of the chip is 700 microns, then the coordinates of the chip may be (4800, 2800).

For ease of understanding, step S302 is further described below with specific examples.

First, the coordinates of all the chips tested in the wafer are determined, and then the set of the coordinates of all the chips tested (denoted as set 0) is classified based on the reference coordinates, in this embodiment, the odd-numbered classifications are based on the X-coordinate values, and the even-numbered classifications are based on the Y-coordinate values.

First classification: comparing the X values of the coordinate values of all the tested chips, selecting the coordinate corresponding to the X value at the most middle position as a reference coordinate, and marking the coordinate as (X ₁,Y₁). After the reference coordinates are determined, all coordinates in set 0 having coordinate values less than X ₁ are placed in set 1, and all coordinates in set 0 having coordinate values greater than or equal to X ₁ are placed in set 2. The subscript of the reference coordinate is the grade corresponding to the reference coordinate. At this time, set 0 is the current coordinate set, and set 1 and set 2 are the next coordinate sets.

Second classification: for the set 1, comparing the Y values of all the coordinate values, selecting the coordinate corresponding to the most middle Y value as the reference coordinate, marking as (X ₁₁,Y₁₁), putting all the coordinates with Y values smaller than Y ₁₁ in the set 1 into the set 3, and putting all the coordinates with Y values larger than or equal to Y ₁₁ in the set 1 into the set 4. At this time, set 1 is the current coordinate set, and sets 3 and 4 are the next coordinate sets.

For the set 2, comparing the Y values of all the coordinate values, selecting the coordinate corresponding to the most middle Y value as the reference coordinate, marking as (X ₁₂,Y₁₂), putting all the coordinates with Y values smaller than Y ₁₂ in the set 2 into the set 5, and putting all the coordinates with Y values larger than or equal to Y ₁₁ in the set 2 into the set 6.

Third classification: for the set 3, comparing the magnitudes of X values in the coordinate values of all the tested chips, selecting the coordinate corresponding to the most middle X value as a reference coordinate, marking as (X ₁₁₁,Y₁₁₁), putting all the coordinates with X values smaller than X ₁₁₁ in the set 3 into the set 7, and putting all the coordinates with X values larger than or equal to X ₁₁₁ in the set 3 into the set 8.

For the set 4, comparing the magnitudes of X values in the coordinate values of all the tested chips, selecting the coordinate corresponding to the most middle X value as a reference coordinate, marking as (X ₁₁₂,Y₁₁₂), putting all the coordinates with X values smaller than X ₁₁₂ in the set 4 into the set 9, and putting all the coordinates with X values larger than or equal to X ₁₁₂ in the set 4 into the set 10.

For the set 5, comparing the magnitudes of the X values in the coordinate values of all the tested chips, selecting the coordinate corresponding to the most middle X value as a reference coordinate, marking as (X ₁₂₁,Y₁₂₁), putting all the coordinates with X values smaller than X ₁₂₁ in the set 5 into the set 11, and putting all the coordinates with X values larger than or equal to X ₁₂₁ in the set 5 into the set 12.

For the set 6, comparing the magnitudes of the X values in the coordinate values of all the tested chips, selecting the coordinate corresponding to the most middle X value as the reference coordinate, marking as (X ₁₂₂,Y₁₂₂), putting all the coordinates with the X values smaller than X ₁₂₂ in the set 6 into the set 13, and putting all the coordinates with the X values larger than or equal to X ₁₂₂ in the set 6 into the set 14. And similarly, classifying all chips to be tested according to the rule, and obtaining a reference coordinate classification table shown in table 1.

Table 1 reference coordinate classification table

Step S303, determining at least one reference coordinate from the reference coordinate classification table according to the coordinates of the chip to be tested.

Specifically, the step S303 includes:

Step S3031, comparing the reference coordinates with the coordinates of the chip to be tested in order according to the level sequence, and determining the reference coordinates meeting the requirements under each level.

Wherein, the more the classification times of the coordinate set, the lower the level of the reference coordinate.

Step S3032, the first N reference coordinates in the first order are determined as at least one reference coordinate.

The first order is an order in which the reference coordinates meeting the requirements are arranged from small to large according to the corresponding grades, N is an integer greater than or equal to 1, that is, N is greater than or equal to 1, N is a preset value, and can be set according to practical situations, for example, N can be 2, 3, 4 or 5. By way of example, the at least one reference coordinate may include a lowest-level reference coordinate and a next lowest-level reference coordinate corresponding to the chip under test.

Step S303 of the present embodiment is exemplarily described as a specific example.

For example, N is 3, the coordinates of the chip to be tested are (X _a,Y_b), and the coordinates in the relation table are sequentially compared, the X value is compared when the number of comparison is odd, the Y value is compared when the number of comparison is even, specifically, the first comparison is compared with (X ₁,Y₁), and if X _a＞X₁, then (X _a,Y_b) is continued to be compared with (X ₁₂,Y₁₂); a second comparison, if Y _a＜Y₁₂, then compare (X _a,Y_b) with (X ₁₂₁,Y₁₂₁); a third comparison, if X _a＜X₁₂₁, then (X _a,Y_b) is continued with (X ₁₂₁₁,Y₁₂₁₁); fourth comparison, if Y _a＞Y₁₂₁₁, (X _a,Y_b) is continued to be compared with (X ₁₂₁₁₂,Y₁₂₁₁₂).

If (X ₁₂₁₁₂,Y₁₂₁₁₂) does not exist, the reference coordinates satisfying the requirements are (X ₁₂₁₁,Y₁₂₁₁）、（X₁₂₁,Y₁₂₁）、（X₁₂,Y₁₂) and (X ₁,Y₁）,（X₁₂₁₁,Y₁₂₁₁) with a rank 1211, (X ₁₂₁,Y₁₂₁) with a rank 121, (X ₁₂,Y₁₂) with a rank 12 and (X ₁,Y₁) with a rank 1, wherein the higher the value of the rank corresponds to the lower the rank. At this time, the first order may be (X ₁₂₁₁,Y₁₂₁₁）、（X₁₂₁,Y₁₂₁）、（X₁₂,Y₁₂) and (X ₁,Y₁), and the at least one reference coordinate may be (X ₁₂₁₁,Y₁₂₁₁）、（X₁₂₁,Y₁₂₁) and (X ₁₂,Y₁₂).

In other embodiments, the reference coordinate with the lowest level in the first order, the other reference coordinate with the same level as the reference coordinate with the lowest level, and the reference coordinate with the next lowest level may be determined as at least one reference coordinate, for example, (X ₁₂₁₁,Y₁₂₁₁）,（X₁₂₁₂,Y₁₂₁₂) and (X ₁₂₁,Y₁₂₁) may be determined as at least one reference coordinate in the above example, that is, the reference coordinates of three chips to be tested closest to the chip to be tested are respectively (X ₁₂₁₁,Y₁₂₁₁）,（X₁₂₁,Y₁₂₁）,（X₁₂₁₂,Y₁₂₁₂).

Step S304, determining the state related chip of the chip to be tested according to at least one reference coordinate.

Please refer to step S103 in the embodiment shown in fig. 1 in detail, which is not described herein.

In step S305, the status flag of the status-related chip is determined as the status flag of the chip to be tested.

Please refer to step S104 in the embodiment shown in fig. 1 in detail, which is not described herein.

According to the wafer testing method provided by the embodiment, the reference coordinates are determined according to the coordinate values in the coordinate set of the tested chip in the wafer, the coordinate set is classified based on the reference coordinates, the reference coordinates of the classified coordinate set are determined, and the reference coordinate classification table can be created by analogy, so that at least one tested chip which is close to the tested chip can be more quickly and accurately determined based on the reference coordinate classification table. The sizes of the reference coordinates and the coordinates of the chip to be tested are compared in sequence according to the rank order, and the reference coordinates corresponding to the tested chip which is close to the chip to be tested can be rapidly screened out from the reference coordinate classification table.

In this embodiment, a wafer testing method is provided, which can be used in the control device of the wafer testing device, and fig. 4 is a schematic flow chart of another wafer testing method according to an embodiment of the invention, as shown in fig. 4, and the method includes the following steps:

In step S401, when the error between the sampling test result and the full test result of the same lot of wafers is smaller than the preset error, the sampling size is determined according to the test result of the same lot of wafers.

The preset error is a preset value, for example, the preset error may be 5%, 6% or 8%.

For example, when there is a piece of defective area in the same lot of wafers, a defective area (designated as a target area) having the smallest area among the plurality of defective areas is determined, a minimum value of a distance between coordinates of a center point of the target area and coordinates of an edge point is determined, and is designated as S, and a sampling size is n×s, that is, a side length of the sampling area is n×s. Where n is determined according to the error between the sampling test result and the full test result of the wafers in the same batch, and n > 0, for example, n may be 0.5, 0.8, 1 or 2. The smaller the value of n, the more helpful it is to reduce the error between the sampled test results and the full test results for the same lot of wafers.

Illustratively, the sample size is a preset value when all of the chips on the same lot of wafers are acceptable.

In particular, a test factory typically has many lots of different wafers to be tested, and the manufacturing process of the same lot of wafers is the same, and the problems may be the same. For a certain batch of wafers to be tested, a plurality of wafers are generally sampled for testing, and each die (chip) on the wafer needs to be tested by a wafer tester during testing, and the testing result is reserved. For the wafer with disqualified testing in the area of the wafer, which represents that the wafer manufacturing process may have problems, the wafer in the same batch as the wafer can be tested by adopting the wafer testing method provided by the invention, and for the wafer with qualified testing of all chips, the wafer testing method provided by the invention can also be used for testing.

In step S402, the wafer is divided into a plurality of sampling areas according to the sampling size.

Step S403, testing at least one chip in the sampling area to determine a plurality of tested chips and status flags corresponding to the tested chips.

Specifically, the whole wafer is divided integrally according to the sampling size to obtain a plurality of sampling areas, at least one chip is determined from each sampling area, the determined at least one chip is tested by a wafer testing machine, and the test result is recorded. Wherein the test results may be characterized by status markers.

In some alternative embodiments, the status flag is used not only to determine whether the chip is acceptable, but also to characterize the cause of the chip failure in the event that the chip is unacceptable. For example, after each chip on the wafer is tested, if the test is qualified, the state is marked as Bin1 (sorting 1), if the test is not qualified, different marks are performed according to the type of the reason of the failure, for example, the test is not qualified due to the gain index, the state is marked as Bin2, the test is not qualified due to the numerical control phase shift index, the state is marked as Bin3, the test is not qualified due to the phase shift precision index, the state is marked as Bin4, the test is not qualified due to the standing wave coefficient index, and the state is marked as Bin5.

Illustratively, as shown in fig. 5, the test results of the wafer may be represented by a sort map (BinMap), where the chips may represent different test results by different colors.

Step S404, obtaining the coordinates of the chip to be tested.

Step S405, determining at least one reference coordinate from the reference coordinate classification table according to the coordinates of the chip to be tested.

Please refer to step S102 in the embodiment shown in fig. 1 in detail, which is not described herein.

Step S406, determining the state related chip of the chip to be tested according to at least one reference coordinate.

Specifically, the step S406 includes:

Step S4061, determining the relative distance between the tested chip and the chip to be tested corresponding to each reference coordinate according to at least one reference coordinate and the coordinates of the chip to be tested.

In step S4062, the chip with the smallest relative distance is determined as the status-related chip of the chip to be tested.

For example, if the coordinates of the chip to be tested are (X _a,Y_b) and (X ₁₂₁₁,Y₁₂₁₁）,（X₁₂₁,Y₁₂₁) and (X ₁₂₁₂,Y₁₂₁₂), respectively, the relative distance S ₁ between the chip to be tested and the measured chip corresponding to (X ₁₂₁₁,Y₁₂₁₁) is determined according to (X _a,Y_b) and (X ₁₂₁₁,Y₁₂₁₁), the relative distance S ₂ between the chip to be tested and the measured chip corresponding to (X ₁₂₁,Y₁₂₁) is determined according to (X _a,Y_b) and (X ₁₂₁,Y₁₂₁), and the relative distance S ₃ between the chip to be tested and the measured chip corresponding to (X ₁₂₁₂,Y₁₂₁₂) is determined according to (X _a,Y_b) and (X ₁₂₁₂,Y₁₂₁₂). And then selecting the minimum value in S ₁、S₂、S₃, wherein the tested chip corresponding to the coordinate corresponding to the minimum value is the state related chip of the chip to be tested.

Under the condition that the relative distances are equal, the measured chip corresponding to the coordinate with the smaller X value is selected as the state related chip of the chip to be measured.

Step S407, determining the state mark of the state-related chip as the state mark of the chip to be tested.

According to the wafer testing method provided by the embodiment, under the condition that errors of sampling test results and full-test results of wafers in the same batch are smaller than preset errors, the sampling size is determined according to the test results of the wafers in the same batch, the wafers are divided into a plurality of sampling areas according to the sampling size, at least one chip in the sampling areas is tested, and a plurality of tested chips and state marks corresponding to the tested chips are determined. By determining the position of the tested chip in the mode, the accuracy of the test result of the wafer to be tested, which is determined based on the tested chip, can be improved. Meanwhile, according to the test result of the tested chip closest to the chip to be tested, the test result of the chip to be tested is determined, and the accuracy of the test result of the wafer can be further improved.

In this embodiment, a wafer testing apparatus is further provided, and the apparatus is used to implement the foregoing embodiments and preferred embodiments, and will not be described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

The present embodiment provides a wafer testing apparatus, as shown in fig. 6, including:

the acquiring module 601 is configured to acquire coordinates of a chip to be tested, where the wafer includes a plurality of chips to be tested and a plurality of tested chips, and the tested chips are configured with status marks, where the status marks are used to characterize whether the chips are qualified;

The first determining module 602 is configured to determine at least one reference coordinate from a reference coordinate classification table according to coordinates of a chip to be tested, where the reference coordinate classification table includes a plurality of reference coordinates, the plurality of reference coordinates correspond to the plurality of coordinate sets one to one, the coordinate sets are sets of coordinates of at least one tested chip, the reference coordinates are coordinates of one of the corresponding coordinate sets, and a distance between the at least one reference coordinate and the coordinates of the chip to be tested is less than a preset distance;

a second determining module 603, configured to determine a state-related chip of the chip to be tested according to at least one reference coordinate, where the state-related chip is a tested chip corresponding to one of the reference coordinates;

A third determining module 604, configured to determine the status flag of the status-related chip as the status flag of the chip to be tested.

In some alternative embodiments, the apparatus further comprises:

And the creating module is used for creating a reference coordinate classification table according to the coordinates of the tested chips in the wafer.

In some alternative embodiments, the creation module includes:

The first determining unit is used for determining the reference coordinate of the current level according to the coordinate value in the current coordinate set, wherein the current coordinate set is the set of the coordinates of the tested chip;

The classifying unit is used for classifying the current coordinate set according to the reference coordinates of the current level to obtain a plurality of next coordinate sets;

A second determining unit, configured to determine a reference coordinate of a next level according to a magnitude of the coordinate values in the next coordinate set, where the next level is smaller than the current level;

and the first creating unit is used for creating a reference coordinate classification table according to the reference coordinate of the current level and the reference coordinate of the next level.

In some alternative embodiments, the first determining module 602 includes:

the third determining unit is used for sequentially comparing the plurality of reference coordinates with the coordinates of the chip to be tested according to the grade sequence and determining the reference coordinates meeting the requirements under each grade;

And a fourth determining unit configured to determine the first N reference coordinates in the first order as at least one reference coordinate, where the first order is an order in which the reference coordinates satisfying the requirement are arranged in corresponding levels from small to large, and N is an integer greater than or equal to 1.

In some alternative embodiments, the second determining module 603 includes:

a fifth determining unit, configured to determine, according to at least one reference coordinate and the coordinates of the chip to be tested, a relative distance between the tested chip and the chip to be tested corresponding to each reference coordinate;

and a sixth determining unit for determining the tested chip with the smallest relative distance as the state related chip of the chip to be tested.

In some alternative embodiments, the status flag is also used to characterize the cause of the chip failure in the event of the chip failure.

In some alternative embodiments, the apparatus further comprises:

A fourth determining module, configured to determine a sampling size according to the test result of the same lot of wafers when the error between the sampling test result of the same lot of wafers and the full test result is less than a preset error;

the dividing module is used for dividing the wafer into a plurality of sampling areas according to the sampling size;

and the test module is used for testing at least one chip in the sampling area to determine a plurality of tested chips and corresponding state marks of the tested chips.

Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.

The wafer test apparatus in this embodiment is presented in the form of a functional unit, where the unit refers to an Application SPECIFIC INTEGRATED Circuit (ASIC), a processor and a memory that execute one or more software or firmware programs, and/or other devices that can provide the above-described functions.

The embodiment of the invention also provides computer equipment, which is provided with the wafer testing device shown in the figure 6.

Referring to fig. 7, fig. 7 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, as shown in fig. 7, the computer device includes: one or more processors 710, memory 720, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 710 is illustrated in fig. 7.

Processor 710 may be a central processor, a network processor, or a combination thereof. The processor 710 may further include a hardware chip, among other things. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.

Wherein the memory 720 stores instructions executable by the at least one processor 710 to cause the at least one processor 710 to perform methods that implement the embodiments described above.

Memory 720 may include a storage program area that may store an operating system, at least one application program required for functionality, and a storage data area; the storage data area may store data created according to the use of the computer device, etc. In addition, memory 720 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 720 optionally includes memory located remotely from processor 710, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Memory 720 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; memory 720 may also include a combination of the above types of memory.

The computer device also includes a communication interface 730 for the computer device to communicate with other devices or communication networks.

The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the claims.

Claims

1. A method of testing a wafer, the method comprising:

Acquiring coordinates of a chip to be tested, wherein a wafer comprises a plurality of chips to be tested and a plurality of tested chips, and the tested chips are configured with state marks which are used for representing whether the chips are qualified or not;

Creating a reference coordinate classification table according to the coordinates of the tested chips in the wafer, wherein the reference coordinate classification table comprises a plurality of reference coordinates, the reference coordinates are in one-to-one correspondence with a plurality of coordinate sets, the coordinate sets are sets of coordinates of at least one tested chip, and the reference coordinates are coordinates of one of the corresponding coordinate sets;

Determining at least one reference coordinate from a reference coordinate classification table according to the coordinates of the chip to be tested, wherein the distance between the at least one reference coordinate and the coordinates of the chip to be tested is smaller than a preset distance, and determining at least one reference coordinate from the reference coordinate classification table according to the coordinates of the chip to be tested comprises: sequentially comparing the reference coordinates with the coordinates of the chip to be tested according to a grade order, and determining the reference coordinates meeting the requirements under each grade; determining the first N reference coordinates in a first sequence as the at least one reference coordinate, wherein the first sequence is the sequence of the reference coordinates meeting the requirements arranged from small to large according to the corresponding grade, and N is an integer greater than or equal to 1;

determining a state related chip of the chip to be tested according to the at least one reference coordinate, wherein the state related chip is a tested chip corresponding to one of the reference coordinates;

and determining the state mark of the state-related chip as the state mark of the chip to be tested.

2. The method of claim 1, wherein the reference coordinates are configured with a hierarchy, the creating the reference coordinate classification table from coordinates of the tested chips in the wafer comprising:

Determining a reference coordinate of a current level according to the coordinate values in a current coordinate set, wherein the current coordinate set is a set of coordinates of a tested chip;

Classifying the current coordinate set according to the reference coordinates of the current level to obtain a plurality of next coordinate sets;

Determining a reference coordinate of a next level according to the coordinate values in the next coordinate set, wherein the next level is smaller than the current level;

and creating the reference coordinate classification table according to the reference coordinates of the current level and the reference coordinates of the next level.

3. The method according to claim 1 or 2, wherein said determining a state-related chip of said chip under test based on said at least one reference coordinate comprises:

determining the relative distance between the tested chip corresponding to each reference coordinate and the chip to be tested according to the at least one reference coordinate and the coordinates of the chip to be tested;

and determining the tested chip with the smallest relative distance as the state related chip of the chip to be tested.

4. The method according to claim 1 or 2, wherein the status flag is further used to characterize the cause of a chip failure in case of a chip failure.

5. The method according to claim 1 or 2, characterized in that before the acquiring the coordinates of the chip to be tested, the method further comprises:

under the condition that the errors of the sampling test result and the full-test result of the wafers in the same batch are smaller than the preset errors, determining the sampling size according to the test result of the wafers in the same batch;

dividing the wafer into a plurality of sampling areas according to the sampling size;

and testing at least one chip in the sampling area to determine the plurality of tested chips and the state marks corresponding to the tested chips.

6. A wafer testing apparatus, the apparatus comprising:

The wafer comprises a plurality of chips to be tested and a plurality of tested chips, wherein the tested chips are configured with state marks, and the state marks are used for representing whether the chips are qualified or not;

The system comprises a creation module, a detection module and a detection module, wherein the creation module is used for creating a reference coordinate classification table according to the coordinates of the chips to be detected in the wafer, the reference coordinate classification table comprises a plurality of reference coordinates, the reference coordinates are in one-to-one correspondence with a plurality of coordinate sets, the coordinate sets are sets of the coordinates of at least one chip to be detected, and the reference coordinates are the coordinates of one of the corresponding coordinate sets to be detected;

The first determining module is configured to determine at least one reference coordinate from a reference coordinate classification table according to the coordinates of the chip to be tested, where a distance between the at least one reference coordinate and the coordinates of the chip to be tested is smaller than a preset distance, and determining at least one reference coordinate from the reference coordinate classification table according to the coordinates of the chip to be tested includes: sequentially comparing the reference coordinates with the coordinates of the chip to be tested according to a grade order, and determining the reference coordinates meeting the requirements under each grade; determining the first N reference coordinates in a first sequence as the at least one reference coordinate, wherein the first sequence is the sequence of the reference coordinates meeting the requirements arranged from small to large according to the corresponding grade, and N is an integer greater than or equal to 1;

the second determining module is used for determining a state related chip of the chip to be tested according to the at least one reference coordinate, wherein the state related chip is a tested chip corresponding to one of the reference coordinates;

And the third determining module is used for determining the state mark of the state-related chip as the state mark of the chip to be tested.

7. A computer device, comprising:

A memory and a processor in communication with each other, the memory having stored therein computer instructions which, upon execution, cause the processor to perform the method of any of claims 1 to 5.

8. A computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method of any one of claims 1 to 5.