CN116821027A - Computing device - Google Patents

Abstract

An embodiment of the present application provides a computing device, including: the mainboard comprises a central processing unit and a mainboard side connector; the main board side connector is connected with the central processing unit and used for receiving and outputting signals provided by the central processing unit; an input-output (IO) board including an IO board-side connector; the IO board side connector is used for receiving and outputting signals provided by the main board side connector; a first cable; the first cable is used for connecting the main board side connector and m IO board side connectors, wherein m is more than or equal to 2; wherein the signal provided by the central processing unit comprises a high-speed signal; the bandwidth of the high-speed signal output by the motherboard-side connector is equal to the sum of the bandwidths of the high-speed signals output by the m IO board-side connectors. According to the computing device, through the first cable, the switching between the mainboard-side connector with the larger bandwidth and the IO board-side connectors with the smaller bandwidth is realized, and the bandwidth resource utilization rate is improved.

Description

Computing device

Technical Field

The present application relates to the field of computing technologies, and in particular, to a computing device.

Background

The connector conversion is performed between a main board and an Input/Output (IO) board of the computing device by adopting a cable. Based on different bandwidth demands, the mainboard-side connector can be connected with an IO side board connector with the same bandwidth as the mainboard-side connector, and also can be connected with an IO side board connector with a bandwidth lower than the mainboard-side connector.

Current cables can support one-to-one conversion between connectors of different bandwidths, for example, a motherboard-side connector with bandwidth X16 can be connected with an IO board-side connector with bandwidth X8 through the cable. This reduced bandwidth use wastes bandwidth resources of the motherboard side connector.

Disclosure of Invention

The embodiment of the application provides a computing device which is used for improving the utilization rate of bandwidth resources.

The embodiment of the application provides a computing device, which comprises a main board, wherein the main board comprises a central processing unit and a main board side connector; the main board side connector is connected with the central processing unit and used for receiving and outputting signals provided by the central processing unit; an input-output (IO) board including an IO board-side connector; the IO board side connector is used for receiving and outputting signals provided by the main board side connector; the first cable is used for connecting the main board side connector with m IO board side connectors, wherein m is more than or equal to 2; wherein the signal provided by the central processing unit comprises a high-speed signal; the bandwidth of the high-speed signal output by the motherboard-side connector is equal to the sum of the bandwidths of the high-speed signals output by the m IO board-side connectors.

The computing device provided by the embodiment of the application can realize the switching between the mainboard-side connector with larger bandwidth and the IO board-side connectors with smaller bandwidth through the first cable, so that the bandwidth resource utilization rate of the mainboard-side connector is improved, more IO board-side connectors can be provided, and the multi-interface requirement of a user is met.

In some implementations, the bandwidths of the high-speed signals output by the m IO board-side connectors are all the same.

The above further defines the bandwidth of the high-speed signals output by the m IO board side connectors.

In some implementations, the computing device further includes a base input output system chip; the basic input/output system chip is electrically connected with the central processing unit and is used for configuring an output mode of the high-speed signal; the central processing unit is used for outputting the high-speed signal into m sub-high-speed signals based on the output mode, and the sum of bandwidths of the m sub-high-speed signals is equal to the bandwidth of the high-speed signal; the main board side connector comprises m high-speed signal pins which are used for respectively receiving and outputting m sub-high-speed signals provided by the central processing unit; each IO board side connector comprises a high-speed signal pin for receiving and outputting sub-high-speed signals; the first cable comprises m high-speed signal wires, wherein the m high-speed signal wires are used for connecting m high-speed signal pins of the main board side connector with high-speed signal pins of the m IO board side connector in a one-to-one correspondence mode.

The above provides the transfer of the high-speed signal, and the output mode of the high-speed signal is configured through the basic input/output chip, so that the high-speed signal with larger bandwidth is distributed into a plurality of sub-high-speed signals with smaller bandwidth, and the sub-high-speed signals are respectively output to the plurality of IO board side connectors through the first cable by the main board side connector.

In some implementations, the high speed signal and the sub-high speed signal are PCIE signals. The PCIE signals with larger bandwidth can be distributed into a plurality of PCIE signals with smaller bandwidth through the basic input/output chip.

In some implementations, the signal provided by the central processor further includes a first signal; the computing device further includes a programmable logic device; the input end of the programmable logic device is connected with the central processing unit and is used for receiving a first signal provided by the central processing unit; the output end of the programmable logic device is connected with the main board side connector and is used for outputting m first signals; the main board side connector comprises m first signal pins, and the m first signal pins of the main board side connector are used for respectively receiving and outputting m first signals output by the programmable logic device; each IO board side connector comprises a first signal pin which is used for receiving and outputting a first signal output by the main board side connector; the first cable comprises m first signal wires, wherein the m first signal wires are used for connecting m first signal pins of the mainboard side connector with first signal pins of the m IO board side connector in a one-to-one correspondence manner.

The above provides a method for processing the first signals by using the programmable logic circuit, so that the motherboard side connector can output a plurality of first signals, so as to ensure that each IO board side connector can receive the first signals.

In some implementations, the signal provided by the central processor further includes a first number of second signals; the main board side connector comprises a first number of second signal pins for receiving and outputting second signals; each IO board-side connector includes a second number of second signal pins for receiving and outputting a second signal; the first number is m times the second number; the first cable comprises a first number of second signal wires, and the first number of second signal wires are used for connecting the first number of second signal pins of the mainboard-side connector with the second number of second signal pins of the m IO board-side connectors in a one-to-one correspondence manner.

The above provides a one-to-one connection of signal pins by using signal lines when the number of signal pins of the main board side connector outputting the second signal and the number of signal pins of the IO board side connector outputting the second signal satisfy the m-fold relationship.

In some implementations, the second signal is a power signal that provides a preset voltage.

The above provides a second signal, typically a plurality of power signals provided by the central processing unit.

In some implementations, the signal provided by the central processor further includes a third signal; the main board side connector comprises a third number of third signal pins for receiving and outputting a third signal; the IO board side connector comprises a third number of third signal pins for receiving and outputting a third signal; the first cable comprises a third number of third signal lines, each third signal line comprising a first end and m second ends; the first ends of the third signal wires are connected with the third signal pins of the mainboard-side connector, and the m second ends of the third signal wires are connected with the third signal pins of the m IO board-side connectors in a one-to-one correspondence mode.

The above provides a signal processing method for implementing duplication and distribution of a third signal by using a third signal line having a plurality of second terminals when the number of signal pins for outputting the third signal of the main board side connector is the same as the number of signal pins for outputting the third signal of the IO board side connector.

In some implementations, the signal provided by the central processor further includes a fourth signal; the main board side connector comprises a fourth signal pin for receiving and outputting a fourth signal; the IO board side connector comprises a transfer pin and a fourth signal pin, wherein the fourth signal pin is used for receiving and outputting a fourth signal; the first cable comprises a fourth signal wire, a first end of the fourth signal wire is connected with a fourth signal pin of the mainboard-side connector, and a second end of the fourth signal wire is connected with a transfer pin of one of the IO board-side connectors; the computing equipment also comprises a road expansion chip, and the road expansion chip is arranged on the IO board; the input end of the road expansion chip is connected with the transfer pin and is used for receiving the fourth signals output by the main board side connector, and the output end of the road expansion chip is connected with the m IO board side connectors and is used for outputting m fourth signals; the fourth signal pins of the m IO board side connectors are used for respectively receiving and outputting m fourth signals output by the circuit expansion chip.

The method for processing the fourth signal by using the path expanding chip is provided, the path expanding chip is enabled to receive the fourth signal output by the main board side connector by using the transfer pin of the IO board side connector, and the path expanding chip is utilized to copy the fourth signal to output a plurality of fourth signals, so that each IO board side connector can receive the fourth signal.

In some implementations, m has a value of 2; the bandwidth of the high-speed signal output by the main board side connector is X16; the bandwidth of the high-speed signal output by the IO board side connector is X8.

The implementation mode that the value of m is 2 is limited, namely the computing device can realize the switching between one mainboard-side connector and two IO board-side connectors, and the waste of bandwidth resources of the mainboard-side connectors is avoided. Alternatively, a motherboard-side connector having a bandwidth of X16 and an IO board-side connector having a bandwidth of X8 are exemplified.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

FIG. 1 is a schematic diagram of a computing device architecture according to an embodiment of the present application;

fig. 2 is a schematic diagram of a transmission manner of a high-speed signal according to an embodiment of the present application;

fig. 3 is a schematic diagram of a transmission manner of a first signal according to an embodiment of the present application;

fig. 4 is a schematic diagram of a transmission manner of a fourth signal according to an embodiment of the present application;

FIG. 5 is a schematic diagram of another computing device architecture according to an embodiment of the present application;

fig. 6 is a schematic diagram of signal connection of a computing device through a first cable according to an embodiment of the present application.

Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. The drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but rather to illustrate the inventive concepts to those skilled in the art by reference to the specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application.

The following describes the technical scheme of the present application and how the technical scheme of the present application solves the above technical problems in detail with specific embodiments. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present application will be described below with reference to the accompanying drawings.

Generally, a computing device includes a main board, an Input/Output (IO) board, and a central processing unit (central processing unit, CPU) located on the main board. Wherein, be provided with mainboard side connector on the mainboard, be provided with IO board side connector on the IO board, mainboard side connector passes through the cable with IO board side connector and realizes the switching.

Based on different bandwidth demands, the mainboard-side connector can be connected with an IO side board connector with the same bandwidth as the mainboard-side connector, and also can be connected with an IO side board connector with a bandwidth lower than the mainboard-side connector. The cable in the related art can support one-to-one conversion between connectors with different bandwidths, for example, a motherboard-side connector with a bandwidth of X16 can be connected with an IO board-side connector with a bandwidth of X8 through the cable. This reduced bandwidth use wastes bandwidth resources of the motherboard side connector.

Fig. 1 is a schematic diagram of a computing device architecture according to an embodiment of the present application. As shown in fig. 1, the computing device 100 includes: a main board 10, an input-output board (hereinafter, referred to as an IO board) 20, and a first cable 30. The motherboard 10 includes a central processor 11 and a motherboard-side connector 12. The motherboard-side connector 12 is connected to the central processing unit 11, and is configured to receive and output signals provided by the central processing unit 11. The IO board 20 includes an IO board side connector 21; the IO board side connector 21 is for receiving and outputting a signal supplied from the motherboard side connector 12. The first cable 30 is used for connecting the motherboard connector 12 and m IO board connectors 21, where m is 2 or more. The signals provided by the central processor 11 include high-speed signals; the bandwidth of the high-speed signal output from the main board side connector 12 is equal to the sum of the bandwidths of the high-speed signals output from the m IO board side connectors 21.

Alternatively, the computing device may be a server, desktop computer, or other communication device requiring a connector for transfer. The embodiment of the application is described by taking a server as an example.

Optionally, the high-speed signal is exemplified by a high-speed serial computer expansion bus standard (peripheral component interconnect express, abbreviated as PCIE) signal, and bandwidths of the PCIE signal have multiple specifications such as X1, X2, X4, X8, and X16.

In some implementations, one or more central processors 11 may be included on the motherboard 10 of the computing device 100, and one or more motherboard-side connectors 12 may be included, wherein each central processor may be correspondingly connected with one or more motherboard-side connectors 12. The computing device may include one or more IO boards 20, on each of which one or more IO board-side connectors 21 may be disposed. One of the motherboard side connectors 12 may be correspondingly connected with one or more of the IO board side connectors 21.

According to the computing device 100 provided by the embodiment of the application, through the first cable 30, the switching between one main board side connector with larger bandwidth and a plurality of IO board side connectors with smaller bandwidth can be realized, so that the bandwidth resource utilization rate of the main board side connector is improved, and meanwhile, more IO board side connectors can be provided, and the multi-interface requirement of a user is met. Taking the motherboard side connector 12 with the bandwidth of X16 as an example, the first cable 30 in the embodiment of the present application is adopted to perform conversion of connectors with different bandwidths, and the motherboard side connector 12 can be connected with two IO board side connectors 21 with the bandwidth of X8, so that waste of bandwidth resources is avoided, and bandwidth resource utilization rate when connectors with different bandwidths perform conversion is improved.

In some implementations, the bandwidths of the high-speed signals output by the m IO board-side connectors 21 are all the same. For example, when m is 2, the high-speed signal output from the main board side connector 12 is X16 bandwidth, and the high-speed signals output from both the IO board side connectors 21 are X8 bandwidth. For another example, when m is 4, the high-speed signals output from the main board side connector 12 are X16 bandwidth, and the high-speed signals output from the four IO board side connectors 21 are X4 bandwidth.

In other implementations, the bandwidth of the high-speed signals output by the m IO board-side connectors 21 is not uniform. For example, when m takes a value of 3, the high-speed signal output from the main board side connector 12 is X16 bandwidth, and the high-speed signals output from the three IO board side connectors 21 are X8 bandwidth, X4 bandwidth, and X4 bandwidth, respectively.

Further, it is known that the bandwidth of the high-speed signal output from the main board side connector 12 is equal to the sum of the bandwidths of the high-speed signals output from the m IO board side connectors 21.

Fig. 2 is a schematic diagram of a transmission manner of a high-speed signal according to an embodiment of the present application, as shown in fig. 2, the computing device further includes a basic input output system (Basic Input Output System, abbreviated as BIOS) chip (hereinafter abbreviated as BIOS chip) 13. The BIOS chip 13 is electrically connected to the CPU 11 for configuring the output mode of the high-speed signal. In some examples, the BIOS chip 13 is disposed on the motherboard 10 and is electrically connected to the central processor 11. The central processor 11 is configured to output the high-speed signal as m sub-high-speed signals based on the output mode, the sum of bandwidths of the m sub-high-speed signals being equal to the bandwidth of the high-speed signal. The motherboard-side connector 12 includes m high-speed signal pins 120 for respectively receiving and outputting m sub-high-speed signals provided by the central processing unit; each IO board side connector 21 includes one high-speed signal pin 120 for receiving and outputting sub-high-speed signals; the first cable includes m high-speed signal lines 31, which are used for connecting m high-speed signal pins 120 of the motherboard side connector with high-speed signal pins 120 of the m IO board side connector in a one-to-one correspondence. In fig. 2, m has a value of 2, and at this time, one main board side connector 12 is connected to two IO board side connectors 21 via two high-speed signal lines 31.

Specifically, the PCIE signal is taken as an example for both the high-speed signal and the sub-high-speed signal. As illustrated in fig. 2, in the case where the bandwidth of the high-speed signal is X16, the BIOS chip may configure the output mode of the high-speed signal as the output modes of X8 and X8; accordingly, the central processor 11 will output 2 sub high speed signals "pcie_x8" with a bandwidth of X8 based on the output mode. Two sub high-speed signals "pcie_x8" are respectively output to the two high-speed signal pins 120 of the motherboard-side connector 12; the first cable 30 is provided with two high-speed signal lines 31 for correspondingly connecting the two high-speed signal pins 120 of the main board side connector 12 and the high-speed signal pins 120 of the two IO board side connectors 21, so that two sub-high-speed signals "pcie_x8" are respectively output to the two IO board side connectors 21.

In another example, when m takes a value of 4, the BIOS chip may further configure the output mode of the high-speed signal as the output modes of X4, and X4; accordingly, the central processing unit 11 will output 4 sub-high speed signals with bandwidth X4 based on the output mode, denoted as "pcie_x4"; the first cable 30 is provided with four high-speed signal lines 31 for correspondingly connecting the four high-speed signal pins 120 of the motherboard side connector 12 and the high-speed signal pins 120 of the four IO board side connectors 21, so that four sub-high-speed signals "pcie_x4" are respectively output to the four IO board side connectors 21.

In yet another example, when m takes a value of 3, the BIOS chip may further configure the output mode of the high-speed signal as X4, and X8 output modes; accordingly, based on the output mode, the central processor 11 will output 2 sub-high speed signals with bandwidth X4 and 1 sub-high speed signal with bandwidth X8, where the sub-high speed signal with bandwidth X4 is denoted as "pcie_x4" and the sub-high speed signal with bandwidth X8 is denoted as "pcie_x8". The first cable 30 is provided with three high-speed signal lines 31 for correspondingly connecting the three high-speed signal pins 120 of the motherboard-side connector 12 and the high-speed signal pins 120 of the three IO board-side connectors 21, so that two sub high-speed signals "pcie_x4" and one sub high-speed signal "pcie_x8" are respectively and correspondingly output to the three IO board-side connectors 21.

It can be seen that the number of pins of the main board side connector for receiving and outputting the sub high speed signals is determined by the output mode of the high speed signals. The motherboard connector may have a free pin, and may be suspended when not needed, and may be configured to output a sub-high-speed signal when needed. Therefore, the signal pins of the motherboard-side connector can be flexibly configured to provide a required number of high-speed signal pins, so as to adapt to different numbers of IO board-side connectors.

In addition to the high-speed signals, the central processor also provides other signals, such as a power signal for powering, a spurious signal with control functions of resetting, waking up, etc. The first cable is provided with corresponding signal wires for connecting the signal pins of the main board side connector with the signal pins of the IO board side connector.

The following describes the signal processing manner of other signals provided by the central processing unit.

In some implementations, the signal provided by the central processor further includes a first signal; each IO board side connector comprises a first signal pin for receiving and outputting a first signal, and the main board side connector comprises m first signal pins for receiving and outputting the first signal respectively. Alternatively, the first signal may be a PERST signal with a reset function, and may also be a pcie_wake signal with a function of waking up the device from a sleep state. In the case that the cpu provides one first signal, m first signals need to be generated based on one first signal to satisfy the requirements of m IO board side connectors.

Fig. 3 is a schematic diagram of a transmission manner of a first signal according to an embodiment of the present application. As shown in fig. 3, the computing device 100 further includes a programmable logic device (Programmable Logic Device, PLD for short) 14; the input end of the programmable logic device 14 is connected with the central processing unit 11 and is used for receiving a first signal provided by the central processing unit 11; an output terminal of the programmable logic device 14 is connected to the motherboard-side connector 12 for outputting m first signals. In fig. 3, m has a value of 2. The motherboard-side connector 12 includes m first signal pins 121, and the m first signal pins 121 of the motherboard-side connector 12 are configured to receive and output m first signals output by the programmable logic device 14, respectively. Each of the IO board-side connectors 21 includes a first signal pin 121 for receiving and outputting the first signal output from the motherboard-side connector 12. The first cable includes m first signal lines 32, and the m first signal lines 32 are used for connecting m first signal pins 121 of the motherboard side connector 12 and first signal pins 121 of the m IO board side connectors 21 in a one-to-one correspondence.

Here, the first signal pin 121 has a signal transmission function, and the first signal pin 121 of the main board side connector 12 has a function of receiving the first signal supplied from the cpu 11 and also has a function of outputting the first signal to the IO board side connector 21. The first signal pin 121 of the IO board-side connector 21 has a function of receiving the first signal output from the main board-side connector 12 and also has a function of outputting the first signal to the back-end connection device.

The programmable logic device 14 may be a complex programmable logic device (Complex Programmable Logic Device, abbreviated as CPLD); CPLD may implement more complex logic functions than PLDs. The signal is duplicated in advance through the device chip with the signal duplication function, and the signals with the required quantity are duplicated. It will be appreciated that the m first signals output by the programmable logic device 14 are identical to the first signals received by the central processor 11.

Further, the idle pins of the main board side connector can be configured to be first signal pins for outputting the first signals, so that the main board side connector is provided with m first signal pins, and the main board side connector can be connected with the first signal pins of m IO board side connectors in a one-to-one correspondence manner, so that signal transmission loss is reduced to a certain extent, and the transmission effect is better.

In some implementations, the signals provided by the central processor 11 further include a first number of second signals, and the motherboard-side connector 12 includes a first number of second signal pins for receiving and outputting the second signals; each IO board side connector 21 includes a second number of second signal pins for receiving and outputting a second signal; the first number is m times the second number. The first cable 30 includes a first number of second signal lines for connecting the first number of second signal pins of the motherboard side connector 12 with the second number of second signal pins of the m IO board side connectors 21 in one-to-one correspondence.

The number of the second signal pins on the motherboard side connector 12 is equal to the sum of the numbers of the second signal pins on the m IO board side connectors 21, that is, the motherboard side connector 12 can provide a sufficient number of the second signal pins to realize one-to-one connection with the second signal pins of the m IO board side connectors 21 without signal duplication.

In some examples, the second signal may be a power signal providing a preset voltage. The motherboard-side connector 12 is exemplified by a dual-density loose-joint bus connector (Union Bus Connector Double density, abbreviated as UBCDD) of a bandwidth X16, hereinafter abbreviated as "X16 UBCDD connector". The IO board side connector 21 is exemplified by a card-edge connector (Card Electromechanical Connector, abbreviated as CEM) of a bandwidth X8, hereinafter abbreviated as "X8 CEM connector".

For example, the X8 CEM connector may require 6 power signals for providing 12V voltage, and the X16UBCDD connector may provide 12 power signals for providing 12V voltage, where the first number is 12, the second number is 6, m is 2, and the first number is 2 times the second number. Thus, the 12V power signal pin of the X16UBCDD connector and the 12V power signal pins of the two X8 CEM connectors may be correspondingly connected through the second signal line, without signal duplication.

For another example, the X8 CEM connector may also require 3 power signals for providing 3.3V, and the X16UBCDD connector may provide 6 power signals for providing 3.3V, where the first number is 6, the second number is 3, and m is 2, and the first number is 2 times the second number. Therefore, the 3.3V power signal pin of the X16UBCDD connector and the 3.3V power signal pins of the two X8 CEM connectors can be correspondingly connected through the second signal line, and signal copying is not required.

Further, in other examples, the second signal may also be a clock signal. The X8 CEM connector requires 2 sets of 100 megahertz (MHz) clock signals and the X16UBCDD connector can provide 4 sets of 100MHz clock signals, a first number of 4, a second number of 2, m of 2, and a first number of 2 times the second number. Thus, the clock signal pins of the X16UBCDD connector and the clock signal pins of the two X8 CEM connectors may be correspondingly connected through the second signal line.

In some implementations, the signals provided by the central processor 11 further include a third signal, and the motherboard-side connector 12 includes a third number of third signal pins for receiving and outputting the third signal; the IO board side connector 21 includes a third number of third signal pins for receiving and outputting a third signal; the first cable comprises a third number of third signal lines, each third signal line comprising a first end and m second ends; the first ends of the third signal lines are connected to the third signal pins of the motherboard-side connector 12, and the m second ends of the third signal lines are connected to the third signal pins of the m IO board-side connectors 21 in one-to-one correspondence.

Specifically, the motherboard-side connector 12 has only one third signal pin for receiving and outputting the third signal, and the third signal pins of the motherboard-side connector 12 are connected to the third signal pins of the m IO board-side connectors 21 through the third signal line having the plurality of second ends, so that the m IO board-side connectors 21 can each receive the third signal.

In some examples, the third signal may be a power signal. The X8 CEM connector requires 1 power signal for providing a 3.3V dc voltage and the X16UBCDD connector may provide 1 power signal for providing a 3.3V dc power signal, where the third number is equal to 1. Thus, the 3.3V dc power signal pin of the X16UBCDD connector and the 3.3V power signal pins of the two X8 CEM connectors may be connected by a third signal line having a first end and two second ends, wherein the first end is connected to the 3.3V dc power signal pin of the X16UBCDD connector and the two second ends are connected to the 3.3V power signal pins of the two X8 CEM connectors, respectively.

In the actual design process, when the motherboard side connector 12 cannot provide a sufficient number of third signal pins to realize one-to-one connection with the third signal pins of the IO board side connector 21, the connection may be realized using the third signal line having multiple ends as described above.

Fig. 4 is a schematic diagram of a connection manner of a fourth signal according to an embodiment of the present application. In some implementations, the signal provided by the central processor further includes a fourth signal. Alternatively, the fourth signal may be an I2C (Inter-Integrated Circuit) serial bus signal of a baseboard management controller (Baseboard Management Controller, abbreviated as BMC), denoted as "BMC-I2C".

As shown in fig. 4, the motherboard side connector 12 includes a fourth signal pin 124 for receiving and outputting a fourth signal "BMC-I2C"; the IO board side connector 21 includes a transfer pin 123 and a fourth signal pin 124 for receiving and outputting a fourth signal "BMC-I2C". The first cable 30 includes a fourth signal line 34, a first end of the fourth signal line 34 is connected to the fourth signal pin 124 of the motherboard-side connector 12, and a second end of the fourth signal line 34 is connected to the transfer pin 123 of one of the IO board-side connectors 21.

Alternatively, the fourth signal line 34 may be connected between the main board side connector 12 and the IO board side connector 21 located above on the IO board in fig. 4; the fourth signal line 34 may also be connected between the main board side connector 12 and the IO board side connector 21 located below on the IO board in fig. 4.

The computing device 100 further includes a road expansion chip 22, where the road expansion chip 22 is disposed on the IO board 20; the input end of the path expansion chip 22 is connected with the transfer pin 123 and is used for receiving a fourth signal BMC-I2C output by the main board side connector 12, and the output end of the path expansion chip 22 is connected with m IO board side connectors 21 and is used for outputting m fourth signals BMC-I2C; the fourth signal pins 124 of the m IO board-side connectors 21 are configured to respectively receive and output m fourth signals "BMC-I2C" output by the circuit-expanding chip 22.

In summary, in some implementations, signal pins of the plurality of IO board connectors are commonly connected to one signal pin of the motherboard connector through signal lines of the plurality of second ends; in other implementations, the device chip with the signal copying function copies the signals in advance to copy the signals with the required quantity, and uses the idle pins of the main board side connector to output the signals, that is to say, the main board side connector provides a plurality of signal pins to output the same signals, so that the signal pins of the plurality of IO board side connectors can be connected with the plurality of signal pins of the main board side connector in a one-to-one correspondence manner.

Comparing the two implementation modes, the signal processing mode adopting a plurality of second-end signal wires can adapt to the signal pins of a fewer mainboard-side connector compared with the signal processing mode adopting a device chip to copy signals in advance; compared with the signal processing mode adopting multi-terminal signal wires, the signal processing mode adopting the device chip to copy signals in advance can improve the signal transmission effect. In the actual design process, the corresponding signal processing mode can be selected according to the type of the signal, and the embodiment of the application is not limited.

Fig. 5 is a schematic diagram of another computing device architecture according to an embodiment of the present application, including a motherboard 10, an IO board 20, and a cpu 11 located on the motherboard 10. Illustratively, two central processors 11 are shown in fig. 5, each central processor 11 is connected to four X16UBCDD connectors 125, and each X16UBCDD connector 125 is correspondingly connected to two X8 CEM connectors 211 through a first cable 30 provided by an embodiment of the present application.

The application realizes the switching between the mainboard side connector with larger bandwidth and the IO board side connectors with smaller bandwidth through the first cable 30 and the signal processing in the implementation modes, and compared with the bandwidth reduction using scheme of carrying out one-to-one switching on connectors with different bandwidths in the related technology, the bandwidth resource using rate of the mainboard side connector is improved, a plurality of IO board side connectors with more bandwidth are provided, and the multi-interface requirement of users is met.

In addition, the circuit design of the motherboard side connector is not changed, the motherboard side connector of the embodiment of the application can be suitable for a connector conversion scheme of one-to-one connection with the IO board side connector with the same bandwidth, and the compatibility of the motherboard side connector can be improved by using the first cable provided by the embodiment of the application and the connector conversion scheme of one-to-many connection with a plurality of IO board side connectors with smaller bandwidth for signal processing in the implementation modes.

The first cable is illustrated in one specific embodiment. Fig. 6 is a schematic diagram of a computing device signal connection through a first cable according to an embodiment of the present application, illustrating the various signals involved between the X16UBCDD connector 125 and the two X8 CEM connectors 211.

As shown in fig. 6, the first cable 30 includes a plurality of signal lines for transmitting a plurality of signals as within a dashed box. The following describes each signal and the signal processing method adopted by the same.

VCC_12V is used to provide a voltage of 12V, and in some implementations VCC_12V represents the supply voltage at the positive side of the power supply for the collector of the transistor or the drain of the field effect transistor. There are 12 vcc_12v signal power signal pins on the X16UBCDD connector 125 and 6 vcc_12v signal power signal pins on each X8 CEM connector 211. That is, the X16UBCDD connector provides a sufficient number of power signal pins, and no signal replication is required, and the power signal pins of the vcc_12v signals of the X16UBCDD connector and the power signal pins of the vcc_12v signals of the two X8 CEM connectors are correspondingly connected by using 12 second signal lines in the signal processing manner of the aforementioned second signals.

Vcc_3v3 is used to provide a voltage of 3.3V, and in some implementations vcc_3v3 represents the supply positive terminal for the supply voltage of the transistor collector or fet drain. There are 6 power signal pins for vcc_3v3 signals on the X16UBCDD connector 125 connector and 3 power signal pins for vcc_3v3 signals on each X8 CEM connector 211. That is, the X16UBCDD connector provides a sufficient number of power signal pins, and no signal replication is required, and the power signal pins of the vcc_3v3 signal of the X16UBCDD connector and the power signal pins of the vcc_3v3 signal of the two X8 CEM connectors can be correspondingly connected by using 6 second signal lines in the signal processing manner of the aforementioned second signal.

Stby_3v3 is used to supply a dc voltage of 3.3V. The X16UBCDD connector 125 is provided with 1 stby_3v3 signal power signal pin, and each X8 CEM connector 211 is also provided with 1 stby_3v3 signal power signal pin. That is, the X16UBCDD connector cannot provide a sufficient number of power signal pins, and signal replication is required, and the signal processing manner of the aforementioned third signal may be adopted, and 1 third signal line having two second ends is used to correspondingly connect the power signal pins of the stby_3v3 signal of the X16UBCDD connector with the power signal pins of the stby_3v3 signals of the two X8 CEM connectors. In the actual design process, the power signal pins of the two X8 CEM connectors 211 share one power signal pin of the X16UBCDD connector 125, and whether the driving capability of the signal can meet the post-stage load is considered.

The 4 sets of 100M clock signals are divided into CLK_100M_DP/DN [0:1] signals and CLK_100M_DP/DN [2:3] signals. Two clock signal pins are disposed on the X16UBCDD connector 125 connector, and 1 clock signal pin is disposed on each X8 CEM connector 211, so that signal replication is not required, and the two clock signal pins of the X16UBCDD connector and the clock signal pins of the two X8 CEM connectors can be correspondingly connected by using 2 second signal lines in the signal processing manner of the second signal.

Further, the X16 bandwidth PCIE signal may be divided into two pcie_x8 signals as shown in fig. 6, and the two pcie_x8 signals are sent to the two X8 CEM connectors 211, and the specific implementation manner of the pcie_x8 signal may refer to the foregoing description of the high-speed signal line and the BIOS chip, which is not repeated.

Further, a plurality of spurious signals are also involved between the X16UBCDD connector 125 and the X8 CEM connector 211. The PERST0 signal, PCIE_WAKE0 signal, PWR_BRAK0 signal, PRSNT_N0 signal, TYPE0_ [ A: C ] signal, TPLE_DET0 signal, CLK_REQ0 signal, HP_I2C0 signal connected to the first X8 CEM connector as shown in FIG. 6. Which are auxiliary signals for PCIE signals, and specific functions may refer to related PCIE specifications. The spurious signals can adopt the signal processing mode of the first signals, the signals are duplicated by using a programmable logic device, and then the idle pins on the X16UBCDD connector are utilized to enable the X16UBCDD connector to output two identical spurious signals, and then the two spurious signals are respectively transmitted to the two X8 CEM connectors by using the two first signal lines.

BMC-I2C signals, 1 BMC-I2C signal pin is provided on the X16UBCDD connector 125 connector, and 1 BMC-I2C signal pin is also provided on each X8 CEM connector 211. That is, the X16UBCDD connector cannot provide a sufficient number of signal pins of the BMC-I2C signal, and needs to perform signal replication, and the signal replication method of the fourth signal can be adopted, and the signal is replicated by using a circuit-expanding chip on the IO board, and the output end of the circuit-expanding chip is connected to the signal pins of the BMC-I2C signals on the two X8 CEM connectors 211.

In some implementations, the computing device may provide multiple X16UBCDD connectors, one possible implementation, i.e., all of the X16UBCDD connectors are correspondingly transitioned to two X8 CEM connectors, as shown in fig. 5; in another possible implementation, a portion of the X16UBCDD connectors are correspondingly transferred to two X8 CEM connectors, and another portion of the X16UBCDD connectors are correspondingly transferred to one X16 CEM connector, that is, the same server provides a motherboard-side connector interface corresponding to different IO board-side connectors. The high-speed interface configuration of the whole machine is more flexible.

In summary, according to the first cable provided by the embodiment of the application, the switching between the X16UBCDD connector and the 2X 8 CEM connectors is realized, the number of PCIE X8 standard interfaces is effectively increased, the multi-interface requirement of a customer is met, and the waste of broadband resources is avoided; because the original design of the mainboard side connector circuit is not changed, the connector conversion scheme that the UBCD connector is suitable for one-to-one switching of X16 CEM connectors with the same bandwidth can be realized, and the connector conversion scheme that the first cable and the signal processing in each implementation mode are suitable for one-to-many switching of 2X 8 CEM connectors can be also realized, so that the compatibility is improved; the connector adapter cable provided by the embodiment of the application enables the configuration of the high-speed interface of the whole machine to be more flexible, and the design of the main board and the IO board are shared, so that the development period and the development cost are effectively reduced.

Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. A computing device, comprising:

a motherboard including a central processor and a motherboard-side connector; the main board side connector is connected with the central processing unit and is used for receiving and outputting signals provided by the central processing unit;

an input-output (IO) board comprising an IO board-side connector; the IO board side connector is used for receiving and outputting signals provided by the main board side connector;

the first cable is used for connecting the mainboard-side connector with m IO board-side connectors, wherein m is more than or equal to 2;

wherein the signal provided by the central processing unit comprises a high-speed signal; the bandwidth of the high-speed signals output by the mainboard-side connector is equal to the sum of the bandwidths of the high-speed signals output by the m IO board-side connectors.

2. The computing device of claim 1, wherein bandwidths of high-speed signals output by the m IO board-side connectors are all the same.

3. The computing device of claim 1, wherein the computing device further comprises a basic input output system chip;

the basic input/output system chip is electrically connected with the central processing unit and is used for configuring the output mode of the high-speed signal;

the central processing unit is used for outputting the high-speed signal into m sub-high-speed signals based on the output mode, and the sum of bandwidths of the m sub-high-speed signals is equal to the bandwidth of the high-speed signal;

the main board side connector comprises m high-speed signal pins which are used for respectively receiving and outputting m sub-high-speed signals provided by the central processing unit; each IO board side connector comprises a high-speed signal pin which is used for receiving and outputting the sub-high-speed signals;

the first cable comprises m high-speed signal wires, wherein the m high-speed signal wires are used for connecting the m high-speed signal pins of the mainboard side connector with the m high-speed signal pins of the IO board side connector in a one-to-one correspondence mode.

4. The computing device of claim 3, wherein the high-speed signal and the sub-high-speed signal are PCIE signals.

5. The computing device of claim 1, wherein the signal provided by the central processor further comprises a first signal;

the computing device further includes a programmable logic device; the input end of the programmable logic device is connected with the central processing unit and is used for receiving the first signal provided by the central processing unit; the output end of the programmable logic device is connected with the main board side connector and is used for outputting m first signals;

the main board side connector comprises m first signal pins, and the m first signal pins of the main board side connector are used for respectively receiving and outputting m first signals output by the programmable logic device;

each IO board side connector comprises a first signal pin which is used for receiving and outputting a first signal output by the main board side connector;

the first cable comprises m first signal wires, wherein the m first signal wires are used for connecting m first signal pins of the mainboard side connector with m first signal pins of the IO board side connector in a one-to-one correspondence manner.

6. The computing device of claim 1, wherein the signal provided by the central processor further comprises a first number of second signals; the main board side connector comprises a first number of second signal pins for receiving and outputting the second signal; each of the IO board side connectors includes a second number of second signal pins for receiving and outputting the second signal; the first number is m times the second number;

the first cable comprises a first number of second signal wires, and the first number of second signal wires are used for connecting the first number of second signal pins of the mainboard-side connector with the second number of second signal pins of the m IO board-side connectors in a one-to-one correspondence mode.

7. The computing device of claim 6, wherein the second signal is a power signal that provides a preset voltage.

8. The computing device of claim 1, wherein the signal provided by the central processor further comprises a third signal; the main board side connector includes a third number of third signal pins for receiving and outputting the third signal; the IO board side connector comprises a third number of third signal pins for receiving and outputting the third signal;

the first cable comprises a third number of third signal lines, each of which comprises a first end and m second ends; the first ends of the third signal wires are connected with the third signal pins of the mainboard-side connector, and the m second ends of the third signal wires are connected with the m third signal pins of the IO board-side connector in a one-to-one correspondence mode.

9. The computing device of claim 1, wherein the signal provided by the central processor further comprises a fourth signal; the main board side connector comprises a fourth signal pin for receiving and outputting the fourth signal; the IO board side connector comprises a transfer pin and a fourth signal pin, wherein the fourth signal pin is used for receiving and outputting the fourth signal;

the first cable comprises a fourth signal wire, a first end of the fourth signal wire is connected with a fourth signal pin of the mainboard-side connector, and a second end of the fourth signal wire is connected with a transfer pin of one of the IO board-side connectors;

the computing equipment further comprises a road expansion chip, wherein the road expansion chip is arranged on the IO board; the input end of the path expansion chip is connected with the transfer pin and is used for receiving the fourth signals output by the main board side connector, and the output end of the path expansion chip is connected with m IO board side connectors and is used for outputting m fourth signals;

and the m fourth signal pins of the IO board side connector are used for respectively receiving and outputting the m fourth signals output by the road expansion chip.

10. The computing device of any of claims 1-9, wherein m has a value of 2; the bandwidth of the high-speed signal output by the main board side connector is X16; and the bandwidth of the high-speed signal output by the IO board side connector is X8.