CN116799015A - Array substrate, manufacturing method and display panel - Google Patents

Abstract

The disclosure provides an array substrate, a manufacturing method and a display panel, and relates to the technical field of display. The array substrate comprises a driving layer, wherein in the driving layer: the semiconductor layer comprises an active part of the transistor, wherein the active part comprises a non-conductive region, and a first conductor region and a second conductor region which are positioned at two sides of the non-conductive region; the gate metal layer includes a conductive portion, and an orthographic projection of the conductive portion covers at least an orthographic projection of the non-conductive region. In the embodiment of the disclosure, the orthographic projection of the conductive part covers the orthographic projection of the non-conductive region, so that when the transistor works, the area between the orthographic projection of the first switching sheet on the active part and the orthographic projection of the conductive part on the active part and the area between the orthographic projection of the second switching sheet on the active part and the orthographic projection of the conductive part on the active part are both conductive structures, so that the situation that large resistance exists between the first switching sheet and the conductive part and between the second switching sheet and the conductive part is avoided, and the performance of the transistor during the work is ensured.

Description

Array substrate, manufacturing method and display panel

Technical Field

The disclosure relates to the technical field of display, in particular to an array substrate, a manufacturing method and a display panel.

Background

The display panel has been widely used in electronic devices such as mobile phones, computers, televisions, etc., and with the rapid development of the display panel, the requirements of users on the picture display of the display panel are also increasing. In the related art, for a display panel including a transistor, various parameters of the transistor are generally adjusted to ensure performance of the transistor, thereby ensuring a picture display effect of the display panel. Such as adjusting the channel region size of the transistor, etc.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The invention aims to provide an array substrate, a manufacturing method and a display panel, which can improve the performance of a transistor and the picture display effect of the display panel.

According to an aspect of the present disclosure, there is provided an array substrate including: a substrate base plate and a driving layer, wherein the driving layer is formed with a transistor;

the driving layer includes: a semiconductor layer located on one side of the substrate and including an active portion of the transistor, the active portion including a non-conductive region and a conductive region, the conductive region including a first conductive region and a second conductive region located on both sides of the non-conductive region, respectively, at least a portion of the conductive region away from a surface of the substrate being higher than a surface of the non-conductive region away from the substrate in a direction perpendicular to the substrate;

The grid insulation layer is positioned on one side of the semiconductor layer, which is away from the substrate base plate, at least covers the non-conductive region and is provided with a first via hole and a second via hole;

the grid metal layer is positioned on one side, away from the substrate, of the grid insulating layer and comprises a conductive part, a first switching sheet and a second switching sheet, wherein the orthographic projection of the conductive part at least covers the orthographic projection of the non-conductive area, the first switching sheet passes through the first through hole to be connected with the first conductor area, and the second switching sheet passes through the second through hole to be connected with the second conductor area;

an interlayer dielectric layer which is positioned on one side of the gate metal layer, which is away from the substrate base plate, at least covers the conductive part, the first conductor region and the second conductor region, and is provided with a third via hole and a fourth via hole;

the source-drain metal layer is positioned on one side, away from the substrate, of the interlayer dielectric layer and comprises a first connecting sheet and a second connecting sheet, the first connecting sheet penetrates through the third through hole to be connected with the first switching sheet, and the second connecting sheet penetrates through the fourth through hole to be connected with the second switching sheet.

The array substrate according to any one of the present disclosure, wherein the first conductor region comprises a continuous first sub-conductor region and a continuous second sub-conductor region;

the second sub-conductor region is positioned between the first sub-conductor region and the non-conductive region, the surface of the second sub-conductor region away from the substrate is flush with the surface of the non-conductive region away from the substrate, and in the direction perpendicular to the substrate, the surface of the first sub-conductor region away from the substrate is higher than the surface of the non-conductive region away from the substrate.

The array substrate according to any one of the present disclosure, wherein the gate insulating layer covers the active portion, the gate insulating layer includes a first conductive hole, and an orthographic projection of the first conductive hole covers at least an orthographic projection of the second sub-conductor region.

The array substrate according to any one of the present disclosure, wherein the second conductor region includes a third sub-conductor region and a fourth sub-conductor region that are continuous;

the third sub-conductor region is located between the fourth sub-conductor region and the non-conductive region, the surface of the third sub-conductor region away from the substrate is flush with the surface of the non-conductive region away from the substrate, and in the direction perpendicular to the substrate, the surface of the fourth sub-conductor region away from the substrate is higher than the surface of the non-conductive region away from the substrate.

The array substrate according to any one of the present disclosure, wherein the gate insulating layer covers the active portion, the gate insulating layer further includes a second conductive via, and an orthographic projection of the second conductive via covers at least an orthographic projection of the third sub-conductor region.

According to any one of the array substrates disclosed in the disclosure, in the direction perpendicular to the substrate, the surface of the first conductor region far away from the substrate and the surface of the second conductor region far away from the substrate are higher than the surface of the non-conductor region far away from the substrate.

According to the array substrate of any one of the present disclosure, the gate insulating layer covers the active portion, and an edge of the orthographic projection of the conductive portion extends out of the edge of the orthographic projection of the non-conductive region.

According to an aspect of the present disclosure, there is provided a method of manufacturing an array substrate, the method including:

providing a substrate base plate;

manufacturing a semiconductor layer on one side of the substrate, wherein the semiconductor layer comprises an active part of a transistor, the active part comprises a non-conductive region and a conductive region, the conductive region comprises a first conductive region and a second conductive region which are positioned on two sides of the non-conductive region, and at least part of the conductive region away from the surface of the substrate is higher than the surface of the non-conductive region away from the substrate in the direction perpendicular to the substrate;

Manufacturing a gate insulating layer on one side of the semiconductor layer, which is away from the substrate, wherein the gate insulating layer at least covers the non-conductive region and is provided with a first via hole and a second via hole;

manufacturing a gate metal layer on one side of the gate insulating layer, which is away from the substrate, wherein the gate metal layer comprises a conductive part, a first switching sheet and a second switching sheet, the orthographic projection of the conductive part at least covers the orthographic projection of the non-conductive area, the first switching sheet passes through the first via hole to be connected with the first conductor area, and the second switching sheet passes through the second via hole to be connected with the second conductor area;

manufacturing an interlayer dielectric layer on one side of the gate metal layer, which is away from the substrate, wherein the interlayer dielectric layer at least covers the conductive part, the first conductor region and the second conductor region, and the interlayer dielectric layer is provided with a third via hole and a fourth via hole;

and manufacturing a source-drain metal layer on one side of the interlayer dielectric layer, which is away from the substrate, wherein the source-drain metal layer comprises a first connecting sheet and a second connecting sheet, the first connecting sheet passes through the third through hole to be connected with the first switching sheet, and the second connecting sheet passes through the fourth through hole to be connected with the second switching sheet.

A method according to any of the present disclosure, for fabricating a semiconductor layer on one side of the substrate base plate, comprising:

manufacturing a semiconductor layer on one side of the substrate base plate, and conducting the surface of an active part included in the semiconductor layer to obtain a conducting structure positioned on the surface of the active part;

carrying out local etching on the conductive structure to obtain a non-conductive region, and a first conductor region and a second conductor region which are positioned at two sides of the non-conductive region, wherein in the direction perpendicular to the substrate, the surface of the first conductor region far away from the substrate and the surface of the second conductor region far away from the substrate are higher than the surface of the non-conductive region far away from the substrate;

manufacturing a gate insulating layer on one side of the semiconductor layer away from the substrate base plate, wherein the gate insulating layer comprises: manufacturing a grid insulating layer on one side of the semiconductor layer, which is away from the substrate, wherein the grid insulating layer covers the active part and is provided with a first via hole and a second via hole;

manufacturing a gate metal layer on one side of the gate insulating layer, which is away from the substrate, and the manufacturing method comprises the following steps: and manufacturing the gate metal layer on one side of the gate insulating layer, which is away from the substrate, wherein the orthographic projection edge of the conductive part extends out of the orthographic projection edge of the non-conductive region, the first switching sheet penetrates through the first via hole to be connected with the first conductor region, and the second switching sheet penetrates through the first via hole to be connected with the first conductor region.

A method according to any of the present disclosure, for fabricating a semiconductor layer on one side of the substrate base plate, comprising:

manufacturing a semiconductor layer on one side of the substrate base plate, and conducting the surface of an active part included in the semiconductor layer to obtain a conducting structure positioned on the surface of the active part;

carrying out partial etching on the conductive structure to obtain an etching region, and a first subconductor region and a fourth subconductor region which are positioned at two sides of the etching region, wherein in the direction perpendicular to the substrate, the surface of the first subconductor region, which is far away from the substrate, and the surface of the fourth subconductor region, which is far away from the substrate, are higher than the surface of the etching region, which is far away from the substrate;

manufacturing a gate insulating layer on one side of the semiconductor layer away from the substrate base plate, wherein the gate insulating layer comprises: manufacturing a grid insulating layer on one side of the semiconductor layer, which is away from the substrate, wherein the grid insulating layer covers the active part and is provided with a first via hole and a second via hole;

manufacturing a gate metal layer on one side of the gate insulating layer, which is away from the substrate, and the manufacturing method comprises the following steps:

manufacturing a gate metal layer on one side of the gate insulating layer, which is away from the substrate, and filling the first via hole and the second via hole with the gate metal layer;

Etching the gate metal layer and the gate insulating layer to obtain a conductive part, a first switching piece and a second switching piece which are positioned on the gate metal layer, and a first conductive hole and a second conductive hole which are positioned on the gate insulating layer;

the orthographic projection of the conductive part is overlapped with the orthographic projection of the non-conductive region, the first transfer sheet passes through the first via hole to be connected with the first sub-conductor region, the second transfer sheet passes through the second via hole to be connected with the fourth sub-conductor region, the orthographic projection of the first conductive hole at least covers the orthographic projection of the region between the non-conductive region and the first sub-conductor region, and the second conductive hole at least covers the orthographic projection of the region between the non-conductive region and the fourth sub-conductor region;

before the interlayer dielectric layer is manufactured on the side, facing away from the substrate, of the gate metal layer, the method further comprises the following steps: and conducting the region between the non-conductive region and the first sub-conductor region and the region between the non-conductive region and the fourth sub-conductor region respectively to obtain a second sub-conductor region between the non-conductive region and the first sub-conductor region and a third sub-conductor region between the non-conductive region and the fourth sub-conductor region, wherein the second sub-conductor region is far away from the surface of the substrate and the surface of the third sub-conductor region far away from the substrate is flush with the surface of the non-conductive region far away from the substrate in the direction perpendicular to the substrate.

According to an aspect of the present disclosure, there is provided a display panel including the array substrate described in the above aspect.

The embodiment of the disclosure at least comprises the following technical effects:

in the embodiment of the disclosure, since the first conductor region and the second conductor region are continuous with the non-conductive region, the orthographic projection of the conductive portion covers the non-conductive region, so that when the transistor works, the area between the orthographic projection of the first switching sheet on the active portion and the orthographic projection of the conductive portion on the active portion and the area between the orthographic projection of the second switching sheet on the active portion and the orthographic projection of the conductive portion on the active portion are both in a conductor structure, thereby avoiding the situation of large resistance between the first switching sheet and the conductive portion and between the second switching sheet and the conductive portion, ensuring the performance of the transistor when working, and improving the picture display effect of the display panel comprising the array substrate.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

Fig. 1 is a schematic cross-sectional structure of an array substrate according to an embodiment of the disclosure.

Fig. 2 is a schematic cross-sectional view of the array substrate shown in fig. 1 after the active portion of the semiconductor layer is made conductive.

Fig. 3 is a schematic cross-sectional structure of the array substrate shown in fig. 1 after etching the conductive active portion.

Fig. 4 is a schematic cross-sectional structure of the array substrate shown in fig. 1 after the gate metal layer is fabricated and etched.

Fig. 5 is a schematic cross-sectional structure of another array substrate according to an embodiment of the disclosure.

Fig. 6 is a schematic cross-sectional view of the array substrate shown in fig. 5 after etching an active portion of a semiconductor layer.

Fig. 7 is a schematic cross-sectional structure of the array substrate shown in fig. 5 after manufacturing a gate metal layer.

Fig. 8 is a schematic cross-sectional structure of the array substrate shown in fig. 5 after the gate metal layer is fabricated and etched.

Fig. 9 is a schematic cross-sectional view of the array substrate shown in fig. 5 after the active portion of the semiconductor layer is secondarily conductive.

Fig. 10 is a flow chart of a manufacturing method of an array substrate according to an embodiment of the disclosure.

Fig. 11 is a flow chart illustrating another method for manufacturing an array substrate according to an embodiment of the disclosure.

Fig. 12 is a flowchart of another method for manufacturing an array substrate according to an embodiment of the disclosure.

Reference numerals:

100. an array substrate;

10. a substrate base; 20. a driving layer;

21. a buffer layer; 22. a semiconductor layer; 23. a gate insulating layer; 24. a gate metal layer; 25. an interlayer dielectric layer; 26. a source drain metal layer; 27. a flat layer;

221. an active part; 222. a non-conductive region; 223. a first conductor region; 224. a second conductor region; 225. a conductive structure;

2231. a first sub-conductor region; 2232. a second sub-conductor region; 2241. a third sub-conductor region; 2242. a fourth subconductor region;

231. a first via; 232. a second via; 233. a first conductive via; 234. a second conductive via;

241. a conductive portion; 242. a first tab; 243. a second switching piece;

251. a third via; 252. a fourth via;

261. a first connecting piece; 262. and a second connecting piece.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and do not limit the number of their objects.

In the present disclosure, a transistor refers to an element including at least three terminals of a gate, a drain, and a source. The transistor has a channel region between a drain (drain terminal, drain region, or drain electrode) and a source (source terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. The channel region refers to a region through which current mainly flows. In the case of using transistors of opposite types, the current direction during circuit operation, or the like, the functions of the "source" and the "drain" are sometimes interchanged. Thus, in this disclosure, "source" and "drain" may be interchanged. Structurally, the transistor may have a first pole, a second pole, and a control pole, wherein the gate of the transistor may act as the control pole of the transistor; one of the source and drain of the transistor may be the first pole of the transistor and the other may be the second pole of the transistor.

In this disclosure, the "on" state of a transistor refers to a state in which the source and drain of the transistor are in electrical connection. The "off state of the transistor refers to a state in which the source and drain of the transistor are electrically disconnected; it will be appreciated that when the transistor is turned off, it may still have leakage current.

The embodiment of the disclosure provides a display panel. The display panel includes an array substrate 100 and a light emitting layer, the array substrate 100 is formed with a plurality of pixel circuits, the light emitting layer is located at one side of the array substrate 100, and has a plurality of light emitting units, and one pixel circuit is connected with at least one corresponding light emitting unit (for example, one pixel circuit is connected with one corresponding light emitting unit). Thus, the corresponding light-emitting units can be driven to emit light through the pixel circuits, and the display of the picture can be realized.

The pixel circuit may be a 1T1C, 2T1C, 7T1C, or the like, as long as it can drive the corresponding at least one light emitting unit to emit light, which is not particularly limited in the embodiment of the present disclosure. nTmC denotes that one pixel circuit includes n transistors (denoted by the letter "T") and m capacitances Cst (denoted by the letter "C").

As shown in fig. 1, the array substrate 100 includes a transparent substrate 10 and a driving layer 20 disposed on one side of the substrate 10, the driving layer 20 is formed with a plurality of pixel circuits included in the array substrate 100, and the plurality of pixel circuits may be distributed in an array on the driving layer 20.

The substrate 10 may be, for example, a glass substrate, a quartz substrate, a plastic substrate, or other transparent hard or flexible substrate, which may be a single-layer or multi-layer structure. Taking a multilayer structure as an example, the substrate 10 includes a first PI (polyimide) layer, a first protective layer, a second PI (polyimide) layer, and a second protective layer, which are sequentially stacked from bottom to top, where the two protective layers are used to protect the PI layer and prevent damage to the PI layer by a subsequent process. The second protective layer is also covered with a buffer layer 21 which can block water and oxygen and block alkaline ions.

As shown in fig. 1, the driving layer 20 includes a buffer layer 21, a transistor layer, an interlayer dielectric layer 25, a source drain metal layer 26, and a planarization layer 27, which are sequentially distributed in a direction away from the substrate base plate 10. The transistor layer includes a semiconductor layer 22, a gate insulating layer 23, and a gate metal layer 24 laminated between a buffer layer 21 and an interlayer dielectric layer 25, and the positional relationship of the semiconductor layer 22 and the gate metal layer 24 may be determined according to the type of the transistor.

The material of the buffer layer 21 may be an inorganic insulating material such as silicon oxide or silicon nitride, and the buffer layer 21 may be one inorganic material layer or a plurality of inorganic material layers stacked. The semiconductor layer 22 may be used to form an active portion 221 of each transistor, each active portion 221 including a channel region and two connection portions (i.e., a source and a drain of the transistor) located on both sides of the channel region. Wherein the channel region can maintain the semiconductor characteristic, and the semiconductor materials corresponding to the two connecting parts are partially or completely conductive. The gate metal layer 24 may be used to form a wiring such as a scan line (the scan line forms a control electrode of a transistor in a region overlapping with a channel region of the active portion 221) and may also be used to form one plate of a capacitor. The source-drain metal layer 26 may be used to form power lines, data lines, sense lines, bond pads, etc., and may also be used to form another plate for forming a capacitor.

In some embodiments, the transistor layer may include one semiconductor layer 22, or may include two semiconductor layers 22. Illustratively, the drive layer 20 includes a layer of semiconductor layer 22, and is an oxide semiconductor layer 22. The transistor layer may include one gate metal layer 24, or may include two or three gate metal layers 24, and may be specifically set according to the number of layers of the semiconductor layer 22. It is to be understood that when the gate metal layer 24, the semiconductor layer 22, or the like has a multilayer structure, the gate insulating layer 23 in the transistor layer may be increased or decreased adaptively. Illustratively, the driving layer 20 includes an oxide semiconductor layer 22, a gate insulating layer 23, and a gate metal layer 24, which are sequentially stacked on a buffer layer 21.

In some embodiments, the driving layer 20 may include one source drain metal layer 26, and may also include two or three source drain metal layers 26. Illustratively, the drive layer 20 includes two source drain metal layers 26. In the case of the multi-layer source-drain metal layer 26, a passivation layer and/or an interlayer dielectric layer 25 is disposed between two adjacent source-drain metal layers 26, so as to insulate the two adjacent source-drain metal layers 26 through the interlayer dielectric layer 25.

In some embodiments, the light emitting unit may be an organic electroluminescent diode, a micro-luminescent diode, a quantum dot-organic electroluminescent diode, a quantum dot luminescent diode, or other types of light emitting units.

Illustratively, in some embodiments, the light emitting unit is an organic electroluminescent diode, and the display panel is an OLED display panel. As follows, an example of a possible structure of the light emitting unit is described using the light emitting unit as an organic electroluminescent diode.

The light emitting unit includes an anode block, a light emitting functional layer, and a cathode block sequentially stacked in a direction away from the array substrate 100, and the light emitting functional layer may include an organic electroluminescent material layer, and may further include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

In addition, the light-emitting layer further comprises a pixel definition layer arranged on one side of the driving layer 20 away from the substrate 10, the pixel definition layer is provided with pixel openings corresponding to the light-emitting units one by one, each light-emitting unit is located in the corresponding pixel opening, the anode block comprises an exposed area exposed at the corresponding pixel opening and an area covered by the pixel definition layer, and the exposed area of the anode block forms a light-emitting area of the corresponding light-emitting unit.

In some embodiments, the display panel may further include a thin film encapsulation layer. The thin film encapsulation layer is disposed at a side of the light emitting layer facing away from the array substrate 10, and may include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked.

The inorganic packaging layer can effectively block external moisture and oxygen, and avoid degradation of materials caused by invasion of the moisture and the oxygen into the organic light-emitting functional layer; the organic encapsulation layer is located between two adjacent inorganic encapsulation layers in order to achieve planarization and to attenuate stresses between the inorganic encapsulation layers.

The display panel is provided with a display area and a peripheral area positioned at the periphery of the display area, the edge of the inorganic encapsulation layer can be positioned at the peripheral area, and the edge of the organic encapsulation layer can be positioned between the edge of the display area and the edge of the inorganic encapsulation layer. Illustratively, the thin film encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on a side of the light emitting layer facing away from the array substrate 10.

In some embodiments, the display panel may further include a touch functional layer, where the touch functional layer is disposed on a side of the thin film encapsulation layer facing away from the array substrate 10, for implementing a touch operation of the display panel.

In the embodiment of the disclosure, for each film structure included in the driving layer 20 described above, as shown in fig. 1, the semiconductor layer 22 includes an active portion 221 of a transistor, the active portion 221 includes a non-conductive region 222 and a conductive region, the conductive region includes a first conductive region 223 and a second conductive region 224 respectively located at two sides of the non-conductive region 222, and at least a portion of the conductive region away from the surface of the substrate 10 is higher than the surface of the non-conductive region 222 away from the substrate 10 in a direction perpendicular to the substrate 10; the gate insulating layer 23 at least covers the non-conductive region 222 and has a first via 231 and a second via 232; the gate metal layer 24 includes a conductive portion 241, a first switching piece 242 and a second switching piece 243, wherein the orthographic projection of the conductive portion 241 at least covers the orthographic projection of the non-conductive region 222, the first switching piece 242 is connected with the first conductive region 223 through the first via 231, and the second switching piece 243 is connected with the second conductive region 224 through the second via 232; the interlayer dielectric layer 25 covers at least the conductive portion 241, the first conductor region 223, and the second conductor region 224, and has a third via 251 and a fourth via 252; the source-drain metal layer 26 includes a first connection tab 261 and a second connection tab 262, the first connection tab 261 is connected with the first connection tab 242 through the third via 251, and the second connection tab 262 is connected with the second connection tab 243 through the fourth via 252.

In the embodiment of the disclosure, since the first conductive region 223 and the second conductive region 224 are continuous with the non-conductive region 222, and the orthographic projection of the conductive portion 241 can cover the non-conductive region 222, when the transistor works, the area between the orthographic projection of the first switching piece 242 on the active portion 221 and the orthographic projection of the conductive portion 241 on the active portion 221 and the area between the orthographic projection of the second switching piece 243 on the active portion 221 and the orthographic projection of the conductive portion 241 on the active portion 221 are both conductive structures, so that the situation that a large resistance exists between the first switching piece 242 and the conductive portion 241 and between the second switching piece 243 and the conductive portion 241 is avoided, the performance of the transistor when the transistor works is ensured, and the image display effect of the display panel including the array substrate 100 is improved.

Wherein the first via 231 on the gate insulating layer 23 exposes a partial region of the first conductor region 223, and the second via 232 exposes a partial region of the second conductor region 224, so that the first switching piece 242 on the gate metal layer 24 can be directly connected to the first conductor region 223 through the first via 231, and the second switching piece 243 can be directly connected to the second conductor region 224 through the second via 232; the region of the conductive portion 241 overlapping the non-conductive region 222 forms a control electrode of the transistor, and since the orthographic projection of the conductive portion 241 at least covers the orthographic projection of the non-conductive region 222, the non-conductive region 222 on the active portion 221 can serve as a channel region of the transistor.

The orthographic projection of the conductive portion 241 included in the gate metal layer 24 is located in the orthographic projection of the gate insulating layer 23, so that the conductive portion 241 is prevented from directly contacting the first conductive region 223 and the second conductive region 224. In addition, the orthographic projection referred to in this disclosure refers to the projection on the substrate 10 along the thickness direction of the substrate 10, and the orthographic projection of the non-conductive region 222 referred to above refers to the projection of the non-conductive region 222 on the substrate 10 along the direction perpendicular to the substrate 10, for example.

In the embodiment of the present disclosure, the first conductor region 223 and the second conductor region 224 on the active portion 221 may be obtained by conducting a conductor on the surface of the active portion 221 included in the semiconductor layer 22. Specifically, the active portion 221 included in the semiconductor layer 22 may be formed by conducting the semiconductor layer 22 after the semiconductor layer 22 is completed, or the active portion 221 may be formed by conducting the semiconductor layer 22 for the first time after the gate metal layer 24 is completed, and the active portion 221 may be exposed outside the conductive portion 241 of the gate metal layer 24 and not conducted for the second time after the gate metal layer 24 is completed.

In some embodiments, as shown in fig. 1, in a direction perpendicular to the substrate 10, the surface of the first conductor region 223 remote from the substrate 10 and the surface of the second conductor region 224 remote from the substrate 10 are both higher than the surface of the non-conductive region 222 remote from the substrate 10.

After the semiconductor is fabricated, as shown in fig. 2, the surface of the active portion 221 of the semiconductor layer 22, which is far from the substrate 10, may be subjected to a conductive process to obtain a conductive structure 225 on the entire surface of the active portion 221; as shown in fig. 3, the conductive structure 225 is partially etched to obtain a non-conductive region 222 (i.e., a region corresponding to the etched region on the conductive structure 225) and a first conductive region 223 and a second conductive region 224 (i.e., regions on the conductive structure 225 that are not etched) located at two sides of the non-conductive region 222, so as to ensure that, in a direction perpendicular to the substrate 10, a surface of the first conductive region 223 away from the substrate 10 and a surface of the second conductive region 224 away from the substrate 10 are higher than a surface of the non-conductive region 222 away from the substrate 10. In this way, the situation that a large resistance exists between the first connecting sheet 261 and the conductive portion 241 and between the second connecting sheet 262 and the conductive portion 241 can be avoided by only one conductive operation, so that the manufacturing process of the transistor is simplified, and the manufacturing efficiency is improved.

In the case where the surface of the first conductor region 223 far from the substrate 10 and the surface of the second conductor region 224 far from the substrate 10 are both higher than the surface of the non-conductive region 222 far from the substrate 10, when the gate insulating layer 23 and the gate metal layer 24 are formed on the side of the semiconductor layer 22 far from the substrate 10, as shown in fig. 4, the gate insulating layer 23 covers the active portion 221 of the semiconductor layer 22 and has the first via 231 and the second via 232, the conductive portion 241 of the gate metal layer 24 covers at least the non-conductive region 222 on the active portion 221, and the first switching tab 242 is connected to the first conductor region 223 through the first via 231, and the second switching tab 243 is connected to the second conductor region 224 through the second via 232.

In this way, the area between the front projection of the first switching piece 242 on the active portion 221 and the front projection of the conductive portion 241 on the active portion 221 of the gate metal layer 24 and the area between the front projection of the second switching piece 243 on the active portion 221 and the front projection of the conductive portion 241 on the active portion 221 are both conductive structures, so that the phenomenon of high resistance between the first switching piece 242, the second switching piece 243 and the conductive portion 241 is avoided.

Illustratively, as shown in fig. 4, the orthographic projected edge of the conductive portion 241 extends beyond the orthographic projected edge of the non-conductive region 222. In this way, the region between the front projection of the first switching piece 242 on the active portion 221 and the front projection of the conductive portion 241 on the active portion 221, and the region between the front projection of the second switching piece 243 on the active portion 221 and the front projection of the conductive portion 241 on the active portion 221 are both conductive structures.

The projecting edge of the conductive portion 241 extends beyond the projecting edge of the non-conductive region 222, which means that the projecting edge of the conductive portion 241 extends beyond the projecting edge of the non-conductive region 222 in the longitudinal direction of the active portion 221 (i.e., the arrangement direction of the first conductive region 223, the non-conductive region 222, and the second conductive region 224), and at this time, the projecting edge of the conductive portion 241 and the projecting edge of the first conductive region 223 and the projecting edge of the second conductive region 224 both have overlapping regions.

In other embodiments, for the first conductor region 223 and the second conductor region 224 included in the conductive region, in the direction perpendicular to the substrate 10, it may be that one of the first conductor region 223 and the second conductor region 224 includes a first conductive portion having a part of the surface flush with the surface of the non-conductive region 222, and a second conductive portion having a part of the surface higher than the surface of the non-conductive region 222, and the other one is located farther from the entire surface of the substrate 10 than the surface of the non-conductive region 222 located farther from the substrate 10; it is also possible that the first conductor region 223 and the second conductor region 224 each include a first conductive portion having a part of the surface flush with the surface of the non-conductive region 222 away from the substrate 10, and a second conductive portion having a part of the surface higher than the surface of the non-conductive region 222 away from the substrate 10.

In the case where the first conductive region 223 and/or the second conductive region 224 include the first conductive portion and the second conductive portion, the size of the non-conductive region 222 in the length direction of the active portion 221 may be appropriately reduced, and thus the size of the conductive portion of the gate metal layer 24 in the extending direction of the active portion 221 may be reduced, so as to reduce the size of the transistor, thereby increasing the arrangement density of the transistor on the array substrate 100 and increasing the pixel density.

Specifically, in the case where the first conductor region 223 includes two conductive portions, as shown in fig. 5, the first conductor region 223 includes a continuous first sub-conductor region 2231 and a second sub-conductor region 2232, the second sub-conductor region 2232 is located between the first sub-conductor region 2231 and the non-conductive region 222, the surface of the second sub-conductor region 2232 is flush with the surface of the non-conductive region 222, and the surface of the first sub-conductor region 2231 away from the substrate 10 is higher than the surface of the non-conductive region 222 away from the substrate 10 in the direction perpendicular to the substrate 10. The succession of the first sub-conductor region 2231 and the second sub-conductor region 2232 refers to the succession in the length direction of the active portion 221. In this way, the occurrence of high resistance between the first switching piece 242 and the conductive portion 241 can be avoided.

After the semiconductor layer 22 is fabricated, as shown in fig. 2, the surface of the active portion 221 of the semiconductor layer 22 away from the substrate 10 may be first subjected to a conductive process to obtain a conductive structure 225 on the entire surface of the active portion 221; as shown in fig. 6, the conductive structure 225 is partially etched to obtain an etched region and a first sub-conductor region 2231 located at one side of the etched region (where a surface of the first sub-conductor region 2231 away from the substrate 10 is higher than a surface of the etched region). Then, when the gate insulating layer 23 and the gate metal layer 24 are formed on the side of the semiconductor layer 22 facing away from the substrate 10, as shown in fig. 7, the gate insulating layer 23 covering the active portion 221 and having the first via 231 and the second via 232 is formed, then the gate metal layer 24 covering the gate insulating layer 23 and filling the first via 231 and the second via 232 is formed, and then the gate metal layer 24 and the gate insulating layer 23 are etched to obtain the conductive portion 241, the first switching piece 242 and the second switching piece 243 located on the gate metal layer 24, and the first conductive hole 233 located on the gate insulating layer 23, as shown in fig. 8.

The first switching piece 242 is connected to the first sub-conductor region 2231 through the first via 231, the second switching piece 243 is connected to the fourth sub-conductor region 2242 through the second via 232, the conductive portion 241 covers only a partial area of the etched region (the partial area is the non-conductive region 222, and an area which is not conductive exists between the partial area and the first sub-conductor region 2231), and the first conductive hole 233 exposes an area which is not covered by the conductive portion 241 and is not conductive in the etched region. At this time, as shown in fig. 9, the region of the etched region which is not covered by the conductive portion 241 and is not conductive may be secondarily conductive through the first conductive via 233, so as to obtain a second sub-conductor region 2232 continuous with both the first sub-conductor region 2231 and the non-conductive region 222, that is, the orthographic projection of the first conductive via 233 covers at least the orthographic projection of the second sub-conductor region 2232. For example, the first conductive via 233 exposes only the region where the second sub-conductor region 2232 is located, that is, the orthographic projection of the first conductive via 233 coincides with the orthographic projection of the second sub-conductor region 2232; or as shown in fig. 7 or fig. 8, the area where the second sub-conductor region 2232 is exposed by the first conductive via 233, and a partial area of the first sub-conductor region 2231, that is, the front projection of the first conductive via 233 covers the front projection of the second sub-conductor region 2232, and there is an overlapping area with the front projection of the first sub-conductor region 2231.

In the case where the second conductor region 224 includes two conductive portions, as shown in fig. 5, the second conductor region 224 includes a third sub-conductor region 2241 and a fourth sub-conductor region 2242 in succession, the third sub-conductor region 2241 being located between the fourth sub-conductor region 2242 and the non-conductive region 222, the surface of the third sub-conductor region 2241 remote from the substrate 10 being flush with the surface of the non-conductive region 222 remote from the substrate 10, and the surface of the fourth sub-conductor region 2242 remote from the substrate 10 being higher than the surface of the non-conductive region 222 remote from the substrate 10 in the direction perpendicular to the substrate 10. The succession of the third sub-conductor region 2241 and the fourth sub-conductor region 2242 refers to the succession in the length direction of the active portion 221. Thus, the occurrence of high resistance between the second connecting member and the conductor portion can be avoided.

After the semiconductor layer 22 is fabricated, as shown in fig. 2, the surface of the active portion 221 of the semiconductor layer 22 away from the substrate 10 may be first subjected to a conductive process to obtain a conductive structure 225 on the entire surface of the active portion 221; as shown in fig. 6, the conductive structure 225 is partially etched to obtain an etched region and a fourth sub-conductor region 2242 located at one side of the etched region (in this case, a surface of the fourth sub-conductor region 2242 away from the substrate 10 is higher than a surface of the etched region). Then, when the gate insulating layer 23 and the gate metal layer 24 are formed on the side of the semiconductor layer 22 facing away from the substrate 10, as shown in fig. 7, the gate insulating layer 23 covering the active portion 221 and having the first via 231 and the second via 232 is formed, then the gate metal layer 24 covering the gate insulating layer 23 and filling the first via 231 and the second via 232 is formed, and then the gate metal layer 24 and the gate insulating layer 23 are etched to obtain the conductive portion 241, the first switching piece 242 and the second switching piece 243 located on the gate metal layer 24, and the second conductive hole 234 located on the gate insulating layer 23, as shown in fig. 8.

The first switching piece 242 is connected to the first sub-conductor region 2231 through the first via 231, the second switching piece 243 is connected to the fourth sub-conductor region 2242 through the second via 232, the conductive portion 241 covers only a partial area of the etched region (the partial area is the non-conductive region 222, and an area which is not conductive exists between the partial area and the fourth sub-conductor region 2242), and the second conductive hole 234 exposes an area which is not covered by the conductive portion 241 and is not conductive in the etched region. At this time, as shown in fig. 9, the region of the etched region which is not covered by the conductive portion 241 and is not conductive may be secondarily conductive through the second conductive via 234, so as to obtain a third sub-conductor region 2241 continuous with both the fourth sub-conductor region 2242 and the non-conductive region 222, that is, the orthographic projection of the second conductive via 234 covers at least the orthographic projection of the third sub-conductor region 2241. For example, the second conductive via 234 exposes only the region where the third sub-conductor region 2241 is located, that is, the orthographic projection of the second conductive via 234 coincides with the orthographic projection of the third sub-conductor region 2241; or as shown in fig. 7 or 8, the second conductive via 234 exposes the area where the third sub-conductor region 2241 is located, and a partial area of the fourth sub-conductor region 2242, that is, the orthographic projection of the second conductive via 234 covers the orthographic projection of the third sub-conductor region 2241, and there is an overlapping area with the orthographic projection of the fourth sub-conductor region 2242.

The embodiment of the disclosure also provides a manufacturing method of the array substrate, which is used for manufacturing the array substrate described in the above embodiment, and the specific structure of the array substrate can be described with reference to the above embodiment. As shown in fig. 10, the method includes the following steps S110 to S160.

Step S110, a substrate is provided.

In step S120, a semiconductor layer is fabricated on one side of the substrate, the semiconductor layer includes an active portion of a transistor, the active portion includes a non-conductive region and a conductive region, the conductive region includes a first conductive region and a second conductive region located on two sides of the non-conductive region, and at least a portion of the conductive region away from the surface of the substrate is higher than the surface of the non-conductive region away from the substrate in a direction perpendicular to the substrate.

Step S130, a gate insulating layer is manufactured on one side of the semiconductor layer, which is away from the substrate, wherein the gate insulating layer at least covers the non-conductive region and is provided with a first via hole and a second via hole.

Step S140, a gate metal layer is fabricated on a side of the gate insulating layer facing away from the substrate, where the gate metal layer includes a conductive portion, a first switching piece and a second switching piece, where the orthographic projection of the conductive portion at least covers the orthographic projection of the non-conductive region, the first switching piece passes through the first via hole to be connected with the first conductor region, and the second switching piece passes through the second via hole to be connected with the second conductor region.

And S150, manufacturing an interlayer dielectric layer on one side of the gate metal layer, which is away from the substrate, wherein the interlayer dielectric layer at least covers the conductive part, the first conductor region and the second conductor region, and the interlayer dielectric layer is provided with a third via hole and a fourth via hole.

And step 160, manufacturing a source-drain metal layer on one side of the interlayer dielectric layer, which is away from the substrate, wherein the source-drain metal layer comprises a first connecting sheet and a second connecting sheet, the first connecting sheet passes through the third through hole to be connected with the first switching sheet, and the second connecting sheet passes through the fourth through hole to be connected with the second switching sheet.

In the embodiment of the disclosure, the array substrate manufactured by the method can ensure that the region between the orthographic projection of the first switching sheet on the active part and the orthographic projection of the conductive part on the active part and the region between the orthographic projection of the second switching sheet on the active part and the orthographic projection of the conductive part on the active part are conductor regions when the transistor works, thereby avoiding the situation that large resistance exists between the first switching sheet and the conductive part and between the second switching sheet and the conductive part, further ensuring the performance of the transistor when the transistor works, and improving the picture display effect of the display panel comprising the array substrate.

In some embodiments, as shown in fig. 11, the step S120 includes the following steps S121 to S122, and correspondingly, the step S130 includes the following step S131, and the step S140 includes the following step S141.

Step S121, a semiconductor layer is formed on one side of the substrate, and the surface of the active portion included in the semiconductor layer is made conductive, thereby obtaining a conductive structure located on the surface of the active portion.

Step S122, carrying out partial etching on the conductive structure to obtain a non-conductive region, and a first conductor region and a second conductor region which are positioned at two sides of the non-conductive region, wherein in the direction perpendicular to the substrate, the surface of the first conductor region far away from the substrate and the surface of the second conductor region far away from the substrate are higher than the surface of the non-conductive region far away from the substrate.

Step S131, a gate insulating layer is manufactured on one side, away from the substrate, of the semiconductor layer, wherein the gate insulating layer covers the active part and is provided with a first via hole and a second via hole.

Step S141, a gate metal layer is manufactured on one side of the gate insulating layer, which is away from the substrate, the orthographic projection edge of the conductive part extends out of the orthographic projection edge of the non-conductive region, the first switching sheet passes through the first via hole to be connected with the first conductive region, and the second switching sheet passes through the first via hole to be connected with the first conductive region.

In the embodiment of the disclosure, the situation that large resistance occurs between the first switching sheet and the conductive part and between the second switching sheet and the conductive part can be avoided only through one-time conductive operation, so that the manufacturing process of the transistor is simplified, and the manufacturing efficiency is improved.

In other embodiments, as shown in fig. 12, the step S120 includes the following step S122-step S123, and correspondingly, the step S130 includes the following step S132, the step S140 includes the following step S142-step S143, and the following step S151 is further included before the step S150.

Step S123, a semiconductor layer is formed on one side of the substrate, and the surface of the active portion included in the semiconductor layer is made conductive, thereby obtaining a conductive structure located on the surface of the active portion.

Step S124, carrying out partial etching on the conductive structure to obtain an etching region, and a first sub-conductor region and a fourth sub-conductor region which are positioned at two sides of the etching region, wherein in the direction perpendicular to the substrate, the surface of the first sub-conductor region far away from the substrate and the surface of the fourth sub-conductor region far away from the substrate are higher than the surface of the etching region far away from the substrate.

Step S132, a gate insulating layer is manufactured on one side of the semiconductor layer, which is away from the substrate, wherein the gate insulating layer covers the active part and is provided with a first via hole and a second via hole.

Step S142, a gate metal layer is manufactured on one side, away from the substrate, of the gate insulating layer, and the gate metal layer fills the first via hole and the second via hole.

And step S143, etching the gate metal layer and the gate insulating layer to obtain a conductive part, a first switching piece and a second switching piece which are positioned on the gate metal layer, and a first conductive hole and a second conductive hole which are positioned on the gate insulating layer.

The orthographic projection of the conductive part coincides with the orthographic projection of the non-conductive region, the first transfer sheet passes through the first via hole to be connected with the first sub-conductor region, the second transfer sheet passes through the second via hole to be connected with the fourth sub-conductor region, the orthographic projection of the first conductive hole at least covers the orthographic projection of the region between the non-conductive region and the first sub-conductor region, and the second conductive hole at least covers the orthographic projection of the region between the non-conductive region and the fourth sub-conductor region.

And S151, conducting the areas between the non-conducting area and the first sub-conductor area and the fourth sub-conductor area respectively to obtain a second sub-conductor area and a third sub-conductor area, wherein the second sub-conductor area is positioned between the non-conducting area and the first sub-conductor area, and the third sub-conductor area is positioned between the non-conducting area and the fourth sub-conductor area.

In this embodiment of the disclosure, for the case that the first conductor region and/or the second conductor region includes two conductive portions, the size of the non-conductive region in the length direction of the active portion may be appropriately reduced, so that the size of the conductor portion of the gate metal layer in the extending direction of the active portion may be reduced, so as to reduce the size of the transistor, thereby improving the arrangement density of the transistors on the array substrate, and improving the pixel density.

It should be noted that, although the steps of the method for manufacturing an array substrate in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in the specific order or that all of the illustrated steps must be performed to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (11)

1. An array substrate, characterized by comprising: a substrate base plate and a driving layer, wherein the driving layer is formed with a transistor;

the driving layer includes: a semiconductor layer located at one side of the substrate base plate and comprising an active part of the transistor, wherein the active part comprises a non-conductive region and a conductive region, the conductive region comprises a first conductive region and a second conductive region which are respectively located at two sides of the non-conductive region, and at least part of the conductive region away from the surface of the substrate base plate is higher than the surface of the non-conductive region away from the substrate base plate in the direction perpendicular to the substrate base plate;

the grid insulation layer is positioned on one side of the semiconductor layer, which is away from the substrate base plate, at least covers the non-conductive region and is provided with a first via hole and a second via hole;

the grid metal layer is positioned on one side, away from the substrate, of the grid insulating layer and comprises a conductive part, a first switching sheet and a second switching sheet, wherein the orthographic projection of the conductive part at least covers the orthographic projection of the non-conductive area, the first switching sheet passes through the first through hole to be connected with the first conductor area, and the second switching sheet passes through the second through hole to be connected with the second conductor area;

An interlayer dielectric layer which is positioned on one side of the gate metal layer, which is away from the substrate base plate, at least covers the conductive part, the first conductor region and the second conductor region, and is provided with a third via hole and a fourth via hole;

the source-drain metal layer is positioned on one side, away from the substrate, of the interlayer dielectric layer and comprises a first connecting sheet and a second connecting sheet, the first connecting sheet penetrates through the third through hole to be connected with the first switching sheet, and the second connecting sheet penetrates through the fourth through hole to be connected with the second switching sheet.

2. The array substrate of claim 1, wherein the first conductor region comprises a continuous first sub-conductor region and second sub-conductor region;

the second sub-conductor region is positioned between the first sub-conductor region and the non-conductive region, the surface of the second sub-conductor region away from the substrate is flush with the surface of the non-conductive region away from the substrate, and in the direction perpendicular to the substrate, the surface of the first sub-conductor region away from the substrate is higher than the surface of the non-conductive region away from the substrate.

3. The array substrate of claim 2, wherein the gate insulating layer covers the active portion, the gate insulating layer including a first conductive via, an orthographic projection of the first conductive via covering at least an orthographic projection of the second sub-conductor region.

4. The array substrate of claim 2 or 3, wherein the second conductor region comprises a third sub-conductor region and a fourth sub-conductor region that are continuous;

the third sub-conductor region is located between the fourth sub-conductor region and the non-conductive region, the surface of the third sub-conductor region away from the substrate is flush with the surface of the non-conductive region away from the substrate, and in the direction perpendicular to the substrate, the surface of the fourth sub-conductor region away from the substrate is higher than the surface of the non-conductive region away from the substrate.

5. The array substrate of claim 4, wherein the gate insulating layer covers the active portion, the gate insulating layer further comprising a second conductive via, an orthographic projection of the second conductive via covering at least an orthographic projection of the third subconductor region.

6. The array substrate of claim 1, wherein the surface of the first conductor region remote from the substrate and the surface of the second conductor region remote from the substrate are each higher than the surface of the non-conductive region remote from the substrate in a direction perpendicular to the substrate.

7. The array substrate of claim 6, wherein the gate insulating layer covers the active portion and an edge of the orthographic projection of the conductive portion extends beyond an edge of the orthographic projection of the non-conductive region.

8. A method for manufacturing an array substrate, the method comprising:

providing a substrate base plate;

manufacturing a semiconductor layer on one side of the substrate, wherein the semiconductor layer comprises an active part of a transistor, the active part comprises a non-conductive region and a conductive region, the conductive region comprises a first conductive region and a second conductive region which are positioned on two sides of the non-conductive region, and at least part of the conductive region away from the surface of the substrate is higher than the surface of the non-conductive region away from the substrate in the direction perpendicular to the substrate;

manufacturing a gate insulating layer on one side of the semiconductor layer, which is away from the substrate, wherein the gate insulating layer at least covers the non-conductive region and is provided with a first via hole and a second via hole;

manufacturing a gate metal layer on one side of the gate insulating layer, which is away from the substrate, wherein the gate metal layer comprises a conductive part, a first switching sheet and a second switching sheet, the orthographic projection of the conductive part at least covers the orthographic projection of the non-conductive area, the first switching sheet passes through the first via hole to be connected with the first conductor area, and the second switching sheet passes through the second via hole to be connected with the second conductor area;

Manufacturing an interlayer dielectric layer on one side of the gate metal layer, which is away from the substrate, wherein the interlayer dielectric layer at least covers the conductive part, the first conductor region and the second conductor region, and the interlayer dielectric layer is provided with a third via hole and a fourth via hole;

and manufacturing a source-drain metal layer on one side of the interlayer dielectric layer, which is away from the substrate, wherein the source-drain metal layer comprises a first connecting sheet and a second connecting sheet, the first connecting sheet passes through the third through hole to be connected with the first switching sheet, and the second connecting sheet passes through the fourth through hole to be connected with the second switching sheet.

9. The method of claim 8, wherein,

fabricating a semiconductor layer on one side of the substrate base plate, comprising:

manufacturing a semiconductor layer on one side of the substrate base plate, and conducting the surface of an active part included in the semiconductor layer to obtain a conducting structure positioned on the surface of the active part;

carrying out local etching on the conductive structure to obtain a non-conductive region, and a first conductor region and a second conductor region which are positioned at two sides of the non-conductive region, wherein in the direction perpendicular to the substrate, the surface of the first conductor region far away from the substrate and the surface of the second conductor region far away from the substrate are higher than the surface of the non-conductive region far away from the substrate;

Manufacturing a gate insulating layer on one side of the semiconductor layer away from the substrate base plate, wherein the gate insulating layer comprises: manufacturing a grid insulating layer on one side of the semiconductor layer, which is away from the substrate, wherein the grid insulating layer covers the active part and is provided with a first via hole and a second via hole;

manufacturing a gate metal layer on one side of the gate insulating layer, which is away from the substrate, and the manufacturing method comprises the following steps: and manufacturing the gate metal layer on one side of the gate insulating layer, which is away from the substrate, wherein the orthographic projection edge of the conductive part extends out of the orthographic projection edge of the non-conductive region, the first switching sheet penetrates through the first via hole to be connected with the first conductor region, and the second switching sheet penetrates through the first via hole to be connected with the first conductor region.

10. The method of claim 8, wherein,

fabricating a semiconductor layer on one side of the substrate base plate, comprising:

manufacturing a semiconductor layer on one side of the substrate base plate, and conducting the surface of an active part included in the semiconductor layer to obtain a conducting structure positioned on the surface of the active part;

carrying out partial etching on the conductive structure to obtain an etching region, and a first subconductor region and a fourth subconductor region which are positioned at two sides of the etching region, wherein in the direction perpendicular to the substrate, the surface of the first subconductor region, which is far away from the substrate, and the surface of the fourth subconductor region, which is far away from the substrate, are higher than the surface of the etching region, which is far away from the substrate;

Manufacturing a gate insulating layer on one side of the semiconductor layer away from the substrate base plate, wherein the gate insulating layer comprises: manufacturing a grid insulating layer on one side of the semiconductor layer, which is away from the substrate, wherein the grid insulating layer covers the active part and is provided with a first via hole and a second via hole;

manufacturing a gate metal layer on one side of the gate insulating layer, which is away from the substrate, and the manufacturing method comprises the following steps:

manufacturing a gate metal layer on one side of the gate insulating layer, which is away from the substrate, and filling the first via hole and the second via hole with the gate metal layer;

etching the gate metal layer and the gate insulating layer to obtain a conductive part, a first switching piece and a second switching piece which are positioned on the gate metal layer, and a first conductive hole and a second conductive hole which are positioned on the gate insulating layer;

the orthographic projection of the conductive part is overlapped with the orthographic projection of the non-conductive region, the first transfer sheet passes through the first via hole to be connected with the first sub-conductor region, the second transfer sheet passes through the second via hole to be connected with the fourth sub-conductor region, the orthographic projection of the first conductive hole at least covers the orthographic projection of the region between the non-conductive region and the first sub-conductor region, and the second conductive hole at least covers the orthographic projection of the region between the non-conductive region and the fourth sub-conductor region;

Before the interlayer dielectric layer is manufactured on the side, facing away from the substrate, of the gate metal layer, the method further comprises the following steps: and conducting the region between the non-conductive region and the first sub-conductor region and the region between the non-conductive region and the fourth sub-conductor region respectively to obtain a second sub-conductor region between the non-conductive region and the first sub-conductor region and a third sub-conductor region between the non-conductive region and the fourth sub-conductor region, wherein the second sub-conductor region is far away from the surface of the substrate and the surface of the third sub-conductor region far away from the substrate is flush with the surface of the non-conductive region far away from the substrate in the direction perpendicular to the substrate.

11. A display panel comprising the array substrate of any one of claims 1-7.