CN116779568A - 功率半导体的晶圆片级芯片规模封装及其制造方法 - Google Patents

功率半导体的晶圆片级芯片规模封装及其制造方法 Download PDF

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Publication number
CN116779568A
CN116779568A CN202211489017.9A CN202211489017A CN116779568A CN 116779568 A CN116779568 A CN 116779568A CN 202211489017 A CN202211489017 A CN 202211489017A CN 116779568 A CN116779568 A CN 116779568A
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China
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metal layer
thickness
semiconductor substrate
wafer level
chip scale
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CN202211489017.9A
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Inventor
朴命镐
朴喜津
金范洙
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MagnaChip Semiconductor Ltd
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MagnaChip Semiconductor Ltd
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Publication of CN116779568A publication Critical patent/CN116779568A/zh
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Abstract

公开了功率半导体的晶圆片级芯片规模封装及其制造方法。晶圆片级芯片规模封装包括：具有第一厚度的半导体衬底；形成在半导体衬底上的输入‑输出垫；形成在输入‑输出垫上的具有第二厚度的前金属层；形成在半导体衬底的底部上的具有第三厚度的后金属层；以及形成在半导体衬底上的金属凸块。

Description

功率半导体的晶圆片级芯片规模封装及其制造方法
相关申请的交叉引用
本申请根据35U.S.C.§119要求于2022年3月17日在韩国知识产权局提交的韩国专利申请第10-2022-0033131号的权益，出于所有目的通过引用将该申请的全部公开内容并入本文。
技术领域
下面的描述涉及功率半导体的晶圆片级芯片规模封装及其制造方法，其可以通过在半导体衬底的上表面上形成具有预定厚度的前金属层来防止由于半导体衬底与后金属层的热膨胀系数之间的差异而导致的半导体管芯的翘曲。
背景技术
目前，半导体工业的主要趋势之一是尽可能减小半导体器件的尺寸。因此，提出芯片规模封装(芯片尺寸封装)以将半导体器件封装的尺寸减小为像芯片一样。特别地，晶圆片级芯片规模封装(WLCSP)可以由半导体晶片一次性组装和制造封装。因此，WLCSP可以以低成本和良好的电子特性制造具有芯片尺寸的最小封装。
然而，封装的厚度可以根据功率半导体的类型而减小。在一个示例中，典型的封装厚度大约超过100μm。由于MOSFET类型的WLCSP需要较低的导通电阻(低Ron)，即，低漏-源电阻(低Rdson)和低源-源电阻(Rsson)，因此设计与典型封装相比更薄厚度的封装可能是重要的。
因此，在传统技术中已经存在减小半导体衬底的厚度以及增加后金属层的厚度的方法。
后金属层可以实现为公共漏电极，并且可以通过增加后金属层的厚度来减小漏电极的电阻。
然而，在具有这样的结构的封装中，由于半导体衬底与后金属层的热膨胀系数之间的差异而可能发生翘曲，并且随着半导体衬底的厚度变得更薄以及随着后金属层的厚度变得更厚，翘曲可能变得更严重。在这种情况下，可能对半导体器件施加过大的应力。因此，当封装安装在印刷电路板(PCB)上时，组装质量可能较差，并且薄半导体衬底可能破裂和破坏。
发明内容
提供该发明内容是为了以简化的形式介绍一系列构思，这些构思将在下面的具体实施方式中进一步描述。该发明内容不旨在标识所要求保护的主题的关键特征或必要特征，也不旨在用作在确定所要求保护的主题的范围时的帮助。
在一般方面，一种晶圆片级芯片规模封装，包括：具有第一厚度的半导体衬底；形成在半导体衬底上的输入-输出垫；形成在输入-输出垫上的具有第二厚度的前金属层；形成在半导体衬底的下表面上的具有第三厚度的后金属层；以及形成在半导体衬底上的金属凸块。
第一厚度可以小于60μm，并且第二厚度可以在10μm至60μm的范围内。第三厚度可以在10μm至100μm的范围内。
前金属层和后金属层可以包括铜(Cu)。
该晶圆片级芯片规模封装还可以包括：围绕前金属层的聚酰亚胺层；以及形成在前金属层上的种子金属层。
前金属层可以形成在除了输入-输出垫之外的半导体衬底上。
在将该晶圆片级芯片规模封装安装在PCB基板上的工艺中，该后金属层的翘曲可以被该前金属层和该聚酰亚胺层抵消。
该前金属层和该后金属层由具有相同热膨胀系数的相同金属形成。
该金属凸块可以包括可焊接金属层。
在另一一般方面，一种晶圆片级芯片规模封装可以包括：具有第一厚度的半导体衬底；形成在该半导体衬底的上表面上的具有第二厚度的前金属层；以及形成在该半导体衬底的下表面上的具有第三厚度的后金属层，其中，前金属层和后金属层具有相同的热膨胀系数，使得该封装被构造成当该封装安装在PCB衬底上时保持平衡状态。
第一厚度大于第二厚度，并且第三厚度大于第一厚度。
在一般方面，一种晶圆片级芯片规模封装的制造方法，包括：制备具有第一厚度的半导体衬底；在半导体衬底上形成第一种子金属层；在第一种子金属层上形成光掩模图案并且形成具有第二厚度的前金属层；去除在除了前金属层之外的区域中形成的光掩模图案和第一种子金属层；在半导体衬底上形成聚酰亚胺层；在聚酰亚胺层上形成第二种子金属层；在第二种子金属层上形成金属凸块；以及在半导体衬底的下表面上形成具有第三厚度的后金属层。
该前金属层的第二厚度可以最薄，并且后金属层的第三厚度可以最厚。
第一厚度可以小于60μm，并且第二厚度可以在10μm至60μm的范围内，并且第三厚度可以在10μm至100μm的范围内。
后金属层的翘曲可以被前金属层和聚酰亚胺层抵消，并且因此，安装在PCB基板上的该晶圆片级芯片规模封装可以保持平衡状态。
该晶圆片级芯片规模封装的制造方法还可以包括：在半导体衬底上形成输入-输出垫，并且前金属层可以形成在半导体衬底的除了输入-输出垫之外的整个区域上。
根据以下具体实施方式、附图以及权利要求，其他特征和方面将是明显的。
附图说明
图1示出了根据本公开内容的一个或更多个实施方式的晶圆片级芯片规模封装。
图2示出了从对角线方向观察的本公开内容中描述的功率半导体的平面图。
图3A和图3B示出了根据本公开内容的一个或更多个实施方式的功率半导体的晶圆片级芯片规模封装结构的截面图。
图4示出了典型的晶圆片级芯片规模封装的翘曲。
图5示出了没有翘曲的本公开内容的晶圆片级芯片规模封装。
图6A至图6L示出了根据本公开内容的一个或更多个实施方式的制造功率半导体的晶圆片级芯片规模封装的工艺的各个操作。
图7和图8示出了显示典型封装和本公开内容的封装的翘曲的SEM照片。
在整个附图和具体实施方式中，相同的附图标记指代相同的元件。附图可能未按比例绘制，并且为了清楚、说明性和方便，附图中的元件的相对尺寸、比例和描绘可能被夸大。
具体实施方式
提供以下具体实施方式以帮助读者获得对本文中描述的方法、设备和/或系统的全面理解。然而，在理解了本申请的公开内容之后，本文中描述的方法、设备和/或系统的各种改变、修改及等同物将变得明显。例如，本文中描述的操作的顺序仅是示例，并且不限于本文中阐述的顺序，而是除了必须以特定顺序发生的操作之外，操作的顺序可以如理解本申请的公开内容之后明显的那样进行改变。另外，为了提高清楚性和简洁性，可以省略在理解本申请的公开内容之后已知的特征的描述，注意，特征及其描述的省略也不旨在承认其为一般知识。
本文描述的特征可以以不同的形式实施，并且不被解释为限于本文描述的示例。而且，提供了本文中描述的示例仅用于说明在本申请的公开内容的理解之后将变得明显的实现本文中描述的方法、装置和/或系统的许多可能的方式中的一些方式。
遍及说明书，当诸如层、区域或基板的元件被描述为在另一元件“上”、“连接至”另一元件或“耦接至”另一元件时，该元件可以直接在另一元件“上”、“连接至”另一元件或“耦接至”另一元件，或者可以存在介于该元件与另一元件之间的一个或更多个其他元件。相比之下，当元件被描述为“直接在”另一元件“上”、“直接连接至”另一元件或“直接耦接至”另一元件时，可以不存在介于该元件与另一元件之间的其他元件。
如在本文中使用的，术语“和/或”包括相关联的列出项目的任何两个或更多个的任何一个和任何组合。
尽管本文中可以使用诸如“第一”、“第二”和“第三”的术语来描述各种构件、部件、区域、层或部分，但是这些构件、部件、区域、层或部分不受这些术语限制。而是，这些术语仅用于区分一个构件、部件、区域、层或部分与另一构件、部件、区域、层或部分。因此，在不偏离本示例的教导的情况下，在本文中描述的示例中被称为的第一构件、第一部件、第一区域、第一层或第一部分也可以被称为第二构件、第二部件、第二区域、第二层或第二部分。
为了便于描述，本文中可以使用诸如“之上”、“上方”、“之下”和“下方”的空间相对术语来描述附图中所示的一个元件与另一元件的关系。除了在附图中描绘的方向之外，这样的空间相对术语旨在涵盖装置在使用或操作中的不同方向。例如，如果附图中的装置被翻转，则相对于另一元件被描述为“之上”或“上方”的元件则相对于其他元件为“之下”或“下方”。因此，取决于装置的空间方向，术语“之上”涵盖之上的方向和之下的方向两者。装置也可以以其他方式定向(例如，旋转90度或在其他方向旋转)，并且相应地理解在本文中使用的空间相对术语。
本文中使用的术语仅用于描述各种示例，并且不用于限制本公开内容。除非上下文另外明确指出，否则不定冠词(a、an)和定冠词(the)也旨在包括复数形式。术语“包括”、“包含”和“具有”指定所陈述的特征、数字、操作、构件、元件和/或其组合的存在，但是不排除存在或添加一个或更多个其他特征、数字、操作、构件、元件和/或其组合。
由于制造技术和/或公差，可以出现附图中示出的形状的变化。因此，本文中描述的示例不限于附图中示出的具体的形状，而是包括在制造期间出现的形状的改变。
如在理解该申请的公开内容之后将明显的，本文中描述的示例的特征可以以各种方式来组合。此外，如在理解本申请的公开内容之后将明显的，尽管本文中描述的示例具有各种构造，但是其他构造也是可以的。
为了解决上述问题，本公开内容可以提供晶圆片级芯片规模封装及其制造方法，以通过在半导体衬底的相对侧上形成金属层来防止封装的翘曲。
一个或更多个示例还可以提供待应用于需要较低导通电阻(低Ron)(即，低漏-源电阻(低Rdson)和低源-源电阻(Rsson))的各种功率半导体的晶圆片级芯片规模封装及其制造方法。
本公开内容的目标问题不受上述问题的限制。相关技术领域的技术人员可以从以下描述中理解其他问题。
下面将结合附图给出详细描述。
根据一个或更多个示例，功率半导体可以实现形成垂直沟道的垂直功率MOSFET器件，但不限于此。可以包括沟槽功率MOSFET半导体器件或平面MOSFET半导体器件等。
图1示出了根据一个或更多个实施方式的晶圆片级芯片规模封装。
如图1所示，半导体器件100可以包括具有第一厚度的半导体衬底110以及具有第三厚度并且形成在半导体衬底110的底部上的后金属层(第二金属层)120。在一个示例中，第一厚度可以小于60μm，并且第三厚度可以在10μm至100μm的范围内。后金属层120可以比半导体衬底110厚。
如图1所示，半导体器件100可以包括形成在半导体衬底110上的输入-输出垫112。输入-输出垫112可以与金属凸块1：1对应地形成，这将在下面描述。输入-输出垫112可以与相邻的输入-输出垫隔开一定距离。可以在输入-输出垫112之间形成保护膜114或钝化膜，以保护形成在半导体衬底上的集成电路(未示出)免受外部空气或水的影响。氧化硅膜(SiO2)和氮化硅膜(SiN)、由氧化硅膜(SiO2)和氮化硅膜(SiN)构成的堆叠结构、以及氮氧化硅膜(SiON)等可以用于钝化膜。保护膜114可以与输入-输出垫112的一部分交叠。
半导体器件100可以包括形成在输入-输出垫112上的前金属层(第一金属层)130。前金属层130不仅可以在金属凸块的底部形成前金属层130，而且可以形成为足以在左右方向上延伸。前金属层130可以具有第二厚度。第二厚度可以在10μm至60μm的范围内。
半导体器件100可以包括聚酰亚胺层140以容易地在保护膜114和前金属层130上形成金属凸块。由于前金属层130具有第二厚度，聚酰亚胺层140可以比典型情况更厚。
根据该配置，可以以前金属层130、半导体衬底110和后金属层120的顺序将厚度形成为更厚。当前金属层130具有第二厚度时，由于前金属层130和聚酰亚胺层140的协作，该层可以具有与后金属层120的热膨胀系数(CTE)相似的热膨胀系数。因此，可以防止封装翘曲。
在图1的半导体器件100中，可以在半导体衬底110的上表面上形成输入-输出垫112，并且可以在输入-输出垫112上形成第一种子金属层150。第一种子金属层150可以实现Ti层或TiW层152和Cu层154的堆叠结构，并且其可以通过溅射方法沉积。当沉积前金属层130时，第一种子金属层150可以增强输入-输出垫112与前金属层130的粘合。当未形成第一种子金属层150时，前金属层130可能由于对输入-输出垫112的粘合不佳而在后续工艺中从输入-输出垫112剥离。
可以在前金属层130上形成第二种子金属层250。可以提供第二种子金属层250以增强金属凸块400(图6I)与前金属层130的粘合。在第二种子金属层250中实现的种子金属可以是钛(Ti)或钛钨(TiW)252和铜(Cu)254的堆叠结构。第二种子金属层250可以通过溅射方法沉积，但不限于此。
金属凸块400可以形成在第二种子金属层250上。金属凸块400可以实现可焊接金属层200的结构而不是焊球，使得封装的整体厚度减小。可焊接金属层200可以从底部以铜(Cu)、镍(Ni)和金(Au)的顺序堆叠。在图1中，作为公共漏电极的后金属层120可以形成在半导体衬底110的相对侧上。后金属层120的第三厚度可以在10μm至100μm的范围内。后金属层120的厚度可以期望是厚的，以便减小漏电极的电阻。具有优异导电性的金属例如铜(Cu)或银(Ag)通常可以用于后金属层120。
第三种子金属层125可以沉积在半导体衬底110与后金属层120之间，以防止半导体衬底110与后金属层120分离。当后金属层120直接沉积在半导体衬底110的底部而不沉积第三种子金属层125时，半导体衬底110可能与后金属层120分离。因此，在封装和PCB安装之后可能出现缺陷，并且因此，它可能不能用作产品。
镍(Ni)、镍钒(NiV)、银(Ag)和铝(Al)金属可以用于第三种子金属层125，并且也可以实现材料的堆叠结构。在一个示例中，可以实现诸如NiV/Ag、Ti/Ag或Al/Ti/Ag等的堆叠结构。第三种子金属层125可以沉积到小于4μm的厚度。
图2示出了从对角线方向观察的本公开内容中描述的功率半导体的平面图。
在图2中，半导体管芯10可以具有一个半导体衬底110。半导体衬底110可以具有虚拟参考表面。基于参考表面，沟槽半导体器件可以并排地形成在半导体管芯10中，并且半导体器件可以由虚拟参考表面物理地分离。可以在每个半导体器件中形成源电极焊盘(S)和栅电极焊盘(G)等，并且位于每个半导体器件中的源电极焊盘(S)和栅电极焊盘(G)可以物理地分离。
可能期望源电极焊盘(S)的尺寸大于栅电极焊盘(G)的尺寸，以减小源电极焊盘(S)的电阻。
前金属层130可以形成在源电极焊盘(S)的底部上，并且前金属层130在图2中以虚线示出。前金属层130的面积可以大于源电极焊盘(S)的面积，并且前金属层130可以不形成在栅电极焊盘(G)上。
图3A和图3B示出了根据本公开内容的一个或更多个示例的功率半导体的晶圆片级芯片规模封装结构的截面图。在本文中，图3A和图3B的截面图示出了半导体衬底110、前金属层(第一金属层)130和后金属层(第二金属层)120的厚度。
图3A示出了图2中A-A'的截面图。如所示出的，半导体器件可以包括具有第一厚度的半导体衬底110。半导体衬底110的厚度可以小于60μm。前金属层130可以形成在半导体衬底110上。前金属层130的第二厚度可以在10μm至60μm的范围内，并且其可以被认为是附加区域。即，形成前金属层130可以用于改善在典型封装结构中发生的翘曲。
后金属层120可以形成在半导体衬底110的相对侧上。后金属层120的第三厚度可以在10μm至100μm的范围内。
如在示例中，本公开内容的半导体器件中，可以从顶部起堆叠前金属层130、半导体衬底110和后金属层120。每个厚度可以按照半导体衬底110、前金属层130和后金属层120的顺序进行调整。在示例中，当半导体衬底110的厚度为10μm时，前金属层130的厚度可以为20μm，并且后金属层120的厚度可以为30μm。在另一示例中，当后金属层120的厚度增加时，前金属层130的厚度可以同样地增加。这是因为当后金属层120的厚度增加时，由于半导体衬底110的热膨胀系数的差异而导致的翘曲可能劣化，并且增加前金属层130的厚度可以有效地防止翘曲。然而，根据半导体器件应用和期望的Rsson和Rdson，半导体衬底110可以比前金属层130和后金属层120厚。即，根据应用并且为了导通电阻的合理化，可能期望将以本公开内容的第一至第三厚度的范围形成前金属层130、半导体衬底110和后金属层120的厚度。
通过形成前金属层130并且调整其厚度，可以改善翘曲，并且可以获得低导通电阻，即，低Rdson和Rsson。
前金属层130和后金属层120可以由相同的金属——铜(Cu)构成。也可以使用具有适当导电性的银(Ag)、金(Au)或铝(Al)等。实现相同金属的原因是通过使热膨胀系数的差异最小化或使用相同的系数来尽可能地防止封装翘曲。
聚酰亚胺层140可以形成在前金属层130的侧部和上部，以容易地形成金属凸块400。聚酰亚胺层140可以比前金属层130厚。可以在前金属层130的预定部分中依次形成第二种子金属层250和可焊接金属层200。对于可焊接金属层200，可以依次堆叠铜(Cu)201-镍(Ni)202-金(Au)203。
输入-输出垫112的宽度可以比第一种子金属层150的宽度宽，并且第一种子金属层150的宽度可以比前金属层130的宽度宽。在示例中，第一种子金属层150的宽度可以与前金属层130的宽度相同。
可以在输入-输出垫112的相对侧上形成保护膜114。
图3B示出了图2中B-B'的截面图。图3B的结构类似于图3A的上述结构。
可以包括半导体衬底110和形成在半导体衬底110上的前金属层130。在本文中，前金属层130可以由虚拟参考表面物理地分离。
聚酰亚胺层140可以形成在前金属层130的侧部和上部。第二种子金属层250和可焊接金属层200可以依次形成在聚酰亚胺层之间。
如图3A，在图3B的结构中，半导体衬底110可以具有小于60μm的厚度。前金属层130可以具有10至60μm的厚度，并且后金属层120可以具有10至100μm的厚度。如图3A，它们的厚度可以按衬底110、前金属层130和后金属层120的顺序变厚。根据应用，半导体衬底110可以比前金属层130和后金属层120厚。即，根据应用并且为了导通电阻的合理化，可能期望以第一至第三厚度的范围形成前金属层130、半导体衬底110和后金属层120的厚度。
输入-输出垫112的宽度可以比第一种子金属层150的宽度宽，并且第一种子金属层150的宽度可以比前金属层130的宽度宽。在示例中，第一种子金属层150的宽度可以与前金属层130的宽度相同。
图4示出了典型的晶圆片级芯片规模封装的翘曲，并且图5示出了没有翘曲的本公开内容的晶圆片级芯片规模封装。
在图4中，半导体衬底1薄，并且后金属层4比半导体衬底1厚。
由于在图4中半导体衬底1的硅(Si)和后金属层4的铜(Cu)具有不同的热膨胀系数，根据表面安装工艺的温度，后金属层4的铜(Cu)可以比半导体衬底1的硅(Si)热膨胀更多。因此，后金属层4可能被拉伸。因此，构成后金属层4的铜(Cu)可能朝向构成半导体衬底1的硅(Si)翘曲，导致翘曲。
铜(Cu)的热膨胀系数为17ppm/`C，并且Si的热膨胀系数为3ppm/`C。当在之后的封装工艺期间温度升高时，构成后金属层4的铜(Cu)可能由于附着至半导体衬底1的后金属层4的热膨胀而凸起地翘曲。
另一方面，在图5所示的本公开内容的结构中，除了半导体衬底110和后金属层120之外，可以在半导体衬底110上形成具有预定厚度的前金属层130。然后，在表面安装工艺中，前金属层130和后金属层120可以在以半导体衬底110为中间的上方和下方被拉伸。即，前金属层130和后金属层120可以朝向半导体衬底110翘曲。在该示例中，由于每个翘曲力被抵消，因此封装可以保持平衡状态。因此，在封装中不会发生翘曲。
图6A至图6L示出了根据本实施方式的一个或更多个示例制造功率半导体的晶圆片级芯片规模封装的每个工艺。
如图6A所示，半导体衬底110可以具有大约100至300μm的厚度。可以在半导体衬底110上形成半导体器件。可以在半导体衬底110的正面上形成输入-输出垫112。输入-输出垫112通常可以包括铝(Al)，并且输入-输出垫112可以指源电极垫或栅电极垫。可以在输入-输出垫112的左/右端形成可以比垫厚的保护膜114。
如图6B所示，可以将第一种子金属层150沉积在输入-输出垫112和保护膜114上。第一种子金属层150可改善输入-输出垫112的铝(Al)与稍后将形成的前金属层130的铜(Cu)之间的粘合。钛(Ti)152、钛钨(TiW)152和铜(Cu)154可以实施为第一种子金属层150的种子金属。可以从输入-输出垫112向上依次形成钛(Ti)层或钛钨(TiW)层152和铜(Cu)层154，并且可以通过溅射方法沉积第一种子金属层150，但不限于此。
如图6C所示，可以在第一种子金属层150中以预定厚度沉积光致抗蚀剂图案300。可以在除了形成前金属层130的前金属区域(FMA)之外的左和右区域中形成光致抗蚀剂图案300。图6C的中心是前金属区域(FMA)。除了FMA之外，可以在彼此面对的区域中形成预定厚度的光致抗蚀剂图案300。
如图6D所示，可以在第一种子金属层150上形成前金属层130，使得其在前金属区域(FMA)中具有第二厚度(10至60μm)。第二厚度可以比半导体衬底110的第一厚度薄。前金属层130可以由铜(Cu)形成。相同的金属可以用于稍后形成的后金属层120。在示例中，可以使用热膨胀系数与后金属层120的热膨胀系数类似的金属。
附加地，通过在第一种子金属层150上的电解电镀工艺和电子电镀工艺，可以将前金属层130形成为期望的厚度。
前金属层130的宽度可以比半导体衬底110的宽度窄。
如图6E所示，可以去除除了前金属层130之外的区域中的光致抗蚀剂图案300和第一种子金属层150的一部分。在本文中，可以通过使用湿法蚀刻工艺或等离子体工艺等的PR剥离工艺来去除光致抗蚀剂图案300。可以通过蚀刻工艺去除第一种子金属层150。即，可以执行包括Ti 152或TiW 152的第一蚀刻工艺和Cu 154的第二蚀刻工艺的两个去除工艺。第一种子金属层150可以保留在第一金属层130的底部上。由于第一种子金属层150的一部分在第二蚀刻工艺之后被去除，因此第一种子金属层150的宽度可以比输入-输出垫112的宽度窄。
根据该工艺，可以在具有第一厚度的半导体衬底110的顶部上形成具有第二厚度的前金属层130。前金属层130可以防止封装在随后的封装安装工艺中弯曲。
如图6F所示，可以在除了金属凸块(可焊接金属层)形成区域(MBFA，金属凸块形成区域)之外的区域中形成聚酰亚胺层140。省略了形成聚酰亚胺的步骤。聚酰亚胺层140可以被分成在前金属层130上的第一聚酰亚胺图案140b和在保护膜114和前金属层130的一侧上的第二聚酰亚胺层140a。第一聚酰亚胺层140b和第二聚酰亚胺层140a可以彼此间隔开预定距离。间隔距离可以是金属凸块形成区域(MBFA)。
第一聚酰亚胺层140b和第二聚酰亚胺层140a可以具有不同的厚度。这是因为第一聚酰亚胺层140b和第二聚酰亚胺层140a的顶表面高低相同，并且第一聚酰亚胺层140b直接形成在前金属层130上，并且第二聚酰亚胺层140a形成在保护膜114的上表面上。第二聚酰亚胺层140a可以比第一聚酰亚胺层140b厚。
如图6G所示，可以在聚酰亚胺层140和前金属层130上形成第二种子金属层250。第二种子金属层250可以直接接触聚酰亚胺层140和前金属层130。钛(Ti)、钛钨(TiW)或铜(Cu)可以实施为第二种子金属层250的种子金属。与第一种子金属层150类似，第二种子金属层250也可以通过溅射方法沉积，但不限于此。
如图6H所示，可以在沉积第二种子金属层250的半导体衬底的上表面上形成光致抗蚀剂图案310以形成金属凸块。可以在除了MBFA之外的区域中形成光致抗蚀剂图案310。
如图6I所示，可以在金属凸块形成区域(MBFA)中形成金属凸块400。在本文中，金属凸块400可以由前面提到的可焊接金属层200构成，以减小封装的整体厚度。可焊接金属层200可以包括铜、镍和金，并且可以使用具有适当导电性的其它金属来代替铜。堆叠顺序可以是从底部起铜、镍和金。
如图6J所示，可以在形成金属凸块400之后去除光致抗蚀剂图案310。可以通过使用湿法蚀刻工艺或等离子体工艺等的PR剥离工艺来去除光致抗蚀剂图案310。
如图6K所示，在去除光致抗蚀剂图案310之后，可以去除通过去除光致抗蚀剂图案310而露出的第二种子金属层250。在去除沉积在除了金属凸块400之外的部分中的第二种子金属层(Ti或TiW、Cu)250之后，完成金属凸块400的形成。
随后，可以通过抛光工艺和化学机械抛光(CMP)工艺减小半导体衬底110的底部厚度。通过抛光工艺和化学机械抛光(CMP)工艺，半导体衬底110可以具有约60μm或更小的薄的厚度。用虚线表示的部分是减小的部分。
接下来，如图6L所示，可以在半导体衬底110的底部上形成第三种子金属层125。第三种子金属层125可以改善半导体衬底110的底部与后金属层120之间的粘合。第三种子金属层125可以由厚度小于4μm的镍(Ni)或镍钒(NiV)金属形成。可以通过溅射方法沉积第三种子金属层125。第三种子金属层125可以改善与后金属层120的粘合，并且银(Ag)可以附加地堆叠在第三种子金属层125中。银层可以防止镍钒(NiV)的氧化，因为镍(Ni)和镍钒(NiV)可以容易地被氧化。因此，之后，后金属沉积工艺可能不能很好地执行。Ti可以仅用于第三种子金属层125，或者可以堆叠Ti/NiV/Ag的三层。在形成第三种子金属层125之后，可以形成具有第三厚度(10至100μm)的后金属层120。后金属层120的厚度可以比半导体衬底110的第一厚度和前金属层130的第二厚度厚。
根据上述制造工艺，可以形成其中具有预定厚度的前金属层130形成在半导体衬底110的顶部上的封装。另外，通过形成前金属层130，可以防止由于半导体衬底110与后金属层120的热膨胀系数的差异而导致的翘曲。因此，在将封装安装至PCB基板中的表面安装技术(SMT)工艺中可以不发生封装翘曲。
参照针对本公开内容的封装翘曲的实际SEM照片，如图7，对于通过图6A至图6L的工艺制造的封装不存在封装翘曲，图6A至图6L的工艺为本公开内容的示例。因此，当不存在封装翘曲并且实现了期望的状态时，可以将封装精确地安装至PCB中，并且可以防止半导体衬底110和封装的破坏以及由于安装中的翘曲而导致的内部破裂。另一方面，如图8，由于在典型的封装结构中没有形成前金属层130，因此由于半导体衬底110与后金属层120的热膨胀系数的差异，可能不能防止翘曲。具体地，当半导体衬底变得更薄并且后金属层变得更厚时，翘曲可能劣化。
根据一个或更多个示例，可以通过形成在半导体衬底的上部和下部上的金属层来防止封装的翘曲。特别地，通过考虑金属层的热膨胀系数而在半导体衬底的上部和下部上形成具有适当厚度的金属层，可以有效地防止封装的翘曲，改进封装和PCB安装的可靠性。
根据一个或更多个示例，通过减小封装的整体厚度和晶片的厚度并且形成后金属层和前金属层，可以设计需要低导通电阻(低Ron)(即，低漏-源电阻(低Rdson)和低源-源电阻(Rsson))的各种功率半导体。
虽然该公开内容包括了具体示例，但是在理解了该申请的一个或更多个示例之后将明显的是，在不脱离权利要求及其等同物的主旨和范围的情况下，可以在这些示例中进行形式和细节上的各种改变。本文中描述的示例应被认为仅是描述性的，而不是出于限制的目的。每个示例中的特征或方面的描述将被认为适用于其他示例中的类似特征或方面。如果所描述的技术以不同顺序被执行，以及/或者如果所描述的系统、结构、装置或电路中的部件以不同的方式被组合和/或通过其他部件或其等同物被代替或补充，可以实现合适的结果。因此，不是通过详细的描述而是通过权利要求书及其等同物来限定本公开内容的范围，并且在权利要求书及其等同物的范围内的所有变化被认为包括在本公开内容内。

Claims (15)

1.一种晶圆片级芯片规模封装，包括：
具有第一厚度的半导体衬底；
形成在所述半导体衬底上的输入-输出垫；
形成在所述输入-输出垫上的具有第二厚度的前金属层；
形成在所述半导体衬底的底部上的具有第三厚度的后金属层；以及
形成在所述半导体衬底上的金属凸块。
2.根据权利要求1所述的晶圆片级芯片规模封装，其中，所述第一厚度小于60μm，并且所述第二厚度在10μm至60μm的范围内，并且所述第三厚度在10μm至100μm的范围内。
3.根据权利要求1所述的晶圆片级芯片规模封装，其中，所述前金属层和所述后金属层包括铜(Cu)。
4.根据权利要求1所述的晶圆片级芯片规模封装，还包括：
围绕所述前金属层的聚酰亚胺层；以及
在所述前金属层上的种子金属层。
5.根据权利要求1所述的晶圆片级芯片规模封装，其中，所述前金属层形成在除了所述输入-输出垫之外的所述半导体衬底上。
6.根据权利要求4所述的晶圆片级芯片规模封装，其中，所述前金属层和所述聚酰亚胺层被构造成在将所述晶圆片级芯片规模封装安装在印刷电路板(PCB)基板上的工艺中抵消所述后金属层的翘曲。
7.根据权利要求4所述的晶圆片级芯片规模封装，其中，所述前金属层和所述后金属层由具有相同热膨胀系数的相同金属形成。
8.根据权利要求1所述的晶圆片级芯片规模封装，其中，所述金属凸块包括可焊接金属层。
9.一种晶圆片级芯片规模封装，包括：
具有第一厚度的半导体衬底；
形成在所述半导体衬底的上表面上的具有第二厚度的前金属层；以及
形成在所述半导体衬底的下表面上的具有第三厚度的后金属层，
其中，所述前金属层和所述后金属层具有相同的热膨胀系数，使得所述封装被构造成在所述封装安装在印刷电路板(PCB)基板上时保持平衡状态。
10.根据权利要求9所述的晶圆片级芯片规模封装，其中，所述第一厚度大于所述第二厚度，并且所述第二厚度大于所述第三厚度。
11.一种晶圆片级芯片规模封装的制造方法，所述方法包括：
制备具有第一厚度的半导体衬底；
在所述半导体衬底上形成第一种子金属层；
在所述第一种子金属层上形成光掩模图案并且形成具有第二厚度的前金属层；
去除形成在除了所述前金属层之外的区域中的所述光掩模图案和所述第一种子金属层；
在所述半导体衬底上形成聚酰亚胺层；
在所述聚酰亚胺层上形成第二种子金属层；
在所述第二种子金属层上形成金属凸块；以及
在所述半导体衬底的下表面上形成具有第三厚度的后金属层。
12.根据权利要求11所述的晶圆片级芯片规模封装的制造方法，其中，所述前金属层的所述第二厚度最薄，并且所述后金属层的所述第三厚度最厚。
13.根据权利要求11所述的晶圆片级芯片规模封装的制造方法，其中，所述第一厚度小于60μm，并且所述第二厚度在10μm至60μm的范围内，并且所述第三厚度在10μm至100μm的范围内。
14.根据权利要求11所述的晶圆片级芯片规模封装的制造方法，其中，所述前金属层和所述聚酰亚胺层被构造成抵消所述后金属层的翘曲，使得安装在印刷电路板(PCB)基板上的所述晶圆片级芯片规模封装保持平衡状态。
15.根据权利要求11所述的晶圆片级芯片规模封装的制造方法，还包括：
在所述半导体衬底上形成输入-输出垫，
其中，所述前金属层形成在所述半导体衬底的除了所述输入-输出垫之外的整个区域上。
CN202211489017.9A 2022-03-17 2022-11-25 功率半导体的晶圆片级芯片规模封装及其制造方法 Pending CN116779568A (zh)

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