CN116779546A - Method for preparing semiconductor structure and semiconductor structure - Google Patents

Method for preparing semiconductor structure and semiconductor structure Download PDF

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Publication number
CN116779546A
CN116779546A CN202310943290.2A CN202310943290A CN116779546A CN 116779546 A CN116779546 A CN 116779546A CN 202310943290 A CN202310943290 A CN 202310943290A CN 116779546 A CN116779546 A CN 116779546A
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layer
hard mask
epitaxial
material layer
dielectric
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刘欣然
徐亚超
张瑞奇
严勋
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Changxin Technology Group Co ltd
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Changxin Technology Group Co ltd
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Priority to CN202310943290.2A priority Critical patent/CN116779546A/en
Publication of CN116779546A publication Critical patent/CN116779546A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Semiconductor Memories (AREA)

Abstract

The present disclosure provides a method of fabricating a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises an array region, a first peripheral region and a second peripheral region; forming a first hard mask layer and a second hard mask layer which are sequentially stacked on a substrate, wherein the first hard mask layer and the second hard mask layer are provided with openings exposing the first peripheral region, and the material of the first hard mask layer is different from that of the second hard mask layer; forming a first epitaxial layer on the first peripheral region by using the second hard mask layer as a mask, wherein the material of the first epitaxial layer is different from that of the substrate; removing the second hard mask layer; forming a second epitaxial layer on the first epitaxial layer by taking the first hard mask layer as a mask, wherein the material of the second epitaxial layer is different from that of the first epitaxial layer; and removing the first hard mask layer.

Description

Method for preparing semiconductor structure and semiconductor structure
Technical Field
The invention relates to the technical field of semiconductors, a preparation method of a semiconductor structure and the semiconductor structure.
Background
Shrinking the device size is an important way to increase the integration density of semiconductor devices. With the gradual shrinking of transistor dimensions, quantum tunneling effects will not be negligible, which can lead to leakage current problems between the gate and the channel. The high-K material is used as the gate dielectric material to reduce the leakage current, but this in turn leads to a decrease in carrier mobility of the channel, affecting the performance of the transistor. The carrier mobility performance of the channel can be improved by preparing a specific epitaxial layer on the substrate. In the actual device manufacturing process, the preparation of the multi-layer epitaxial layer is generally required, but the performance of the multi-layer epitaxial layer is often difficult to be compatible, so that the preparation difficulty is high.
Disclosure of Invention
Based on this, in order to reduce the difficulty in preparing the multi-layered epitaxial layers in the semiconductor device, it is necessary to provide a method for preparing the semiconductor structure.
According to some embodiments of the present disclosure, there is provided a method of manufacturing a semiconductor structure, including:
providing a substrate, wherein the substrate comprises an array region, a first peripheral region and a second peripheral region;
forming a first hard mask layer and a second hard mask layer which are sequentially stacked on the substrate, wherein the first hard mask layer and the second hard mask layer are provided with openings exposing the first peripheral region, and the material of the first hard mask layer is different from that of the second hard mask layer;
forming a first epitaxial layer on the first peripheral region with the second hard mask layer as a mask, wherein the material of the first epitaxial layer is different from that of the substrate;
removing the second hard mask layer;
forming a second epitaxial layer on the first epitaxial layer by taking the first hard mask layer as a mask, wherein the material of the second epitaxial layer is different from that of the first epitaxial layer; the method comprises the steps of,
and removing the first hard mask layer.
In some embodiments of the present disclosure, forming the first and second hard mask layers sequentially stacked on the substrate includes:
Forming a first hard mask material layer, a second hard mask material layer and a third hard mask material layer which are sequentially stacked on the substrate, wherein the material of the third hard mask material layer is the same as that of the first hard mask material layer;
forming a patterned first photoresist layer on the third hard mask material layer, the first photoresist layer having an opening exposing the third hard mask material layer on the first peripheral region;
removing the third hard mask material layer on the first peripheral region by wet etching by taking the first photoresist layer as a mask, and taking the reserved third hard mask material layer as a third hard mask layer;
removing the first photoresist layer;
removing the second hard mask material layer on the first peripheral region by wet etching with the third hard mask layer as a mask, wherein the second hard mask material layer is reserved as the second hard mask layer;
and removing the third hard mask layer and the first hard mask material layer on the first peripheral region by wet etching, so that the first hard mask material layer is reserved as the first hard mask layer.
In some embodiments of the present disclosure, a ratio of a thickness of the first hard mask material layer to a thickness of the third hard mask material layer is greater than or equal to 1 and less than or equal to 1.1.
In some embodiments of the present disclosure, after removing the first hard mask layer, further comprising:
forming a first dielectric layer and a second dielectric layer which are sequentially stacked on the substrate, wherein openings exposing the second epitaxial layer positioned on the first peripheral region and exposing the second peripheral region are formed in the first dielectric layer and the second dielectric layer;
oxidizing the second epitaxial layer to convert the second epitaxial layer into a first gate oxide layer, and forming a second gate oxide layer on the second peripheral region;
forming a first gate structure on the first gate oxide layer, and forming P-type source and drain regions on two opposite sides of the first gate structure to form a P-type transistor, wherein a channel region of the P-type transistor comprises the first epitaxial layer;
and forming a second grid electrode structure on the second grid electrode oxide layer, and forming N-type source drain regions on two opposite sides of the second grid electrode structure to form an N-type transistor, wherein a channel region of the N-type transistor is positioned in the substrate.
In some embodiments of the present disclosure, forming the first dielectric layer and the second dielectric layer sequentially stacked on the substrate includes:
Forming a first dielectric material layer, a second dielectric material layer and a third dielectric material layer which are sequentially stacked on the substrate, wherein the material of the third dielectric material layer is the same as that of the first dielectric material layer;
forming a patterned second photoresist layer on the third dielectric material layer, the second photoresist layer having openings exposing the third dielectric material layer on the first and second peripheral regions;
removing the third dielectric material layer on the first peripheral region and the second peripheral region by wet etching by taking the second photoresist layer as a mask, and taking the reserved third dielectric material layer as a third dielectric layer;
removing the second photoresist layer;
removing the second dielectric material layer on the first peripheral region and the second peripheral region by wet etching by taking the third dielectric layer as a mask, and taking the reserved second dielectric material layer as the second dielectric layer;
and removing the third dielectric layer and the first dielectric material layer positioned on the first peripheral region and the second peripheral region by wet etching, wherein the first dielectric material layer is reserved as the first dielectric layer.
In some embodiments of the present disclosure, a ratio of a thickness of the first dielectric material layer to a thickness of the third dielectric material layer is greater than or equal to 1 and less than or equal to 1.1.
In some embodiments of the present disclosure, the material of the first dielectric layer comprises silicon oxide and the material of the second dielectric layer comprises one or more of silicon nitride and silicon oxynitride.
In some embodiments of the present disclosure, forming the second epitaxial layer on the first epitaxial layer using the first hard mask layer as a mask includes:
forming a second epitaxial material layer on the first epitaxial layer and the first hard mask layer, wherein the second epitaxial material layer on the first epitaxial layer is in a single crystal state, and the second epitaxial material layer on the first hard mask layer is in a polycrystalline state;
selectively removing the second epitaxial material layer on the first hard mask layer, and reserving the second epitaxial material layer on the first epitaxial layer to serve as the second epitaxial layer.
In some embodiments of the present disclosure, the material of the substrate comprises silicon, the material of the first epitaxial layer comprises silicon germanium, the material of the second epitaxial layer comprises silicon, the material of the first hard mask layer comprises silicon oxide, and the material of the second hard mask layer comprises one or more of silicon nitride and silicon oxynitride.
In some embodiments of the present disclosure, a buried transistor is formed in the array region.
In some embodiments of the present disclosure, the first epitaxial layer has a thickness of 7-15nm.
In some embodiments of the present disclosure, the second epitaxial layer has a thickness of 3-7nm.
Only one mask is typically used in conventional techniques to complete the preparation of the multi-layered epitaxial layers. However, the present disclosure has found during research that there is a relatively close relationship between the performance of the epitaxial layer and the mask used in the growth. In the method for preparing the semiconductor structure, a plurality of layers of masks are creatively adopted, the first epitaxial layer is prepared by adopting the second hard mask layer, and then the second epitaxial layer is prepared by adopting the first hard mask layer, so that the first epitaxial layer and the second epitaxial layer can be prepared in more proper masks, and the performances of the first epitaxial layer and the second epitaxial layer are more easily taken into consideration. The method not only ensures that the prepared epitaxial layers have better performance, but also can reduce the requirement of preparing the multi-layer epitaxial layers on a process window, thereby reducing the preparation difficulty of the multi-layer epitaxial layers in the semiconductor device.
The foregoing description is only an overview of the present invention, and is intended to provide a better understanding of the present invention, as it is embodied in the following description, with reference to the preferred embodiments of the present invention and the accompanying drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and that other embodiments of the drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram showing steps of a method for fabricating a semiconductor structure;
FIG. 2 is a schematic cross-sectional structure of a substrate;
FIG. 3 is a schematic diagram of a structure for preparing a first hard mask material layer, a second hard mask material layer, and a third hard mask material layer based on the structure shown in FIG. 2;
FIG. 4 is a schematic diagram of a structure for preparing a first photoresist layer based on the structure shown in FIG. 3;
FIG. 5 is a schematic diagram of a structure for forming a third hard mask layer based on the structure shown in FIG. 4;
FIG. 6 is a schematic diagram of a structure for forming a second hard mask layer and a first hard mask layer based on the structure shown in FIG. 5;
fig. 7 is a schematic view of a structure for forming a first epitaxial layer on the basis of the structure shown in fig. 6;
FIG. 8 is a schematic diagram of a structure for removing the second hard mask layer based on the structure shown in FIG. 7;
FIG. 9 is a schematic diagram of a structure for preparing a second epitaxial layer based on the structure shown in FIG. 8;
FIG. 10 is a schematic diagram of a structure with a first mask layer removed based on the structure shown in FIG. 9;
FIG. 11 is a schematic diagram of a structure for preparing a first dielectric material layer, a second dielectric material layer, a third dielectric material layer, and a second photoresist layer based on the structure shown in FIG. 10;
FIG. 12 is a schematic diagram of a structure for forming a third dielectric layer based on the structure shown in FIG. 11;
FIG. 13 is a schematic diagram of a structure in which a second dielectric layer and a first dielectric layer are formed on the basis of the structure shown in FIG. 12;
fig. 14 is a schematic view of a structure for forming a first gate structure and a second gate structure on the basis of the structure shown in fig. 13;
wherein, each reference sign and meaning are as follows:
100. a substrate; 101. a first peripheral region; 102. a second peripheral region; 103. an array region; 1031. an active region; 1032. shallow trench isolation structures; 1033. a buried word line structure; 110. a first epitaxial layer; 120. a second epitaxial layer; 130. a first gate oxide layer; 140. a first gate structure; 150. a second gate oxide layer; 160. a second gate structure; 210. a first hard mask layer; 211. a first hard mask material layer; 220. a second hard mask layer; 221. a second hard mask material layer; 230. a third hard mask layer; 231. a third hard mask material layer; 240. a first dielectric layer; 241. a first dielectric material layer; 250. a second dielectric layer; 251. a second dielectric material layer; 260. a third dielectric layer; 261. a third dielectric material layer; 310. a first photoresist layer; 320. and a second photoresist layer.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the conventional technology, when preparing a lamination of a silicon germanium epitaxial layer and a silicon epitaxial layer, if the uniformity of the silicon germanium epitaxial layer is good, the etching selectivity of the silicon epitaxial layer is often poor, and if the etching selectivity of the silicon epitaxial layer is good, the uniformity of the silicon germanium epitaxial layer is often poor. The present disclosure finds during the course of the study: if the silicon germanium epitaxial layer is required to have good uniformity, a silicon nitride material can be used as a mask, but the etching rate of the silicon epitaxial layer grown on the silicon nitride material and the etching rate of the silicon epitaxial layer grown on the prepared silicon germanium epitaxial layer in the etching process are relatively close, and it is difficult to selectively remove only the silicon epitaxial layer on the mask. While a silicon oxide material may be used as a mask if it is desired that the silicon epitaxial layer be selectively removed, the uniformity of the silicon germanium epitaxial layer grown based on the silicon oxide mask is poor overall. Balancing the properties of a multilayer epitaxial layer places extremely high demands on the process, which makes it difficult to prepare the multilayer epitaxial layer, and even if it is prepared, it is difficult to obtain a multilayer epitaxial layer with better properties at the same time.
The disclosure provides a method for manufacturing a semiconductor structure, and fig. 1 is a schematic diagram of steps of the method for manufacturing a semiconductor structure. Referring to fig. 1, the method for fabricating the semiconductor structure includes steps S1 to S5.
Step S1, providing a substrate, wherein the substrate comprises an array area, a first peripheral area and a second peripheral area.
Fig. 2 is a schematic cross-sectional structure of a substrate 100. Referring to fig. 2, the substrate 100 includes an array region 103 and a peripheral region, which further includes a first peripheral region 101 and a second peripheral region 102. The first peripheral region 101, the second peripheral region 102, and the array region 103 are respectively at different positions on the substrate 100.
It will be appreciated that the semiconductor structure to be fabricated may include an array of memory cells and peripheral circuitry that may be electrically connected to the array of memory cells and conduct it to external circuitry. The array region 103 may be used as a preparation region of a memory cell array, and the peripheral region may be used as a preparation region of a peripheral circuit. In some examples of this embodiment, the substrate of the array region 103 has formed therein buried transistors that may participate in the formation of the memory cell array.
Referring to fig. 2, in some examples of this embodiment, an active region 1031, shallow trench isolation structures 1032, and buried word line structures 1033 may be included in the array region 103. The shallow trench isolation structure 1032 may define a plurality of active regions 1031 in the array region 103, the active regions 1031 may be used to form channels of transistors, and the buried word line structure 1033 may be used to control the on/off of the channels.
In some examples of this embodiment, the substrate 100 in the first peripheral region 101 and the substrate 100 in the second peripheral region 102 may have different doping types. For example, the substrate 100 in the first peripheral region 101 may be N-doped and the substrate 100 in the second peripheral region 102 may be P-doped. Correspondingly, the first peripheral region 101 may be used as a preparation region of a P-type transistor (PMOS) in the peripheral circuit, and the second peripheral region 102 may be used as a preparation region of an N-type transistor (NMOS) in the peripheral circuit.
In some examples of this embodiment, the material of the substrate 100 may include a semiconductor material. For example, the material of the substrate 100 may be silicon, germanium, silicon germanium, gallium nitride, or silicon carbide. Further, the substrate 100 may be a wafer.
And S2, forming a first hard mask layer and a second hard mask layer which are sequentially stacked on the substrate.
In some examples of this embodiment, the step of forming the first hard mask layer 210 and the second hard mask layer 220, which are sequentially stacked, on the substrate 100 may include:
forming a first hard mask material layer 211, a second hard mask material layer 221, and a third hard mask material layer 231 stacked once on the substrate 100, the material of the third hard mask material layer 231 being the same as the material of the first hard mask material layer 211;
Forming a patterned first photoresist layer 310 on the third hard mask material layer 231, the first photoresist layer 310 having an opening exposing the third hard mask material layer 231 located on the first peripheral region 101;
removing the third hard mask material layer 231 located on the first peripheral region 101 under the shielding of the first photoresist layer 310 by wet etching, so as to leave the third hard mask material layer 231 as the third hard mask layer 230;
removing the first photoresist layer 310 and removing the second hard mask material layer 221 located on the first peripheral region 101 by wet etching using the third hard mask layer 230 as a mask, with the remaining second hard mask material layer 221 as the second hard mask layer 220;
the third hard mask layer 230 is removed using a wet etch, and the first hard mask material layer 211 located on the first peripheral region 101 is etched based on the second hard mask layer 220 to leave the first hard mask material layer 211 as the first hard mask layer 210.
Fig. 3 is a schematic structural view of preparing the first, second and third hard mask material layers 211, 221 and 231 on the basis of the structure shown in fig. 2. Referring to fig. 3, a first hard mask material layer 211, a second hard mask material layer 221, and a third hard mask material layer 231 are sequentially stacked on the substrate 100 and cover the array region 103, the first peripheral region 101, and the second peripheral region 102. The material of the first hard mask material layer 211 and the material of the second hard mask material layer 221 are different, and the material of the first hard mask material layer 211 and the material of the third hard mask material layer 231 are the same.
In some examples of this embodiment, the material of the first hard mask material layer 211 may include silicon oxide.
In some examples of this embodiment, the material of the second hard mask material layer 221 may include one or more of silicon nitride and silicon oxynitride.
Fig. 4 is a schematic diagram of a structure for preparing a first photoresist layer 310 based on the structure shown in fig. 3. Referring to fig. 4, a first photoresist layer 310 is disposed on the third hard mask material layer 231, and the first photoresist layer 310 has an opening therein located on the first peripheral region 101. It will be appreciated that the opening exposes the third hard mask material layer 231 on the first peripheral region 101.
In some examples of this embodiment, the step of preparing the first photoresist layer 310 may include: a photoresist material is coated on the third hard mask material layer 231, baked and exposed and developed to obtain a first photoresist layer 310 having an opening.
Fig. 5 is a schematic diagram illustrating a structure in which a third hard mask layer 230 is formed on the basis of the structure shown in fig. 4. The third hard mask layer 230 may be etched from the third hard mask material layer 231. For example, with the first photoresist layer 310 as a mask, since the opening of the first photoresist layer 310 is located on the first peripheral region 101, when the third hard mask material layer 231 is etched, the third hard mask material layer 231 on the first peripheral region 101 is etched and removed, and a remaining portion of the third hard mask material layer 231 serves as the third hard mask layer 230. It is understood that after etching, the third hard mask layer 230 has the same pattern therein as the first photoresist layer 310.
In some examples of this embodiment, the second hard mask material layer 221 may be employed as an etch stop layer when etching the third hard mask material layer 231. The third hard mask material layer 231 and the second hard mask material layer 221 should have a high etching selectivity during etching. For example, the etch selectivity of the third hard mask material layer 231 to the second hard mask material layer 221 may be (10 to 100): 1.
In some examples of this embodiment, in order to make the third hard mask material layer 231 have a higher etching selectivity than the second hard mask material layer 221, etching may be performed by wet etching. Further, the etchant used for wet etching may include dilute hydrofluoric acid (DHF), which has a significantly higher etching selectivity for silicon oxide and silicon nitride.
In some examples of this embodiment, after etching the third hard mask material layer 231, a step of removing the first photoresist layer 310 is further included. The photoresist layer may be removed by ashing.
Fig. 6 is a schematic diagram of a structure in which a second hard mask layer 220 and a first hard mask layer 210 are formed on the basis of the structure shown in fig. 5. Referring to fig. 6, a first hard mask layer 210 and a second hard mask layer 220 are sequentially stacked on the substrate 100, and each of the first hard mask layer 210 and the second hard mask layer 220 has an opening exposing the substrate 100 in the first peripheral region 101.
The second hard mask layer 220 may be etched from the second hard mask material layer 221. For example, with the third hard mask layer 230 as a mask, since the opening of the third hard mask layer 230 is located on the first peripheral region 101, only the second hard mask material layer 221 on the first peripheral region 101 is etched away when the second hard mask material layer 221 is etched, and a remaining portion of the second hard mask material layer 221 serves as the second hard mask layer 220.
In some examples of this embodiment, the first hard mask material layer 211 may be employed as an etch stop layer when etching the second hard mask material layer 221. The second hard mask material layer 221 should have a high etching selectivity to the first hard mask material layer 211 during etching. For example, the etching selectivity of the second hard mask material layer 221 to the first hard mask material layer 211 may be (10 to 100): 1.
In some examples of this embodiment, the etching may be performed by wet etching in order to have a higher etching selectivity of the second hard mask material layer 221 to the first hard mask material layer 211. Further, the etchant used for wet etching may include phosphoric acid, which has a significantly higher etching selectivity for silicon nitride and silicon oxide. In addition, in the process of etching the second hard mask material layer 221 using phosphoric acid, the third hard mask layer 230 is made of the same material as the first hard mask material layer 211, and is difficult to be etched by phosphoric acid, and thus can be used as a suitable mask. In this process, if photoresist is used as a mask, the photoresist may fail due to the reaction of phosphoric acid with the photoresist.
Further, the first hard mask layer 210 may be etched from the first hard mask material layer 211. In etching the first hard mask material layer 211, etching may be performed using the second hard mask layer 220 as a mask. Since the first hard mask material layer 211 and the third hard mask material layer 231 are made of the same material, the third hard mask layer 230 is etched and removed together when the first hard mask material layer 211 is etched, thereby exposing the second hard mask layer 220.
In some examples of this embodiment, the ratio of the thickness of the first hard mask material layer 211 to the thickness of the third hard mask material layer 231 is 1 to 1.1, i.e., the ratio of the thickness of the first hard mask material layer 211 to the thickness of the third hard mask material layer 231 is greater than or equal to 1 and less than or equal to 1.1. Controlling the thickness of the first hard mask material layer 211 to be slightly thicker than the thickness of the third hard mask material layer 231 can ensure that the third hard mask layer 230 is etched away prior to the first hard mask material layer 211, thereby exposing the second hard mask layer 220, while also minimizing damage to the second hard mask layer 220.
In some examples of this embodiment, the etch selectivity of the third hard mask layer 230 and the second hard mask layer 220 may be controlled to be relatively high when etching the first hard mask material layer 211, thereby further reducing damage to the second hard mask layer 220. The etching manner of this step may be the same as that used when forming the third hard mask layer 230.
And S3, forming a first epitaxial layer on the first peripheral area by taking the second hard mask layer as a mask.
Fig. 7 is a schematic view of a structure in which a first epitaxial layer 110 is formed on the basis of the structure shown in fig. 6. In this embodiment, the material of the first epitaxial layer 110 is different from the material of the substrate 100. For example, in this embodiment, the material of the substrate 100 may be silicon and the material of the first epitaxial layer 110 may be silicon germanium.
In some examples of this embodiment, the first epitaxial layer 110 may be prepared by epitaxial growth. In an actual manufacturing process, since the epitaxial growth has a high selectivity to the growth base, the first epitaxial layer 110 can be controlled to be grown on the substrate 100 without being grown on the second hard mask layer 220.
It will be appreciated that since the second hard mask layer 220 is located above the first hard mask layer 210, the second hard mask layer 220 is used as a mask during the formation of the first epitaxial layer 110. The use of the second hard mask layer 220 comprising silicon nitride and/or silicon oxynitride as a mask to fabricate the first epitaxial layer 110 comprising silicon germanium may result in a surface of the first epitaxial layer 110 having a higher uniformity than if the silicon germanium were fabricated using other dielectric materials (e.g., silicon oxide) as a mask. The uniformity refers to the difference of the thicknesses of the first epitaxial layers 110 at different positions, and the higher the uniformity is, the smaller the difference of the thicknesses of the first epitaxial layers 110 at different positions is.
In some examples of this embodiment, in the step of preparing the first epitaxial layer 110, the thickness of the first epitaxial layer 110 may be controlled to be 7nm to 15nm. For example, the thickness of the first epitaxial layer 110 may be controlled to be 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, or 15nm, or the thickness of the first epitaxial layer 110 may be controlled to be within a range between any two of the above thicknesses. By controlling the thickness of the first epitaxial layer 110 within the above-described range, it is possible to effectively reduce the absolute value of the difference in thickness of the first epitaxial layer 110 at different positions while improving channel carrier mobility.
And S4, removing the second hard mask layer.
Fig. 8 is a schematic diagram of a structure in which the second hard mask layer 220 is removed on the basis of the structure shown in fig. 7. Referring to fig. 8, a first hard mask layer 210 is disposed on the substrate 100, and the first hard mask layer 210 is positioned at the top of the substrate 100. The first hard mask layer 210 has an opening therebetween on the first peripheral region 101, and the first epitaxial layer 110 is disposed in the opening of the first hard mask layer 210.
In some examples of this embodiment, the second hard mask layer 220 may be removed by wet etching. When the second hard mask layer 220 is removed, the etching selectivity of the second hard mask layer 220 to the first hard mask layer 210 may be controlled to be relatively high, for example, the etching selectivity of the second hard mask layer 220 to the first hard mask layer 210 may be (10 to 100): 1. In addition, the etching selectivity of the second hard mask layer 220 to the first epitaxial layer 110 may be controlled to be high, for example, the etching selectivity of the second hard mask layer 220 to the first epitaxial layer 110 may be (10 to 100): 1. Because the second hard mask layer 220 has a relatively high etching rate, the second hard mask layer 220 can be removed effectively without damaging the first epitaxial layer 110 and the first hard mask layer 210 by only chemically cleaning the second hard mask layer 220 on the substrate 100 with an etchant during etching.
In some examples of this embodiment, in the step of removing the second hard mask layer 220, the etchant used for the wet etching may include phosphoric acid.
And S5, forming a second epitaxial layer on the first epitaxial layer by using the first hard mask layer as a mask.
Fig. 9 is a schematic diagram of a structure for preparing the second epitaxial layer 120 on the basis of the structure shown in fig. 8. Referring to fig. 9, in this embodiment, a second epitaxial layer 120 may be formed on the first epitaxial layer 110 and the first hard mask layer 210. The material of the second epitaxial layer 120 is different from the material of the first epitaxial layer 110.
In some examples of this embodiment, the step of forming the second epitaxial layer 120 on the first epitaxial layer 110 includes: forming a second epitaxial material layer on the first epitaxial layer 110 and the first hard mask layer 210, wherein the second epitaxial material layer on the first epitaxial layer 110 is in a single crystalline state, and the second epitaxial material layer on the first hard mask layer 210 is in a polycrystalline state; the second epitaxial material layer on the first hard mask layer 210 is selectively removed, leaving the second epitaxial material layer on the first epitaxial layer 110 as the second epitaxial layer 120.
In some examples of this embodiment, the material of the second epitaxial material layer may include silicon. The silicon material can be deposited in monocrystalline form on the first epitaxial layer 110 comprising silicon germanium and in polycrystalline form on the first mask layer comprising silicon oxide.
Since the second epitaxial material layer of the polycrystalline state has a higher etching rate than the second epitaxial material layer of the single crystalline state, the second epitaxial material layer on the first hard mask layer 210 may be selectively removed by etching. The etching may be wet etching. By controlling the etching time, the polycrystalline second epitaxial material layer can be completely removed, and the single crystalline second epitaxial material layer on the first epitaxial layer 110 remains as the second epitaxial layer 120.
In some examples of this embodiment, the thickness of the second epitaxial layer 120 may be 3nm to 7nm. For example, the thickness of the second epitaxial layer 120 may be 3nm, 4nm, 5nm, 6nm, or 7nm, or the thickness of the second epitaxial layer 120 may be in a range between any two of the above thicknesses.
Step S6, removing the first hard mask layer.
Fig. 10 is a schematic diagram of a structure in which the first hard mask layer 210 is removed on the basis of the structure shown in fig. 9. Referring to fig. 9, the first hard mask layer 210 is removed, and the first epitaxial layer 110 and the second epitaxial layer 120 on the first peripheral region 101 are disposed on the substrate 100.
In this embodiment, the material of the first hard mask layer 210 is different from that of the second epitaxial layer 120, so that the first hard mask layer 210 can be selectively removed and the second epitaxial layer 120 can be preserved. In some examples of this embodiment, the manner in which the first hard mask layer 210 is removed may be etching. Further, the first mask layer may be removed by wet etching. For example, dilute hydrofluoric acid may be used as the etchant.
In some examples of this embodiment, after removing the first hard mask layer 210, it may further include:
forming a first dielectric layer 240 and a second dielectric layer 250 on the substrate 100, the first dielectric layer 240 and the second dielectric layer 250 being sequentially stacked, each having an opening on the first peripheral region 101 and the second peripheral region 102, it being understood that the second epitaxial layer 120 and the substrate 100 of the second peripheral region 102 are exposed from the openings; converting the second epitaxial layer 120 into a first gate oxide 130 and converting the substrate 100 portion of the second peripheral region 102 into a second gate oxide 150 using an oxidation process; forming a first gate structure 140 and P-type source and drain regions on both sides of the first gate structure 140 on the first gate oxide layer 130 to obtain a P-type transistor (PMOS), a channel region of the P-type transistor including the first epitaxial layer 110; a second gate structure 160 and N-type source and drain regions on both sides of the second gate structure 160 are formed on the second gate oxide layer 150 to obtain an N-type transistor (NMOS), a channel region of which is located in the substrate 100 of the second peripheral region 102.
In some examples of this embodiment, forming the first dielectric layer 240 and the second dielectric layer 250 on the substrate 100 in a stacked arrangement includes:
Forming a first dielectric material layer 241, a second dielectric material layer 251 and a third dielectric material layer 261 which are sequentially stacked on the substrate 100, wherein the material of the third dielectric material layer 261 is the same as that of the first dielectric material layer 241;
forming a patterned second photoresist layer 320 on the third dielectric material layer 261, the second photoresist layer 320 having openings exposing the third dielectric material layer 261 located on the first peripheral region 101 and the second peripheral region 102;
under the shielding of the second photoresist layer 320, removing the third dielectric material layer 261 on the first peripheral region 101 and the second peripheral region 102 by wet etching, so that the reserved third dielectric material layer 261 is used as a third dielectric layer 260;
removing the second photoresist layer 320, and using the third dielectric layer 260 as a mask, removing the second dielectric material layer 251 located on the first peripheral region 101 and the second peripheral region 102 by wet etching, so as to leave the second dielectric material layer 251 as the second dielectric layer 250;
the third dielectric layer 260 is removed by wet etching, and the first dielectric material layer 241 on the first and second peripheral regions 101 and 102 is etched based on the second dielectric layer 250 to remain the first dielectric material layer 241 as the first dielectric layer 240.
Fig. 11 is a schematic structural view of preparing a first dielectric material layer 241, a second dielectric material layer 251, a third dielectric material layer 261 and a second photoresist layer 320 on the basis of the structure shown in fig. 10. Referring to fig. 11, a first dielectric material layer 241, a second dielectric material layer 251 and a third dielectric material layer 261 are sequentially stacked on the substrate 100, a second photoresist layer 320 is disposed on the third dielectric material layer 261, and the second photoresist layer 320 has openings therein located on the first peripheral region 101 and the second peripheral region 102.
In some examples of this embodiment, the material of the first dielectric material layer 241 is the same as the material of the third dielectric material layer 261. The material of the first dielectric material layer 241 is different from the material of the second dielectric material layer 251.
In some examples of this embodiment, the material of the first dielectric material layer 241 may include silicon oxide.
In some examples of this embodiment, the material of the second dielectric material layer 251 may include one or more of silicon nitride and silicon oxynitride.
Fig. 12 is a schematic structural view of forming a third dielectric layer 260 on the basis of the structure shown in fig. 11. Referring to fig. 12, a third dielectric layer 260 is disposed on the second dielectric material layer 251, and the third dielectric layer 260 has openings therein located on the first and second peripheral regions 101 and 102.
The third dielectric layer 260 may be etched from the third dielectric material layer 261. The second photoresist layer 320 may be used as a mask during etching. In some examples of this embodiment, the second dielectric material layer 251 may be employed as an etch stop layer when etching the third dielectric material layer 261. The third dielectric material layer 261 and the second dielectric material layer 251 should have a high etching selectivity during etching. For example, the etch selectivity of the third dielectric material layer 261 to the second dielectric material layer 251 may be (10-100): 1. Further, the third dielectric material layer 261 may be etched using a wet etching, and an etchant used for the etching may include dilute hydrofluoric acid.
Fig. 13 is a schematic structural view of forming the second dielectric layer 250 and the first dielectric layer 240 on the basis of the structure shown in fig. 12. Referring to fig. 12, a second dielectric layer 250 is disposed on the first dielectric material layer 241, and the second dielectric layer 250 has openings therein located on the first and second peripheral regions 101 and 102.
The second dielectric layer 250 may be etched from the second dielectric material layer 251. The third dielectric layer 260 may be used as a mask during etching. In some examples of this embodiment, the first dielectric material layer 241 may be employed as an etch stop layer when etching the second dielectric material layer 251. The second dielectric material layer 251 should have a high etching selectivity to the first dielectric material layer 241 during the etching process. For example, the etching selectivity of the second dielectric material layer 251 to the first dielectric material layer 241 may be (10 to 100): 1. Further, the second dielectric material layer 251 may be etched using a wet etching, and an etchant used for the etching may include phosphoric acid.
The first dielectric layer 240 may be etched from the first dielectric material layer 241. The second dielectric layer 250 may be used as a mask for etching when etching the first dielectric material layer 241. Since the materials of the first dielectric material layer 241 and the third dielectric material layer 261 are the same, the third dielectric layer 260 is etched away together when the first dielectric material layer 241 is etched, so that the second dielectric layer 250 is exposed.
In some examples of this embodiment, the ratio of the thickness of the first dielectric material layer 241 to the thickness of the third dielectric material layer 261 is 1 to 1.1, i.e., the ratio of the thickness of the first dielectric material layer 241 to the thickness of the third dielectric material layer 261 is greater than or equal to 1 and less than or equal to 1.1.
Referring to fig. 13, the second dielectric layer 250 and the first dielectric layer 240 have openings on the first and second peripheral regions 101 and 102, so that the substrate 100 in the second epitaxial layer 120 and the second peripheral region 102 is exposed from the openings. The second dielectric layer 250 and the first dielectric layer 240 serve to protect structures in the array region 103 during subsequent formation of the first gate structure 140 and the second gate structure 160.
Fig. 14 is a schematic view of a structure in which a first gate structure 140 and a second gate structure 160 are formed on the basis of the structure shown in fig. 13. Further, fig. 14 also shows a first gate oxide 130 and a second gate oxide 150. Referring to fig. 14, a first gate oxide layer 130 is disposed on the first epitaxial layer 110, a first gate structure 140 is disposed on the first gate oxide layer 130, a second gate oxide layer 150 is disposed on the substrate 100, and a second gate structure 160 is disposed on the second gate oxide layer 150.
In some examples of this embodiment, the thickness of the first gate oxide 130 may be 1nm to 2nm, and the thickness of the second gate oxide 150 may be 1nm to 2nm.
The first gate oxide layer 130 may be formed by oxidizing the second epitaxial layer 120, and a material of the first gate oxide layer 130 is related to a material of the second epitaxial layer 120. For example, the material of the second epitaxial layer 120 is silicon, and the material of the first gate oxide layer 130 is silicon oxide.
The first epitaxial layer 110 is disposed on a side of the first gate oxide layer 130 away from the first gate structure 140, where the first epitaxial layer 110 may be used as a part of a channel region, and the first epitaxial layer 110 can effectively improve mobility of carriers, so as to improve a response speed of the transistor.
The second gate oxide layer 150 may be formed by oxidizing the substrate 100, and a material of the second gate oxide layer 150 is related to a material of the substrate 100. For example, the material of the substrate 100 is silicon, and the material of the second gate oxide layer 150 is silicon oxide.
It can be appreciated that the method for manufacturing a semiconductor structure provided in the present disclosure can be completed through the above steps S1 to S6.
Only one mask is typically used in conventional techniques to complete the preparation of the multi-layered epitaxial layers. However, the present disclosure has found during research that there is a relatively close relationship between the performance of the epitaxial layer and the mask used in the growth. In the method for preparing the semiconductor structure, a plurality of layers of masks are creatively adopted, the first epitaxial layer is prepared by adopting the second hard mask layer, and then the second epitaxial layer is prepared by adopting the first hard mask layer, so that the first epitaxial layer and the second epitaxial layer can be prepared in more proper masks, and the performances of the first epitaxial layer and the second epitaxial layer are more easily taken into consideration. The method not only ensures that the prepared epitaxial layers have better performance, but also can reduce the requirement of preparing the multi-layer epitaxial layers on a process window, thereby reducing the preparation difficulty of the multi-layer epitaxial layers in the semiconductor device.
Note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.
It should be understood that the steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the preparation process may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order in which the sub-steps or stages are performed is not necessarily sequential, and may be performed in turn or alternately with at least a portion of the sub-steps or stages of other steps or steps.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

Claims (10)

1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises an array region, a first peripheral region and a second peripheral region;
forming a first hard mask layer and a second hard mask layer which are sequentially stacked on the substrate, wherein the first hard mask layer and the second hard mask layer are provided with openings exposing the first peripheral region, and the material of the first hard mask layer is different from that of the second hard mask layer;
forming a first epitaxial layer on the first peripheral region with the second hard mask layer as a mask, wherein the material of the first epitaxial layer is different from that of the substrate;
removing the second hard mask layer;
forming a second epitaxial layer on the first epitaxial layer by taking the first hard mask layer as a mask, wherein the material of the second epitaxial layer is different from that of the first epitaxial layer; the method comprises the steps of,
and removing the first hard mask layer.
2. The method of manufacturing a semiconductor structure according to claim 1, wherein forming the first hard mask layer and the second hard mask layer stacked in this order on the substrate comprises:
forming a first hard mask material layer, a second hard mask material layer and a third hard mask material layer which are sequentially stacked on the substrate, wherein the material of the third hard mask material layer is the same as that of the first hard mask material layer;
Forming a patterned first photoresist layer on the third hard mask material layer, the first photoresist layer having an opening exposing the third hard mask material layer on the first peripheral region;
removing the third hard mask material layer on the first peripheral region by wet etching by taking the first photoresist layer as a mask, and taking the reserved third hard mask material layer as a third hard mask layer;
removing the first photoresist layer;
removing the second hard mask material layer on the first peripheral region by wet etching with the third hard mask layer as a mask, wherein the second hard mask material layer is reserved as the second hard mask layer;
and removing the third hard mask layer and the first hard mask material layer on the first peripheral region by wet etching, so that the first hard mask material layer is reserved as the first hard mask layer.
3. The method of claim 2, wherein a ratio of a thickness of the first hard mask material layer to a thickness of the third hard mask material layer is greater than or equal to 1 and less than or equal to 1.1.
4. The method of manufacturing a semiconductor structure according to any one of claims 1 to 3, further comprising, after removing the first hard mask layer:
Forming a first dielectric layer and a second dielectric layer which are sequentially stacked on the substrate, wherein openings exposing the second epitaxial layer positioned on the first peripheral region and exposing the second peripheral region are formed in the first dielectric layer and the second dielectric layer;
oxidizing the second epitaxial layer to convert the second epitaxial layer into a first gate oxide layer, and forming a second gate oxide layer on the second peripheral region;
forming a first gate structure on the first gate oxide layer, and forming P-type source and drain regions on two opposite sides of the first gate structure to form a P-type transistor, wherein a channel region of the P-type transistor comprises the first epitaxial layer;
and forming a second grid electrode structure on the second grid electrode oxide layer, and forming N-type source drain regions on two opposite sides of the second grid electrode structure to form an N-type transistor, wherein a channel region of the N-type transistor is positioned in the substrate.
5. The method of manufacturing a semiconductor structure according to claim 4, wherein forming the first dielectric layer and the second dielectric layer stacked in this order on the substrate comprises:
forming a first dielectric material layer, a second dielectric material layer and a third dielectric material layer which are sequentially stacked on the substrate, wherein the material of the third dielectric material layer is the same as that of the first dielectric material layer;
Forming a patterned second photoresist layer on the third dielectric material layer, the second photoresist layer having openings exposing the third dielectric material layer on the first and second peripheral regions;
removing the third dielectric material layer on the first peripheral region and the second peripheral region by wet etching by taking the second photoresist layer as a mask, and taking the reserved third dielectric material layer as a third dielectric layer;
removing the second photoresist layer;
removing the second dielectric material layer on the first peripheral region and the second peripheral region by wet etching by taking the third dielectric layer as a mask, and taking the reserved second dielectric material layer as the second dielectric layer;
and removing the third dielectric layer and the first dielectric material layer positioned on the first peripheral region and the second peripheral region by wet etching, wherein the first dielectric material layer is reserved as the first dielectric layer.
6. The method of claim 5, wherein a ratio of a thickness of the first dielectric material layer to a thickness of the third dielectric material layer is greater than or equal to 1 and less than or equal to 1.1.
7. The method of claim 5, wherein the material of the first dielectric layer comprises silicon oxide and the material of the second dielectric layer comprises one or more of silicon nitride and silicon oxynitride.
8. The method of manufacturing a semiconductor structure according to any one of claims 1 to 3 and 5 to 7, wherein forming the second epitaxial layer on the first epitaxial layer using the first hard mask layer as a mask, comprises:
forming a second epitaxial material layer on the first epitaxial layer and the first hard mask layer, wherein the second epitaxial material layer on the first epitaxial layer is in a single crystal state, and the second epitaxial material layer on the first hard mask layer is in a polycrystalline state;
selectively removing the second epitaxial material layer on the first hard mask layer, and reserving the second epitaxial material layer on the first epitaxial layer to serve as the second epitaxial layer.
9. The method of any one of claims 1-3 and 5-7, wherein the material of the substrate comprises silicon, the material of the first epitaxial layer comprises silicon germanium, the material of the second epitaxial layer comprises silicon, the material of the first hard mask layer comprises silicon oxide, and the material of the second hard mask layer comprises one or more of silicon nitride and silicon oxynitride; and/or the number of the groups of groups,
The array region has a buried transistor formed therein.
10. A method of fabricating a semiconductor structure according to any one of claims 1 to 3, wherein the thickness of the first epitaxial layer is 7-15nm; and/or the number of the groups of groups,
the thickness of the second epitaxial layer is 3-7nm.
CN202310943290.2A 2023-07-27 2023-07-27 Method for preparing semiconductor structure and semiconductor structure Pending CN116779546A (en)

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