CN116779001A - Method and device for refreshing NOR flash memory - Google Patents
Method and device for refreshing NOR flash memory Download PDFInfo
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Abstract
The invention relates to a refresh method of a NOR flash memory, which is used for generating new page addresses in the refresh of flash memory units, wherein the flash memory units in the NOR flash memory are divided into a plurality of arrays, each array comprises a plurality of blocks, each block comprises a plurality of word lines, each word line comprises a plurality of pages, and the refresh comprises: a first step of determining whether there is a flash memory cell to be refreshed by verification and scanning based on a page address of the array of flash memory cells, starting from a start page address of the array of flash memory cells; sequentially generating new page addresses, and repeating the step of the first step for each newly generated page address; and a second step of refreshing the flash memory cells determined to be required to be refreshed in the first step by a refresh program, wherein the refresh method of the NOR flash memory generates a next page address in an out-of-order manner based on a previous page address.
Description
Technical Field
The invention relates to a refreshing method and a refreshing device for a NOR flash memory.
Background
Semiconductor memories are an indispensable component of modern information processing systems, and flash memories (flash memories) are currently the most common nonvolatile memories, and current flash memories are mainly classified into NOR-type flash memories and NAND-type flash memories according to the memory cell array structure and the read/write manner. The basic operations of flash memory include writing (program), erasing (erase) and reading (read), wherein writing and erasing correspond to the charge and discharge processes of fg (floating gate layer) or ONO (silicon oxide-silicon nitride-silicon oxide) layer of flash memory, respectively.
In order to save the chip area, the flash memory chip storage area is generally placed in a physical centralized manner to form a storage matrix, and then is logically divided into a plurality of blocks. This structure determines that when an erase operation is performed on one of the blocks, since this block is physically connected to the surrounding block substrate and source region, it tends to have an influence on the adjacent other blocks. In general, to avoid over-erasing of a block "memory cell", a pre-program is generally performed before an erase operation, so that a portion of "1" in all "memory cells" of the block to be erased is changed to "0" and then the erase operation is performed on the block to be erased. Because the substrate and source regions of the "memory cells" between blocks are connected, preprogramming, overerase correction programming, soft programming, etc. all affect adjacent blocks that do not need to be erased, and the data of the "memory cells" can be changed as long as the impact time is sufficient, and erase disturbance occurs.
Disclosure of Invention
Technical problem to be solved by the invention
For a NOR flash memory, flash cells (flash cells) in the NOR flash memory are divided into a plurality of arrays (arrays) according to the capacity, the flash cells (flash cells) in each array (array) share a substrate, gates of the plurality of cells are connected with a word line (word line), an erase operation unit is a cluster (sector) (4 KB) or a block (block) (32/64 KB), and a plurality of blocks (block) (64 KB) are arranged in one array (array).
In general, in an erase operation of an SLC NOR flash memory, a high voltage (about +10v) of a substrate during an erase pulse may cause cumulative disturbance to flash cells (flash cells) on unselected word lines (word lines) in the same array (array), resulting in a gradual decrease in threshold voltage of the flash cells (flash cells) programmed on the unselected word lines (word lines) until the threshold voltage is lower than a read voltage Vrd, resulting in data errors, so a refresh sub-algorithm needs to be added during the erase algorithm to reprogram the flash cells (flash cells) programmed to have the threshold voltage higher than a specific value to offset the effect of the disturbance. However, when refreshing is performed by using the conventional refresh method, under a serious erase disturbance, it is possible to repeatedly refresh the blocks (blocks) having priority, but not refresh all the blocks (blocks), and the affected flash cells (flash cells) may fail to be read due to the inability to get refreshed, thereby causing a problem.
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a refresh method and apparatus for a NOR flash memory, which is improved in the scan order of the refresh algorithm, so that the algorithm does not preferentially refresh the blocks (blocks) scanned earlier, but refreshes each block (block) with a more uniform probability, thereby making the refresh algorithm more efficient and contributing to the improvement of the performance of the overall erase (erase) operation.
Technical proposal adopted for solving the technical problems
A refresh method for a NOR flash memory according to an embodiment of the present invention is for generating a new page address in a refresh of flash memory cells, the flash memory cells in the NOR flash memory being divided into a plurality of arrays, each array including a plurality of blocks, each block including a plurality of word lines, each word line including a plurality of pages, the refresh comprising: a first step of determining whether there is a flash memory cell to be refreshed by verification and scanning based on a page address of the array of flash memory cells, starting from a start page address of the array of flash memory cells; sequentially generating new page addresses, and repeating the step of the first step for each newly generated page address; and a second step of refreshing the flash memory cells determined to be required to be refreshed in the first step by a refresh program, wherein the refresh method of the NOR flash memory generates a next page address in an out-of-order manner based on a previous page address.
In the refresh method for a NOR flash memory according to the second aspect of the present invention, in the first aspect, it is preferable that the page address is obtained by sequentially combining a block address, a word line address, and a page sub-address.
In the second aspect of the refresh method for a NOR flash memory according to the third aspect of the present invention, it is preferable that each array of the NOR flash memory includes M blocks, each block includes N word lines, each word line includes P pages, wherein M, N, P is a natural number, and the page addresses are obtained by combining the forms of [ the block addresses, the word line addresses, the page sub-addresses ], wherein the block addresses are 0 to M-1, the word line addresses are 0 to N-1, and the page sub-addresses are 0 to P-1.
In a third aspect of the refresh method for a NOR flash memory according to the fourth aspect of the present invention, it is preferable that generating the new page address includes: the new page sub-address is the remainder obtained by dividing the old page sub-address +1 by P, and whether the page sub-address is carried or not is recorded; if the page sub-address does not carry, the new block address is equal to the old block address, otherwise, the new block address is the remainder obtained by dividing the old block address +1 by M, and whether the block address carries is recorded; if the block address does not carry, the new word line address is equal to the old word line address, otherwise, the new word line address is the remainder obtained by dividing the old word line address by N after adding word line offset; and combining the new block address, the new word line address and the new page sub-address in sequence to obtain the new page address.
In the third aspect of the refresh method for a NOR flash memory according to the fifth aspect of the present invention, it is preferable that M is 16, N is 64, and P is 4.
In the fourth aspect of the refresh method for a NOR flash memory according to the sixth aspect of the present invention, it is preferable that the word line offset is a scanning word line interval.
In the sixth aspect of the refresh method for a NOR flash memory according to the seventh aspect of the present invention, the word line offset is preferably 1, 2, 4 or 8.
An eighth aspect of the present invention relates to an apparatus for performing the refresh method for a NOR flash memory described in any one of the first to seventh aspects.
Effects of the invention
According to the invention, the scanning sequence of the refreshing algorithm is improved, so that the algorithm does not refresh the blocks (blocks) scanned first preferentially, but refreshes each block (block) according to more equal probability, so that the refreshing algorithm has higher efficiency, and the performance of the whole erase operation is improved.
Drawings
Fig. 1 is a flowchart showing the steps of a refresh sub-algorithm during an erase algorithm.
Fig. 2 is a diagram of an address generation algorithm in the refresh sub-algorithm, which is a schematic diagram showing an existing algorithm for generating a next page (page) address within the same array (array) according to a current page (page) address.
Fig. 3 is a diagram of an address generation algorithm in the refresh sub-algorithm, which is a schematic diagram showing an algorithm of generating a next page (page) address in the same array (array) range according to a current page (page) address according to the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings.
1. Refresh sub-algorithm in process of erase algorithm
Fig. 1 is a flowchart showing the steps of a refresh sub-algorithm during an erase algorithm. The following describes in detail with reference to fig. 1.
The refresh sub-algorithm (shown in fig. 1) in the erase algorithm process includes two main steps, namely scanning (first step, S1 to S6 in fig. 1) and refreshing (second step, step S7 to step S13 in fig. 1), where the refreshing is performed in blocks.
In the first step, two threshold voltages Vrd and Vpld 1 are employed. When the first scanning starts, a page (page) address is set as a start scanning page address of an array (array) in step S1.
Next, in steps S2 and S3, for the flash cell (flash cell) in the current page, the threshold voltage of the flash cell is determined by two read operations (i.e., scanning and verifying).
If no flash cell (flash cell) threshold voltage falls within a range between Vrd and Vpsrd1 within a page, then no refresh is considered necessary. That is, in the case where step S4 is Y, refreshing is not performed, but scanning of other pages in the array is continued.
Specifically, in this case, the flow advances to step S5, and it is confirmed whether or not it is the last page in the array, and if it is the last page (in the case of Y), the scanning is completed, and the flow ends. If it is not the last page (in the case of N), a new page address (next page address) is generated by an address generation algorithm, that is, step S6 (described later in detail), and the flow is returned and the processing of S2 to S5 described above is repeated.
If there is a flash cell (flash cell) within a page whose threshold voltage falls within a range between Vrd and Vpsrd1, then refresh is considered to be required. In this case, the page (page) address at this time is recorded and the process advances to the second step, that is, to step S7.
In the refresh step, two threshold voltages Vrd and vprd 2 are employed. In step S7, the page (page) address is set at the first refresh to the first page (page) address of the block (block) where the page (page) address recorded in the scanning step is located, that is, the load block start page address. Next, in steps S8, S9, the threshold voltage of the flash cell (flash cell) is determined by two read operations (i.e., scanning and verifying).
If there is a case where the threshold voltage of the flash cell (flash cell) falls within the range between Vrd and Vpsrd2 within one page, i.e., N in step S10, it is considered that refresh is required. A flash cell (flash cell) to be refreshed is programmed (program) to reach a threshold voltage Vpgm using a refresh program algorithm in step S11, and proceeds to step S12.
Conversely, if no flash cell (flash cell) has a threshold voltage within a range between Vrd and Vpsrd2 within one page, that is, Y in step S10, the process proceeds to step S12.
In step S12 it is determined whether it is the last page in the block, the algorithm ends when the page address is the last page in the block, otherwise the page address is incremented in step S13 and steps S7 to S12 are repeated.
2. Address generation algorithms in accordance with the prior art
As described above, in the scanning process (steps S2 to S6), a new page address needs to be generated through step S6. The address generation algorithm related to the prior art is shown in fig. 2.
The address generation algorithm is an algorithm for generating a next page (page) address from a current page (page) address within the same array (array). As shown in fig. 2, each array includes M blocks (blocks), each block includes N word lines (word lines), and each word line includes P pages (pages). Here, for convenience, it may be set that each array contains 16 blocks, each block contains 64 word lines, and each word line contains 4 pages. That is, m=16, n=64, and p=4.
The block address, the word line address and the page sub-address are sequentially combined to obtain the page address. Specifically, the page address is obtained by combining the forms of [ block address, word line address, page sub-address ], wherein the block address is 0 to M-1, the word line address is 0 to N-1, and the page sub-address is 0 to P-1.
That is, the address generation algorithm is mainly used to generate a new page sub-address (i.e., a next page sub-address), and based thereon, obtain a new page address (i.e., a next page address).
The address generation algorithm according to the prior art generates the new page sub-address in the order of page0, page1, page2, page3, starting from the first page (page 0) of the first word line (word 0) of the first block (block 0) in the order when generating the new page sub-address. When the page sub-address is carried, the word line offset is added to the address of the word line in sequence to obtain a new word line address, and the new page sub-address is obtained in sequence according to the new word line address. For example, when carrying to word line 1, the page sub-addresses are page4, page5, page6, page7.
Then, when the refresh of the first block (block 0) is completed, the next block (block 1, block2, … …, block M-1) is sequentially refreshed in the same manner until the refresh is completed.
A specific example is given below.
If a 12 bit address [19:8] is taken as an example, address [19:16] represents a block (block) address, each array (array) contains 16 blocks (blocks), address [15:10] represents a word line (word line) address, each block (block) contains 64 word lines (word line), address [9:8] represents a page (page) sub-address, and each word line (word line) contains 4 pages (pages).
A word line offset wl_ofest is defined, and is set to 1, 2, 4, 8, or the like, for example, at intervals of scanning word lines (word lines). When wl_offest is set to 1, the scanning is performed line by line in the word line order (i.e., word line0, word line 1, word lines 2, … …, word line N-1). And in the case of 2, the word lines are interlaced in word line order (i.e., word line0, word line 2, word lines 4, … …, word line N-1). And so on.
In this case, the algorithm for generating the next page address is as follows:
1. the new page sub-address is the remainder of the old page sub-address +1 divided by P, the last 2 bits of the binary address are reserved and whether the page sub-address is carried is recorded.
2. If the page sub-address does not carry, the new word line address is equal to the old word line address, otherwise the new word line address is the remainder of the old word line address plus the word line offset (wl_offset) divided by N, the last 6 bits of the binary address are reserved, and whether the word line address carries is recorded.
3. If the word line address does not carry, the new block address is equal to the old block address, otherwise, the new block address is the remainder obtained by dividing the old block address +1 by M, the last 4 bits of the binary address are reserved, and whether the block address carries is recorded.
4. The new block address, the new word line address and the new page sub-address are sequentially combined to obtain the next page address.
However, in the case of employing the address generation algorithm as described above, the following problems are encountered.
(1) Scanning and refreshing the flash memory cells in the entire array can take a long time, which can affect the performance of the erase operation.
(2) If the algorithm of interlacing and refreshing according to blocks is adopted for refreshing, the time of a single refreshing algorithm can be reduced, but partial memory cells are not refreshed.
(3) In severe disturbance situations, an algorithm employing interlacing and block-wise refreshing may result in only the previously scanned blocks being refreshed (repeated refreshes), while the remaining blocks cannot be refreshed, resulting in data errors.
3. The address generation algorithm of the invention
In order to solve the problems, the invention optimizes the address generation algorithm.
Fig. 3 is a diagram of an address generation algorithm in the refresh sub-algorithm, which is a schematic diagram showing an algorithm of generating a next page (page) address in the same array (array) range according to a current page (page) address according to the present invention.
As shown in fig. 3, each array includes M blocks (blocks), each block includes N word lines (word lines), and each word line includes P pages (pages). Here, for convenience, it may be set that each array contains 16 blocks, each block contains 64 word lines, and each word line contains 4 pages. That is, m=16, n=64, and p=4.
The block address, the word line address and the page sub-address are sequentially combined to obtain the page address. Specifically, the page address is obtained by combining the forms of [ block address, word line address, page sub-address ], wherein the block address is 0 to M-1, the word line address is 0 to N-1, and the page sub-address is 0 to P-1.
That is, the address generation algorithm is mainly used to generate a new page sub-address (i.e., a next page sub-address), and based thereon, obtain a new page address (i.e., a next page address).
The address generation algorithm according to the present invention generates the next page address in an out-of-order manner based on the previous page address.
Specifically, when generating a new page sub-address, starting from the first page (page 0) of the first word line (word 0) of the first block (block 0), the new page sub-addresses are sequentially generated in the order of page0, page1, page2, page 3. When the page sub-address is carried, the next block (block 1) is skipped to the block (block) address +1, and a new page sub-address is generated in the order of page0, page1, page2, and page 3. When the refresh of the first word line (word line 0) in all blocks (block) is completed, the word line address is carried back to the first block (block 0), the word line address is added with the word line offset to obtain a new word line address, new page sub-addresses are sequentially obtained according to the new word line address, and all blocks (block 0 to block M-1) are sequentially refreshed.
A specific example is given below. If a 12 bit address [19:8] is taken as an example, address [19:16] represents a block (block) address, each array (array) contains 16 blocks (blocks), address [15:10] represents a word line (word line) address, each block (block) contains 64 word lines (word line), address [9:8] represents a page (page) sub-address, and each word line (word line) contains 4 pages (pages).
A word line offset wl_ofest is defined, and is set to 1, 2, 4, 8, or the like, for example, at intervals of scanning word lines (word lines). When wl_offest is set to 1, the scanning is performed line by line in the word line order (i.e., word line0, word line 1, word lines 2, … …, word line N-1). And in the case of 2, the word lines are interlaced in word line order (i.e., word line0, word line 2, word lines 4, … …, word line N-1). And so on.
In this case, the algorithm for generating the next address is as follows:
1. the new page sub-address is the remainder of the old page sub-address +1 divided by P, the last 2 bits of the binary address are reserved and whether the page sub-address is carried is recorded.
2. If the page sub-address does not carry, the new block address is equal to the old block address, otherwise, the new block address is the remainder obtained by dividing the old block address +1 by M, the last 4 bits of the binary address are reserved, and whether the block address carries is recorded.
3. If the block address is not carried, the new word line address is equal to the old word line address, otherwise, the new word line address is the remainder of the old word line address plus the word line offset (wl_ofest) divided by N, and the last 6 bits of the binary address are reserved.
4. The new block address, the new word line address and the new page sub-address are sequentially combined to obtain the next page address.
By adopting the address generation method, the algorithm can refresh each block (block) without preferentially refreshing the block (block) scanned earlier, so that the efficiency of the refreshing algorithm is higher, and the performance of the whole erase operation is improved.
In addition, it is possible to avoid a situation in which the threshold voltage of the flash memory cell programmed on the unselected word line gradually decreases until it is lower than the read voltage, resulting in a data error, due to cumulative disturbance.
The present invention has been described in detail, but the above description is only an example in all aspects, and the present invention is not limited thereto. Numerous modifications, not illustrated, can be construed as being contemplated within the scope of the present invention.
Industrial applicability
The invention is applicable to the refreshing of NOR flash memories.
Claims (8)
1. A refresh method of NOR flash memory is used for generating new page address in the refresh of flash memory unit,
the flash memory cells in the NOR flash memory are divided into a plurality of arrays, each array including a plurality of blocks, each block including a plurality of word lines, each word line including a plurality of pages,
the refreshing includes:
a first step of determining whether there is a flash memory cell to be refreshed by verification and scanning based on a page address of the array of flash memory cells, starting from a start page address of the array of flash memory cells;
sequentially generating new page addresses, and repeating the step of the first step for each newly generated page address; and
a second step of refreshing the flash memory cells determined to be required to be refreshed in the first step by a refresh program,
the method for refreshing the NOR flash memory is characterized in that,
the next page address is generated in an out-of-order manner based on the previous page address.
2. The method for refreshing a NOR flash memory according to claim 1, wherein,
the page address is obtained by sequentially combining a block address, a word line address, and a page sub-address.
3. The method for refreshing a NOR flash memory according to claim 2, wherein,
each array of the NOR flash memory includes M blocks, each block including N word lines, each word line including P pages, wherein M, N, P is a natural number,
the page address is obtained by combining the forms of [ the block address, the word line address, the page sub-address ], wherein the block address is 0 to M-1, the word line address is 0 to N-1, and the page sub-address is 0 to P-1.
4. The method for refreshing a NOR flash memory according to claim 3, wherein,
generating a new said page address comprises the steps of:
the new page sub-address is the remainder obtained by dividing the old page sub-address +1 by P, and whether the page sub-address is carried or not is recorded;
if the page sub-address does not carry, the new block address is equal to the old block address, otherwise, the new block address is the remainder obtained by dividing the old block address +1 by M, and whether the block address carries is recorded;
if the block address does not carry, the new word line address is equal to the old word line address, otherwise, the new word line address is the remainder obtained by dividing the old word line address by N after adding word line offset;
and combining the new block address, the new word line address and the new page sub-address in sequence to obtain the new page address.
5. The method for refreshing a NOR flash memory according to claim 3, wherein,
the M is 16, the N is 64, and the P is 4.
6. The method for refreshing a NOR flash memory according to claim 4, wherein,
the word line offset is the spacing of the scanned word lines.
7. The method for refreshing a NOR flash memory according to claim 6, wherein,
the word line offset is set to 1, 2, 4 or 8.
8. An apparatus, characterized in that,
the apparatus performs the refresh method of NOR flash memory as claimed in any one of claims 1 to 7.
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| CN202310800165.6A CN116779001A (en) | 2023-06-30 | 2023-06-30 | Method and device for refreshing NOR flash memory |
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| CN202310800165.6A CN116779001A (en) | 2023-06-30 | 2023-06-30 | Method and device for refreshing NOR flash memory |
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