CN116775552A - Multichannel assembly line FFT treater based on FPGA - Google Patents
Multichannel assembly line FFT treater based on FPGA Download PDFInfo
- Publication number
- CN116775552A CN116775552A CN202310706774.5A CN202310706774A CN116775552A CN 116775552 A CN116775552 A CN 116775552A CN 202310706774 A CN202310706774 A CN 202310706774A CN 116775552 A CN116775552 A CN 116775552A
- Authority
- CN
- China
- Prior art keywords
- butterfly
- data
- transformation
- module
- conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 94
- 230000009466 transformation Effects 0.000 claims abstract description 69
- 238000004364 calculation method Methods 0.000 claims abstract description 51
- 238000012545 processing Methods 0.000 claims abstract description 38
- 238000013500 data storage Methods 0.000 claims abstract description 26
- 238000012544 monitoring process Methods 0.000 claims abstract description 5
- 230000015654 memory Effects 0.000 claims description 28
- 238000000605 extraction Methods 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 21
- 108091006146 Channels Proteins 0.000 claims description 12
- 239000000203 mixture Substances 0.000 claims description 4
- 238000010295 mobile communication Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 10
- 238000004891 communication Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000010183 spectrum analysis Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/141—Discrete Fourier transforms
- G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Data Mining & Analysis (AREA)
- Discrete Mathematics (AREA)
- Algebra (AREA)
- Databases & Information Systems (AREA)
- Software Systems (AREA)
- Complex Calculations (AREA)
Abstract
The application relates to the technical field of mobile communication signal processing, in particular to a multichannel pipeline FFT processor based on an FPGA, which comprises the following components: the input data storage module is used for storing data to be subjected to FFT conversion in a multi-channel input mode; a computation control module for generating FFT transformed control signals; the cascade twiddle factor storage module is used for storing twiddle factors of the butterfly transformation module; the butterfly transformation unit consists of a plurality of butterfly transformation modules and is used for finishing FFT butterfly transformation calculation; and the output data storage module is used for storing butterfly transformation data and finishing multi-channel data output processing. By adopting the technical scheme of the application, the pipeline FFT processing of the multichannel data can be realized, the multichannel FFT processing efficiency is improved, and the FPGA resource overhead is reduced. The technical scheme of the application can be widely applied to the fields of 4G/5G mobile communication, monitoring receiver signal processing and the like.
Description
Technical Field
The application relates to the technical field of mobile communication signal processing, in particular to a multichannel pipeline FFT processor based on an FPGA.
Background
Fast Fourier Transform (FFT) algorithms are widely used in mobile communications to achieve a time-to-frequency domain conversion of signals. An OFDM-based communication system employs an FFT algorithm to effect the conversion of a time domain signal to a frequency domain signal. The current 5G NR communication standard adopts an OFDM technology, and the FFT operation result directly influences the performance of the whole 5G communication system.
The FFT algorithm can be implemented by FFT processor hardware, and the FFT processor hardware is mainly implemented by four methods of sequential processing, pipeline processing, parallel processing and array processing. The pipeline architecture is a main method in the current communication system, and the method has the advantages of high processing speed and less occupied resources, and is suitable for large-scale circuit implementation. However, in the current 5G NR communication, with the application of the MIMO technology, the multi-antenna transceiving requirement increases, so that when processing a multi-antenna service, a plurality of FFT processing pipelines are required to be opened correspondingly, which causes a multiple increase in resources and greatly increases the hardware resource overhead.
However, for the design of the FFT processor hardware for communication signal processing, the wide range of FPGAs is currently adopted, but due to the limited resources of FPGAs, multichannel parallel computation cannot be arranged without limitation. The hardware resource overhead is also very high if the multi-channel computing effect is to be achieved.
Disclosure of Invention
The application aims to provide a multichannel pipeline FFT processor based on an FPGA, which uses a multichannel data serial pipeline to carry out FFT processing, thereby greatly reducing the resource consumption of the FPGA.
In order to achieve the above purpose, the multi-channel pipelined FFT processor based on FPGA is provided, comprising an input data storage module, a calculation control module, a cascade twiddle factor storage module, a butterfly conversion unit and an output data storage module, wherein the butterfly conversion unit comprises a plurality of butterfly conversion modules connected in series;
an input data storage module: the method comprises the steps of receiving input multichannel parallel data and configuration parameters, carrying out parallel-to-serial conversion of the multichannel parallel data, and carrying out conversion processing on the multichannel parallel data according to a configured extraction method to obtain a new data sequence which is serially arranged according to a channel sequence;
and the calculation control module is used for: the device is used for generating a reference data address and a control signal required by the butterfly conversion unit for butterfly conversion and a cascade twiddle factor memory read-write signal according to the configuration parameters and the new data sequence;
a cascading twiddle factor storage module: the cascade twiddle factor coefficients are used for storing cascade twiddle conversion performed by each butterfly conversion module;
butterfly transformation unit: the method comprises the steps that a new data sequence is calculated step by step through butterfly transformation modules, and each level of butterfly transformation module is connected with a calculation control module in parallel and is calculated according to a control signal of the calculation control module; the cascade twiddle factor storage module is used for storing cascade twiddle factor coefficients according to the cascade twiddle factor storage read-write signals after the calculation of each level of butterfly transformation module is completed and before the calculation of each level of butterfly transformation module is transmitted to the next level of butterfly transformation module, and multiplying the calculation result of the current butterfly transformation module by the cascade twiddle factor coefficients;
an output data storage module: the device is used for temporarily storing the output data processed by the butterfly conversion unit, converting the output data according to a configured extraction method and converting the serial-parallel conversion of the multichannel data.
Further, the FFT processor implements an N-point-based rFFT processor for parallel input multi-channel parallel data, where n=2 M M is a positive integer, r is a transformation base number of the FFT processor, and the configuration parameters comprise channel numbers, data addresses and data valid flag signals corresponding to the multichannel parallel data; the input data storage module converts multi-channel parallel data with N points into new data sequences which are serially arranged according to the channel sequence.
Further, the extraction method comprises a time extraction method DIT and a frequency domain extraction method DIF, wherein for the operation of the time extraction method DIT, the data input into the butterfly transformation unit are input in a reverse order and output in a positive order, and finally a new data sequence is obtained; for the operation based on the frequency domain extraction method DIF, the data input into the butterfly transformation unit is input in a positive sequence and output in a reverse sequence, and finally a new data sequence is obtained.
Further, the butterfly transformation modules in the butterfly transformation unit are all basic rL-level butterfly transformation modules and are connected in sequence, wherein L=log r N，N＝2 M M is a positive integer, and r is the transformation base of the FFT processor; according to the difference of the FFT calculation point number N and the transformation base r, different butterfly transformation modules are designed according to the actually configured base r; when a mixed base is adopted, sequentially combining butterfly conversion modules corresponding to each base r to obtain butterfly conversion modules; the butterfly conversion processing length of the butterfly conversion module of each stage in the butterfly conversion unit is respectively as follows:
where r is the actual transform basis of the corresponding stage for the mixture basis.
Further, the control signal includes:
the data memory read-write enabling signal is used for controlling the butterfly conversion unit to read and write the data memory;
the data is subjected to a basic butterfly operator control signal to control the basic butterfly calculator to calculate;
the butterfly conversion unit is multiplied by a twiddle factor enabling signal, and the required data is controlled to be multiplied by a cascade twiddle factor coefficient;
the butterfly transformation module comprises:
a data storage: the butterfly conversion module is used for storing data input into the butterfly conversion module according to the read-write enabling signal of the data memory;
base r butterfly calculator: the butterfly transformation calculation of the base r is carried out on the data after the control signal of the basic butterfly operator is received;
cascaded twiddle factor multipliers: the method comprises the steps that after a butterfly transformation unit is received and multiplied by a twiddle factor enabling signal, complex multiplication is carried out on a calculation result of a radix r butterfly calculator and a cascade twiddle factor coefficient;
status monitor: and the data processing unit is used for monitoring whether the data processed by the radix r butterfly calculator and the cascade twiddle factor multipliers overflows or not and generating an overflow mark.
Further, the radix r butterfly calculator basically comprises 4 adders for completing basic butterfly operation of data.
Further, the cascade twiddle factor multiplier includes:
a complex multiplier for completing complex multiplication of the output result of the radix r butterfly converter and the output data of the twiddle factor memory; and the cascade twiddle factor multipliers are dynamically configured according to the configured FFT conversion length N.
Principle and advantage:
compared with the prior art, the application has the following characteristics:
1. because the application adopts the FPGA to realize the FFT processor, the resource cost of a multiplier for calculating FFT and the like is reduced when the multichannel application is carried out, and the application can be suitable for FFT processing of various multichannel communication systems;
2. the application simplifies the data storage control logic in the pipeline FFT processor, only adopts a sequential storage mode, reduces the read-write operation of the memory and improves the calculation efficiency;
3. the method is suitable for FFT calculation with any length and any FFT base combination.
Drawings
FIG. 1 is a block diagram of the overall architecture of an FPGA-based multichannel pipelined FFT processor according to an embodiment of the present application;
fig. 2 is a block diagram of a butterfly conversion unit according to an embodiment of the present application;
FIG. 3 is a block diagram of a radix-8 butterfly transform module according to an embodiment of the application;
FIG. 4 is a block diagram of the basic butterfly operator of an embodiment of the application;
FIG. 5 is a data flow diagram of a radix-8 butterfly transformation module according to one embodiment of the application;
FIG. 6 is a schematic diagram of data processing according to an embodiment of the present application;
FIG. 7 is a schematic diagram illustrating parallel-to-serial conversion and corresponding data address indication according to an embodiment of the present application;
FIG. 8 is a diagram illustrating a calculation control signal according to an embodiment of the present application.
Detailed Description
The following is a further detailed description of the embodiments:
examples
An FPGA-based multichannel pipelined FFT processor implementing an N-point radix FFT processor for parallel input multichannel parallel data, where n=2 M M is a positive integer, and r is the transform radix of the FFT processor. Basically as shown in fig. 1, including inputs for multi-channel parallel data and configuration parameters and outputs for FFT processor calculations, the device comprises an input data storage module, a calculation control module, a cascade twiddle factor storage module, a butterfly conversion unit and an output data storage module, wherein the butterfly conversion unit comprises a plurality of butterfly conversion modules which are connected in series.
An input data storage module: the system comprises a multi-channel parallel data input end, a multi-channel parallel data output end, a multi-channel configuration parameter input end, a multi-channel parallel data output end and a multi-channel parallel data input end, wherein the multi-channel parallel data input end is used for receiving the input multi-channel parallel data and the multi-channel parallel data output end, the multi-channel parallel data input end is used for receiving the input multi-channel parallel data and the configuration parameter from the multi-channel parallel data input end, the multi-channel parallel data input end is used for carrying out parallel-serial conversion processing according to a; the configuration parameters comprise channel numbers, data addresses and data valid flag signals corresponding to the multichannel parallel data; in this embodiment, the input data storage module converts multi-channel parallel data with N points in length into a new data sequence serially arranged in channel order.
The extraction method comprises a time extraction method DIT and a frequency domain extraction method DIF, wherein for the operation of the time extraction method DIT, the data input into the butterfly transformation unit are input in a reverse order and output in a positive order, and finally a new data sequence is obtained; for the operation based on the frequency domain extraction method DIF, the data input into the butterfly transformation unit is input in a positive sequence and output in a reverse sequence, and finally a new data sequence is obtained. The two have completely symmetrical butterfly structures, and the difference is that the input and output sequences are different.
And the calculation control module is used for: the device is used for generating a reference data address and a control signal required by the butterfly conversion unit for butterfly conversion and a cascade twiddle factor memory read-write signal according to the configuration parameters and the new data sequence; in this embodiment, the reference data address required for calculation by the butterfly conversion unit is recalculated according to the track number, the corresponding data address and the data valid flag signal of the received multi-channel parallel data, and the control signal required by the butterfly conversion unit is generated according to the pipeline butterfly conversion processing flow.
A cascading twiddle factor storage module: the cascade twiddle factor coefficients are used for storing cascade twiddle conversion performed by each butterfly conversion module;
butterfly transformation unit: the butterfly conversion module is used for calculating the new data sequence step by step through the butterfly conversion module, and each level of butterfly conversion module is connected to the calculation control module in parallel and calculates according to the control signal of the calculation control module; and the cascade twiddle factor storage module is used for reading the cascade twiddle factor coefficient according to the cascade twiddle factor storage read-write signal after the calculation of each level butterfly conversion module is completed and before the transmission of the calculation result to the next level butterfly conversion module, and multiplying the calculation result of the current butterfly conversion module by the cascade twiddle factor coefficient.
As shown in fig. 2, the butterfly transformation unit includes L-level radix r butterfly transformation modules and is connected sequentially, where l=log r N，N＝2 M M is a positive integer, and r is the transformation base of the FFT processor; different butterfly transformation modules can be designed according to different FFT calculation points N and transformation bases r which are actually configured; when a mixed base is adopted, sequentially combining butterfly conversion modules corresponding to each base r to obtain butterfly conversion modules; for example, for a data sequence with N of 8192 points, a mixed base of base 8 and base 2 is adopted, and the data sequence can be divided into a 4-level base 8 butterfly conversion module and a 1-level base 2 butterfly conversion module to form the butterfly conversion unit.
The butterfly conversion processing length of the butterfly conversion module of each stage in the butterfly conversion unit is respectively as follows:
where r is the actual transform basis of the corresponding stage for the mixture basis.
The control signal includes:
the data memory read-write enabling signal is used for controlling the butterfly conversion unit to read and write the data memory;
the data is subjected to a basic butterfly operator control signal to control the basic butterfly calculator to calculate;
the butterfly transformation unit multiplies the twiddle factor enabling signal to control the multiplication of the required data by the cascade twiddle factor coefficients.
As shown in fig. 3, the butterfly transformation module includes:
a data storage: the butterfly conversion module is used for storing data input into the butterfly conversion module according to the read-write enabling signal of the data memory;
base r butterfly calculator: the butterfly transformation calculation of the base r is carried out on the data after the control signal of the basic butterfly operator is received; the radix r butterfly calculator is different according to the difference of radix r, and the basic composition comprises a plurality of adders for completing basic butterfly operation of data; in this embodiment, 4 adders are used to complete the cross addition and subtraction computation of a pair of input complex data, as shown in fig. 4, a set of basic butterfly operators is formed by the adders, so as to implement the data addition and subtraction function.
Cascaded twiddle factor multipliers: the method comprises the steps that after a butterfly transformation unit is received and multiplied by a twiddle factor enabling signal, complex multiplication is carried out on a calculation result of a radix r butterfly calculator and a cascade twiddle factor coefficient; the cascade twiddle factor multiplier includes: a complex multiplier for completing complex multiplication of the output result of the radix r butterfly converter and the output data of the twiddle factor memory; and the cascade twiddle factor multipliers are dynamically configured according to the configured FFT conversion length N.
Status monitor: and the data processing unit is used for monitoring whether the data processed by the radix r butterfly calculator and the cascade twiddle factor multipliers overflows or not and generating an overflow mark.
An output data storage module: the device is used for temporarily storing the output data processed by the butterfly conversion unit, converting the output data according to a configured extraction method and converting the serial-parallel conversion of the multichannel data. There are also data addresses, benefit flags, etc.
For convenience of explanation: taking the basic 8DIF FFT algorithm as an example, let us consider parallel input 4 channels of data, each channel of input data being a complex sequence of long N points, where n=8 is satisfied L . The technical scheme in the embodiment of the application is described in detail by combining the drawings in the embodiment of the application. The following examples are illustrative only and are not to be construed as limiting the application.
As shown in fig. 5, the butterfly conversion module structure of the radix 8DIF FFT includes 3 basic butterfly operators connected in sequence, and according to the pipeline processing architecture, 12 adders, 2 complex multipliers and 2 data memories are needed.
Fig. 6 is a data flow diagram of an embodiment of the present application, where a butterfly transformation unit is formed by a plurality of butterfly transformation modules according to a configured data length N and a transformation basis r. Each butterfly transformation module performs parallel computation along the pipeline structure, and the data processing process is described in detail below with reference to the data flow diagram.
Writing 4 paths of parallel data into the input data storage module, wherein the input data storage module mainly completes two processes: first, according to the extraction method of the configuration, the data sequence processing is carried out. For DIT extraction, converting the data sequence into a reverse sequence, wherein the embodiment adopts DIF extraction, and the data sequence is a positive sequence; second, the input 4-channel, N-point long parallel data is converted into a new data sequence serially arranged in channel order, i.e., the new data sequence is 4N long, as shown in fig. 7.
The calculation control module recalculates to generate a new serial data address (0, 1,2, …, 4N-1) according to the input data channel number (0, 1, & 3) and the data address (0, 1, … N-1), generates a read enable signal of the data storage module according to the new serial data address, reads memory data and inputs the memory data into the butterfly conversion unit; simultaneously generating the butterfly conversion unit control signal, comprising: the data memory read-write enabling signal in the butterfly conversion unit is used for controlling the butterfly conversion unit to read and write the data memory and controlling basic butterfly operation calculation; the butterfly conversion module is used for cascading twiddle factor register reading signals and reading cascading twiddle factor parameters; the butterfly operator twiddle factor multiply enable signal controls the butterfly operator to multiply the data calculated by the cascade twiddle factor coefficient.
The data are sequentially input into the butterfly conversion unit, the data are calculated step by step through the butterfly conversion modules, and each level of butterfly conversion module calculates according to the control parameters of the control unit. As shown in fig. 8, the control signal generated by the calculation control module and the calculation process of the radix-8 butterfly transformation module are shown, the input sequence length is N (i), the radix-8 butterfly transformation module is composed of 3 layers of butterfly operators, and the lengths of the butterfly operation sequences corresponding to each layer are respectively:
therefore, the depth of the data memory corresponding to each butterfly operator layer is
As shown in fig. 8, the data sequence is input into the butterfly conversion unit, in the first stage of the butterfly conversion module, according to the instruction of the read-write signal of the first layer butterfly operator data memory, when the signal is high, the input data is written into the data memory, and when the instruction is low, the data is read out from the data memory, that is, for DIF extraction, the first half of the input data sequence is stored into the data memory, then the memory is read out, and butterfly operation is performed with the second half of the data sequence. Further, for the butterfly operator calculation result, according to the first layer butterfly operator twiddle factor calculation signal indication, multiplying partial data by a cascade twiddle factor coefficient, and then for the complex multiplication result, inputting the second layer butterfly operator into a data storage.
Further, the processing procedures of the second layer butterfly operator and the third layer butterfly operator are the same as those of the first layer butterfly operator, and are indicated by control signals of the calculation control module to perform calculation processing. In the third layer butterfly operator, the butterfly operator twiddle factor calculation is not included, and after the third layer butterfly operator calculation is completed, a data result is output.
After the first-stage butterfly computation is completed, multiplying the data by a cascade butterfly transformation twiddle factor to complete the data computation of the first-stage butterfly transformation module, and then outputting the data.
In the calculation process of each butterfly operator layer, data saturation judgment is designed, whether data overflows in the calculation process is judged, and an overflow mark is output.
Further, the processing of each stage of butterfly conversion module in the butterfly conversion unit is the same, a corresponding control signal is generated by the calculation control module, and the parallel calculation processing of each stage of butterfly conversion module is performed.
In the application, the butterfly transformation and data storage unit of the FFT adopts a pipeline architecture, the butterfly transformation of each stage is composed of a memory and an independent butterfly transformation module, the calculation is performed step by step in sequence, and the butterfly transformation length is reduced step by step. And the pipeline structure is adopted to improve the FFT operation efficiency, each stage of butterfly transformation is performed in parallel, and when the input data rates are matched, the total system operation time is only the time of one stage of pipeline. The method has the advantages of high processing speed and moderate consumed hardware resources, and for FFT operation with different points, FFT conversion with different points can be realized by only adding or deleting the butterfly conversion module series.
The application provides an FPGA-based multichannel pipeline FFT processor implementation method, which can be applied to applications such as spectrum analysis in digital signal processing, OFDM signal processing in 4G LTE/5G NR, monitoring receiver signal processing and the like, and has important significance and application. The application solves the problem of larger resource expenditure when the multichannel parallel data sequence is processed by FFT, uses a primary pipeline structure to serially process the multichannel parallel data, and saves the resources such as a multiplier and the like under the same storage resource utilization. Therefore, the application can be applied to the implementation of a multi-channel FFT processor realized by an FPGA.
The foregoing is merely exemplary of the present application, and the specific structures and features well known in the art will be described in detail herein so that those skilled in the art will be able to ascertain the general knowledge of the technical field of the application, whether it is the application date or the priority date, and to ascertain all of the prior art in this field, with the ability to apply the conventional experimental means before this date, without the ability of those skilled in the art to make various embodiments with the benefit of this disclosure. It should be noted that modifications and improvements can be made by those skilled in the art without departing from the structure of the present application, and these should also be considered as the scope of the present application, which does not affect the effect of the implementation of the present application and the utility of the patent. The protection scope of the present application is subject to the content of the claims, and the description of the specific embodiments and the like in the specification can be used for explaining the content of the claims.
Claims (7)
1. The utility model provides a multichannel pipelined FFT treater based on FPGA which characterized in that: the device comprises an input data storage module, a calculation control module, a cascade twiddle factor storage module, a butterfly conversion unit and an output data storage module, wherein the butterfly conversion unit comprises a plurality of butterfly conversion modules which are connected in series;
an input data storage module: the method comprises the steps of receiving input multichannel parallel data and configuration parameters, carrying out parallel-to-serial conversion of the multichannel parallel data, and carrying out conversion processing on the multichannel parallel data according to a configured extraction method to obtain a new data sequence which is serially arranged according to a channel sequence;
and the calculation control module is used for: the device is used for generating a reference data address and a control signal required by the butterfly conversion unit for butterfly conversion and a cascade twiddle factor memory read-write signal according to the configuration parameters and the new data sequence;
a cascading twiddle factor storage module: the cascade twiddle factor coefficients are used for storing cascade twiddle conversion performed by each butterfly conversion module;
butterfly transformation unit: the method comprises the steps that a new data sequence is calculated step by step through butterfly transformation modules, and each level of butterfly transformation module is connected with a calculation control module in parallel and is calculated according to a control signal of the calculation control module; the cascade twiddle factor storage module is used for storing cascade twiddle factor coefficients according to the cascade twiddle factor storage read-write signals after the calculation of each level of butterfly transformation module is completed and before the calculation of each level of butterfly transformation module is transmitted to the next level of butterfly transformation module, and multiplying the calculation result of the current butterfly transformation module by the cascade twiddle factor coefficients;
an output data storage module: the device is used for temporarily storing the output data processed by the butterfly conversion unit, converting the output data according to a configured extraction method and converting the serial-parallel conversion of the multichannel data.
2. The FPGA-based multi-channel pipelined FFT processor of claim 1, wherein: the FFT processor realizes an N-point base rFFT processor for parallel input multi-channel parallel data, wherein N=2 M M is a positive integer, r is a transformation base number of the FFT processor, and the configuration parameters comprise channel numbers, data addresses and data valid flag signals corresponding to the multichannel parallel data; the input data storage module converts multi-channel parallel data with N points into new data sequences which are serially arranged according to the channel sequence.
3. The FPGA-based multi-channel pipelined FFT processor of claim 2, wherein: the extraction method comprises a time extraction method DIT and a frequency domain extraction method DIF, wherein for the operation of the time extraction method DIT, the data input into the butterfly transformation unit are input in a reverse order and output in a positive order, and finally a new data sequence is obtained; for the operation based on the frequency domain extraction method DIF, the data input into the butterfly transformation unit is input in a positive sequence and output in a reverse sequence, and finally a new data sequence is obtained.
4. A method according to claim 3The utility model provides a multichannel pipelined FFT treater based on FPGA which characterized in that: the butterfly transformation modules in the butterfly transformation unit are all basic rL-level butterfly transformation modules and are connected in sequence, wherein L=log r N，N＝2 M M is a positive integer, and r is the transformation base of the FFT processor; according to the difference of the FFT calculation point number N and the transformation base r, different butterfly transformation modules are designed according to the actually configured base r; when a mixed base is adopted, sequentially combining butterfly conversion modules corresponding to each base r to obtain butterfly conversion modules; the butterfly conversion processing length of the butterfly conversion module of each stage in the butterfly conversion unit is respectively as follows:
where r is the actual transform basis of the corresponding stage for the mixture basis.
5. The FPGA-based multi-channel pipelined FFT processor of claim 4, wherein: the control signal includes:
the data memory read-write enabling signal is used for controlling the butterfly conversion unit to read and write the data memory;
the data is subjected to a basic butterfly operator control signal to control the basic butterfly calculator to calculate;
the butterfly conversion unit is multiplied by a twiddle factor enabling signal, and the required data is controlled to be multiplied by a cascade twiddle factor coefficient;
the butterfly transformation module comprises:
a data storage: the butterfly conversion module is used for storing data input into the butterfly conversion module according to the read-write enabling signal of the data memory;
base r butterfly calculator: the butterfly transformation calculation of the base r is carried out on the data after the control signal of the basic butterfly operator is received;
cascaded twiddle factor multipliers: the method comprises the steps that after a butterfly transformation unit is received and multiplied by a twiddle factor enabling signal, complex multiplication is carried out on a calculation result of a radix r butterfly calculator and a cascade twiddle factor coefficient;
status monitor: and the data processing unit is used for monitoring whether the data processed by the radix r butterfly calculator and the cascade twiddle factor multipliers overflows or not and generating an overflow mark.
6. The FPGA-based multi-channel pipelined FFT processor of claim 5, wherein: the radix r butterfly calculator basically comprises 4 adders and is used for completing basic butterfly operation of data.
7. The FPGA-based multi-channel pipelined FFT processor of claim 6, wherein: the cascade twiddle factor multiplier includes:
a complex multiplier for completing complex multiplication of the output result of the radix r butterfly converter and the output data of the twiddle factor memory; and the rotating cascade factor multiplier is also used for dynamically configuring the rotating cascade factor multiplier according to the configured FFT conversion length N.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310706774.5A CN116775552A (en) | 2023-06-14 | 2023-06-14 | Multichannel assembly line FFT treater based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310706774.5A CN116775552A (en) | 2023-06-14 | 2023-06-14 | Multichannel assembly line FFT treater based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116775552A true CN116775552A (en) | 2023-09-19 |
Family
ID=88012727
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310706774.5A Pending CN116775552A (en) | 2023-06-14 | 2023-06-14 | Multichannel assembly line FFT treater based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116775552A (en) |
-
2023
- 2023-06-14 CN CN202310706774.5A patent/CN116775552A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6247034B1 (en) | Fast fourier transforming apparatus and method, variable bit reverse circuit, inverse fast fourier transforming apparatus and method, and OFDM receiver and transmitter | |
| Chen et al. | An indexed-scaling pipelined FFT processor for OFDM-based WPAN applications | |
| KR100989797B1 (en) | Fast fourier transform/inverse fast fourier transform operating core | |
| CN106803750B (en) | Multichannel running water FIR filter | |
| US9727531B2 (en) | Fast fourier transform circuit, fast fourier transform processing method, and program recording medium | |
| Liu et al. | A high performance four-parallel 128/64-point radix-2 4 FFT/IFFT processor for MIMO-OFDM systems | |
| CN104657334B (en) | A kind of base 2-4-8 mixed base butterfly of fast Fourier variation calculates device and its application | |
| US9164959B1 (en) | Discrete fourier transform calculation method and apparatus | |
| Kavitha et al. | An efficient FPGA architecture for reconfigurable FFT processor incorporating an integration of an improved CORDIC and Radix-2 r Algorithm | |
| CN116775552A (en) | Multichannel assembly line FFT treater based on FPGA | |
| CN108008665B (en) | Large-scale circular array real-time beam former based on single-chip FPGA and beam forming calculation method | |
| Su et al. | Reconfigurable FFT design for low power OFDM communication systems | |
| Wenqi et al. | Design of fixed-point high-performance FFT processor | |
| KR20080040978A (en) | Parallel and pipelined radix - 2 to the fourth power fft processor | |
| CN115033293A (en) | Zero-knowledge proof hardware accelerator, generating method, electronic device and storage medium | |
| CN101764778B (en) | Base band processor and base band processing method | |
| Tsai et al. | Power-efficient continuous-flow memory-based FFT processor for WiMax OFDM mode | |
| Yuan et al. | A 256-point dataflow scheduling 2× 2 MIMO FFT/IFFT processor for IEEE 802.16 WMAN | |
| Dora et al. | Low complexity implementation of OTFS transmitter using fully parallel and pipelined hardware architecture | |
| Yan et al. | Implementation of an OFDM underwater acoustic communication system on an underwater vehicle with multiprocessor structure | |
| KR20120109214A (en) | Fft processor and fft method for ofdm system | |
| Yuan et al. | Pruning split-radix FFT with time shift | |
| CN101833540A (en) | Signal processing method and device | |
| CN100388699C (en) | Discrete Fourier transform equipment of ADSL system | |
| CN107454030B (en) | Power line broadband carrier semi-parallel transmitter and implementation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |