CN116774564A

CN116774564A - Free window selection method applied to array readout circuit

Info

Publication number: CN116774564A
Application number: CN202310733823.4A
Authority: CN
Inventors: 吴金; 胡闽伟; 万成功; 郑丽霞; 孙伟锋
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2023-06-20
Filing date: 2023-06-20
Publication date: 2023-09-19

Abstract

The application discloses a free window selection method applied to an array reading circuit. In the array configuration stage, a configuration module supports the size and the position of a user-defined window, and an execution module activates pixels in the window according to configuration information and forms a special data transmission path; in the array quantization stage, the execution module selects a time-to-digital converter to quantize photon flight time; in the array transmission stage, the transmission module adaptively adjusts the transmission time length according to the window size, and the quantized data are orderly output from a special data transmission channel. The window selection circuit can provide various spatial resolutions and frame frequency selections on the premise of ensuring the consistency of the time resolutions of the arrays, improves the application flexibility of the arrays, reduces the system power consumption and has better portability.

Description

Free window selection method applied to array readout circuit

Technical Field

The application belongs to the technical field of laser radar imaging, and is applied to a large-scale reading circuit system which directly measures flight time and needs to face a complex environment, in particular relates to a free window selection method applied to an array reading circuit.

Background

In the conventional readout circuit (ReadOutIntegratedCircuit, ROIC), performance indexes are mutually restricted, and in order to improve the spatial resolution, problems of crosstalk, thermal pixels, data size, pixel size and the like must be solved. In addition, the conventional ROIC generally sacrifices performance in other aspects when solving the above-mentioned problems, and although a balance point can be achieved by combining multiple technologies, compatibility between different technologies increases design difficulty, such as combining multiple echo and macro-pixel technologies, and the time and space information of echo photons need to be recorded at the same time, but macro-pixels increase difficulty in recording space information. Therefore, the advantages of multiple technologies are integrated within a limited pixel size, so that the ROIC can effectively work when facing more complex environments, and the biggest difficulty is reached. Window selection techniques, as an effective means to address the above difficulties, allow both high resolution, full window, wide field mode readout, and readout at high data rates over a narrow field of view.

The existing window selection technology mainly comprises two types, one type is applied to an ROIC taking a transimpedance amplifier as a main body, and is realized by adopting a Gray code decoder, the window selection has strong freedom, but the imaging speed is limited by a decoding and reading mode; another type of application is in ROIC, which is based on a Time-to-DigitalConverter, TDC converter (Time-to-DigitalConverter, TDC), where the position of a single spot is tracked by photon counting, and the pixels exceeding the counting threshold re-enable TDC, so as to implement window selection, where the intelligentization is high but the size of the maximum window is limited by the preset spot diameter, and where the accuracy of photon counting directly affects the tracking performance. It can be seen that the existing window selection technology cannot achieve both high-speed reading and high-degree-of-freedom window selection.

Disclosure of Invention

The application aims to provide a free window selection method applied to an array reading circuit, which can provide various spatial resolutions and frame frequency selections on the premise of ensuring consistent time resolution of a TDC array, improves the application flexibility of an ROIC, has great significance on the expansion of the scale of the ROIC, and solves the technical problem that the complex environment limits the scale, performance and power consumption of ROIC pixels.

In order to solve the technical problems, the specific technical scheme of the application is as follows:

a free window selection method applied to an array readout circuit comprises a transmission module, a configuration module and an execution module; wherein:

the reset signal, the flag bit, the configuration data and the configuration clock required by the configuration module are all programmed and input by a user; because the programming information is set as the input of the upper left corner of the read-out circuit ROIC, when the ROIC is regarded as a plane rectangular coordinate system, the coordinate origin is placed at the lower right corner of the ROIC, and meanwhile, the whole time sequence adopts the sequence of firstly configuring and then operating the ROIC; the configuration module is formed by connecting a D trigger and a two-choice selector in parallel and serves as a transverse axis X and a longitudinal axis Y of a coordinate system; when the outputs of the ith configuration module of the horizontal axis and the jth configuration module of the vertical axis are both high levels, the horizontal axis X is represented _i Longitudinal axis Y _j All valid, the pixel unit corresponding to the ith row and ith column in the ROIC is enabled, and the enabled pixel unit is called as a pixel in the window; conversely, if the horizontal axis X _i Longitudinal axis Y _j When only one pixel is valid or not, the pixel unit corresponding to the ith row and the ith column in the ROIC is disabled, and the disabled pixel is called as a pixel outside the window; thus, window size, location, number represent the size, location, and number of enabled pixels, and various windows are formed by the configuration module processing different configuration data and configuration clocks, with the minimum window size allowing configuration to be 1×1;

the execution module is used as a part of each pixel unit, and the cooperative configuration module is used for controlling the pixel units; the pixel unit consists of a Single Photon Avalanche Diode (SPAD), a quenching circuit, a time-to-digital converter (TDC) and an execution module, wherein the execution module consists of two AND gates, a two-in-one selector and a demultiplexer; the output of the configuration module and the reset signal are used as the input of an AND gate in the execution module, the output of the AND gate is used as the input of a quenching circuit, and the input and the output of the two-way selector and the demultiplexer are controlled to be directly connected in series to form a transmission path I, or the input and the output of the two-way selector and the demultiplexer are controlled to be connected in series with the input and the output of the TDC to form a transmission path II; when the execution module detects that the pixel is marked in the window, the SPAD, the quenching circuit and the TDC in the pixel work normally, and the transmission path II is used for transmitting input and output data between adjacent pixel units; when the pixel is detected to be marked outside the window, the function of the quenching circuit for detecting the avalanche current is disabled, and a transmission path I is adopted to replace a transmission path II;

the transmission module belongs to a peripheral circuit in the ROIC, and consists of a module 64 counter, a demultiplexer, a time adjustment module, an OR tree, RC allocation logic and row invalidation judgment; the configuration data and the configuration clock are used as inputs of a module 64 counter and an OR tree, the module 64 counter controls the demultiplexer to select time adjustment modules at different positions, the outputs of the time adjustment modules and the OR tree are connected to the input of RC allocation logic, and the output of the OR tree simultaneously controls the line invalidation judgment to be used for processing special configuration data; the transmission module adopts a parallel transmission reading mode to divide the ROIC into a left auxiliary ROIC and a right auxiliary ROIC, and each auxiliary ROIC is subdivided into a plurality of sub ROICs; the transmission module respectively controls the transmission time sequences of two auxiliary ROICs, wherein the sub ROICs under the auxiliary ROICs adopt the same transmission time sequence; the transmission module determines the length, width and position of the maximum window in each auxiliary ROIC by extracting the effective information of the horizontal axis and the vertical axis, further controls the pixel data transmission time and the transmission times required by each row in the auxiliary ROIC, and sequentially distributes the pixel data transmission time and the transmission times to the effective rows in the sub-ROIC, thereby realizing the change of window information of the self-adaptive user programming of the transmission time.

Further, when the transmission module extracts the horizontal axis effective information, the transmission module drives the OR tree count in the transmission module to generate a sampling clock through configuring the clock: the number of sampling clocks corresponds to the maximum line number N in the sub-ROIC, the period of the sampling clocks is N times of that of the configuration clocks, and the sampling starting points of different sampling clocks are sequentially separated by one period of the configuration clocks; sampling configuration data by using N sampling clocks, respectively driving N D triggers, and when the D triggers are triggered, representing that the corresponding sub-ROIC rows are valid; the maximum width of the window, i.e. the number of valid horizontal axes in the sub ROIC, is thus determined.

Further, the RC allocation logic in the transmission module will arrange the transmission clock paths corresponding to the effective rows of the sub ROICs according to the effective number of the horizontal axes in the sub ROICs, and generate the RC configuration number as the programming value of the RC counter in the time adjustment module in the transmission module, so as to realize the number of transmission times required by the sub ROICs.

Further, when the transmission module extracts the vertical axis valid information, the programmable row pixel counter in the time adjustment module in the transmission module is time-division multiplexed: the configuration stage is based on a configuration clock and configuration data which are input by user programming, the configuration clock is used as a driving clock of the programmable row pixel counter through an AND gate, and the final counting result is used as a programming value of the programmable row pixel counter; in the transmission stage, the maximum count value of the pixel counter of the programmable row is a programming value, and each time the pixel counter is full represents the transmission time required by the pixels in the window of the generated row; the maximum length of the window, i.e. the number of active longitudinal axes, is thus determined.

The free window selection method applied to the array reading circuit has the following advantages:

1. the free window selection method applied to the array reading circuit is realized by the mutual matching of the configuration module, the execution module and the transmission module, and the time resolution of the TDC array is not affected, wherein the configuration module and the execution module can provide various spatial resolutions, and meanwhile, the transmission module can realize the self-adaptive adjustment of the transmission time according to different spatial resolutions. Thus, the small window will have a higher frame rate, faster imaging speed.

2. The application provides a free window selection method applied to an array reading circuit, which is realized by a circuit, and because a configuration module and a transmission module belong to the peripheral circuit of an ROIC, an execution module is only composed of two AND gates, one two-in-one selector and a multi-way selector, and occupies a small part of pixel area, thus the application has good portability.

3. The free window selection method applied to the array reading circuit provided by the application has lower area consumption and more excellent power consumption utilization rate compared with the traditional method through a strategy based on sampling configuration data and configuration clocks when effective information of a horizontal axis and a vertical axis is extracted.

4. Compared with the method of decoding windowing, the method of the application allows the user to program a plurality of windows simultaneously, has higher degree of freedom in window number, separates the configuration stage and the transmission stage in the arrangement of circuit time sequence, and the transmission stage is not limited by decoding reading.

5. Compared with the windowing method of photon counting, the free window selection method applied to the array reading circuit provided by the application has the advantages that the configuration module and the execution module not only improve the freedom degree of window selection, but also realize the window information of self-adaptive user programming of transmission time in the aspect of data transmission, and can intelligently regulate and control the imaging speed.

6. The free window selection method applied to the array reading circuit provided by the application has better flexibility. For example, the technology can only designate the pixels of interlaced columns to work or the pixels of specific positions to work through the cooperation of a configuration module and an execution module by user programming, and other pixels are disabled, so that the subsampling function is supported, and the crosstalk between adjacent pixels is restrained; the thermal pixel detection is supported, and the function of disabling the pixels is realized; meanwhile, the method can also be used for spot positioning and processing data aiming at the region of interest; in addition, the method can provide high-spatial-resolution 2D image data and high-time-resolution low-spatial-resolution 3D graphic data in the ROIC which integrates photon counting and photon timing functions, and provides technical support for the realization of 2D-3D fusion of subsequent algorithms.

7. The window selection method provided by the application is applied to an array readout circuit taking a time-to-digital converter as a main body, and is different from the prior art, the window selection method provided by the application supports the simultaneous configuration of a plurality of windows with different scales, and the minimum window size is allowed to be configured as 1 multiplied by 1; the data is read by adopting a parallel reading mode of sub-reading circuits, the size and the number of the self-adaptive window of the reading time length are changed, and the frame frequency is allowed to be intelligently adjusted.

Drawings

FIG. 1 is a schematic diagram of a free window selection method applied to an array readout circuit according to the present application;

FIG. 2 is a schematic diagram of a configuration timing and configuration module;

FIG. 3 is a schematic diagram of an implementation of a pixel unit, including an execution module;

fig. 4 is a schematic diagram of a transmission policy performed by the transmission module;

FIG. 5 is a schematic diagram of a transmission module;

FIG. 6 is a schematic diagram of an OR tree in a transport module;

FIG. 7 is a schematic diagram of a time adjustment module in a transmission module;

fig. 8 is a schematic diagram of RC allocation logic in a transmission module.

Detailed Description

In order to better understand the purpose, structure and function of the present application, a method for selecting a free window applied to an array readout circuit according to the present application will be described in further detail below with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of a free window selection method applied to an array readout circuit according to the present application. The configuration module is attached to the periphery of the ROIC of the read-out circuit, and the configuration data, the clock, the zone bit and the reset signal can be programmed by a user and are input from the upper left corner of the ROIC, so that the selection of the spatial resolution is diversified; the execution module is embedded in the pixel unit; the transmission module controls the auxiliary ROICs of the left and right parts to be output from the two ends of the ROIC, each 4 rows of pixels in the auxiliary ROIC form a sub-ROIC, and share an output port.

FIG. 2 is a schematic diagram of a configuration timing and configuration module. The present application is different from the conventional ROIC in that the configuration phase is placed before the quantization phase, and the configuration frame is formed by the configuration phase and the ordinary frame. The window selection method requires that the first frame of the array must be a configuration frame, otherwise the full array is disabled by default; the default is the ordinary frame in the second frame of the array and a plurality of frames after the second frame, and the ordinary frame works according to the configuration result of the last configuration frame. In the configuration phase, a Reset signal Reset needs to be input first to perform a Reset operation on the ROIC, and during the low level period of the FLAG bit FLAG, the configuration clock clk_data samples the Column Data row_data and the Row Data column_data by rising edges, and during this period, the change of the Column Data is kept to occur at the low level of the configuration clock. Since the configuration module regards the bottom right corner of the ROIC as the origin of the coordinate system, the first data of the configuration clock samples is ultimately embodied at the bottom right corner of the ROIC. The implementation of the horizontal axis and the vertical axis of the coordinate system is formed by connecting the configuration modules in series through a unit consisting of a D trigger and a selector. When the FLAG signal is in a low level, the output Contro_i signal of the alternative selector is grounded, so that the influence on the ROIC in the configuration process is avoided, until the FLAG signal is in a high level after the configuration is completed, and the Contro_i signal is assigned by a corresponding D trigger.

Fig. 3 is a schematic diagram of a pixel unit in the ROIC. The pixel unit originally comprises a single photon avalanche device SPAD, a quenching circuit AQC and an event-driven quantized TDC, and the rest two AND gates, one alternative selector and a demultiplexer form an execution module together. The execution module takes Row-Column signals Contro_Row and Contro_Column as control signals, when a pixel is regarded as a pixel outside a window, an event-driven quantized TDC is short-circuited, a previous pixel output is directly connected to a current pixel output to form a new data transmission path, and in addition, a reset signal of a quenching circuit AQC is also shielded, so that the potential of a cathode and an anode of the SPAD is kept close, and an avalanche current signal cannot be generated; when the pixel is regarded as a pixel in a window, the pixel keeps a normal working state, namely, the SPAD and the ROIC are interconnected through an indium column, a reset signal enters an AQC, the SPAD is biased in a reverse bias state, once a photon signal is detected, an avalanche current is generated, the AQC is triggered to quench the SPAD and generate a pulse signal STOP, the pulse signal STOP is transmitted to the TDC as a quantization starting point of the TDC, the TDC STOPs working until the quantization stage is finished, the TDC also STOPs working until the transmission stage arrives, and the TDC at the moment is used as a data transmission path to sequentially output current pixel data and previous pixel data.

Fig. 4 shows a schematic diagram of a transmission strategy performed by the transmission module. Every 4×8 pixels constitute one sub ROIC,1 to 3 sub ROICs are output from the left side, and 4 to 6 sub ROICs are output from the right side, and 4 windows are configured by user programming in the schematic diagram, with scales of 3×3, 3×4, 2×3, and 2×4, respectively. Theoretically, sub ROIC3 needs to perform 3-pixel 3-time transmission, sub ROIC6 needs to perform 4-pixel 3-time transmission, sub ROIC2 needs to perform 3-pixel 2-time transmission, and sub ROIC5 needs to perform 4-pixel 2-time transmission; also, since the duration of the ROIC transmission phase depends on the longest transmission duration among the sub ROICs, the left sub ROIC is required to perform 3 transmissions of 3 pixels in total and the right sub ROIC is required to perform 3 transmissions of 4 pixels in total. Therefore, in the transmission strategy executed by the transmission module, the ROIC is divided into a left part and a right part, and then is subdivided into a plurality of sub ROICs, and the windows of the sub ROICs are combined in each part to be used as M pixels to be executed by all the sub ROICs in the current part for N times of transmission.

Fig. 5 is a schematic diagram of a transmission module. Taking a ROIC with a size of 128×128 as an example, the modulo-64 counter counts the falling edge of the configuration clock, that is, the first 64 columns of valid information are sent to the right time adjustment module, and the last 64 columns of valid information are sent to the left time adjustment module; the OR tree processes the configuration clock and the row configuration data into subarray row effective information, and RC configuration numbers are generated by RC distribution logic to program the transmission times of the time adjustment module; after receiving the RC configuration number and the column effective information, the time adjustment module respectively generates BIT, WORD, FRAM signals of the left array and the right array and outputs 4 signals to RC distribution logic; the RC distribution logic distributes and transmits RC distribution clocks of the left part and the right part according to the input condition; the row disable determination is used to prevent the full array from being disabled in the event that there is a column active and a row inactive, but the number of RC configurations generated is such that the time adjustment module continues to operate, thus requiring masking of the input clock in that case.

Fig. 6 is a schematic diagram of an OR tree in a transmission module. To obtain the union of the window widths in all sub-ROICs, the conventional approach is to output the a-D rows in all sub-ROICs through an OR array, respectively, but doing so consumes a large number of OR cells and power consumption. Therefore, the OR tree drives a narrow pulse generator to generate A-D sampling clocks through the configuration clock, and the frequency of the sampling clocks is 4 times of that of the configuration clock; the sampling clock and configuration data phase drive the D flip-flop once the output of the D flip-flop goes high, representing that there are at least 1 sub-ROICs for all sub-ROICs that are active in the row.

Fig. 7 is a schematic diagram of a time adjustment module in the transmission module. The sense clock LCK passes through four parts, thereby generating a synchronous BIT, WORD, FRAM signal and an RC clock. The clock gating part is used for ensuring that the time adjusting module only works in the transmission stage; a gated clock-driven word generation counter for generating the transfer time T required for a single pixel; then, the row pixel counter is driven by a word, and the column effective information L is programmed as the upper limit of the row pixel counter, so that when the count reaches the maximum value, the generated transmission time is L multiplied by T; then, a column-driving RC counter is generated, which also takes the programmed number Q of RCs as an upper count limit, selects an output channel corresponding to the RC count value, and generates a synchronous BIT, WORD, FRAM signal and an RC clock.

Fig. 8 is a schematic diagram of RC allocation logic in a transmission module. The effective information of subarrays generates RC number Q through RC configuration number, and generates S1-S10 through switch control, wherein RC 1-4 are RC clocks. The RC clock is distributed to ARC-DRC channels by the switch control and then transmitted to the subarray, namely the corresponding row of the subarray.

Compared with the traditional scheme, the free window selection method applied to the array reading circuit has the advantages that: (1) The method is mainly aimed at improving the peripheral circuit of the ROIC, and has low power consumption and strong portability. (2) The selection of the spatial resolution supports the coexistence of multiple choices, so the freedom of the number of windows is higher. (3) The time length of the transmission stage is adaptive to the change of window information, and the intelligent adjustment of the imaging speed can be realized.

It will be understood that the application has been described in terms of several embodiments, and that various changes and equivalents may be made to these features and embodiments by those skilled in the art without departing from the spirit and scope of the application. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the application without departing from the essential scope thereof. Therefore, it is intended that the application not be limited to the particular embodiment disclosed, but that the application will include all embodiments falling within the scope of the appended claims.

Claims

1. The free window selection method applied to the array reading circuit is characterized in that the circuit comprises a transmission module, a configuration module and an execution module; wherein:

2. The method according to claim 1, wherein the transmission module, when extracting the horizontal axis valid information, drives the OR tree count in the transmission module to generate the sampling clock by configuring the clock: the number of sampling clocks corresponds to the maximum line number N in the sub-ROIC, the period of the sampling clocks is N times of that of the configuration clocks, and the sampling starting points of different sampling clocks are sequentially separated by one period of the configuration clocks; sampling configuration data by using N sampling clocks, respectively driving N D triggers, and when the D triggers are triggered, representing that the corresponding sub-ROIC rows are valid; the maximum width of the window, i.e. the number of valid horizontal axes in the sub ROIC, is thus determined.

3. The method according to claim 2, wherein the RC allocation logic in the transmission module is configured to arrange the transmission clock paths corresponding to the effective rows of the sub-ROICs according to the effective number of the horizontal axes in the sub-ROICs, and generate the RC configuration number as the programming value of the RC counter in the time adjustment module in the transmission module, so as to realize the number of transmissions required by the sub-ROICs.

4. A free window selection method applied to an array readout circuit according to claim 3, wherein the transmission module extracts the vertical axis valid information, and the programmable row pixel counter in the time adjustment module in the transmission module is time-division multiplexed: the configuration stage is based on a configuration clock and configuration data which are input by user programming, the configuration clock is used as a driving clock of the programmable row pixel counter through an AND gate, and the final counting result is used as a programming value of the programmable row pixel counter; in the transmission stage, the maximum count value of the pixel counter of the programmable row is a programming value, and each time the pixel counter is full represents the transmission time required by the pixels in the window of the generated row; the maximum length of the window, i.e. the number of active longitudinal axes, is thus determined.