CN115696077A - Imaging device and imaging control method - Google Patents

Abstract

The embodiment of the application discloses an imaging device and an imaging control method, and belongs to the technical field of photoelectric detection. In the embodiment of the application, a switch array and a multiplexer in an imaging unit may sequentially output one path of first image data corresponding to each macro pixel in a plurality of macro pixels, and a processing unit receives the first image data corresponding to each macro pixel and generates a fused image according to the first image data corresponding to each macro pixel and a position of the corresponding macro pixel. Because the overlapped SPAD sub-pixels are arranged between every two adjacent macro-pixels in the plurality of macro-pixels included in the SPAD array in the imaging unit, the quantity of image data corresponding to the macro-pixels output by the imaging unit is increased through the switch array and the multiplexer, and therefore the plane resolution of an output image is improved under the condition that the quantity of the SPAD sub-pixels and subsequent storage are not increased.

Description

Imaging device and imaging control method

technical field

The present application relates to the field of photoelectric detection technology, in particular to an imaging device and an imaging control method.

Background technique

3D imaging technology based on SPAD (Single Photon Avalanche Diode) array is a research hotspot in recent years, and has great application prospects in consumer electronics, security, robotics, autonomous driving and other fields.

In the related art, in order to save the circuit area, the n SPAD sub-pixels spatially adjacent to each other in the SPAD array are divided into one macro-pixel, and the n SPAD sub-pixels in each macro-pixel share the same set of processing circuits, thus, Each macropixel will correspond to one pixel data. Correspondingly, the resolution of the final output image will also be reduced to 1/n of the resolution before the macro pixels are not divided. For example, referring to FIG. 1 , spatially adjacent 2*2 SPAD sub-pixels are divided into a macro-pixel, and a pixel data is output. In this case, when 320*240 SPAD sub-pixels are included in the SPAD array, The resolution of the output image will be 160*120. It can be seen that the imaging method in the related art causes a large loss in the planar resolution of the output image of the SPAD array.

Contents of the invention

The embodiment of the present application provides an imaging device and an imaging control method, which can improve the planar resolution on the basis that the number of sub-pixels of the SPAD array and subsequent circuits remain unchanged. Described technical scheme is as follows:

In one aspect, an imaging device is provided, the imaging device includes: an imaging unit and a processing unit, the imaging unit includes a single photon avalanche diode SPAD array, a switch array and a multiplexer, and the SPAD array includes a plurality of macro A pixel, each macro pixel in the plurality of macro pixels includes (N×M) SPAD sub-pixels, and there are overlapping SPAD sub-pixels between every two adjacent macro pixels;

The switch array is used to receive the sub-pixel data respectively output by the (N×M) SPAD sub-pixels included in each macro-pixel in the plurality of macro-pixels, and the (N×M) SPADs included in each macro-pixel Synthesizing the sub-pixel data respectively output by the sub-pixels to obtain one channel of first image data corresponding to the corresponding macro-pixel, and outputting one channel of first image data corresponding to each macro-pixel;

The multiplexer is used to receive multiple channels of first image data output by the switch array, and sequentially output the multiple channels of first image data to the processing unit;

The processing unit is configured to receive the first image data corresponding to each macro pixel sequentially output by the multiplexer, and generate a fused image according to the position of each macro pixel and the corresponding first image data and the corresponding macro pixel.

Optionally, the switch array includes a first-level logic OR gate and a second-level logic OR gate, a row of SPAD sub-pixels in the first macro pixel is connected to a first-level logic OR gate, and multiple rows of SPAD sub-pixels in the first macro pixel A plurality of first-level logic OR gates connected to sub-pixels is connected to a second-level logic OR gate, and the first macro pixel is any one of the plurality of macro pixels;

Each first-stage logical OR gate connected to the first macro-pixel is used to receive the sub-pixel data output by each SPAD sub-pixel in a row of SPAD sub-pixels connected to itself, and synthesize the received sub-pixel data into one row Pixel data, outputting the row of pixel data;

The second-level logical OR gate connected to the first macro pixel is used to receive row pixel data respectively outputted by multiple first-level logical OR gates connected to itself, and synthesize the received row pixel data to obtain the first the first image data corresponding to the macro pixels, and output the first image data corresponding to the first macro pixels.

Optionally, the switch array includes a first-level logical OR gate and a second-level logical OR gate, a column of SPAD sub-pixels in the first macro pixel is connected to a first-level logical OR gate, and multiple columns of SPAD sub-pixels in the first macro pixel A plurality of first-level logic OR gates connected to sub-pixels is connected to a second-level logic OR gate, and the first macro pixel is any one of the plurality of macro pixels;

Each first-stage logical OR gate connected to the first macro-pixel is used to receive one path of sub-pixel data output by each SPAD sub-pixel in a connected column of SPAD sub-pixels, and synthesize the received sub-pixel data into one path of column Pixel data, outputting the column of pixel data;

The second-level logical OR gate connected to the first macro pixel is used to receive the column pixel data respectively output by the connected multiple first-level logical OR gates, and synthesize the received column pixel data to obtain the first macro pixel the first image data corresponding to the pixel, and output the first image data corresponding to the first macro pixel.

Optionally, the multiplexer includes a plurality of input terminals, an output terminal and a control terminal, the multiple input terminals of the multiplexer are connected to the switch array, and the control of the multiplexer The terminal is connected to the control terminal of the processing unit, and the output terminal of the multiplexer is connected to the input terminal of the processing unit;

Each input terminal of the multiplexer is used to receive one channel of first image data output by the switch array;

The control terminal of the multiplexer is used to receive the strobe signal output by the control terminal of the processing unit at each measurement moment;

The output terminal of the multiplexer is used for outputting one path of first image data corresponding to the strobe signal received at the corresponding measurement moment at each measurement moment.

Optionally, the processing unit is configured to determine the position of the macropixel corresponding to the first image data corresponding to the received corresponding strobe signal according to the strobe signal output at each measurement moment, and correspond the corresponding strobe signal to The first image data is used as the determined pixel data at the position of the macro pixel to generate the fused image.

Optionally, every two adjacent macro pixels in the multiple macro pixels have (N-1) rows of overlapping SPAD sub-pixels, or, every two adjacent macro pixels in the multiple macro pixels have (M-1) columns of overlapping SPAD sub-pixels.

In another aspect, an imaging control method is provided, the method is applied to a processing unit of an imaging device, the imaging device further includes an imaging unit, and the imaging unit includes a single photon avalanche diode SPAD array, A switch array and a multiplexer, the SPAD array includes a plurality of macro pixels, each macro pixel in the plurality of macro pixels includes (N×M) SPAD sub-pixels, and every two adjacent macro pixels There are overlapping SPAD sub-pixels between them, wherein the switch array is used to receive sub-pixel data respectively output by (N×M) SPAD sub-pixels included in each macro-pixel in the plurality of macro-pixels, for each Combining the sub-pixel data respectively output by the (N×M) SPAD sub-pixels included in the macro-pixel to obtain one path of first image data corresponding to the corresponding macro-pixel, and outputting one path of first image data corresponding to each macro-pixel to the multiple a way selector; the method comprising:

The processing unit sequentially outputs different types of strobe signals to the multiplexer according to a preset timing, so that the multiplexer outputs each time a strobe signal output by the processing unit is received. first image data corresponding to the corresponding strobe signal;

The processing unit receives the first image data corresponding to each macro pixel sequentially output by the multiplexer, and generates a fused image according to the first image data corresponding to each macro pixel and the position of the corresponding macro pixel.

Optionally, the switch array includes a first-level logical OR gate and a second-level logical OR gate, a row of SPAD sub-pixels in the first macro pixel is connected to a first-level logical OR gate, and multiple A plurality of first-level logical OR gates connected to row SPAD sub-pixels are connected to a second-level logical OR gate, and the first macro pixel is any one of the plurality of macro pixels;

Each first-stage logical OR gate connected to the first macro-pixel is used to receive the sub-pixel data output by each SPAD sub-pixel in a row of SPAD sub-pixels connected to itself, and synthesize the received sub-pixel data into one row Pixel data, outputting the row of pixel data;

The second-level logical OR gate connected to the first macro pixel is used to receive row pixel data respectively outputted by multiple first-level logical OR gates connected to itself, and synthesize the received row pixel data to obtain the first the first image data corresponding to the macro pixels, and output the first image data corresponding to the first macro pixels.

Optionally, the switch array includes a first-level logical OR gate and a second-level logical OR gate, a column of SPAD sub-pixels in the first macro pixel is connected to a first-level logical OR gate, and multiple columns of SPAD sub-pixels in the first macro pixel A plurality of first-level logic OR gates connected to sub-pixels is connected to a second-level logic OR gate, and the first macro pixel is any one of the plurality of macro pixels;

Each first-stage logical OR gate connected to the first macro-pixel is used to receive one path of sub-pixel data output by each SPAD sub-pixel in a connected column of SPAD sub-pixels, and synthesize the received sub-pixel data into one path of column Pixel data, outputting the column of pixel data;

The second-level logical OR gate connected to the first macro pixel is used to receive the column pixel data respectively output by the connected multiple first-level logical OR gates, and synthesize the received column pixel data to obtain the first macro pixel the first image data corresponding to the pixel, and output the first image data corresponding to the first macro pixel.

Optionally, the multiplexer includes a plurality of input terminals, an output terminal and a control terminal, the multiple input terminals of the multiplexer are connected to the switch array, and the control of the multiplexer The terminal is connected to the control terminal of the processing unit, the output terminal of the multiplexer is connected to the input terminal of the processing unit, and each input terminal of the multiplexer is used to receive the output of the switch array. One channel of first image data;

The processing unit sequentially outputs different types of strobe signals to the multiplexer according to a preset timing sequence, including:

The control terminal of the processing unit outputs a first gating signal to the control terminal of the multiplexer at the first measurement moment, so that the output terminal of the multiplexer outputs the same signal at the first measurement moment. One path of first image data corresponding to the first gating signal, and the first measurement moment is any one of the plurality of measurement moments.

Optionally, the processing unit generates a fused image according to the first image data corresponding to each macropixel and the position of the corresponding macropixel, including:

According to the gate signal output at each measurement moment, determine the position of the macro pixel corresponding to the first image data corresponding to the received corresponding gate signal;

The first image data corresponding to the corresponding gate signal is used as the pixel data at the position of the macro pixel determined at the corresponding measurement moment, so as to generate the fused image.

Optionally, every two adjacent macro pixels in the multiple macro pixels have (N-1) rows of overlapping SPAD sub-pixels, or, every two adjacent macro pixels in the multiple macro pixels have (M-1) columns of overlapping SPAD sub-pixels.

In another aspect, an imaging device is provided, the device comprising:

processor;

memory for storing processor-executable instructions;

Wherein, the processor executes the executable instructions in the memory to implement the above imaging control method.

In another aspect, there is provided a computer program product containing instructions, which, when run on a computer, causes the computer to execute the steps of the above-mentioned imaging control method.

The beneficial effects brought by the technical solutions provided by the embodiments of the present application at least include:

In the embodiment of the present application, through the switch array and the multiplexer in the imaging unit, one channel of first image data corresponding to each macro pixel in the plurality of macro pixels can be sequentially output, and the processing unit receives the first image data corresponding to each macro pixel. image data, and generate a fused image according to the first image data corresponding to each macro pixel and the position of the corresponding macro pixel. Since there are overlapping SPAD sub-pixels between every two adjacent macro-pixels in the multiple macro-pixels included in the SPAD array in the imaging unit, the image corresponding to the macro-pixels output by the imaging unit is made through the switch array and the multiplexer The amount of data increases, so that the planar resolution of the output image is improved without increasing the number of SPAD sub-pixels and subsequent storage.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort.

Fig. 1 is a structural diagram of a SPAD array;

FIG. 2 is a system architecture diagram related to an imaging device provided by an embodiment of the present application;

FIG. 3 is a schematic structural diagram of an imaging device provided in an embodiment of the present application;

FIG. 4 is a schematic diagram of a macro pixel in a SPAD array provided by an embodiment of the present application;

FIG. 5 is a schematic diagram of a connection relationship between a macro pixel and a switch array provided by an embodiment of the present application;

FIG. 6 is a schematic diagram of another connection relationship between a macro pixel and a switch array provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of another imaging device provided by an embodiment of the present application;

FIG. 8 is a schematic diagram of a fused image generated by an imaging device provided in an embodiment of the present application;

FIG. 9 is a flowchart of an imaging control method provided by an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the implementation manners of the present application will be further described in detail below in conjunction with the accompanying drawings.

Before explaining the embodiment of the present application in detail, the system architecture involved in the embodiment of the present application is firstly introduced.

FIG. 2 is a system architecture diagram related to an imaging device provided by an embodiment of the present application. As shown in FIG. 2 , the system includes an imaging device 10 , a router 20 and a server 30 . The imaging device 10 is connected to the router 20 , and the router 20 is connected to the server 30 . Wherein, the imaging device 10 is used to generate an image, and output the generated image to the router 20; the router 20 is used to transmit the image generated by the imaging device 10 to the server 30; the server 30 is used to receive the image transmitted by the router 20, and receive images are stored.

Wherein, the imaging device 10 includes a processing unit 101 and an imaging unit 102 . The imaging unit 102 includes a SPAD array. Wherein, the SPAD array includes a plurality of macro pixels, each macro pixel includes a plurality of SPAD sub-pixels, and there are overlapping SPAD sub-pixels between every two adjacent macro pixels. The imaging unit 102 is used to output the first image data corresponding to each macro pixel, and the processing unit 101 is used to receive the first image data corresponding to each macro pixel output by the imaging unit 102, and according to the first image data corresponding to each macro pixel The image data and the locations of the corresponding macropixels are used to generate a fused image. It should be noted that, for the detailed implementation of the imaging unit 102 , reference may be made to the introduction below, which will not be repeated here.

In addition, the imaging device 10 may further include a laser driver 103 , a laser 104 , a transmitting lens 105 and a receiving lens 106 .

The laser driver 103 can be connected to the imaging unit 102 and the laser 104 respectively. The imaging unit 102 may send an emission start instruction to the laser driver 103, and start timing while sending the emission start instruction. The laser driver 103 drives the laser 104 to emit laser light after receiving the emission start instruction.

The emitting lens 105 is used for emitting the laser light emitted by the laser 104 to irradiate the target object. The emitting lens 105 can be fixed on the laser 104 or installed in the laser 104 .

The receiving lens 106 is used to receive the light reflected by the target object, and then transmit the received reflected light to each SPAD sub-pixel of the SPAD array in the imaging unit 102, so that each SPAD sub-pixel of the SPAD array in the imaging unit 102 can detect The received reflected light signal outputs sub-pixel data, so that the imaging unit 102 outputs the first image data corresponding to each macro-pixel according to each sub-pixel data. The receiving lens 106 can be fixed on the SPAD array in the imaging unit 102 , or installed inside the SPAD array 102 .

Optionally, in some possible implementations, after the imaging device 10 obtains the fused image, it can also perform intelligent analysis based on the fused image, and then send the fused image and the intelligent analysis result to the server 30 through the router 20 , so that the server 30 stores the fused image and the intelligent analysis result for subsequent use by other businesses.

Next, the imaging device provided by the embodiment of the present application will be introduced.

FIG. 3 is a schematic diagram of an imaging device provided by an embodiment of the present application. As shown in Figure 3, the device includes: an imaging unit 301 and a processing unit 302, the imaging unit 301 includes a SPAD array 3011, a switch array 3012 and a multiplexer 3013, the SPAD array 3011 includes a plurality of macro pixels, a plurality of macro pixels Each macro pixel in the pixel includes (N×M) SPAD sub-pixels, and there are overlapping SPAD sub-pixels between every two adjacent macro pixels. Among them, the switch array 3012 is used to receive the sub-pixel data respectively outputted by (N×M) SPAD sub-pixels included in each macro-pixel in multiple macro-pixels, and the (N×M) SPAD sub-pixels included in each macro-pixel The sub-pixel data respectively output by the pixels are synthesized to obtain one channel of first image data corresponding to the corresponding macro pixel, and output one channel of first image data corresponding to each macro pixel; the multiplexer 3013 is used to receive the multiple channels output by the switch array 3012 The first image data, and multiple channels of first image data are sequentially output to the processing unit 302; the processing unit 302 is used to receive the first image data corresponding to each macro pixel output by the SPAD array, and according to the corresponding first image data of each macro pixel An image data and the location of the corresponding macro-pixels are used to generate a fused image.

In the embodiment of the present application, the SPAD array 3011 includes a plurality of SPAD sub-pixels arranged in a rectangular array, and (N×M) SPAD sub-pixels in the SPAD array 3011 can be formed into a macro pixel. Then the SPAD array 3011 includes a plurality of macro pixels composed of (N×M) SPAD sub-pixels. Wherein, N is the number of rows of macro pixels, and M is the number of columns of macro pixels, and N and M may or may not be equal, which is not limited in this embodiment of the present application.

It should be noted that, in the embodiment of the present application, among the plurality of macro-pixels in the SPAD array 3011 , there are overlapping SPAD sub-pixels between every two adjacent macro-pixels.

Exemplarily, when each macro pixel includes (N×M) SPAD sub-pixels, two adjacent macro pixels up and down may have multiple rows of overlapping SPAD sub-pixels, and two macro pixels adjacent to left and right may have multiple columns Overlapping SPAD subpixels. For example, two vertically adjacent macro pixels may have (N-1) rows of overlapping SPAD sub-pixels, or may have (N-2) rows of overlapping SPAD sub-pixels, which is not limited in this embodiment of the present application. Two adjacent left and right macro pixels have (M-1) columns of overlapping SPAD sub-pixels, and may also have (M-2) columns of overlapping SPAD sub-pixels, which is not limited in this embodiment of the present application.

For example, referring to FIG. 4 , a 4×4 SPAD array with 16 SPAD sub-pixels in total, taking N=M=3 as an example, a macro pixel includes 3×3 SPAD sub-pixels. Among them, 2 rows overlap between the upper and lower adjacent macro pixels 1 and 2, the SPAD sub-pixels overlapping in the first row include SPAD5-SPAD7, and the overlapping SPAD sub-pixels in the second row include SPAD9-SPAD11; the left and right adjacent macro pixels 2 and macro pixel 3 are overlapped by 2 columns, the overlapping SPAD sub-pixels in the first column include SPAD6, SPAD10, SPAD14, and the overlapping SPAD sub-pixels in the second column include SPAD7, SPAD11, SPAD15.

In the embodiment of the present application, the switch array 3012 includes a first-level logic OR gate and a second-level logic OR gate. In a possible implementation manner, taking any macro pixel in the plurality of macro pixels in the SPAD array 3011 as an example, it is called the first macro pixel, and each row of SPAD sub-pixels in the first macro pixel is respectively connected to a A first-level logic OR gate, a plurality of first-level logic OR gates corresponding to multiple rows of SPAD sub-pixels in each macro pixel is connected to a second-level logic OR gate.

Wherein, each first-level logical OR gate connected to the first macro-pixel is used to receive one path of sub-pixel data output by each SPAD sub-pixel in the connected row of SPAD sub-pixels, and then the first-level logical OR gate will receive the The sub-pixel data is synthesized to obtain a row of pixel data, and the row of pixel data is output. For example, for a macro pixel composed of (N×M) SPAD sub-pixels, the macro pixel is connected with N first-level logical OR gates, and each first-level logical OR gate will output a row of pixel data, so that N The first logical OR gate will output N rows of pixel data.

The second-level logical OR gate connected to the first macro-pixel is used to receive row pixel data respectively outputted by multiple first-level logical OR gates connected to itself, and then, the second-level logical OR gate performs multi-channel row pixel data received by the second-level logical OR gate. Synthesize to obtain a channel of first image data, and output the first image data.

It should be noted that, in a possible situation, when the first macro-pixel includes 4 SPAD sub-pixels, a first-level logical OR gate may be a two-input OR gate. Correspondingly, a second-level logical OR gate can also be a two-input OR gate.

For example, referring to FIG. 5 , assuming that the SPAD array includes 3×3 SPAD sub-pixels, SPAD1, SPAD2, SPAD4, and SPAD5 form a macro pixel 1, and the SPAD1 and SPAD2 of the first row in the macro pixel 1 are connected to a first-level logical OR gate, the first-level logical OR gate is a two-input OR gate. In this case, the first-level logical OR gate receives the sub-pixel data respectively output by SPAD1 and SPAD2, and synthesizes the two-way sub-pixel data into one line of pixel data 1+2; similarly, SPAD4 and SPAD2 in the second line SPAD5 is connected to a first-level logical OR gate, which receives the sub-pixel data output by SPAD4 and SPAD5 respectively, and synthesizes the two channels of sub-pixel data into one channel of row pixel data 4+5.

Further, the two first-level logical OR gates corresponding to the two rows of SPAD sub-pixels of the macro pixel 1 are connected to a second-level logical OR gate, and the second logical OR gate is also a two-input OR gate. In this way, the second logical OR gate The first-level logical OR gate receives the row pixel data 1+2 and the row pixel data 4+5 output by the two first-level logical OR gates, and synthesizes the row pixel data 1+2 and the row pixel data 4+5 into a first image data 1245, and output the first image data 1245.

In another possible situation, when the first macro pixel includes X SPAD sub-pixels, and X is greater than 4, each first-level logical OR gate connected to the first macro pixel may include one or more two-input The OR gate, the second logical OR gate connected to the first macro pixel may also include one or more two-input OR gates.

For example, when X is 9, R=4 is calculated according to R=ceiling(log ₂ X), where ceiling(*) refers to rounding up. In this case, the switch array will include 4 layers of two-input OR gates, wherein each first-level logical OR gate can be composed of two layers of two-input OR gates, and each second-level logical OR gate can also be composed of two layers of two-input OR gates. Layer 2 is composed of input OR gates.

For example, referring to FIG. 6 , assuming that the SPAD array includes 4×4 SPAD sub-pixels, SPAD1, SPAD2, SPAD3, SPAD5, SPAD6, SPAD7, SPAD9, SPAD10 and SPAD11 form a macro pixel 1, in this case, the macro pixel 1 Every two adjacent SPAD sub-pixels in the first row can be connected with a two-input OR gate, so that these two two-input OR gates are the first level of connection between the SPAD sub-pixels in the first row of the macro pixel 1 The first layer of two-input OR gates in logical OR gates. On this basis, the adjacent first-level input OR gate in the first-level logic OR gate is connected to a two-input OR gate, so that this two-input OR gate is the first-level logic connected to the SPAD sub-pixels in the first row The second layer of OR gates is an input OR gate. In this way, each of the first-level two-input OR gates in the first-level logical OR gates connected to the SPAD sub-pixels in each row of the macro pixel 1 receives the sub-pixel data output by the connected two SPAD sub-pixels, and combines the two-way sub-pixel data After output. Each second-layer two-input OR gate receives two channels of data output by the connected two first-layer input OR gates, and combines the received two channels of data to obtain one channel of row pixel data.

After the row pixel data corresponding to each row of SPAD sub-pixels in the macro pixel is obtained by the above method, for these three rows of pixel data, the two second-layer two-input OR gates that output the row pixel data of two adjacent rows can be A two-input OR gate is connected. At this time, the connected two-input OR gate is the first layer two-input OR gate in the second-level logic OR gate. After that, the two first-level two-input OR gates in the second-level logical OR gate are connected to a two-input OR gate. At this time, this two-input OR gate is the second-level two-input OR gate in the second-level logical OR gate. OR gate. In this way, each first-layer two-input OR gate in the second-level logical OR gate can combine the received row pixel data of two adjacent rows, and output one road of data, after that, the second layer two-input OR gate combines two The two channels of data input by the two-input OR gate of the first layer are combined to obtain the first image data.

The above is only an example of a macro pixel including 9 SPAD sub-pixels. When a macro pixel includes 8, 6 or more SPAD sub-pixels, the above method can be referred to for processing. repeat.

In addition, for each macro pixel among the multiple macro pixels, it can refer to the above-mentioned first macro pixel, and connect multiple first-level logical OR gates and one second-level logical OR gate. In this way, the switch array 3012 will include multiple first-level logic OR gates and multiple second-level logic OR gates.

Optionally, in another possible implementation, still taking the first macro pixel as an example, a column of SPAD sub-pixels in the first macro pixel is connected to a first-level logical OR gate, and multiple columns of SPAD sub-pixels in the first macro pixel Multiple first-level logical OR gates connected to the sub-pixels are connected to one second-level logical OR gate.

Wherein, each first-level logical OR gate connected to the first macro-pixel can be used to receive one path of sub-pixel data output by each SPAD sub-pixel in a column of SPAD sub-pixels connected to itself, and then the first-level logical OR gate will receive Synthesize the sub-pixel data to obtain a column of pixel data, and output the column of pixel data. For example, in a macro pixel composed of (N×M) SPAD sub-pixels, the macro pixel is connected with M first-level logical OR gates, and each first-level logical OR gate will output a column of pixel data, so that M The first level logic OR gate will output M columns of pixel data.

The second level logical OR gate connected to the first macro pixel is used to receive column pixel data respectively output by multiple first level logical OR gates connected to itself, and then the second level logical OR gate synthesizes the received column pixel data, Obtain one channel of first image data, and output the first image data.

It should be noted that when the number of SPAD sub-pixels included in the macro-pixel is 4, each of the first-level logic OR gate and the second-level logic OR gate can be realized by a two-input OR gate. Optionally, when the macro-pixel includes more SPAD sub-pixels, you can refer to the method introduced above, each first-level logical OR gate is realized by one or more two-input OR gates, each second-level The logical OR gate is also implemented by one or more two-input OR gates, which will not be repeated in this embodiment of the present application.

After each second-level logical OR gate in the switch array 3012 outputs one channel of first image data, the multiplexer 3013 receives one channel of first image data respectively output by multiple second-level logical OR gates, and converts the received The multiple channels of first image data are sequentially output to the processing unit 302 .

In the embodiment of the present application, the multiplexer 3013 includes a plurality of input terminals, an output terminal and a control terminal, the multiple input terminals of the multiplexer 3013 are connected to the switch array 3012, and the control terminal of the multiplexer 3013 It is connected with the control terminal of the processing unit 302 , and the output terminal of the multiplexer 3013 is connected with the input terminal of the processing unit 302 .

Wherein, each input terminal of the multiplexer 3013 is used to receive one path of first image data output by the switch array 3012; Strobe signal; the output terminal of the multiplexer 3013 is used to output a path of first image data corresponding to the strobe signal received at the corresponding measurement moment at each measurement moment.

It should be noted that the number of input terminals of the multiplexer 3013 is the same as the number of the second-stage logical OR gates included in the switch array 3012, so that each input terminal of the multiplexer 3013 is connected to a first-order logic gate in the switch array 3012. a second-level logical OR gate to receive the first image data output by the connected second-level logical OR gate.

Wherein, in a possible implementation manner, according to the position in the SPAD array 3011 of the macro pixel corresponding to the first image data output by each second-level logical OR gate in the switch array 3012, the multiplexer Each input terminal in 3013 is connected with each second-level logical OR gate in turn. For example, the second level logical OR gate for outputting the first image data corresponding to the macropixels in the first row and first column among the plurality of macropixels of the SPAD array 3011 can be combined with the first input in the multiplexer 3013 terminal connection, the second level logical OR gate for outputting the first image data corresponding to the macropixels in the first row and the second column among the plurality of macropixels of the SPAD array 3011 can be connected with the second one in the multiplexer 3013 input connections, and so on.

While receiving multiple channels of first image data, the control terminal of the multiplexer 3013 may also receive a gate signal output by the control terminal of the processing unit 302 according to a preset timing. Wherein, the processing unit 302 can pass the position of the plurality of macro pixels in the SPAD array 3011 and the input terminal for receiving the first image data corresponding to each macro pixel in the multiplexer 3013, through its own The control terminal sequentially outputs gating signals for gating different input terminals in the multiplexer. Correspondingly, the multiplexer 3013 can receive the gate signal output by the control terminal of the processing unit 302 at each measurement moment through its own control terminal, and output the first image data input by the corresponding input terminal according to the gate signal.

For example, the processing unit determines that the first image data corresponding to the macro pixel 1 in the first row and the first column in the SPAD array will be input to the input terminal 1 of the multiplexer, and the first image data corresponding to the macro pixel 2 in the first row and the second column The data will be input to the input terminal 2 of the multiplexer, the first image data corresponding to the macro pixel 3 in the second row and the first column will be input to the input terminal 3 of the multiplexer, and the macro pixel 4 in the second row and the second column corresponds to The first image data will be input to the input terminal 4 of the multiplexer, on this basis, at the first measurement moment, the control terminal of the processing unit outputs a strobe signal for gating the input terminal 1 of the multiplexer 0000. After receiving the strobe signal 0000, the control terminal of the multiplexer outputs the first image data of the macro-pixel 1 input from the input terminal 1 of the multiplexer to the processing unit. At the second measurement instant, the control terminal of the processing unit outputs a gate signal 0001 for gate input 2 of the multiplexer. After receiving the strobe signal 0001, the control terminal of the multiplexer outputs the first image data of the macro-pixel 2 input from the input terminal 2 of the multiplexer to the processing unit. At the third measurement moment, the control terminal of the processing unit outputs a gating signal 0010 for gating the input terminal 3 of the multiplexer. After receiving the gating signal 0010, the control terminal of the multiplexer switches the multiplexer The first image data of the macro pixel 3 input by the input terminal 3 of the selector is output to the processing unit. At the fourth measurement moment, the control terminal of the processing unit outputs a gating signal 0011 for gating the input terminal 4 of the multiplexer, and after receiving the gating signal 0011, the control terminal of the multiplexer switches the multiplexer The first image data of the macro pixel 4 input by the input terminal 4 of the selector is output to the processing unit.

After receiving the first image data corresponding to each gate signal, the processing unit 302 can determine the macro pixel corresponding to the first image data corresponding to the received corresponding gate signal according to the gate signal output at each measurement moment and using the first image data corresponding to the corresponding gate signal as the determined pixel data at the position of the macro pixel to generate a fused image.

It should be noted that there may be a certain period of time between the above two adjacent measurement moments, and within this period of time, the processing unit 302 may process the received first image data.

Exemplarily, after the processing unit 302 outputs a gating signal through its own control terminal at a certain measurement moment, it may receive the first image data output by the multiplexer 3013 according to the gating signal. It can be seen from the foregoing introduction that when the processing unit 302 sends the strobe signal, it sends the strobe signal according to the position of the macro pixel and the input terminal for outputting the image data of the corresponding macro pixel in the multiplexer 3013. Based on this, the processing unit 302 can According to the position of the macro pixel corresponding to the strobe signal output at the measurement moment, determine which macro pixel the received first image data corresponds to, and then use the first image data as the position of the macro pixel. pixel data. Afterwards, the processing unit 302 may continue to send the gate signal to the multiplexer 3013 through the control terminal after the next measurement time arrives, and process the first image data corresponding to the received corresponding gate signal. In this way, the processing unit 302 receives and processes the multiple channels of first image data sequentially output by the multiplexer to obtain pixel data at the position of each macro pixel, thereby generating a fused image.

In order to better understand the device of the embodiment of the present application, a 3×3 SPAD array is taken as an example to describe the imaging device provided by the embodiment of the present application in detail, wherein, referring to FIG. 7, the SPAD array includes 9 SPAD sub-pixels , SPAD1 to SPAD9, respectively. In addition, each macro pixel in the SPAD array includes 2×2 SPAD sub-pixels. Among them, SPAD1, SPAD2, SPAD4, SPAD5 form macro pixel 1, SPAD2, SPAD3, SPAD5, SPAD6 form macro pixel 2, SPAD4, SPAD5, SPAD7, SPAD8 form macro pixel 3, and SPAD5, SPAD6, SPAD8, SPAD9 form macro pixel 4. The overlapping SPAD sub-pixels in macro pixel 1 and macro pixel 2 are SPAD2 and SPAD5, the overlapping SPAD sub-pixels in macro pixel 3 and macro pixel 4 are SPAD5 and SPAD8, and the overlapping SPAD sub-pixels in macro pixel 1 and macro pixel 3 are SPAD4 and SPAD5 , the overlapping SPAD sub-pixels in macro pixel 2 and macro pixel 4 are SPAD5 and SPAD6.

A row of SPAD subpixels of each of the above four macropixels is connected to a first-level logical OR gate, so that two SPAD subpixels in a row of SPAD subpixels of each macropixel will output two channels of subpixel data to the connection For example, the SPAD1 and SPAD2 sub-pixels of the first row of the macro pixel 1 are connected to a first-level logical OR gate, so that SPAD1 outputs sub-pixel data 1 to the connected first-level logical OR gate, SPDA2 outputs the sub-pixel data 2 to the connected first-level logic OR gate, and after receiving the sub-pixel data 1 and 2, the first-level logic OR gate synthesizes the two-way sub-pixel data into one line of pixel data 1+2, and Output the row of pixel data 1+2. For each row of SPAD sub-pixels in other macro pixels, each row of SPAD sub-pixels is connected with a first-level logic OR gate, so that 6 rows of pixel data will be output through 6 first-level logic OR gates. In addition, multiple first-level logic OR gates connected to multiple rows of SPAD sub-pixels in each macro pixel will be connected to a second-level logic OR gate, for example, the two sub-pixels of SPAD1 and SPAD2 in the first row of macro pixel 1 are connected The first-level logic OR gate and the first-level logic OR gate connected to the two subpixels of SPAD4 and SPAD5 in the second row will be connected to a second-level logic OR gate, so that this second-level logic OR gate will receive row pixel data 1+ 2 and row pixel data 4+5, and then the second-level logical OR gate synthesizes row pixel data 1+2 and row pixel data 4+5 into first image data 1245. For the first-level logical OR gate connected to each row of SPAD sub-pixels of other macro pixels, a second-level logical OR gate can also be connected, so that each second-level logical OR gate can be connected to two rows of SPAD in a macro pixel The two first-level logic OR gates corresponding to the sub-pixels, and the two row pixel data output by the connected two first-level logic OR gates are synthesized into one path of first image data, thereby obtaining four paths of first image data, respectively These are the first image data 1245 , the first image data 4578 , the first image data 2356 and the first image data 5689 .

Each second-level logical OR gate can output one channel of first image data obtained by itself to the multiplexer, and the multiplexer can sequentially output each channel of first image data to the processing unit according to the received strobe signal .

Among them, the second level logic OR gate corresponding to macro pixel 1 can be connected to the input terminal 1 of the multiplexer, the second level logic OR gate corresponding to macro pixel 2 can be connected to the input terminal 2 of the multiplexer, and the macro pixel 3 corresponds to The second level logical OR gate of the macro pixel 4 is connected to the input terminal 3 of the multiplexer, and the second level logical OR gate corresponding to the macro pixel 4 is connected to the input terminal 4 of the multiplexer. Correspondingly, the control terminal of the processing unit may output strobe signals 00, 01, 10 and 11 in sequence. When the multiplexer receives the strobe signal 00, it outputs the first image data 1245. After receiving the first image data 1245, the processing unit uses the first image data 1245 as the pixel data at the position of the macro pixel 1. When the gate signal 01 is received, the first image data 2356 is output, and the processing unit takes the first image data 2356 as the pixel data at the position of the macro pixel 2 after receiving the first image data 2356 . By analogy, the final fused image is shown in Figure 8.

In the embodiment of the present application, through the switch array and the multiplexer in the imaging unit, one channel of first image data corresponding to each macro pixel in the plurality of macro pixels can be sequentially output, and the processing unit receives the first image data corresponding to each macro pixel. image data, and generate a fused image according to the first image data corresponding to each macro pixel and the position of the corresponding macro pixel. Since there are overlapping SPAD sub-pixels between every two adjacent macro-pixels in the multiple macro-pixels included in the SPAD array in the imaging unit, the image data of the macro-pixels output by the imaging unit are output by the switch array and the multiplexer. The number increases, but the TDC and histogram calculation circuits of the SPAD array do not increase. It can be seen that the image processing method provided by the embodiment of the present application can be used without increasing the number of SPAD sub-pixels, subsequent storage, and main circuit area. Next, the planar resolution of the output image of the SPAD array is improved.

Next, the imaging method provided in the embodiment of the present application is introduced.

Fig. 9 is a flow chart of an imaging control method provided by an embodiment of the present application, the method is applied to the processing unit of the imaging device introduced in the foregoing embodiments, the imaging device also includes an imaging unit, and the imaging unit includes a single photon avalanche diode SPAD Array, the SPAD array includes a plurality of macro pixels, each macro pixel in the plurality of macro pixels includes (N×M) SPAD sub-pixels, and there are overlapping SPAD sub-pixels between every two adjacent macro pixels, wherein , the switch array is used to receive sub-pixel data respectively output by (N×M) SPAD sub-pixels included in each macro-pixel in a plurality of macro-pixels, and the (N×M) SPAD sub-pixels included in each macro-pixel are respectively The output sub-pixel data is synthesized to obtain one path of first image data corresponding to the corresponding macro pixel, and one path of first image data corresponding to each macro pixel is output to the multiplexer. The method includes the following steps:

Step 901: The processing unit sequentially outputs different types of strobe signals to the multiplexer according to the preset timing, so that the multiplexer outputs a corresponding strobe signal every time it receives a strobe signal output by the processing unit. corresponding to the first image data.

Wherein, the implementation process of the processing unit sequentially outputting different types of strobe signals according to the preset time sequence can refer to the implementation manners introduced in the foregoing embodiments, and the embodiments of the present application will not repeat them here.

Step 902: The processing unit receives the first image data corresponding to each macro pixel sequentially output by the multiplexer, and generates a fused image according to the first image data corresponding to each macro pixel and the position of the corresponding macro pixel.

Wherein, the process of outputting the corresponding first image data by the multiplexer according to the strobe signal sent by the processing unit may refer to the implementation manners in the foregoing embodiments. In addition, the process of generating the fused image by the processing unit may also refer to the foregoing implementation manners, which will not be repeated in this embodiment of the present application.

Optionally, the switch array includes a first-level logical OR gate and a second-level logical OR gate, a row of SPAD sub-pixels in the first macro pixel is connected to a first-level logical OR gate, and multiple rows of SPAD sub-pixels in the first macro pixel A plurality of connected first-level logical OR gates are connected to a second-level logical OR gate, and the first macro pixel is any one of the plurality of macro pixels;

Wherein, each first-stage logical OR gate connected to the first macro pixel receives a road of sub-pixel data output by each SPAD sub-pixel in a row of SPAD sub-pixels connected to itself, and synthesizes the received sub-pixel data into a road of pixel data , output row pixel data;

The second-level logical OR gate connected to the first macro pixel receives row pixel data respectively outputted by multiple first-level logical OR gates connected to itself, and synthesizes the received row pixel data to obtain the first pixel corresponding to the first macro pixel. Image data, outputting first image data corresponding to the first macro pixel.

Optionally, the switch array includes a first-level logical OR gate and a second-level logical OR gate, a column of SPAD sub-pixels in the first macro-pixel is connected to a first-level logical OR gate, and multiple columns of SPAD sub-pixels in the first macro-pixel A plurality of connected first-level logical OR gates are connected to a second-level logical OR gate, and the first macro pixel is any one of the plurality of macro pixels;

Each first-level logical OR gate connected to the first macro-pixel is used to receive a channel of sub-pixel data output by each SPAD sub-pixel in a connected column of SPAD sub-pixels, and synthesize the received sub-pixel data into a column of pixel data , output column pixel data;

The second-level logical OR gate connected to the first macro pixel is used to receive column pixel data respectively output by the connected multiple first-level logical OR gates, and synthesize the received column pixel data to obtain the first macro pixel corresponding to the first macro pixel. Image data, outputting the first image data corresponding to the first macro pixel.

Optionally, the multiplexer includes multiple input terminals, an output terminal and a control terminal, multiple input terminals of the multiplexer are connected to the switch array, and the control terminal of the multiplexer is connected to the control terminal of the processing unit , the output end of the multiplexer is connected to the input end of the processing unit, and each input end of the multiplexer receives one path of first image data output by the switch array;

The processing unit sequentially outputs different types of strobe signals to the multiplexer according to the preset timing, including:

The control terminal of the processing unit outputs the first strobe signal to the control terminal of the multiplexer at the first measurement moment, so that the output terminal of the multiplexer outputs one channel corresponding to the first strobe signal at the first measurement moment. For the first image data, the first measurement moment is any one of the plurality of measurement moments.

Optionally, the processing unit generates a fused image according to the first image data corresponding to each macropixel and the position of the corresponding macropixel, including:

According to the gate signal output at each measurement moment, determine the position of the macro pixel corresponding to the first image data corresponding to the received corresponding gate signal;

The first image data corresponding to the corresponding gate signal is used as the pixel value at the position of the macro pixel determined at the corresponding measurement time, so as to generate a fused image.

Optionally, every two adjacent macro pixels in the multiple macro pixels have (N-1) rows of overlapping SPAD sub-pixels, or, every two adjacent macro pixels in the multiple macro pixels have (M-1 ) columns of overlapping SPAD sub-pixels.

It should be noted that, for implementation manners of the foregoing steps, reference may be made to the implementation manners of the imaging device in the foregoing embodiments, and details are not repeated in this embodiment of the present application.

To sum up, in the embodiment of the present application, through the switch array and multiplexer in the imaging unit, one channel of first image data corresponding to each macro pixel among the multiple macro pixels can be sequentially output, and the processing unit receives each macro pixel The pixel corresponds to the first image data, and according to the first image data corresponding to each macro pixel and the position of the corresponding macro pixel, a fused image is generated. Since there are overlapping SPAD sub-pixels between every two adjacent macro-pixels in the multiple macro-pixels included in the SPAD array in the imaging unit, the image data of the macro-pixels output by the imaging unit are output by the switch array and the multiplexer. The number increases, but the TDC and histogram calculation circuits of the SPAD array do not increase. It can be seen that the image processing method provided by the embodiment of the present application can be used without increasing the number of SPAD sub-pixels, subsequent storage, and main circuit area. Next, the planar resolution of the output image of the SPAD array is improved.

The embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by the aforementioned imaging device, the imaging control method shown in FIG. 9 can be realized.

The embodiment of the present application also provides a computer program product including instructions, which, when running on the aforementioned imaging device, causes the imaging device to execute the imaging control method provided in the embodiment shown in FIG. 9 above.

The above description is not intended to limit the embodiments of the present application, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the embodiments of the present application shall be included within the scope of protection of the embodiments of the present application.

Claims (12)

1. An image forming apparatus, characterized in that the image forming apparatus comprises: the device comprises an imaging unit and a processing unit, wherein the imaging unit comprises a single photon avalanche diode SPAD array, a switch array and a multiplexer, the SPAD array comprises a plurality of macro pixels, each macro pixel in the plurality of macro pixels comprises (N multiplied by M) SPAD sub-pixels, and each two adjacent macro pixels have overlapped SPAD sub-pixels;

the switch array is used for receiving sub-pixel data respectively output by (N multiplied by M) SPAD sub-pixels included by each macro-pixel in the macro-pixels, synthesizing the sub-pixel data respectively output by (N multiplied by M) SPAD sub-pixels included by each macro-pixel to obtain a path of first image data corresponding to the corresponding macro-pixel, and outputting a path of first image data corresponding to each macro-pixel;

the multiplexer is used for receiving the multiple paths of first image data output by the switch array and sequentially outputting the multiple paths of first image data to the processing unit;

the processing unit is used for receiving the first image data corresponding to each macro pixel sequentially output by the multiplexer, and generating a fusion image according to the position of each macro pixel, the corresponding first image data and the corresponding macro pixel.

2. The imaging device of claim 1, wherein the switch array comprises a first stage logical OR gate and a second stage logical OR gate, one row of SPAD sub-pixels in a first macro-pixel is connected with one first stage logical OR gate, a plurality of first stage logical OR gates connected with a plurality of rows of SPAD sub-pixels in the first macro-pixel are connected with one second stage logical OR gate, and the first macro-pixel is any one macro-pixel in the plurality of macro-pixels;

each first-stage logic or gate connected with the first macro pixel is used for receiving sub-pixel data output by each SPAD sub-pixel in a row of SPAD sub-pixels connected with the first macro pixel, synthesizing the received sub-pixel data into a row of pixel data, and outputting the row of pixel data;

the second-level logic or gate connected with the first macro pixel is used for receiving row pixel data respectively output by the plurality of first-level logic or gates connected with the second macro pixel, synthesizing the received row pixel data to obtain first image data corresponding to the first macro pixel, and outputting the first image data corresponding to the first macro pixel.

3. The imaging device of claim 1, wherein the switch array comprises a first stage logical OR gate and a second stage logical OR gate, one column of SPAD sub-pixels in the first macro-pixel is connected with one first stage logical OR gate, a plurality of first stage logical OR gates connected with a plurality of columns of SPAD sub-pixels in the first macro-pixel are connected with one second stage logical OR gate, and the first macro-pixel is any one macro-pixel in the plurality of macro-pixels;

each first-level logic or gate connected with the first macro-pixel is used for receiving one path of sub-pixel data output by each SPAD sub-pixel in a connected row of SPAD sub-pixels, synthesizing the received sub-pixel data into one path of row pixel data and outputting the row of pixel data;

the second-level logic or gate connected with the first macro-pixel is used for receiving column pixel data respectively output by the plurality of first-level logic or gates connected with the first macro-pixel, synthesizing the received column pixel data to obtain first image data corresponding to the first macro-pixel, and outputting the first image data corresponding to the first macro-pixel.

4. The imaging apparatus of claim 1, wherein the multiplexer includes a plurality of input terminals, an output terminal, and a control terminal, the plurality of input terminals of the multiplexer being connected to the switch array, the control terminal of the multiplexer being connected to the control terminal of the processing unit, the output terminal of the multiplexer being connected to the input terminal of the processing unit;

each input end of the multiplexer is used for receiving one path of first image data output by the switch array;

the control end of the multiplexer is used for receiving the gating signal output by the control end of the processing unit at each measuring moment;

and the output end of the multiplexer is used for outputting one path of first image data corresponding to the gating signal received at the corresponding measuring moment at each measuring moment.

5. The imaging apparatus according to claim 4, wherein the processing unit is configured to determine, according to the gating signal output at each measurement time, a position of a macro pixel corresponding to the first image data corresponding to the received corresponding gating signal, and use the first image data corresponding to the corresponding gating signal as the pixel data at the determined position of the macro pixel to generate the fused image.

6. The imaging device of any of claims 1-5, wherein each adjacent two of the plurality of macropixels have (N-1) rows of overlapping SPAD subpixels, or wherein each adjacent two of the plurality of macropixels have (M-1) columns of overlapping SPAD subpixels.

7. An imaging control method is applied to a processing unit of an imaging device, the imaging device further comprises an imaging unit, the imaging unit comprises a single-photon avalanche diode SPAD array, a switch array and a multiplexer, the SPAD array comprises a plurality of macro pixels, each macro pixel in the macro pixels comprises (N × M) SPAD sub-pixels, and overlapped SPAD sub-pixels are arranged between every two adjacent macro pixels, wherein the switch array is used for receiving sub-pixel data respectively output by the (N × M) SPAD sub-pixels included by each macro pixel in the macro pixels, synthesizing the sub-pixel data respectively output by the (N × M) SPAD sub-pixels included by each macro pixel to obtain a path of first image data corresponding to the corresponding macro pixel, and outputting the path of first image data corresponding to each macro pixel to the multiplexer; the method comprises the following steps:

the processing unit sequentially outputs different types of gating signals to the multiplexer according to a preset time sequence, so that the multiplexer outputs first image data corresponding to the corresponding gating signals when receiving one type of gating signal output by the processing unit;

and the processing unit receives the first image data corresponding to each macro pixel sequentially output by the multiplexer, and generates a fusion image according to the first image data corresponding to each macro pixel and the position of the corresponding macro pixel.

8. The method of claim 7, wherein the switch array comprises a first-stage logical OR gate and a second-stage logical OR gate, one row of SPAD sub-pixels in the first macro-pixel is connected with one first-stage logical OR gate, a plurality of first-stage logical OR gates connected with a plurality of rows of SPAD sub-pixels in the first macro-pixel are connected with one second-stage logical OR gate, and the first macro-pixel is any one of the plurality of macro-pixels;

each first-stage logic or gate connected with the first macro-pixel is used for receiving sub-pixel data output by each SPAD sub-pixel in a row of SPAD sub-pixels connected with the first macro-pixel, synthesizing the received sub-pixel data into a row of pixel data, and outputting the row of pixel data;

the second-level logic or gate connected with the first macro pixel is used for receiving row pixel data respectively output by a plurality of first-level logic or gates connected with the second macro pixel, synthesizing the received row pixel data to obtain first image data corresponding to the first macro pixel, and outputting the first image data corresponding to the first macro pixel.

9. The method of claim 7, wherein the switch array comprises a first stage logical OR gate and a second stage logical OR gate, one column of SPAD sub-pixels in the first macro-pixel is connected with one first stage logical OR gate, a plurality of first stage logical OR gates connected with a plurality of columns of SPAD sub-pixels in the first macro-pixel are connected with one second stage logical OR gate, and the first macro-pixel is any one macro-pixel in the plurality of macro-pixels;

each first-stage logic or gate connected with the first macro pixel is used for receiving one path of sub-pixel data output by each SPAD sub-pixel in a connected line of SPAD sub-pixels, synthesizing the received sub-pixel data into one line of pixel data and outputting the line of pixel data;

the second-level logic or gate connected with the first macro-pixel is used for receiving column pixel data respectively output by the plurality of first-level logic or gates connected with the first macro-pixel, synthesizing the received column pixel data to obtain first image data corresponding to the first macro-pixel, and outputting the first image data corresponding to the first macro-pixel.

10. The method according to claim 7, wherein the multiplexer comprises a plurality of input terminals, an output terminal and a control terminal, the plurality of input terminals of the multiplexer are connected to the switch array, the control terminal of the multiplexer is connected to the control terminal of the processing unit, the output terminal of the multiplexer is connected to the input terminal of the processing unit, and each input terminal of the multiplexer is configured to receive a path of the first image data output by the switch array;

the processing unit sequentially outputs different kinds of gating signals to the multiplexer according to a preset time sequence, and the gating signals comprise:

the control end of the processing unit outputs a first gating signal to the control end of the multiplexer at a first measurement time, so that the output end of the multiplexer outputs one path of first image data corresponding to the first gating signal at the first measurement time, and the first measurement time is any one of a plurality of measurement times.

11. The method of claim 10, wherein the processing unit generates the fused image according to the first image data corresponding to each macro-pixel and the position of the corresponding macro-pixel, and comprises:

determining the position of a macro pixel corresponding to first image data corresponding to the received corresponding gating signal according to the gating signal output at each measuring moment;

and taking the first image data corresponding to the corresponding gating signal as pixel data at the position of the macro pixel determined at the corresponding measuring moment to generate the fused image.

12. The method of any of claims 7-11, wherein each adjacent two of the macropixels have (N-1) rows of overlapping SPAD subpixels, or wherein each adjacent two of the macropixels have (M-1) columns of overlapping SPAD subpixels.

Images