CN116759425A

CN116759425A - electronic device

Info

Publication number: CN116759425A
Application number: CN202210209918.1A
Authority: CN
Inventors: 宋立伟; 陈承佐; 陈宏昆; 康承泰
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2022-03-03
Filing date: 2022-03-03
Publication date: 2023-09-15
Also published as: TW202403520A

Abstract

The present disclosure provides an electronic device, comprising: a first gate line, a second gate line, a data line, and a semiconductor pattern. The first gate line has a first extension line and a first gate electrode protruding from the first extension line. The second gate line is adjacent to the first gate line, wherein the second gate line has a second extension line and a second gate electrode protruding from the second extension line. In a top view of the electronic device, the data lines are interleaved with the first gate lines and the second gate lines. The semiconductor pattern is electrically connected to the data line, wherein the semiconductor pattern is disposed between the first extension line and the second extension line, and the semiconductor pattern overlaps the first gate electrode and overlaps the second gate electrode.

Description

Electronic device

Technical Field

The present disclosure relates to an electronic device, and more particularly, to a semiconductor pattern layout design.

Background

Electronic devices have become an indispensable product for modern life. However, the present electronic devices still do not meet the expectations of consumers in various aspects, for example, the border area of the non-display area still occupies a large space, and the manufacturing process is complicated due to the use of multiple masks. Therefore, developing a structural design that can improve the quality or performance of an electronic device is one of the subjects of the current research in the industry.

Disclosure of Invention

Drawings

In order to make the features and advantages of the present disclosure more comprehensible, several embodiments accompanied with figures are described in detail below.

FIG. 1 shows a top view of an electronic device, according to some embodiments of the present disclosure;

FIG. 2 shows an enlarged top view corresponding to block E of FIG. 1, in accordance with some embodiments of the present disclosure;

FIG. 3 shows a top view of an electronic device subsequent to FIG. 1 and having pixel electrodes disposed therein, in accordance with some embodiments of the present disclosure;

FIG. 4 illustrates a top view of a pixel electrode corresponding to block E' of FIG. 3 and omitting portions, in accordance with some embodiments of the present disclosure;

FIGS. 5-6 show schematic cross-sectional views of an electronic device corresponding to section lines AA 'and BB' of FIG. 4, respectively, in accordance with some embodiments of the present disclosure;

fig. 7 shows a circuit diagram of an electronic device, according to some embodiments of the present disclosure.

[ symbolic description ]

10 electronic device

11 display area

12 non-display area

100 substrate

200 buffer layer

210 nitride buffer layer

220 oxide buffer layer

300 gate dielectric layer

400 interlayer dielectric layer

410 nitride dielectric layer

420 oxide dielectric layer

500 Flat layer

600 common electrode

700 insulating layer

BP branch position

C conductor layer

E square frame

E': box

M conductive pattern

N pattern

T: touch signal line

CKH1, CKH2, CKH3 routing

S [ n ], S [ n+1]: source signal source

R, G, B pixel unit

D data line

D1, D2, D3, D4, D5, D6 data line

G: grid line

Ga gate protrusion

GE: gate electrode

GT gate extension line

G1 (first) gate line

GT1 first gate extension line

GE1 first gate electrode

G2 (second) gate line

Ga2 second Gate protrusion

GT2 second gate extension line

GE2 second gate electrode

G-1, G0, G3, G4, G5, G6, G7, G8: gate line

S: semiconductor pattern

S1 first branch portion

S2 second branching portion

S2C channel (of second branch portion)

S2D, S2B (of the second branch portion)

SM main part

SMD (major part) doped region

L11: first length

L22: second length

Length of L1

Length of L2

Tr: thin film transistor

Tr1 first thin film transistor

Tr2 second thin film transistor

P0 edge

P1 first edge

P2:second edge

V1 first guide hole

V2 second guide hole

V3 third guide hole

V4 fourth guide hole

x is the first direction

y is in the second direction

X-pixel unit

XE pixel electrode

XE (1, 1), XE (2, 1), XE (3, 1), XE (4, 1), XE (1, 2), XE (2, 2), XE (3, 2), XE (4, 2) pixel electrode

XEA finger part

XEB connecting portion

XE1 first pixel electrode

XE2 second pixel electrode

Detailed Description

The following describes an electronic device according to an embodiment of the present disclosure in detail. It is to be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the disclosure. The specific components and arrangements described below are merely illustrative of some embodiments of the present disclosure. These are, of course, merely examples and are not intended to be limiting of the present disclosure. Moreover, similar and/or corresponding reference numerals may be used in different embodiments to identify similar and/or corresponding components in order to clearly describe the present disclosure. However, the use of such similar and/or corresponding reference numerals is merely for simplicity and clarity in describing some embodiments of the present disclosure and is not intended to represent any relevance between the various embodiments and/or structures discussed.

The present disclosure may be understood by referring to the following detailed description in conjunction with the accompanying drawings, it being noted that, in order to facilitate the understanding of the reader and the brevity of the drawings, the various drawings in the present disclosure depict only a portion of the electronic device and the specific components in the drawings are not necessarily drawn to scale. In addition, the number and size of the components in the drawings are illustrative only and are not intended to limit the scope of the present disclosure.

It should be understood that the components or devices of the drawings may exist in various forms well known to those skilled in the art. In addition, relative terms, such as "lower" or "bottom" or "upper" or "top", may be used in embodiments to describe the relative relationship of one element to another element of the figures. It will be appreciated that if the device of the figures is turned upside down, the elements described as being on the "lower" side would then be elements on the "upper" side. Embodiments of the present disclosure may be understood together with the accompanying drawings, which are also considered part of the disclosure description. Furthermore, when a first material layer is referred to as being on or over a second material layer, it includes situations where the first material layer is in direct contact with the second material layer, or where one or more other material layers may be spaced therebetween, in which case there may not be direct contact between the first material layer and the second material layer.

Certain terms are used throughout the description and following claims to refer to particular components. Those skilled in the art will appreciate that electronic device manufacturers may refer to a same component by different names. It is not intended to distinguish between components that differ in function but not name. In the following description and claims, the terms "include", "have", and the like are open-ended terms, and thus should be interpreted to mean "include, but not limited to …". Thus, when the terms "comprises," "comprising," "includes," and/or "including" are used in the description of the present disclosure, they specify the presence of stated features, regions, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, regions, steps, operations, and/or components.

Directional terms mentioned herein, such as: "up", "down", "front", "back", "left", "right", etc., refer only to the orientation of the drawing figures. Thus, directional terminology is used for purposes of illustration and is not intended to be limiting of the disclosure. In the drawings, the various figures illustrate the general features of methods, structures and/or materials used in certain embodiments. However, these drawings should not be construed as defining or limiting the scope or nature of what is covered by these embodiments. For example, the relative dimensions, thicknesses, and locations of various layers, regions, and/or structures may be reduced or exaggerated for clarity.

When a corresponding element (e.g., a film layer or region) is referred to as being "on" another element, it can be directly on the other element or other elements can be present therebetween. On the other hand, when an element is referred to as being "directly on" another element, there are no elements therebetween. In addition, when a component is referred to as being "on" another component, the two are in a top-down relationship in the top-down direction, and the component may be above or below the other component, and the top-down relationship depends on the orientation of the device.

Furthermore, it should be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components or portions, these elements, components or portions should not be limited by these terms. These terms are only used to distinguish between different components, regions, layers or sections. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

As used herein, the term "about" or "substantially" generally means within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. Where a given amount is an approximate amount, that is, where "about" and "substantially" are not specifically recited, the meaning of "about" and "substantially" may still be implied. Furthermore, the term "range between a first value and a second value" means that the range includes the first value, the second value, and other values therebetween.

It is to be understood that the following exemplary embodiments may be substituted, rearranged, and mixed for the features of several different embodiments to achieve other embodiments without departing from the spirit of the disclosure. Features of the embodiments can be mixed and matched at will without departing from the spirit of the invention or conflicting.

In the present disclosure, the thickness, length and width may be measured by an optical microscope, and the thickness may be measured by a cross-sectional image in an electron microscope, but is not limited thereto. In addition, any two values or directions used for comparison may have some error. If the first value is equal to the second value, it implies that there may be about a 10% error between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be appreciated that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

According to some embodiments, the device characteristics may be made uniform by a semiconductor pattern in a clip type (papertype), wherein the semiconductor pattern overlaps two gate electrodes by two branches. In addition, according to some embodiments, by connecting two thin film transistors to the same data line, the data line signal source can be halved, and the number of light shielding regions and source integrated circuits can be greatly reduced.

Referring to fig. 1, fig. 1 illustrates a top view of an electronic device 10 according to some embodiments of the present disclosure. In some embodiments, the electronic apparatus 10 may be a display device or a non-display device. For example, the electronic device 10 may be a touch display, such as a touch liquid crystal display, such as a thin film transistor liquid crystal display. Alternatively, the liquid crystal display may be a Twisted Nematic (TN) type liquid crystal display, a super Twisted Nematic (Super Twisted Nematic, STN) type liquid crystal display, a double layer super Twisted Nematic (Double layer Super Twisted Nematic, DSTN) type liquid crystal display, a vertical alignment (Vertical Alignment, VA) type liquid crystal display, an In-Plane Switching (IPS) type liquid crystal display, a Cholesteric (Cholesteric) type liquid crystal display, a Blue Phase (Blue Phase) type liquid crystal display, a fringe field effect (FFS) type liquid crystal display, a low temperature polysilicon liquid crystal display (LTPS) or any other suitable liquid crystal display. It should be noted that fig. 1 only shows some components, and other film layers and/or components (e.g., flat layers, etc.) are omitted for brevity.

For convenience of description, the electronic device 10 is illustrated by a touch display device, but is not limited thereto. As shown in fig. 1, the electronic device 10 includes a plurality of gate lines G and a plurality of data lines D disposed on a substrate 100. In some embodiments, the gate line G extends substantially along the first direction x, and the gate line G is non-linear but has a main extending direction substantially along the first direction x. The data line D extends substantially along the second direction y. In some embodiments, the data line D is non-linear, but extends substantially along the second direction y, for example, the data line D may have an angle between 5 ° and 25 °, for example, between 0 ° and 10 °, for example, between 0 ° and 5 °. In some embodiments, the first direction x is substantially perpendicular to the second direction y. That is, the gate line G is substantially vertical (perpendicular) or orthogonal (orthogonal) to the data line D. In some embodiments, the Gate line G may be connected to a Gate driving circuit, which may be disposed on the substrate 100, to form a Gate On Panel (GOP) structure of the Gate circuit.

In some embodiments, the gate line G may include gate extension lines GT, gate electrodes GE respectively connected to the gate extension lines GT. The gate extension line GT extends substantially along the first direction x, and the gate electrode GE may protrude from the gate extension line GT toward the second direction y. In some embodiments, the gate line G may further include a gate protrusion Ga, and the details may correspond to those described with reference to the second gate protrusion Ga2 in fig. 2.

As shown in fig. 1, the electronic device 10 includes a plurality of touch signal lines T disposed on a substrate 100. The touch signal line T extends substantially along the second direction y, and the touch signal line T is non-linear but substantially extends along the second direction y, wherein an included angle between the touch signal line T and the second direction y is approximately between 5 ° and 25 °, for example, may be between 0 ° and 10 °, for example, may be between 0 ° and 5 °. In some embodiments, along the first direction x, the touch signal lines T and the data lines D are staggered and substantially parallel to each other. That is, the touch signal line T and the data line D do not overlap each other.

According to some embodiments, by staggering the touch signal lines T and the data lines D, the touch signal lines T and the data lines D can be disposed on the same film layer, so as to reduce the number of masks used.

As shown in fig. 1, the electronic device 10 includes a plurality of thin film transistors Tr disposed on a substrate 100 at intersections of gate lines G and data lines D. In some embodiments, the thin film transistor Tr corresponds to one pixel electrode (see fig. 3). In some embodiments, the thin film transistor Tr is surrounded by two gate lines G, a data line D, and a touch signal line T. In some embodiments, 2n thin film transistors Tr are included between any two data lines D, where n is a positive integer. The thin film transistor Tr includes a gate electrode GE (electrically connected to the gate line G), a drain electrode (electrically connected to the conductive pattern M), a source electrode (electrically connected to the data line D), and an active layer (illustrated as a semiconductor pattern S). In some embodiments, the data line D provides a source signal to the pixel unit through the thin film transistor Tr, and the gate line G (scan line) controls whether the data signal is written to the pixel unit through the thin film transistor Tr.

In some embodiments, the thin film transistors Tr are arranged zigzag along both sides of the data line D (substantially along the second direction y). That is, along the data line D, the thin film transistors Tr are sequentially arranged on the left and right sides (first direction +x and first direction-x) of the data line D. In some embodiments, the thin film transistor Tr is disposed between two gate lines G (dual gate line design). Thus, the number of data line signal sources can be halved, and the number of light shielding regions (such as Black Matrix (BM)) and source integrated circuits can be greatly reduced.

The electronic device 10 includes a semiconductor pattern S as an active layer, which will be described in detail later in fig. 2. Note that each two thin film transistors Tr corresponds to one semiconductor pattern S.

The electronic device 10 includes a plurality of first vias V1, a plurality of second vias V2, a plurality of third vias V3, and a plurality of fourth vias V4 disposed on the substrate 100 for vertical electrical connection. According to some embodiments, one thin film transistor Tr may correspond to one first via V1, one second via V2, one third via V3. Two thin film transistors Tr may correspond to one fourth via V4. The connection of the vias will be described in detail later with reference to the cross-sectional view.

The electronic device 10 may include a conductive pattern M. According to some embodiments, one thin film transistor Tr may correspond to one conductive pattern M. According to some embodiments, the electronic device 10 may include a pattern N, and two thin film transistors Tr may correspond to one pattern N. The first via V1 and the second via V2 and/or the third via V3 may be electrically connected to the conductive pattern M, which will be described in detail later in the cross-sectional view (refer to fig. 5). It should be noted that the data line D, the touch signal line T, the conductive pattern M and the pattern N are collectively referred to as a conductive layer C hereinafter, that is, may be the same layer.

Referring next to fig. 2, fig. 2 shows an enlarged top view corresponding to block E of fig. 1, in accordance with some embodiments of the present disclosure.

As shown in fig. 2, the block E includes two thin film transistors (hereinafter, referred to as a first thin film transistor Tr1 and a second thin film transistor Tr2, respectively) that may be disposed on both sides of the touch signal line T. In some embodiments, the first thin film transistor Tr1 and the second thin film transistor Tr2 are disposed substantially diagonally with respect to the touch signal line T. That is, the pixel electrodes XE1, XE2 formed on the first thin film transistor Tr1 and the second thin film transistor Tr2, respectively, are also arranged substantially diagonally (see fig. 4). In some embodiments, two thin film transistors are electrically connected to the same data line D. That is, two thin film transistors share the same source. Therefore, the number of the data lines D can be halved, the number of the source integrated circuits can be further reduced, and the shading area can be greatly saved.

As shown in fig. 2, the electronic device 10 may include a first gate line G1, a second gate line G2, a data line D, and a semiconductor pattern S. The two gate lines are respectively shown as a first gate line G1 and a second gate line G2 adjacent to the first gate line G1. In fig. 2, the first gate line G1 is located above the second gate line G2. The first gate line G1 has a first gate extension line GT1 and a first gate electrode GE1 protruding from the first gate extension line GT 1. The second gate line G2 has a second gate extension line GT2 and a second gate electrode GE2 protruding from the second gate extension line GT 2. The first gate extension line GT1 and the second gate extension line GT2 extend along the first direction x. The first gate electrode GE1 protrudes from the first gate extension line GT1 toward the second gate extension line GT2 along the second direction y. The second gate electrode GE2 protrudes from the second extension line GT2 toward the first gate extension line GT1 along the second direction y. In some embodiments, the first gate line G1 and the second gate line G2 do not overlap each other. The protruding direction of the first gate electrode GE1 and the protruding direction of the second gate electrode GE2 may be opposite directions, for example, the protruding direction of the first gate electrode GE1 may be a-y direction and the protruding direction of the second gate electrode GE2 may be a +y direction.

In the embodiment of fig. 2, the first thin film transistor Tr1 and the second thin film transistor Tr2 are disposed between the first gate extension line GT1 and the second gate extension line GT2. In the embodiment of fig. 2, two first guide holes V1, two second guide holes V2 and/or two third guide holes V3, and one fourth guide hole V4 are provided between the first gate extension line GT1 and the second gate extension line GT2.

According to some embodiments, the gate line G may further include a gate protrusion. As shown in fig. 2, the second gate line G2 may include a second gate protrusion Ga2, which may protrude from the gate extension line GT toward the second direction y, and is electrically connected to the second gate extension line GT2. The second gate protrusion Ga2 may be disposed opposite to the first gate electrode GE1, for example, in the second direction y.

As shown in fig. 2, the conductive layer C includes a data line D, a touch signal line T, a conductive pattern M and a pattern N.

As shown in fig. 2, the data line D is electrically connected to the doped region (source) in the semiconductor pattern S through the fourth via V4 (refer to fig. 5). In some embodiments, in a top view of the electronic device 10 (e.g., fig. 2), the data line D is interleaved with the first gate line G1 and the second gate line G2. That is, in fig. 2, the first gate line G1 and the second gate line G2 overlap the data line D, respectively. In some embodiments, the common electrode may have a pattern to form a plurality of touch electrodes. The touch signal line T may be electrically connected to a common electrode (e.g., the common electrode 600 of fig. 5). The capacitance change is generated during touch control, and the generated induced current can be transmitted to the touch control signal line T and transmitted back to the integrated circuit to calculate the coordinate position. In some embodiments, the touch signal line T is between two thin film transistors Tr. As shown in fig. 2, the conductive pattern M is electrically connected to the doped region (drain electrode) in the semiconductor pattern S through the first via V1, and is electrically connected to the pixel electrode (see also fig. 5) through the second via V2 and/or the third via V3. As shown in fig. 2, the pattern N is disposed corresponding to the second gate protrusion Ga2, and can be connected in parallel with the gate line G2, so as to reduce the resistance of the gate line.

As shown in fig. 2, the semiconductor pattern S (as an active layer) is electrically connected to the data line D. The semiconductor pattern S is disposed between the first gate extension line GT1 and the second gate extension line GT 2. The semiconductor pattern S overlaps the first gate electrode GE1 and the second gate electrode GE 2.

In some embodiments, the semiconductor pattern S includes a main portion SM, a first branch portion S1, and a second branch portion S2. The first branch portion S1 is connected to the main portion SM, and the second branch portion S2 is connected to the main portion SM. In some embodiments, the first branch portion S1 and the first gate electrode GE1 overlap each other, and the second branch portion S2 and the aforementioned second gate electrode GE2 overlap each other.

In some embodiments, the first and second branch portions S1 and S2 may be connected with the main portion SM, and branched by a branching position BP, and extend in different directions. That is, in the semiconductor pattern S, the position extending from the main portion SM in the different directions may be the branch position BP. In detail, as shown in fig. 2, in some embodiments, starting from the main portion SM, a position starting to extend toward different directions may be defined as a branching position BP. The portion extending from the branching position BP toward the first direction x is a first branching portion S1, and the portion extending from the branching position BP toward the second direction y is a second branching portion S2, but the present invention is not limited thereto. According to some embodiments, the middle line of the width is taken in the extending direction (first direction x) of the main portion SM, and the middle line of the width is taken in the extending direction (second direction y) of the second branch portion S2, and the intersection of the two middle lines may be defined as the branch position BP.

According to some embodiments, as shown in fig. 2, the first branch portion S1 and the main portion SM are extending along the first direction x. A portion of the second branch portion S2 extends along the second direction y and is connected to the main portion SM and/or the first branch portion S1 via the branch position BP, and another portion of the second branch portion S2 extends along the first direction x toward the data line D and is arranged in parallel with the main portion SM and/or the first branch portion S1. That is, from the branching position BP, the main portion SM extending toward the data line D and electrically connected thereto is the second branching portion S2 extending toward the second gate line G2 and electrically connected to the conductive pattern M, and the first branching portion S1 overlapping the touch signal line T and electrically connected to the other conductive pattern M. In some embodiments, in the upper view, as shown in fig. 2, the data line D overlaps the semiconductor pattern S, for example, the data line D overlaps the main portion SM. According to some embodiments, in the upper view, the touch signal line T overlaps the semiconductor pattern S, for example, the touch signal line T overlaps the first branch portion S1.

In some embodiments, as shown in fig. 2, the main portion SM is disposed in a first direction x, the second branch portion S2 is disposed in a second direction y, and then is pivoted to be disposed toward the first direction x of the data line D, so that the main portion SM and the second branch portion S2 have a U-shape with openings toward the data line D, and the first branch portion S1 protrudes from the U-shape, which is herein referred to as a clip-type semiconductor pattern S.

In some embodiments, as shown in fig. 2, the semiconductor pattern S has a first length L11, and the first length L11 may be a length from an edge P0 of the main portion SM to an edge P1 of the first gate electrode GE1 along the first branch portion S1. The semiconductor pattern S has a second length L22, and the second length L22 may be a length from an edge P0 of the main portion SM to an edge P2 of the second gate electrode GE2 along the second branch portion S2. As shown in fig. 2, the measuring positions of the first length L11 and the second length L22 may be, but not limited to, the outer edge, the inner edge, or the inner edge of the semiconductor pattern S. The outer edge may be, for example, an edge farther from the second gate electrode GE 2. According to some embodiments, the outer edge of the semiconductor pattern S may be straight or non-straight, or may have an arc shape. In the case where the outer edge of the semiconductor pattern S is not a straight line, the measurement positions of the first length L11 and the second length L22 may be a straight line overlapping the edge of the semiconductor pattern S or may be a straight line inside the semiconductor pattern S.

According to some embodiments, the middle line of the width is taken in the extending direction (first direction x) of the main portion SM, and the middle line of the width is taken in the extending direction (second direction y) of the second branch portion S2, and the intersection of the two middle lines may be defined as the branch position BP. For example, the first length L11 may be measured as a straight line length starting from the edge P0, passing through the main portion SM and the first branch portion S1, and reaching the edge P1 of the first gate electrode GE 1. For example, a straight line (a straight line parallel to the first direction x) along the extending direction thereof may be measured at the edge or inside the main portion SM. The measurement position of the second length L22 may be a first straight line (a straight line parallel to the first direction x) passing through the main portion SM from the edge P0, a second straight line (extending along the second direction y) turning through the second branch portion S2, and a third straight line (a straight line parallel to the first direction x) turning through the second branch portion S2 to the edge P2 of the second gate electrode GE2, and the second length L22 may be a length of a sum of the three straight lines.

According to some embodiments, the first length L11 and the second length L22 may be substantially equal. In this way, the lengths through which signals transmitted to the two transistors Tr1, tr2 by the data line D pass are equal, that is, the electronic conduction path lengths are equal, so that the component characteristics of the two transistors Tr1, tr2 can be made uniform. According to some embodiments, when the first length L11 and the second length L22 are measured, the measurement positions of the first gate electrode GE1 and the second gate electrode GE2 may be the same corresponding positions. For example, the edge P1 of the first gate electrode GE1 may be the edge nearest to the touch signal line T, and the edge P2 of the second gate electrode GE2 may be the edge nearest to the same touch signal line T, but is not limited thereto.

According to some embodiments, the first length L11 and the second length L22 may be measured in the following manner. The semiconductor pattern S branches from the main portion SM into a first branch portion S1 and a second branch portion S2 via a branch position BP. The semiconductor pattern S has a first length, which may be a length from an edge P0 of the main portion SM to an edge P1 of the first gate electrode GE1 along the first branch portion S1. In detail, the first length of the semiconductor pattern S may be a sum of a length L0 of the main portion SM and a length L1 of the first branch portion S1 to an edge P1 of the first gate electrode GE1, that is, l0+l1. In addition, the semiconductor pattern S has a second length L2, and the second length L2 may be a length from an edge P0 of the main portion SM to an edge P2 of the second gate electrode GE2 along the second branch portion S2. In detail, the second length may be a sum of a length L0 of the main portion SM and a length L2 of the second branch portion S2 to an edge P2 of the second gate electrode GE2, that is, l0+l2.

In fig. 2, the edge P0 of the main portion SM may be substantially parallel to the data line D, and the edge furthest from the touch contact line T (or the edge furthest from the branching position BP). The first edge P1 of the first gate electrode GE1 and the second edge P2 of the second gate electrode GE2 may be close to the touch signal line T and located at two sides of the touch signal line T respectively.

As shown in fig. 2, the block E further includes a plurality of light shielding portions LS (not shown in fig. 1 for brevity) overlapping the gate electrode GE to prevent the light irradiation device from causing photo leakage of the semiconductor layer.

Next, fig. 3 shows a top view of the electronic device of fig. 1 with pixel electrodes disposed therein, according to some embodiments of the present disclosure. Fig. 4 shows a top view of a portion of a pixel electrode corresponding to block E' of fig. 3 and omitted, according to some embodiments of the present disclosure. Fig. 5-6 show schematic cross-sectional views of an electronic device corresponding to the cross-sectional lines AA 'and BB' of fig. 4, respectively, in accordance with some embodiments of the present disclosure.

Next, as shown in fig. 3, the electronic device 10 includes a plurality of pixel electrodes XE disposed on the substrate 100. In some embodiments, the pixel electrode XE may include more than two fingers XEA and one connection XEB. For example, in the embodiment of fig. 3, the pixel electrode XE includes one connection portion XEB and five finger portions XEA connected to the connection portion XEB. The finger XEA extends generally along the second direction y, e.g., parallel to the data line D. The connection portion XEB is electrically connected to the semiconductor pattern S. Thus, the light transmittance, contrast ratio and the like of the electronic device can be changed. In some embodiments, the pixel electrode XE may span two gate lines G. That is, in the upper view, the pixel electrode XE may overlap with two gate lines G.

For convenience of explanation, as shown in fig. 3, the pixel electrodes in different rows (row) and columns (column) can be defined by using the gate line G and the touch signal line T/data line D as coordinate axes. The direction of the row (row) is the first direction x and the direction of the column (column) is the second direction y. For example, as shown in fig. 3, the pixel electrodes at the bottom left are defined on the 1 st row and the 1 st column, and are denoted as XE (1, 1), and to the right (first direction +x), denoted as XE (2, 1), XE (3, 1), XE (4, 1), respectively. The upper left pixel electrode is defined on row 2 and column 1, and is therefore denoted as XE (1, 2), and to the right (first direction +x), as XE (2, 2), XE (3, 2), XE (4, 2), respectively. By block E' (corresponding to block E of fig. 1).

It should be noted that, for convenience of explanation of the positional relationship between the pixel electrodes, fig. 4 only shows the pixel electrode XE (2, 2) and the pixel electrode XE (3, 1) corresponding to the box E' of fig. 3, and is referred to as a first pixel electrode XE1 and a second pixel electrode XE2, respectively. In detail, the first pixel electrode XE (2, 2) is on the 2 nd column and the 2 nd row, the second pixel electrode XE (3, 1) is on the 3 rd column and the 1 st row, that is, the second pixel electrode XE (3, 1) is at the position of the adjacent column and the adjacent row of the first pixel electrode XE (2, 2), and the first pixel electrode XE (2, 2) and the second pixel electrode XE (3, 1) may be referred to as a diagonal direction arrangement. As shown in fig. 4, according to some embodiments, the same data line D may control transistors Tr1, tr2 of two adjacent columns (columns) via the semiconductor pattern S, and may further control pixel electrodes of the two adjacent columns. In detail, the same data line D may control the first pixel electrode XE1 and the second pixel electrode XE2 disposed diagonally.

As shown in fig. 4, the first pixel electrode XE1 and the second pixel electrode XE2 are provided on the first thin film transistor Tr1 and the second thin film transistor Tr2, respectively, and are provided substantially diagonally. In some embodiments, the first pixel electrode XE1 is electrically connected to the first branch portion S1, and the second pixel electrode XE2 is electrically connected to the second branch portion S2. In fig. 4, the first pixel electrode XE1 and the second pixel electrode XE2 are separated from each other by a touch signal line T.

Next, a cross-sectional view of a specific cross-section line will be drawn below. Fig. 5-6 are cross-sectional views along section lines AA 'and BB' of fig. 4, respectively. The cut line AA' is a section cut along the second branch portion S2 of the semiconductor pattern S toward the main portion SM of the semiconductor pattern S connected to the data line D. The section line BB' is a section cut along one gate line G. Note that the cross section BB' does not overlap the thin film transistor Tr, and thus the thin film transistor Tr is not shown in the cross section of fig. 5.

As shown in fig. 5-6, the substrate 100 is disposed as the bottom-most layer. The substrate 100 may be a hard substrate or a soft substrate, and is not limited. For example, the substrate 100 may include glass, quartz, sapphire (sapphire), ceramic, polyimide (PI), polycarbonate (PC), polyethylene terephthalate (polyethylene terephthalate, PET), polypropylene (PP), other suitable materials, or a combination of the foregoing, but is not limited thereto.

As shown in fig. 5-6, a buffer layer 200 is disposed on the substrate 100. The buffer layer 200 serves as a barrier layer to prevent alkali metal in the substrate 100 from diffusing into the upper film. In some embodiments, the buffer layer 200 may be a single layer or a multi-layer structure. The buffer layer 200 may include an organic material or an inorganic material, such as an organic silicon oxide compound, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, hafnium oxide, other suitable materials, or a combination of the foregoing, but is not limited thereto. In the embodiment of fig. 5-6, the buffer layer 200 is a bilayer structure of a nitride buffer layer 210 (e.g., comprising silicon nitride) and an oxide buffer layer 220 (e.g., comprising silicon oxide).

As shown in fig. 5, the light shielding portion LS is further disposed on the substrate 100 and covered by the buffer layer 200 to prevent the light leakage phenomenon. In some embodiments, the light shielding portion LS may include metal, black photoresist, black printing ink, black resin, or any other suitable light shielding material and color. In some embodiments, the formation of the light shielding portion LS is similar to that of the buffer layer 200, and will not be described herein.

As shown in fig. 5, the semiconductor pattern S is disposed on the buffer layer 200. In some embodiments, the semiconductor pattern S may include a doped region and a channel region. For example, the second branch portion S2 of the semiconductor pattern S includes a doped region S2D as a drain electrode, a doped region S2B, and a channel region S2C. The main portion SM of the semiconductor pattern S contains a doped region SMD as a source. The first branch portion S1 and the second branch portion S2 of the semiconductor pattern S may have similar structures and are not described herein.

In some embodiments, the semiconductor pattern S may include a semiconductor material, such as an elemental semiconductor, a compound semiconductor, an alloy semiconductor, other suitable materials, or a combination of the foregoing, but is not limited thereto, such as doped or undoped polysilicon (polycrystalline silicon), amorphous silicon (amorphous silicon). The elemental semiconductor may for example comprise silicon, germanium (germanium). The compound semiconductor may include, for example, gallium nitride (GaN), silicon carbide (silicon carbide), gallium arsenide (gallium arsenide), gallium phosphide (gallium phosphide), indium phosphide (indium phosphide), indium arsenide (indium arsenide), and/or indium antimonide (indium antimonide). The alloy semiconductor may include, for example, silicon germanium alloy (SiGe), gallium arsenide alloy (GaAsP), aluminum indium arsenide alloy (AlInAs), aluminum gallium arsenide alloy (AlGaAs), indium gallium arsenide alloy (GaInAs), indium gallium phosphide alloy (GaInP), and/or indium gallium arsenide phosphide alloy (GaInAsP), or the like. The semiconductor pattern S may also be a metal oxide, such as indium gallium zinc oxide (indium gallium zinc oxide, IGZO).

In some embodiments, the dopants of the doped regions S2B, S2D and SMD may comprise dopants of the first conductivity type (n-type) or the second conductivity type (p-type), such as nitrogen, arsenic, phosphorus, antimony ions or boron, aluminum, gallium, indium, boron trifluoride ions (BF ³⁺ ) But is not limited thereto. In some embodiments, the doping concentrations of the doped region S2B and the doped region S2D may be different, for example, the doped region S2B may be a lightly doped region and the doped region S2D may be a heavily doped region.

As shown in fig. 5-6, a gate dielectric layer 300 is disposed on the buffer layer 200. In detail, as shown in fig. 5, the gate dielectric layer 300 covers the semiconductor pattern S. The gate dielectric layer 300 may be a single layer or multiple layers.

In some embodiments, the gate dielectric layer 300 may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, or any other suitable dielectric material, or a combination thereof, but is not limited thereto. The material of the high-k dielectric material may comprise metal oxide, metal nitride, metal silicide, transition metal oxideMetal nitrides, transition metal silicides, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, and the like, but are not limited thereto. For example, the high-k dielectric material may be LaO, alO, zrO, tiO, ta ₂ O ₅ 、Y ₂ O ₃ 、SrTiO ₃ (STO)、BaTiO ₃ (BTO)、BaZrO、HfO ₂ 、HfO ₃ 、HfZrO、HfLaO、HfSiO、HfSiON、LaSiO、AlSiO、HfTaO、HfTiO、HfTaTiO、HfAlON、(Ba,Sr)TiO ₃ (BST)、Al ₂ O ₃ Other high-k dielectric materials, other suitable materials, or combinations thereof, but are not limited thereto.

In some embodiments, the gate dielectric layer 300 may be formed by a method similar to that of the buffer layer 200, which is not described herein.

In some embodiments, gate lines (e.g., first gate lines G1 and/or second gate lines G2) are disposed on the gate dielectric layer 300 as shown in fig. 5-6. In some embodiments, the first gate line G1 includes a first gate electrode GE1 and a first gate extension line GT1; the second gate line G2 includes a second gate electrode GE2 and a second gate extension line GT2. In detail, as shown in fig. 5, the second gate electrode GE2 is spaced from the channel region S2C in the semiconductor pattern S by the gate dielectric layer 300, and the second gate electrode GE2 is disposed corresponding to the channel region S2C. As shown in fig. 6, the first gate extension line GT1 covers the gate dielectric layer 300.

In some embodiments, the first gate line G1 and the second gate line G2 may include conductive materials, such as one or more metals, metal nitrides, conductive metal oxides, suitable materials, or combinations thereof. The metal may include molybdenum (molybden), tungsten (tungsten), titanium (titanium), tantalum (tantalum), platinum (platinum), or hafnium (hafnium), but is not limited thereto. The metal nitride may include molybdenum nitride (molybdenum nitride), tungsten nitride (tungsten nitride), titanium nitride (titanium nitride), and tantalum nitride (tantalum nitride), but is not limited thereto. The conductive metal oxide may include ruthenium metal oxide (ruthenium oxide) and indium tin metal oxide (indium tin oxide), but is not limited thereto. The conductive material constituting the first gate line G1 and the second gate line G2 may be a single layer or a plurality of layers.

As shown in fig. 5, an interlayer dielectric layer 400 is disposed on the gate dielectric layer 300. In some embodiments, the interlayer dielectric layer 400 may be a single-layer or multi-layer structure. The interlayer dielectric layer 400 may include silicon nitride, silicon dioxide, or silicon oxynitride, a suitable material, or a combination thereof, but is not limited thereto. Interlayer dielectric 400 may be a bilayer structure of a nitride dielectric layer 410 (e.g., comprising silicon nitride) and an oxide dielectric layer 420 (e.g., comprising silicon oxide).

In some embodiments, the interlayer dielectric layer 400 may be formed by a method similar to that of the buffer layer 200, and will not be described here.

As shown in fig. 5, in some embodiments, the first and fourth vias V1 and V4 are formed in the gate dielectric layer 300 and the interlayer dielectric layer 400 by a patterning process (e.g., a photolithography process and an etching process) to expose the semiconductor pattern S. Then, the conductive material is filled into the first via V1 and the fourth via V4, and the conductive material is patterned by a patterning process to form the conductive layer C. The conductive layer C includes a conductive pattern M, a touch signal line T and a data line D. The conductor layer C may be a single layer or a plurality of layers.

As shown in fig. 4 and 5, the conductive pattern M may be electrically connected to the semiconductor pattern S via the first via V1, for example, to the second branch portion S2 of the semiconductor pattern S. The second pixel electrode XE2 may be electrically connected to the conductive pattern M via the second via V2. In detail, the second pixel electrode XE2 may be electrically connected to the conductive pattern M via the second and third via holes V2 and V3. The third guide hole V3 may be disposed within the second guide hole V2. The conductive pattern M may serve as a drain electrode. The cross-sectional view of fig. 5 is illustrated by the position of the second pixel electrode XE2, but the first via V1, the second via V2, and the third via V3 at the position of the first pixel electrode XE1 are similarly connected, and will not be described herein. That is, the left conductive pattern M in fig. 4 may be electrically connected to the semiconductor pattern S via another first via V1, for example, to the first branch portion S1 of the semiconductor pattern S. The first pixel electrode XE1 may be electrically connected to the conductive pattern M via another second via V2. According to some embodiments, as shown in fig. 4, in the upper view, the first and second vias V1 and V2 may be disposed between the first and second gate extension lines GT1 and GT 2. The data line D may be electrically connected to the semiconductor pattern S via the fourth via V4, for example, the main portion SM of the semiconductor pattern S.

In some embodiments, the conductive material may comprise a metal, a metal alloy, other materials with good conductivity, such as copper, aluminum, molybdenum, tungsten, gold, chromium, nickel, platinum, titanium, iridium, rhodium, alloys thereof, combinations thereof, or a three-layer structure of molybdenum aluminum molybdenum (Mo/Al/Mo) or titanium aluminum titanium (Ti/Al/Ti), but is not limited thereto.

On the other hand, according to some embodiments, the conductive pattern M, the touch signal line T and the data line D may be formed simultaneously in the same process step. That is, the conductive pattern M, the touch signal line T and the data line D may be the same layer. Therefore, the number of photomasks required when the touch signal lines T and the data lines D are arranged on different film layers can be reduced, and the manufacturing cost is further reduced.

As shown in fig. 5 and 6, a planarization layer 500 is disposed on the interlayer dielectric layer 400. In some embodiments, the planarization layer 500 is disposed on the conductor layer C. In detail, the planarization layer 500 is disposed on the data line D and the touch signal line T. In detail, the planarization layer 500 is disposed on the conductive pattern M, the touch signal line T and the data line D. In some embodiments, the planarization layer 500 includes an organic or inorganic dielectric material, such as, but not limited to, a photosensitive resin, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, aluminum oxide, suitable materials, combinations thereof.

As shown in fig. 5-6, a common electrode 600 is disposed on the planarization layer 500. In some embodiments, the common electrode 600 may include a conductive material, such as Indium Tin Oxide (ITO), tin oxide (SnO), indium Zinc Oxide (IZO), indium Gallium Zinc Oxide (IGZO), indium Tin Zinc Oxide (ITZO), antimony Tin Oxide (ATO), antimony Zinc Oxide (AZO), a combination of the above, or any other suitable conductive oxide material.

In some embodiments, the second via V2 is formed in the planarization layer 500 (facilitating subsequent electrical connection with the conductive pattern M), and the common electrode material is formed substantially conformally along the planarization layer 500 by a method similar to the gate line G, and the common electrode 600 is formed by removing the common electrode material in the second via V2 and a portion of the common electrode material located on the planarization layer 500 by a patterning process. That is, the second via V2 is surrounded by the planarization layer 500.

As shown in fig. 5-6, an insulating layer 700 is disposed on the common electrode 600. In some embodiments, the insulating layer 700 may include a dielectric material similar to that described above, and will not be described again. In some embodiments, the insulating material is conformally formed substantially along the common electrode 600, the planarization layer 500 and the second via V2 by a method similar to the buffer layer 200, and the insulating material in the second via V2 and on the conductive pattern M is removed by a patterning process to form a third via V3 in the insulating layer 700 (facilitating subsequent electrical connection with the conductive pattern M). That is, the third via V3 is surrounded by the common electrode 600. Specifically, the second via V2 is defined by the planarization layer 500 and the common electrode 600, and the third via V3 is defined by the common electrode 600 and the insulating layer 700.

As shown in fig. 5 to 6, the pixel electrode XE is disposed on the insulating layer 700. In some embodiments, the pixel electrode XE may include materials similar to those of the common electrode 600, which are not described herein. In some embodiments, the pixel electrode XE is formed by conformally forming a pixel electrode material on the insulating layer 700 and on the third via V3 by a method similar to the common electrode 600, and patterning the pixel electrode material by a patterning process. In the embodiment of fig. 5, the pixel electrode XE2 covers the entire third via V3. In the embodiment of fig. 6, a plurality of pixel electrodes XE2 are spaced apart from one another. Thus, as shown in fig. 5, the planarization layer 500 includes the second via V2, and the pixel electrode XE2 may be electrically connected to the conductive pattern M through the second via V2.

In some embodiments, a display medium, a color filter layer, another substrate, etc. (not shown) may be disposed on the insulating layer 700. The display medium may be, for example, a liquid crystal.

Fig. 7 shows a circuit diagram of an electronic device, according to some embodiments of the present disclosure. In fig. 7, the electronic device 10 includes a display region 11 and a non-display region 12. In the display region 10, a plurality of gate lines (G-1, G0, G1 … G8 are sequentially shown from top to bottom) and a plurality of data lines (D1, D2, D3 … D6 are sequentially shown from left to right) are disposed, which are substantially staggered. In the display area 11, a plurality of pixel units X are disposed at intersections of the gate lines and the data lines. As shown in fig. 7, the data lines D1 and D2 surround two pixel units X with the gate lines G0 and G1. The pixel units X can be set as the pixel units R, G and B according to the requirement. In some embodiments, the pixel units R, G, and B may emit light of the same or different colors, for example, but not limited to, the pixel units R, G, and B may emit red light, green light, and blue light, respectively. For example, as shown in fig. 7, between the gate lines G0 and G1, the pixel units R, G, and B are repeatedly arranged in order from the data line D1.

Further, the pixel unit R, G, B shown in fig. 7 may correspond to the pixel electrode in the foregoing figures, or may include the pixel electrode in the foregoing figures. The top view of fig. 4 may be corresponded by block F in the circuit diagram of fig. 7. As can be seen from fig. 7, the gate line G1 is connected to the pixel unit B, and the gate line G2 is connected to the pixel unit R.

As shown in fig. 7, the traces CKH1, CKH2, CKH3 are disposed in the non-display area 12, and may be disposed in a Multiplexer (MUX) which is provided with a switch for controlling the source signal source S [ n ] and the source signal source S [ n+1] to the data lines D1, D2, … and D6. For simplicity of illustration, the gate lines, data lines, and source signal sources are shown in specific numbers, and those skilled in the art will understand that the numbers and circuit configurations may be modified according to actual requirements in practical applications.

In fig. 7, the source signal source S [ n ] can control the data line D1, the data line D3 and the data line D5 in a time sequence manner by the trace CKH1, the trace CKH2 and the trace CKH3 respectively; the source signal source S [ n+1] can control the data line D2, the data line D4 and the data line D6 in a time sequence manner by the trace CKH1, the trace CKH2 and the trace CKH 3. That is, one source signal line may control the circuit architecture of three data lines, i.e., MUX 3. Furthermore, with the above description, one data line can control two rows (columns) of pixels, so that the source signal source is halved. Thus, the same effect of MUX6 can be achieved by the circuit architecture of MUX 3. Thus, the space of an Outer Lead Bond (OLB) area can be reduced, the space of the non-display area 12 can be saved, and the number of source integrated circuits (source ICs) can be reduced.

In summary, according to some embodiments of the present disclosure, the semiconductor pattern overlaps with the two gate electrodes, which may be used to form two transistors, and may further electrically connect the two pixel electrodes through the two branches of the same semiconductor pattern, respectively. According to some embodiments, two pixel electrodes may be disposed diagonally. According to some embodiments, the number of data lines is halved by connecting two thin film transistors to the same data line, and the number of light shielding regions and source integrated circuits is greatly reduced, so that the outer frame space for arranging the integrated circuits is reduced. Furthermore, according to some embodiments, by staggering the touch signal lines and the data lines in parallel, the number of masks used in the process steps can be reduced, and the problem of reduced aperture ratio can be reduced, thereby reducing power consumption.

Although embodiments of the present disclosure and their advantages have been disclosed above, it should be understood that various changes, substitutions and alterations can be made herein by those skilled in the art without departing from the spirit and scope of the disclosure. Features of the embodiments of the present disclosure may be mixed and matched at will without departing from the spirit or conflict of the present disclosure. Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, and those of skill in the art will appreciate from the present disclosure that any process, machine, manufacture, composition of matter, means, methods and steps which may be practiced in the practice of the embodiments described herein or with substantially the same result. Accordingly, the scope of the present disclosure includes such processes, machines, manufacture, compositions of matter, means, methods, or steps. The scope of the present disclosure is defined by the scope of the appended claims. Not all of the objects, advantages, features of the disclosure are required to be achieved by any one embodiment or claim of the disclosure.

Claims

1. An electronic device, comprising:

a first gate line having a first gate extension line and a first gate electrode protruding from the first gate extension line;

a second gate line adjacent to the first gate line, wherein the second gate line has a second gate extension line and a second gate electrode protruding from the second gate extension line;

a data line crossing the first gate line and the second gate line in a top view of the electronic device; and

and a semiconductor pattern electrically connected to the data line, wherein the semiconductor pattern is disposed between the first gate extension line and the second gate extension line, and the semiconductor pattern overlaps the first gate electrode and overlaps the second gate electrode.

2. The electronic device according to claim 1, wherein the semiconductor pattern comprises:

a main portion;

a first branch portion connected to the main portion; and

a second branch portion connected to the main portion.

3. The electronic device of claim 2, wherein the first branch portion and the first gate electrode overlap each other, and the second branch portion and the second gate electrode overlap each other.

4. The electronic device of claim 3, wherein the semiconductor pattern has a first length from an edge of the main portion along the first branch portion to an edge of the first gate electrode, and a second length from the edge of the main portion along the second branch portion to an edge of the second gate electrode, the first length and the second length being substantially equal.

5. The electronic device of claim 2, further comprising a first pixel electrode electrically connected to the first branch portion; and a second pixel electrode electrically connected to the second branch portion, wherein the first pixel electrode and the second pixel electrode are disposed diagonally.

6. The electronic device of claim 5, further comprising a conductive pattern, wherein the conductive pattern is electrically connected to the second branch portion via a first via, wherein the second pixel electrode is electrically connected to the conductive pattern via a second via, wherein the first via and the second via are disposed between the first gate extension line and the second gate extension line.

7. The electronic device of claim 1, further comprising a touch signal line and a planarization layer, wherein the planarization layer is disposed on the data line and the touch signal line.

8. The electronic device of claim 7, further comprising a pixel electrode and a conductive pattern, wherein the planarization layer comprises a second via, wherein the pixel electrode is electrically connected to the conductive pattern through the second via.

9. The electronic device of claim 8, further comprising a conductive layer, wherein the conductive layer comprises the data line, the conductive pattern, and the touch signal line.

10. The electronic device of claim 1, further comprising a touch signal line, wherein in the top view, the touch signal line overlaps the semiconductor pattern.