CN116759398A - 封装元件及其制作方法 - Google Patents

封装元件及其制作方法 Download PDF

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Publication number
CN116759398A
CN116759398A CN202210268844.9A CN202210268844A CN116759398A CN 116759398 A CN116759398 A CN 116759398A CN 202210268844 A CN202210268844 A CN 202210268844A CN 116759398 A CN116759398 A CN 116759398A
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China
Prior art keywords
layer
conductive
package
bridge chip
chip
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CN202210268844.9A
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Inventor
张简上煜
林南君
徐宏欣
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Powertech Technology Inc
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Powertech Technology Inc
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Publication of CN116759398A publication Critical patent/CN116759398A/zh
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Abstract

本发明提供一种封装元件及其制作方法。封装元件包括基板、多个导电柱、重布线层、至少一桥接芯片、至少两主动芯片、封装体以及底部填充层。导电柱并排设置于基板上，重布线层设置于导电柱上，且桥接芯片设置于基板与重布线层之间。主动芯片设置于重布线层上，桥接芯片耦接于主动芯片之间，且封装体设置于重布线层上，并围绕主动芯片。底部填充层设置于两相邻导电柱之间以及导电柱中的一个与桥接芯片之间。

Description

封装元件及其制作方法
技术领域
本发明有关于一种封装元件及其制作方法，特别是一种利用桥接芯片耦接主动芯片的封装元件及其制作方法。
背景技术
近年来，为了整合各种功能，以满足使用需求，已发展出将多个主动芯片密封在同一个封装元件中。然而，随着主动芯片的功能越多或运算能力愈高，耦接主动芯片之间的互连(interconnection)结构的需求也越高。有鉴于此，如何提升主动芯片之间的互连效率并降低封装元件的制作成本以及工艺复杂度实为业界的一大课题。
发明内容
本发明的一实施例提供一种封装元件，其包括基板、多个第一导电柱、重布线层、至少一桥接芯片、至少两主动芯片、封装体以及第一底部填充层。第一导电柱并排设置于基板上，重布线层设置于第一导电柱上，且桥接芯片设置于基板与重布线层之间。主动芯片设置于重布线层上，桥接芯片耦接于主动芯片之间，且封装体设置于重布线层上，并围绕主动芯片。第一底部填充层设置于第一导电柱中的相邻两个之间以及第一导电柱中的一个与桥接芯片之间。
本发明的另一实施例提供一种封装元件的制作方法。首先，于第一载板上形成重布线层。然后，于重布线层上设置至少两主动芯片，并于重布线层上形成封装体，其中封装体围绕主动芯片。接着，将重布线层、主动芯片以及封装体转移到第二载板上，以露出重布线层相对于主动芯片的表面。随后，于重布线层相对于主动芯片的表面上形成多个第一导电柱。于重布线层上设置至少一桥接芯片。然后，移除该第二载板，并将第一导电柱接合于一基板。
附图说明
图1至图7为本发明一实施例的封装元件的制作方法流程示意图。
图8为本发明另一实施例的封装元件的剖面示意图。
附图标号：
1,2:封装元件
12,42:载板
14,44:离型层
16:重布线层
16s:表面
18,20,22:介电层
18a,20a,22a:穿孔
24,26,28:导电层
24a,26a:走线
28a:区块
30,34,52:导电凸块
32,32a,32b:主动芯片
32m,50m:主体部
32n,50n:绝缘层
32p:输入/输出焊垫
32s:背面
36,54,62:底部填充层
38:封装体
40,56:半成品结构
42s:上表面
46,48:导电柱
46a:柱状部
46b:接合部
50:桥接芯片
50p:焊垫
58:封装结构
60:基板
64:加固件
66:焊球
68:金属盖
70:散热膏
CG:芯片群组
H1,H2:高度
ND:法线方向
具体实施方式
下文结合具体实施例和附图对本申请的内容进行详细描述，且为了使本申请的内容更加清楚和易懂，下文各附图为可能为简化的示意图，且其中的元件可能并非按比例绘制。并且，附图中的各元件的数量与尺寸仅为示意，并非用于限制本申请的范围。
以下实施例中所提到的方向用语，例如：上、下、左、右、前或后等，仅是参考附加图式的方向。因此，使用的方向用语是用来说明并非用来限制本发明。必需了解的是，为特别描述或图示之元件可以此技术人士所熟知之各种形式存在。
当元件或膜层被称为在另一元件或另一膜层上或之上时，应被了解为所述的元件或膜层是直接位于另一元件或另一膜层上，也可以是两者之间存在有其他的元件或膜层(非直接)。但相反地，当元件或膜层被称为“直接”在另一个元件或膜层“上”时，则应被了解两者之间不存在有插入的元件或膜层。
于文中提及一元件“电性连接”或“耦接”另一元件时，可包括“元件与另一元件之间可更存在其它元件而将两者电性连接”的情况，或是包括“元件与另一元件之间未存有其它元件而直接电性连接”的情况。若于文中提及一元件“直接电性连接”或“直接耦接”另一元件时，则指“元件与另一元件之间未存有其它元件而直接电性连接”的情况。
请参考图1至图7。图1至图7为本发明一实施例的封装元件的制作方法流程示意图，图7为本发明一实施例的封装元件的剖面示意图。图1至图7所显示的结构可分别为在制作封装元件的不同过程中的部分结构，且可省略部分膜层或元件，但不限于此。如图1所示，首先提供载板12，其中载板12上可具有离型层14。然后，于离型层14上形成重布线层16。载板12可用以承载形成于其上的膜层或元件，载板12可例如包括玻璃、晶圆基板、金属或其他合适的支撑材料，但不限于此。离型层14可用以在完成后续步骤之后将载板12与其上所形成的元件(例如，图3所示的封装结构40)分离。离型层14的解离方式可例如包括光解离或其他合适的方式。离型层14可例如包括聚乙烯(polyethylene,PE)、聚对苯二甲酸乙二酯(polyethylene terephthalate,PET)、环氧树脂(epoxy)、定向拉伸聚丙烯(Orientedpolypropylene,OPP)或其他合适的材料，但不限于此。
重布线层16可包括至少一层介电层以及至少一层导电层。在图1的实施例中，重布线层16以包括三层介电层18、20、22以及三层导电层24、26、28为例，但不以此为限。介电层18、导电层24、介电层20、导电层26、介电层22以及导电层28可依序形成于离型层14上。介电层18可具有多个穿孔18a，且导电层24可设置于介电层18上，并包括多条走线24a，延伸到穿孔18a中。介电层20可设置于导电层24上，并具有多个穿孔20a，暴露出对应的走线24a。导电层26可设置于介电层20上，并包括多条走线26a，延伸到穿孔20a中，以与对应的走线24a耦接。介电层22可设置于导电层26上，并具有多个穿孔22a，且导电层28可包括多个区块28a，设置于对应的穿孔22a中。在一些实施例中，导电层的层数以及介电层的层数可依据实际需求作调整。
需说明的是，由于重布线层16可在离型层14(或载板12)上尚未形成其他元件之前形成在离型层14(或载板12)的平坦表面上，因此可降低制作重布线层16的复杂度，从而可缩小重布线层16中同一层导电层的走线间距(例如，细节距(fine pitch))。举例来说，重布线层16的走线间距可例如为2微米(μm)到10微米。
如图1所示，在形成重布线层16之后，可选择性于导电层28的区块28a上形成多个导电凸块30，以助于与后续设置的主动芯片(例如，图2的主动芯片32)接合与耦接。导电凸块30可例如包括多层结构。多层结构可例如包括铜(copper)、镍(nickel)、金(gold)、其他合适的材料或上述的组合，但不限于此。
如图2所示，在形成导电凸块30之后，可于重布线层16上设置至少两个主动芯片32。在图2的实施例中，主动芯片32的数量可例如为多个，且主动芯片32可区分为至少两个芯片群组CG，分别对应所欲形成的封装元件(例如图7所示的封装元件1)，但不限于此。需说明的是，由于重布线层16并非形成在模塑材料上，而是载板12上，因此重布线层16不会有明显的翘曲，故不需对重布线层16的布局作位移补偿，从而可提升制作效率。
在图2的实施例中，每个主动芯片32可例如包括多个导电凸块34，以助于与重布线层16接合，但不限于此。举例来说，主动芯片32可还包括主体部32m、多个输入/输出焊垫32p以及绝缘层32n，其中输入/输出焊垫32p可设置于主体部32m与绝缘层32n之间，且绝缘层32n具有多个开口，暴露出对应的输入/输出焊垫32p。导电凸块34可分别形成在对应的输入/输出焊垫32p上。并且，主动芯片32的导电凸块34可以面朝下(face down)的方式通过覆晶(flip chip)接合工艺与重布线层16上的导电凸块30接合，使得主动芯片32可耦接重布线层16。导电凸块34以及导电凸块30之间可还包括金属焊料(图中未显示)，用以接合导电凸块34与导电凸块30，金属焊料可例如包括锡合金焊料或其他合适的材料，但不限于此。
主动芯片32可例如包括电源管理芯片(power management integrated circuit,PMIC)、微机电系统(micro-electro-mechanical-system,MEMS)芯片、特殊应用集成电路芯片(application-specific integrated circuit,ASIC)、动态随机存取存储器(dynamicrandom access memory,DRAM)芯片、静态随机存取存储器(static random accessmemory,SRAM)芯片、高频宽存储器(high bandwidth memory,HBM)芯片、系统芯片(systemon chip,SoC)、高效能运算(high performance computing,HPC)芯片或其他类似的主动芯片，但不限于此。在图2的实施例中，芯片群组CG可包括同质或异质的主动芯片32a与主动芯片32b。当主动芯片32a与主动芯片32b为异质时，主动芯片32a与主动芯片32b可例如分别为系统芯片与高频宽存储器芯片，但不限于此。举例来说，一个芯片群组CG可包括一颗主动芯片32a以及四颗主动芯片32b，但不限于此。在本文中，主动芯片32可指包括主动元件的芯片，主动元件32可包括晶体管、二极管、集成电路、光电元件或其他具有增益的合适元件，但不限于此。在本文中，芯片也可以称为晶粒，但不限于此。耦接也可称为电性连接，但不限于此。导电凸块34可例如包括多层结构。导电凸块34可例如包括铜、镍、锡(tin)、银(silver)、其他合适的材料、上述至少两者的合金或上述的组合，但不限于此。
在一些实施例中，由于重布线层16可在设置主动芯片32之前形成，因此可在设置主动芯片32之前，选择性对重布线层16进行自动光学检测(automated opticalinspection,AOI)及/或开路与短路测试(open/short test,O/S test)，以确保重布线层16的品质，如此可避免或减少因重布线层16的不良所造成的芯片损失或浪费。在一些实施例中，自动光学检测及/或开路与短路测试可在完成重布线层16之后进行或在形成重布线层16的过程中重复进行多次。
如图2所示，在设置完主动芯片32之后，可于重布线层16上形成封装体38，以形成半成品结构40，其中封装体38可至少横向围绕主动芯片32，用以保护主动芯片32以及主动芯片32与重布线层16之间的接合。举例来说，封装体38可通过模封(molding)工艺形成在主动芯片32之间以及主动芯片32的背面32s上，用以将主动芯片32密封在重布线层16上。封装体38可例如包括模塑化合物(molding compound)或其他合适的封装材料，但不限于此。
需说明的是，由于重布线层16是在设置主动芯片32以及需在高温环境进行并降温的模封工艺之前形成，因此主动芯片32可在尚未遇到高温差的环境下设置于重布线层16上，如此可降低重布线层16受到高温差所产生的翘曲影响，从而简化工艺的复杂度。
在一些实施例中，可选择性对封装体38进行减薄工艺，移除封装体38位于主动芯片32上的部分，以露出主动芯片32的背面32s，从而可有助于主动芯片32的散热。减薄工艺可例如包括化学机械研磨(chemical mechanical polishing,CMP)工艺、机械研磨(mechanical grinding)、刻蚀(etching)或其他合适的工艺，但不限于此。
在一些实施例中，如图2所示，在将主动芯片32设置于重布线层16上与形成封装体38的步骤之间，可选择性于主动芯片32与重布线层16之间填入底部填充层36，以助于强化主动芯片32与重布线层16之间的接合度，从而降低导电凸块30与导电凸块34之间的断裂。底部填充层36可例如包括毛细填充胶(capillary underfill,CUF)或其他合适的填充材料，但不限于此。底部填充层36可例如通过点胶工艺形成，但不限于此。
如图3所示，可将包含有重布线层16、主动芯片32以及封装体38的半成品结构40转移到载板42上，以露出重布线层16相对于主动芯片32的表面16s。举例来说，在形成封装体38之后，可将主动芯片32的背面32s以及封装体38相对于重布线层16的表面与载板42贴合，以降低半成品结构40的翘曲。载板42与主动芯片32之间以及载板42与封装体38之间可例如设置有离型层44。离型层44的材料可例如相同或类似离型层14的材料，在此不多赘述。然后，移除载板12。移除载板12的方式可例如包括对离型层14照射光线，以降低离型层14的粘着力，进而移除载板12，但不限于此。
如图4所示，接着将半成品结构40上下翻转，使得重布线层16相对于主动芯片32的表面16s朝上，而主动芯片32的背面32s朝下。然后于重布线层16相对于主动芯片32的表面16s上形成多个并排设置的导电柱46，使得每个导电柱46可耦接对应的走线24a。并且，导电柱46可通过重布线层16耦接主动芯片32。导电柱46可例如通过沉积工艺搭配光刻与刻蚀工艺、电镀工艺搭配刻蚀工艺或其他适合的工艺所形成，但不限于此。在图4的实施例中，导电柱46可例如为多层结构，但不限于此。举例来说，导电柱46可包括柱状部46a以及接合部46b，其中柱状部46a可例如包括铜、铝、镍、其他合适的导电材料、上述至少两者的合金或上述的组合，接合部46b可例如包括锡银合金、其他合适的材料或上述的组合，但不限于此。
在一些实施例中，可选择性于重布线层16相对于主动芯片32的表面16s上形成多个导电柱48，以助于与后续设置的桥接芯片接合。导电柱48可通过重布线层16耦接对应的主动芯片32。导电柱48的高度可小于或远小于导电柱46的高度。在一些实施例中，导电柱48可于形成导电柱46之前或之后形成。导电柱48可例如通过沉积工艺搭配光刻与刻蚀工艺、电镀工艺搭配刻蚀工艺或其他适合的工艺所形成，但不限于此。
如图5所示，在形成导电柱46之后，可以面朝下(face down)的方式通过芯片倒装焊封装工艺于重布线层16上设置至少一个桥接芯片50。换言之，桥接芯片50可具有多个导电凸块52，且在进行接合时，以导电凸块52面对重布线层16且以桥接芯片50的背面50b朝向上的方式将桥接芯片50接合于重布线层16上。导电凸块52可例如包括多层结构。导电凸块52可例如包括铜、镍、锡、银、其他合适的材料、上述至少两者的合金或上述的组合，但不限于此。在图5的实施例中，桥接芯片50可例如还包括主体部50m、多个焊垫50p以及绝缘层50n，其中焊垫50p设置于主体部50m上，绝缘层50n设置于焊垫50p与主体部50m上并可具有多个开口，分别暴露出对应的焊垫50p，且导电凸块52分别形成于对应的焊垫50p上，以助于与重布线层16接合，但不限于此。
在图5的实施例中，桥接芯片50的导电凸块52可与设置于重布线层16上的导电柱48接合，从而耦接重布线层16。借此，单一桥接芯片50可通过重布线层16耦接不同的主动芯片32。导电凸块52以及导电柱48之间可还包括金属焊料(图中未显示)，用以接合导电凸块52与导电柱48，金属焊料可例如包括锡合金焊料或其他合适的材料，但不限于此。桥接芯片50可例如包括多条走线(图中未显示)，其中走线间距(例如，细节距)可例如为约1微米到2微米或次微米等级，但不限于此。由于桥接芯片50的走线间距可小于重布线层16的走线间距，因此通过桥接芯片50耦接不同的主动芯片32，可提升主动芯片32之间的互连密度，从而降低主动芯片32之间的信号传输路径或时间，并提升信号传输效率。在此情况下，重布线层16的走线间距可不需达到细节距，以简化工艺复杂度并降低制作成本。并且，通过走线间距较小的桥接芯片50，重布线层16的层数可降低，从而可降低制作过程中的翘曲，从而降低工艺复杂度。
在一些实施例中，主动芯片32的两相邻导电凸块(如图2所示的导电凸块34)之间的间距可小于或等于桥接芯片50的两相邻导电凸块52之间的间距。当导电凸块34之间的间距等于导电凸块52之间的间距时，重布线层16中耦接的导电凸块52与导电凸块34的走线(如图1所示的走线24a与走线26a)以及区块(如图1所示的区块28a)在垂直于载板42的上表面42s的法线方向ND上可彼此对齐，但不限于此。在一些实施例中，两相邻导电凸块52之间的间距可小于两相邻导电柱46之间的间距。图6所示的桥接芯片50的数量可为多个，但不限于此。桥接芯片50的数量可例如依据芯片群组CG中的主动芯片32以及芯片群组CG的数量而定。
在一些实施例中，桥接芯片50可选择性还包括被动元件，例如电阻、电容、电感或其他类似的元件。在一些实施例中，桥接芯片50也可选择性还包括主动元件。在此情况下，桥接芯片50中的主动元件与主动芯片32的主动元件可由不同的半导体工艺技术节点所制作出，举例来说，桥接芯片50中的主动元件的密度大于主动芯片32的主动元件的密度，但不限于此。在一些实施例中，桥接芯片50在法线方向ND上的厚度可例如为约10微米到100微米或更高。
如图5所示，在设置完桥接芯片50之后，可于桥接芯片50与重布线层16之间形成底部填充层54，以保护桥接芯片50与重布线层16之间的接合与耦接，从而形成半成品结构56。在图5的实施例中，底部填充层54可延伸到桥接芯片50中的两相邻导电凸块52之间。底部填充层54的材料与形成方式可例如相同或类似底部填充层36的材料与形成方式，因此在此不多赘述。
需说明的是，如图5所示，为了避免桥接芯片50的背面50b在后续将封装结构接合至基板上时碰撞到基板而造成桥接芯片50的破裂，导电柱46的高度H1可大于桥接芯片50的背面50b的高度H2(即，桥接芯片50的背面50b与重布线层16的表面16s之间的间距)。进一步而言，导电柱46的高度H1在经过回焊(reflow)之后仍可高于桥接芯片50的背面50b的高度H2。举例来说，高度H1与高度H2的差异可大于或等于50微米，但不限于此。
如图6所示，在形成半成品结构56之后，可移除载板42。移除载板12的方式可例如包括对离型层44照射光线，以降低离型层44的粘着力，进而移除载板42，但不限于此。然后，可对半成品结构56进行单一化工艺(singulation process)，以形成至少一个封装结构58。在图6的实施例中，半成品结构56可包括至少两个芯片群组CG，因此单一化工艺可将不同的芯片群组CG分隔开，且将对应不同芯片群组CG的桥接芯片50与导电柱46分隔开，以形成至少两个封装结构58。单一化工艺可例如包括切割工艺或其他合适的工艺。
如图7所示，在单一化工艺之后，可将封装结构58上下翻转，并将封装结构58的导电柱46设置于基板60上。导电柱46可将封装结构58耦接并接合于基板60上。然后，于封装结构58的两相邻导电柱46之间以及导电柱46与桥接芯片50之间形成底部填充层62，以形成封装元件1。需说明的是，由于重布线层16与基板60之间仅需设置单层的底部填充层62，因此可简化封装元件1的制作步骤以及工艺复杂度。基板60可例如包括封装基板、电路板或其他合适的基板。底部填充层62可延伸到封装结构58封装体38的侧壁上，并可强化封装结构58与基板60之间的接合度。在图7的实施例中，底部填充层62可例如延伸到基板60与桥接芯片50之间。底部填充层62的材料与形成方式可例如相同或类似底部填充层36或底部填充层54的材料与形成方式，因此在此不多赘述。
在一些实施例中，基板60上可设置有加固件64，且加固件64可例如围绕封装结构58，并与底部填充层62分隔开。加固件64可例如包括金属。在一些实施例中，基板60下方可选择性设置有焊球66，以助于封装元件1进一步与其他元件的耦接与接合，但不限于此。
需说明的是，在图7的封装元件1中，由于重布线层16设置于主动芯片32与导电柱46以及桥接芯片50之间，因此主动芯片32可通过重布线层16同时耦接到具有不同间距的导电柱46以及桥接芯片50的焊垫。此外，主动芯片32可通过重布线层16以及导电柱46耦接至基板60，相较于通过硅中介层(silicon interposer)耦接到基板60，导电柱46及桥接芯片50的制作成本可明显低于硅中介层的制作成本，因此可有效地降低封装元件1的制作成本。
图8为本发明另一实施例的封装元件的剖面示意图。如图8所示，本实施例的封装元件2与图7所示的封装元件1的区别在于，封装元件2可还包括金属盖68，取代图7的加固件64，并设置于封装结构58以及基板60上。金属盖68可例如覆盖并围绕封装结构58，以保护封装结构58。金属盖68可例如为一体成形的结构，但不限于此。在一些实施例中，封装元件2可选择性还包括散热膏70，设置于主动芯片32的背面32s上。散热膏70可例如直接接触主动芯片32与金属盖68，以助于对主动芯片32散热。散热膏70可例如在设置金属盖68之前涂布于主动芯片32的背面上，但不限于此。
综合上述，在本发明的封装元件中，通过桥接芯片耦接不同的主动芯片，可提升主动芯片之间的互连密度，从而提升信号传输效率。并且，由于与桥接芯片并排设置的导电柱的高度可大于桥接芯片的背面的高度，因此在将封装结构接合至基板上时，可避免桥接芯片碰撞到基板，从而降低桥接芯片的破裂。另外，重布线层可设置于主动芯片与导电柱以及桥接芯片之间，因此主动芯片可通过重布线层耦接到具有不同间距的导电柱以及桥接芯片的焊垫，并可通过导电柱耦接至基板，进而可降低封装元件的制作成本。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求保护范围所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (21)

1.一种封装元件，其特征在于，包括：
一基板；
多个第一导电柱，并排设置于所述基板上；
一重布线层，设置于所述多个第一导电柱上；
至少一桥接芯片，设置于所述基板与所述重布线层之间；
至少两主动芯片，设置于所述重布线层上，且所述至少一桥接芯片耦接于所述至少两主动芯片之间；
一封装体，设置于所述重布线层上，并围绕所述至少两主动芯片；以及
一第一底部填充层，设置于所述多个第一导电柱中的相邻两个之间以及所述多个第一导电柱中的一个与所述至少一桥接芯片之间。
2.根据权利要求1所述的封装元件，其特征在于，所述第一底部填充层设置于所述基板与所述至少一桥接芯片之间。
3.根据权利要求1所述的封装元件，其特征在于，还包括一第二底部填充层，设置于所述至少一桥接芯片与所述重布线层之间。
4.根据权利要求3所述的封装元件，其特征在于，所述至少一桥接芯片包括多个导电凸块，面对所述重布线层设置。
5.根据权利要求4所述的封装元件，其特征在于，所述第二底部填充层设置于所述多个导电凸块中的相邻两个之间。
6.根据权利要求4所述的封装元件，其特征在于，所述多个导电凸块中的相邻两个之间的间距小于所述多个第一导电柱中的相邻两个之间的间距。
7.根据权利要求1所述的封装元件，其特征在于，还包括多个第二导电柱，设置于所述至少一桥接芯片与所述重布线层之间。
8.根据权利要求1所述的封装元件，其特征在于，还包括一第三底部填充层，设置于所述重布线层与所述至少两主动芯片之间。
9.根据权利要求1所述的封装元件，其特征在于，所述多个第一导电柱中的一个的高度大于所述至少一桥接芯片的背面与所述重布线层相对于所述至少两主动芯片的表面之间的间距。
10.一种封装元件的制作方法，其特征在于，包括：
于一第一载板上形成一重布线层；
于所述重布线层上设置至少两主动芯片；
于所述重布线层上形成一封装体，其中所述封装体围绕所述至少两主动芯片；
将所述重布线层、所述至少两主动芯片以及所述封装体转移到一第二载板上，以露出所述重布线层相对于所述至少两主动芯片的表面；
于所述重布线层相对于所述至少两主动芯片的所述表面上形成多个第一导电柱；
于所述重布线层上设置至少一桥接芯片；
移除所述第二载板；以及
将所述多个第一导电柱接合于一基板。
11.根据权利要求10所述的封装元件的制作方法，其特征在于，于将所述多个第一导电柱接合于所述基板之后，所述制作方法还包括于所述多个第一导电柱之间以及所述多个第一导电柱中的一个与所述至少一桥接芯片之间形成一第一底部填充层。
12.根据权利要求11所述的封装元件的制作方法，其特征在于，所述第一底部填充层设置于所述基板与所述至少一桥接芯片之间。
13.根据权利要求10所述的封装元件的制作方法，其特征在于，于设置所述至少一桥接芯片与移除所述第二载板之间，所述制作方法还包括于所述至少一桥接芯片与所述重布线层之间形成一第二底部填充层。
14.根据权利要求10所述的封装元件的制作方法，其中所述多个第一导电柱中的一个的高度大于所述至少一桥接芯片的背面与所述重布线层相对于所述至少两主动芯片的所述表面之间的间距。
15.根据权利要求10所述的封装元件的制作方法，其特征在于，所述至少一桥接芯片包括多个导电凸块，且设置所述至少一桥接芯片包括以所述多个导电凸块面对所述重布线层的方式将所述至少一桥接芯片接合于所述重布线层上。
16.根据权利要求15所述的封装元件的制作方法，其特征在于，所述多个导电凸块中的相邻两个之间的间距小于所述多个第一导电柱中的相邻两个之间的间距。
17.根据权利要求10所述的封装元件的制作方法，其特征在于，于设置所述至少一桥接芯片之前，所述制作方法还包括于所述重布线层相对于所述至少两主动芯片的所述表面上形成多个第二导电柱。
18.根据权利要求17所述的封装元件的制作方法，其特征在于，所述多个第二导电柱中的一个的高度小于所述多个第一导电柱中的一个的高度。
19.根据权利要求10所述的封装元件的制作方法，其特征在于，形成所述封装体包括对所述封装体进行减薄工艺，以露出所述至少两主动芯片的背面。
20.根据权利要求10所述的封装元件的制作方法，其特征在于，于形成所述重布线层与设置所述至少两主动芯片之间，所述制作方法还包括对所述重布线层进行自动光学检测。
21.根据权利要求10所述的封装元件的制作方法，其特征在于，于设置所述至少两主动芯片与形成所述封装体之间，所述制作方法还包括于所述重布线层与所述至少两主动芯片之间形成一第三底部填充层。
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