CN116758866A

CN116758866A - Pixel circuit, driving method thereof and display panel

Info

Publication number: CN116758866A
Application number: CN202310511400.8A
Authority: CN
Inventors: 王宁波; 李博资; 王发永; 张春雷; 胡凤章
Original assignee: Kunshan Govisionox Optoelectronics Co Ltd; Hefei Visionox Technology Co Ltd; Guangzhou Guoxian Technology Co Ltd
Current assignee: Kunshan Govisionox Optoelectronics Co Ltd; Hefei Visionox Technology Co Ltd; Guangzhou Guoxian Technology Co Ltd
Priority date: 2023-05-06
Filing date: 2023-05-06
Publication date: 2023-09-15

Abstract

The invention discloses a pixel circuit, a driving method thereof and a display panel, wherein the pixel circuit comprises a driving module, a first voltage writing module, a storage module, a precharge module, a second voltage writing module and a light emitting module, wherein the precharge module is used for transmitting data voltage on a data line to a first end of the storage module in a precharge stage and transmitting a first power voltage transmitted on a first power line to a second end of the storage module; the second voltage writing module is used for enabling the second end of the storage module to be communicated with the first end of the driving module in the first initialization stage, and the first end of the storage module is communicated with the control end of the driving module. The voltage difference between the first end and the control end of the driving module can be close to or kept constant in the first initialization stage and the light-emitting stage, the drift degree of the threshold voltage of the driving transistor included in the driving module is reduced, the hysteresis effect of the driving transistor is further reduced, and the picture flicker phenomenon is improved.

Description

Pixel circuit, driving method thereof and display panel

Technical Field

The present invention relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display panel.

Background

With the continuous development of display technology, an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel has been widely used in the field of optoelectronic display by virtue of excellent characteristics of self luminescence, high brightness, wide viewing angle and the like.

A display panel generally includes a plurality of pixel circuits, wherein the pixel circuits include driving transistors that generate driving signals to drive light emitting elements to emit light for display. In the prior art, the OLED display panel emits light by current driving, so that the characteristics of the driving transistor affect the gray-scale brightness of the display, thereby reducing the display quality.

Disclosure of Invention

The invention provides a pixel circuit, a driving method thereof and a display panel, which are used for improving the brightness difference of the display panel in the display process, so as to improve the display quality.

According to an aspect of the present invention, there is provided a pixel circuit including: the device comprises a driving module, a first voltage writing module, a storage module, a precharge module, a second voltage writing module and a light emitting module;

the precharge module is connected with the data line and the storage module at least, and is used for transmitting the data voltage on the data line to the first end of the storage module in the precharge stage, and the first power voltage transmitted on the first power line is transmitted to the second end of the storage module;

The second voltage writing module is at least connected with the first end of the driving module and the storage module, and is used for enabling the second end of the storage module to be communicated with the first end of the driving module in a first initialization stage, and the first end of the storage module is communicated with the control end of the driving module;

the first voltage writing module is used for transmitting the data voltage to the driving module in the data writing stage;

the driving module and the light-emitting module are connected between the first power line and the second power line, and the driving module is used for driving the light-emitting module to emit light in a light-emitting stage;

wherein the precharge phase is located before the first initialization phase.

The pre-charging module comprises a first charging unit and a second charging unit; the control end of the first charging unit is connected with the first scanning line, the first end of the first charging unit is connected with the data line, the second end of the first charging unit is connected with the first end of the storage module, the first end of the second charging unit is connected with the first power line, the second end of the second charging unit is connected with the second end of the storage module, and the control end of the second charging unit is connected with the second scanning line;

optionally, the first charging unit includes a first transistor, a gate of the first transistor is a control end of the first charging unit, a first pole of the first transistor is a first end of the first charging unit, and a second pole of the first transistor is a second end of the first charging unit;

The second charging unit comprises a second transistor, the grid electrode of the second transistor is the control end of the second charging unit, the first end of the second transistor is the first end of the second charging unit, and the second end of the second transistor is the second end of the second charging unit;

optionally, a voltage dividing module is further included on a connection path between the first charging unit and the data line, and the voltage dividing module includes at least one diode; the on-state voltage drop of the voltage dividing module is larger than the absolute value of the threshold voltage of the driving module; the voltage dividing module is conducted in the pre-charging stage;

optionally, the diode comprises a transistor with a gate and a first pole shorted.

Optionally, the second voltage writing module includes a first voltage writing unit; the first end of the first voltage writing unit is connected with the second end of the storage module, the second end of the first voltage writing unit is connected with the first end of the driving module, and the control end of the first voltage writing unit is connected with the third scanning line;

the first end of the storage module is connected with the control end of the driving module, or the second voltage writing module further comprises a second voltage writing unit, the first end of the second voltage writing unit is connected with the first end of the storage module, the second end of the second voltage writing unit is connected with the control end of the driving module, and the control end of the second voltage writing unit is connected with the fourth scanning line;

Optionally, the first voltage writing unit includes a third transistor, a gate of the third transistor is a control end of the first voltage writing unit, a first pole of the third transistor is a first end of the first voltage writing unit, and a second pole of the third transistor is a second end of the first voltage writing unit;

the second voltage writing unit comprises a fourth transistor, the gate of the fourth transistor is the control end of the second voltage writing unit, the first pole of the fourth transistor is the first end of the second voltage writing unit, and the second pole of the fourth transistor is the second end of the second voltage writing unit;

the memory module comprises a capacitor, a first electrode of the capacitor is a first end of the memory module, and a second electrode of the capacitor is a second end of the memory module.

Optionally, the first scan line, the second scan line, the third scan line and the fourth scan line are used for transmitting scan signals,

in the precharge stage, the first charging unit and the second charging unit are turned on, the first voltage writing unit is turned off, and the second voltage writing unit is turned off;

in the first initialization stage, the first voltage writing unit is conducted, and the second voltage writing unit is conducted; the first charging unit and the second charging unit are both turned off;

In the data writing stage and the light-emitting stage, the first charging unit is turned off, the second charging unit is turned on, the first voltage writing unit is turned off, and the second voltage writing unit is turned on;

optionally, when the display brightness value of the display panel is smaller than the preset value, the at least one first display period includes a precharge phase, a first initialization phase, a data writing phase, and a light emitting phase.

The pixel circuit further comprises a first initialization module connected with the driving module, wherein the first initialization module is used for transmitting a first initialization voltage to a control end of the driving module in a first initialization stage when the display brightness value of the display panel is smaller than a preset value;

and/or the first initialization module is used for transmitting the first initialization voltage to the control end of the driving module in a second initialization stage when the display brightness value of the display panel is larger than a preset value;

optionally, when the display brightness value of the display panel is greater than a preset value, at least one second display period includes a second initialization phase, a data writing phase and a light emitting phase;

optionally, in a second initialization stage when the display brightness value of the display panel is greater than a preset value, the first charging unit is turned off, the second charging unit is turned on, the first voltage writing unit is turned off, and the second voltage writing unit is turned on;

Optionally, the control end of the first initialization module is connected with the seventh scan line, the first end of the first initialization module is connected with the first initialization signal line, and the second end of the first initialization module is connected with the control end of the driving module.

Optionally, the pixel circuit further includes a compensation module, the compensation module is connected between the second end and the control end of the driving module, and the control end of the compensation module is connected with the fifth scan line; the control end of the first voltage writing module is connected with the sixth scanning line, the first end of the first voltage writing module is connected with the data line, and the second end of the first voltage writing module is connected with the first end of the driving module;

optionally, the pixel circuit further includes a first light emission control unit and a second light emission control unit;

the first light-emitting control unit is connected between the first power line and the first end of the driving module, the second light-emitting control unit is connected between the second end of the driving module and the first end of the light-emitting module, the second end of the light-emitting module is connected with the second power line, and the control end of the first light-emitting control unit and the control end of the second light-emitting control unit are both connected with the light-emitting control signal line;

optionally, the pixel circuit further includes a second initialization module, a control end of the second initialization module is connected to the eighth scan line, a first end of the second initialization module is connected to the second initialization signal line, and a second end of the second initialization module is connected to the first end of the light emitting module.

According to another aspect of the present invention, there is provided a driving method of a pixel circuit, the pixel circuit including a driving module, a first voltage writing module, a storage module, a precharge module, a second voltage writing module, a first initialization module and a light emitting module, a first end of the precharge module being connected to a data line, a second end of the precharge module being connected to a first power line, a third end of the precharge module being connected to the first end of the storage module, a fourth end of the precharge module being connected to the second end of the storage module, a first end of the second voltage writing module being connected to the first end of the storage module, a second end of the second voltage writing module being connected to the second end of the storage module, a third end of the second voltage writing module being connected to a control end of the driving module, a fourth end of the second voltage writing module being connected to the first end of the driving module, the driving module and the light emitting module being connected between the first power line and the second power line;

the driving method of the pixel circuit includes:

in the precharge stage, controlling the precharge module to transmit the data voltage on the data line to the first end of the memory module, and transmitting the first power supply voltage transmitted on the first power supply line to the second end of the memory module;

In a first initialization stage, a second end of the storage module is communicated with a first end of the driving module, and the first end of the storage module is communicated with a control end of the driving module;

in the data writing stage, the first voltage writing module is controlled to transmit the data voltage transmitted on the data line to the driving module so that the data voltage is written into the control end of the driving module;

in the light-emitting stage, the driving module is controlled to drive the light-emitting module to emit light.

Optionally, the precharge module includes a first charging unit and a second charging unit, the control end of the first charging unit is connected with the first scan line, the first end of the first charging unit is connected with the data line, the second end of the first charging unit is connected with the first end of the storage module, the first end of the second charging unit is connected with the first power line, the second end of the second charging unit is connected with the second end of the storage module, and the control end of the second charging unit is connected with the second scan line; the second voltage writing module comprises a first voltage writing unit and a second voltage writing unit, the first end of the first voltage writing unit is connected with the second end of the storage module, the second end of the first voltage writing unit is connected with the first end of the driving module, and the control end of the first voltage writing unit is connected with the third scanning line; the first end of the second voltage writing unit is connected with the first end of the storage module, the second end of the second voltage writing unit is connected with the control end of the driving module, and the control end of the second voltage writing unit is connected with the fourth scanning line;

In the precharge phase, the step of controlling the precharge module to transmit the data voltage on the data line to the first terminal of the memory module and to transmit the first power voltage transmitted on the first power line to the second terminal of the memory module includes:

in the pre-charging stage, the first charging unit is controlled to be conducted in response to a first scanning signal on a first scanning line so as to transmit a data voltage on a data line to a first end of the memory module, and the second charging unit is controlled to be conducted in response to a second scanning signal on a second scanning line so as to transmit a first power voltage transmitted on a first power line to a second end of the memory module;

in the first initialization stage, the step of communicating the second end of the storage module with the first end of the driving module, and the first end of the storage module with the control end of the driving module includes:

in the first initialization stage, controlling the second voltage writing unit to respond to the fourth scanning signal on the fourth scanning line to conduct, and transmitting the data voltage to the first end of the memory module; simultaneously controlling the first voltage writing unit to respond to the third scanning signal on the third scanning line to conduct, and writing the voltage of the second end of the storage module into the first end of the driving module;

Optionally, the pixel circuit further includes a compensation module, the compensation module is connected between the second end and the control end of the driving module, and the control end of the compensation module is connected with the fifth scan line; the connection path of the first charging unit and the data line also comprises a voltage dividing module, and the voltage dividing module comprises at least one diode; the on-state voltage drop of the voltage dividing module is larger than the absolute value of the threshold voltage of the driving module;

the pixel circuit also comprises a first initialization module which is connected with the driving module; when the display brightness value of the display panel is smaller than the preset value, in the pre-charging stage, the step of controlling the pre-charging module to transmit the data voltage on the data line to the first end of the storage module and transmitting the first power voltage transmitted on the first power line to the second end of the storage module comprises the following steps:

in the pre-charging stage, the first charging unit is controlled to be conducted in response to a first scanning signal on a first scanning line so as to transmit a data voltage on a data line to a first end of the memory module through the voltage dividing module, and the second charging unit is controlled to be conducted in response to a second scanning signal on a second scanning line so as to transmit a first power voltage transmitted on a first power line to a second end of the memory module;

the first initialization stage is used for controlling the first initialization module to transmit a first initialization voltage to the control end of the driving module, and controlling the second voltage writing unit to respond to the conduction of a fourth scanning signal on a fourth scanning line and transmit the first initialization voltage to the first end of the storage module; simultaneously controlling the first voltage writing unit to respond to the third scanning signal on the third scanning line to conduct, and writing the voltage of the second end of the storage module into the first end of the driving module;

in the data writing stage, the step of controlling the first voltage writing module to transmit the data voltage transmitted on the data line to the driving module so that the data voltage is written to the control end of the driving module includes:

in the data writing stage, the first voltage writing module is controlled to transmit the data voltage transmitted on the data line to the control end of the driving module through the compensation module.

According to another aspect of the present invention, there is provided a display panel including the pixel circuit provided by any of the embodiments of the present invention.

According to the technical scheme provided by the embodiment of the invention, the precharge module and the second voltage writing module are arranged, the precharge module is controlled to be conducted in the precharge stage before the first initialization stage so as to write the data voltage into the first end of the memory module, and meanwhile, the first power supply voltage is written into the second end of the memory module, so that the voltage difference between two ends of the memory module is the difference between the first power supply voltage and the data voltage; and the driving module is reset by the voltage difference in the first initialization stage, so that the voltage difference between the first end and the control end of the driving module is close to or kept constant in the first initialization stage and the light-emitting stage, the drift degree of the threshold voltage of the driving transistor included in the driving module is reduced, the hysteresis effect of the driving transistor is further reduced, the brightness of the display panel applying the pixel circuit is kept consistent when the picture is switched, and the picture flicker phenomenon is improved, so that the display quality is improved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a hysteresis effect characteristic of a prior art driving transistor;

fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

Fig. 10 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 12 is a driving timing diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 13 is a timing diagram illustrating another embodiment of a driving scheme of a pixel circuit;

fig. 14 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

FIG. 15 is a timing diagram illustrating another embodiment of a driving scheme of a pixel circuit;

FIG. 16 is a timing diagram illustrating another embodiment of a driving scheme of a pixel circuit;

fig. 17 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present invention;

fig. 18 is a schematic structural diagram of a display panel according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

As described in the background art, the characteristics of the driving transistors in the prior art affect the gray scale brightness of the display, and the characteristics of the driving transistors are inconsistent in different stages, so that brightness differences occur in different frames, and the display quality is reduced. The inventors have found that the cause of the above problem is related to the hysteresis effect of the driving transistor. When the existing pixel circuit works, the voltage difference of the gate and the source of the driving transistor is different in an initialization stage and a light-emitting stage, so that the characteristics of the driving transistor drift to generate a hysteresis effect. Fig. 1 is a schematic diagram of a characteristic curve of a hysteresis effect of a driving transistor in the prior art, referring to fig. 1, an abscissa is a gate-source voltage difference of the driving transistor, an ordinate is a driving current, a curve 1 is a characteristic curve of the driving transistor in a light emitting stage, a curve 2 is a characteristic curve of the driving transistor in an initialization stage, and characteristics of the driving transistor drift due to misalignment of the characteristic curves of the driving transistor in the initialization stage and the light emitting stage caused by the hysteresis effect of the driving transistor. Even if the voltage written in the gate of the driving transistor is the same in the next frame and the current frame, the voltage of the first electrode (source electrode) is different due to the influence of hysteresis effect, so that the voltage difference of the gate and source of the driving transistor is different, the generated driving current is also different, the light-emitting brightness of the light-emitting element is different, the display brightness of the display panel is unstable, and the flicker phenomenon occurs. Flicker is more pronounced especially at low frequencies and low brightness.

In view of the foregoing, embodiments of the present invention provide a pixel circuit to improve the display quality of a display panel to which the pixel circuit is applied. Fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, referring to fig. 2, the pixel circuit includes a driving module 110, a first voltage writing module 120, a storage module 130, a precharge module 140, a second voltage writing module 150, and a light emitting module 170; the precharge module 140 is connected to at least the data line and the memory module 130, and the precharge module 140 is configured to transmit the data voltage Vdata on the data line to the first terminal a of the memory module 130 and the first power voltage VDD transmitted on the first power line L1 to the second terminal b of the memory module during the precharge phase. For example, a first terminal of the precharge module 140 is connected to the data line, a second terminal of the precharge module 140 is connected to the first power line L1, a third terminal of the precharge module 140 is connected to the first terminal a of the memory module 130, a fourth terminal of the precharge module 140 is connected to the second terminal b of the memory module 130, the precharge module 140 is turned on during the precharge phase, the data voltage Vdata on the data line is written to the first terminal a of the memory module 130, and the first power voltage VDD transmitted on the first power line L1 is written to the second terminal b of the memory module 130;

The second voltage writing module 150 is at least connected to the first end S of the driving module 110 and the storage module 130, for example, the first end of the second voltage writing module 150 is connected to the first end a of the storage module 130, the second end of the second voltage writing module 150 is connected to the second end b of the storage module 130, the third end of the second voltage writing module 150 is connected to the control end G of the driving module 110, the fourth end of the second voltage writing module 150 is connected to the first end S of the driving module 110, the second voltage writing module 150 is configured to make the second end b of the storage module 130 communicate with the first end of the driving module 110 in the first initialization stage, and the first end a of the storage module 130 communicates with the control end G of the driving module 110. So configured, a voltage difference across the memory module 130 may be applied to the first terminal S and the control terminal G of the driving module 110 in the first initialization stage so that the gate-source voltage differences of the driving transistors in the driving module 110 in the first initialization stage and the light emitting stage are close to or identical to each other, so that the characteristics of the driving transistors in the driving module 110 in the first initialization stage and the light emitting stage are close to or identical to each other.

The first voltage writing module 120 is configured to transmit the data voltage Vdata on the data line to the driving module 110 in the data writing stage, so that the data voltage Vdata is written to the control terminal G of the driving module 110; the driving module 110 and the light emitting module 170 are connected between the first power line L1 and the second power line L2, and the driving module 110 is used for driving the light emitting module 170 to emit light in a light emitting stage.

Specifically, the first power line L1 is used for transmitting a first power voltage VDD, the second power line L2 is used for transmitting a second power voltage VSS, one of the first power voltage VDD and the second power voltage VSS is a high voltage, and the other is a low voltage. The driving module 110 and the light emitting module 170 are connected between the first power line L1 and the second power line L2, and the driving module 110 is configured to drive the light emitting module 170 to emit light in a light emitting phase of the display period according to voltages of the control terminal G and the first terminal S thereof when a connection path between the first power line L1 and the second power line L2 is turned on. Wherein, a light emitting control module 180 may be disposed on the connection path to ensure light emitting reliability.

The pixel circuit provided in this embodiment at least includes a precharge phase, a first initialization phase, a data writing phase and a light emitting phase, wherein the precharge phase is located before the first initialization phase in a display period.

Taking the pixel circuit shown in fig. 2 as an example, in the precharge phase, the precharge module 140 is turned on, the data voltage Vdata on the data line is transmitted to the first terminal a of the memory module 130 through the first terminal and the third terminal of the precharge module 140, the first power voltage VDD on the first power line L1 is transmitted to the second terminal b of the memory module 130 through the second terminal and the fourth terminal of the precharge module 140, and therefore, the data voltage Vdata and the first power voltage VDD are respectively stored on the memory module 130.

In the first initialization stage, the second voltage writing module 150 is turned on between the first terminal and the third terminal, and at the same time, the second terminal and the fourth terminal of the second voltage writing module 150 are also turned on. The data voltage Vdata at the first terminal a of the memory module 130 is transmitted to the control terminal G of the driving module 110 through the first terminal and the third terminal of the second voltage writing module 150, and the first power voltage VDD at the second terminal b of the memory module 130 is transmitted to the first terminal S of the driving module 110 through the second terminal and the fourth terminal of the second voltage writing module 150. In the first initialization stage, the voltage difference between the first terminal S and the control terminal G of the driving module 110 is VDD-Vdata.

In the data writing stage, the first voltage writing module 120 is turned on, and the data voltage Vdata is written to the control terminal G of the driving module 110 through the first voltage writing module 120.

In the light emitting stage, the connection path between the first power line L1 and the second power line L2 is turned on, and the driving module 110 generates a driving current according to the voltages of the control terminal G and the first terminal S thereof, so as to drive the light emitting module 170 to emit light. At this time, the voltage at the first terminal S of the driving module 110 is the first power voltage VDD, the voltage at the control terminal G is Vdata, and the voltage difference between the first terminal S of the driving module 110 and the control terminal G is VDD-Vdata.

In this embodiment, since the voltage difference between the first terminal S and the control terminal G of the driving module 110 is close to or the same as that of the first initialization stage and the light emitting stage, the characteristics of the driving transistor included in the driving module 110 will not change, so that the characteristic curves of the driving transistor can overlap or nearly overlap (in the data writing stage, the driving transistor performs data writing in a diode state, and the characteristic curves thereof will not deviate) in the first initialization stage and the light emitting stage, thereby improving the flicker phenomenon.

According to the technical scheme provided by the embodiment of the invention, the precharge module and the second voltage writing module are arranged, the precharge module is controlled to be conducted in the precharge stage before the first initialization stage to write the data voltage into the first end of the memory module, and meanwhile, the first power supply voltage is written into the second end of the memory module, so that the voltage difference between two ends of the memory module is close to or equal to the difference between the first power supply voltage and the data voltage; and the driving module is reset by the voltage difference in the first initialization stage, so that the voltage difference between the first end and the control end of the driving module is close to or kept constant in the first initialization stage and the light-emitting stage, the drift degree of the threshold voltage of the driving transistor included in the driving module is reduced, the hysteresis effect of the driving transistor is further reduced, the brightness of the display panel applying the pixel circuit is kept consistent when the picture is switched, and the picture flicker phenomenon is improved, so that the display quality is improved.

In this embodiment, the precharge phase is located in a blank phase between the first initialization phase of the n-th frame and the light-emitting phase of the n-1 th frame, n being an integer greater than 1. That is, the precharge phase is located after the light-emitting phase of the current frame and before the first initialization phase of the next frame, and the precharge phase is located in a blank phase between two adjacent frames, so that the precharge phase does not occupy the time of other phases in one frame.

Fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and referring to fig. 3, on the basis of the above technical solution, optionally, the precharge module 140 includes a first charging unit 1401 and a second charging unit 1402; the control end of the first charging unit 1401 is connected to the first scan line, the first end of the first charging unit 1401 is connected to the data line, the second end of the first charging unit 1401 is connected to the first end a of the memory module 130, the first end of the second charging unit 1402 is connected to the first power line L1, the second end of the second charging unit 1402 is connected to the second end b of the memory module 130, and the control end of the second charging unit 1402 is connected to the second scan line.

The first scan line is used for transmitting a first scan signal S1, and the second scan line is used for transmitting a second scan signal S2. In the precharge phase, the first charging unit 1401 is turned on in response to the first scan signal S1 to transmit the data voltage on the data line to the first terminal a of the memory module 130; the second charging unit 1402 is configured to be turned on in response to the second scan signal S2 to transmit the first power voltage VDD on the first power line L1 to the second terminal b of the memory module 130.

Fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and referring to fig. 4, on the basis of the above technical solution, the pixel circuit optionally further includes a compensation module 190. The compensation module 190 is connected between the second end D and the control end G of the driving module 110, and the control end of the compensation module 190 is connected to the fifth scan line.

The control end of the first voltage writing module 120 is connected to the sixth scan line, the first end of the first voltage writing module 120 is connected to the data line, and the second end of the first voltage writing module 120 is connected to the first end S of the driving module 110.

With continued reference to fig. 4, optionally, a voltage dividing module 210 is further included on the connection path between the first charging unit 1401 and the data line, and the on-state voltage drop of the voltage dividing module 210 is greater than the absolute value of the threshold voltage of the driving module 110. In the present embodiment, the voltage dividing module 210 is configured to be turned on in the precharge phase, so that the voltage written at the first terminal a of the memory module 130 is the difference between the data voltage Vdata and the on-state voltage drop of the voltage dividing module 210, so that the driving module 110 can write the data voltage Vdata in the data writing phase.

Optionally, the voltage divider module 210 includes at least one diode. Fig. 5 is a schematic diagram of another pixel circuit according to an embodiment of the present invention, and fig. 5 schematically illustrates a case where the voltage dividing module 210 includes two diodes, and referring to fig. 5, the first diode DO1 and the second diode DO2 are connected in series between the data line and the first charging unit 1401 to increase a voltage drop between the data line and the first charging unit 1401. Fig. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and referring to fig. 6, a diode includes a transistor with a gate and a first electrode shorted. The diode included in the voltage dividing module 210 may be formed of a transistor, and the gate of the transistor may be shorted to the first electrode to form a diode connection structure, which may have the same technical effect as the structure shown in fig. 5.

Fig. 7 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, referring to fig. 7, based on the above technical solutions, optionally, the second voltage writing module 150 includes a first voltage writing unit 1501, a first end of the first voltage writing unit 1501 is connected to a second end b of the memory module 130, a second end of the first voltage writing unit 1501 is connected to a first end S of the driving module 110, and a control end of the first voltage writing unit 1501 is connected to a third scan line.

Specifically, the third scan line is configured to transmit the third scan signal S3, the first terminal of the first voltage writing unit 1501 is used as the second terminal of the second voltage writing module 150, and the second terminal of the first voltage writing unit 1501 is used as the fourth terminal of the second voltage writing module 150; the first terminal of the second voltage writing module 150 and the third terminal of the second voltage writing module 150 are directly connected such that the first terminal a of the memory module 130 is connected to the control terminal G of the driving module 110. In the first initialization stage, the first charging unit 1401 is turned off in response to the first scan signal S1, the second charging unit 1402 is turned off in response to the second scan signal S2, and the voltage difference across the memory module 130 is VDD-Vdata. The first voltage writing unit 1501 is turned on in response to the third scan signal S3, the first power voltage VDD stored at the second terminal b of the memory module 130 is transmitted to the first terminal S of the driving module 110 through the first voltage writing unit 1501, and the voltage difference between the first terminal S and the control terminal G of the driving module 110 is VDD-Vdata. Therefore, the voltage difference between the first end S and the control end G of the driving module 110 is the same or similar to the voltage difference between the first initialization stage and the light-emitting stage, so as to reduce the drift degree of the threshold voltage of the driving module 110, effectively reduce the hysteresis effect, and improve the problem of inconsistent brightness, thereby improving the display quality.

Fig. 8 is a schematic structural diagram of another pixel circuit according to the embodiment of the present invention, referring to fig. 8, based on the above technical solutions, optionally, the second voltage writing module 150 further includes a second voltage writing unit 1502, a first end of the second voltage writing unit 1502 is connected to the first end a of the memory module 130, a second end of the second voltage writing unit 1502 is connected to the control end G of the driving module 110, and a control end of the second voltage writing unit 1501 is connected to the fourth scan line. The second voltage writing unit 1502 is configured to be turned on in response to the fourth scan signal S4 transmitted on the fourth scan line in the first initialization stage, and transmit the voltage stored at the first terminal a of the memory module 130 to the control terminal G of the driving module 110

The fourth scan line is used for transmitting a fourth scan signal S4. A first end of the first voltage writing unit 1501 serves as a second end of the second voltage writing module 150, and a second end of the first voltage writing unit 1501 serves as a fourth end of the second voltage writing module 150; the first terminal of the second voltage writing unit 1502 serves as the first terminal of the second voltage writing module 150, and the second terminal of the second voltage writing unit 1502 serves as the third terminal of the second voltage writing module 150.

Optionally, in the precharge phase, the first and second charging units 1401 and 1402 are turned on, the first voltage writing unit 1501 is turned off, and optionally, the second voltage writing unit 1502 is turned off.

Alternatively, in the first initialization stage, the first voltage writing unit 1501 is turned on, and both the first charging unit 1401 and the second charging unit 1402 are turned off; optionally, the second voltage writing unit 1502 is turned on.

In the data writing stage and the light emitting stage, the first charging unit 1401 is turned off, the second charging unit 1401 is turned on, the first voltage writing unit 1501 is turned off, and optionally, the second voltage writing unit 1502 is turned on.

Optionally, when the display brightness value (Display Brightness Value, DBV) of the display panel is less than the preset value, corresponding to the low-light mode, the at least one first display period includes a precharge phase, a first initialization phase, a data writing phase, and a light emitting phase.

Fig. 9 is a schematic structural diagram of another pixel circuit provided in this embodiment of the present invention, specifically, a structural diagram of a device made of a part of the blocks of the pixel circuit shown in fig. 8, referring to fig. 9, based on the above technical scheme, optionally, a first charging unit 1401 includes a first transistor M1, a gate of the first transistor M1 is a control end of the first charging unit 1401, and is connected to a first scan line, a first end of the first transistor M1 is a first end of the first charging unit 1401, and is connected to a data line, specifically, may be connected to the data line via a voltage dividing module 210, and a second end of the first transistor M1 is a second end of the first charging unit 1401, and is connected to a first end a of the storage module 130; the second charging unit 1402 includes a second transistor M2, a gate of the second transistor M2 is a control end of the second charging unit 1402, and is connected to the second scan line, a first pole of the second transistor M2 is a first end of the second charging unit 1402, and is connected to the first power line L1, a second pole of the second transistor M2 is a second end of the second charging unit 1402, and is connected to the second end b of the memory module 130.

The first voltage writing unit 1501 includes a third transistor M3, a gate of the third transistor M3 is a control terminal of the first voltage writing unit 1501, a first pole of the third transistor M3 is a first terminal of the first voltage writing unit 1501, and is connected to the second terminal b of the memory module 130, and a second pole of the third transistor M3 is a second terminal of the first voltage writing unit 1501, and is connected to the first terminal S of the driving module 110; the second voltage writing unit 1502 includes a fourth transistor M4, wherein a gate of the fourth transistor M4 is a control terminal of the second voltage writing unit 1502, a first terminal of the fourth transistor M4 which is the second voltage writing unit 1502 is connected to the first terminal a of the memory module 130, and a second terminal of the fourth transistor M4 which is the second voltage writing unit 1502 is connected to the control terminal G of the driving module 110; the memory module 130 includes a capacitor C, a first terminal a of the memory module 130, and a second terminal b of the memory module 130.

In the present embodiment, the scan signals transmitted by the first scan line, the second scan line, the third scan line, and the fourth scan line satisfy the following conditions: in the precharge phase, the first transistor M1 and the second transistor M2 are turned on, and the third transistor M3 and the fourth transistor M4 are turned off; in the first initialization stage, the first transistor M1 and the second transistor M2 are turned off, and the third transistor M3 and the fourth transistor M4 are turned on; in the data writing stage, the fourth transistor M4 and the second transistor M2 remain turned on, so that the capacitor C can store the voltage of the control terminal G of the driving module 110, and the first transistor M1 and the third transistor M3 are turned off; in the light emitting stage, the fourth transistor M4 and the second transistor M2 remain on, and the first transistor M1 and the third transistor M3 are both off.

With continued reference to fig. 9, the pixel circuit further includes a first initialization module 161 connected to the driving module 110, for example, the first initialization module 161 is connected to the control terminal G of the driving module 110. The first initialization module 161 is configured to transmit a first initialization voltage Vref1 to the control terminal G of the driving module 110 in a first initialization stage when the display brightness value (Display Brightness Value, DBV) of the display panel is less than a preset value. When the DBV is lower than the preset value, the data voltage Vdata is higher, the driving transistor in the driving module 110 is in a sub-threshold on state, and the gate-source voltage difference of the driving transistor in the driving module 110 is smaller than the threshold voltage Vth5.

The first initialization module 161 is configured to transmit a first initialization voltage to the control terminal G of the driving module 110 in a first initialization stage when the display brightness value of the display panel is less than a preset value. Alternatively, in the first initialization stage, the first initialization module 161 may not be operated, i.e. turned off, without transmitting the first initialization voltage to the control terminal G of the driving module 110.

Optionally, the first initialization module 161 is configured to transmit the first initialization voltage to the control terminal G of the driving module 110 in a second initialization stage when the display brightness value of the display panel is greater than a preset value.

Optionally, when the display brightness value of the display panel is greater than a preset value, the at least one second display period includes a second initialization phase, a data writing phase, and a light emitting phase. This may correspond to not having a precharge phase.

Optionally, in a second initialization stage when the display luminance value of the display panel is greater than a preset value, the first charging unit 1401 is turned off, the second charging unit 1402 is turned on, the first voltage writing unit 1501 is turned off, and optionally, the second voltage writing unit 1502 is turned on.

Specifically, when the display brightness value of the display panel is smaller than the preset value, in the precharge phase, the first charging unit 1401 is turned on in response to the first scan signal S1, the second charging unit 1402 is turned on in response to the second scan signal S2, the first voltage writing unit 1501 is turned off in response to the third scan signal S3, and the second voltage writing unit 1502 is turned off in response to the fourth scan signal S4. The voltage at the first terminal a of the memory module 130 is Vdata-VD, and the voltage at the second terminal b is VDD. The voltage difference across the memory module 130 is VDD-vdata+vd. Where VD is the on-state voltage drop of the voltage divider block 210.

In the first initialization stage, the first charging unit 1401 is turned off in response to the first scan signal S1, the second charging unit 1402 is turned off in response to the second scan signal S2, and the voltage difference across the memory module 130 is VDD-vdata+vd, wherein VD is the on-state voltage drop of the voltage dividing module 210. The first initialization module 161 is turned on, and the first initialization voltage VREF1 is transmitted to the control terminal G of the driving module 110 through the first initialization module 161, so as to reset the potential of the control terminal G of the driving module 110. Meanwhile, the first voltage writing unit 1501 is turned on in response to the third scan signal S3, the second voltage writing unit 1502 is turned on in response to the fourth scan signal S4, and the first initialization voltage VREF1 of the control terminal G of the driving module 110 is transmitted to the first terminal a of the memory module 130 through the second voltage writing unit 1502, so that the voltage at the first terminal a of the memory module 130 is changed from Vdata-VD to the first initialization voltage VREF1. Under the coupling action of the memory module 130, the voltage at the second terminal b is coupled to vdd+vref1-vdata+vd. Since the first voltage writing unit 1501 is turned on, the potential of the first terminal S of the driving module 110 is reset to vdd+vref1-vdata+vd. Here, the voltage difference between the first terminal S and the control terminal G of the initialization stage driving module 110 is approximately VDD-VREF1 when the precharge stage is not set, and the voltage difference between the first terminal S and the control terminal G of the first initialization stage driving module 110 is VDD-vdata+vd when the precharge stage is set, more closely to the voltage difference VDD-Vdata-Vth5 between the first terminal S and the control terminal G of the light emitting stage driving module 110, vth5 being the threshold voltage of the driving transistor in the driving module 110. Therefore, the voltage difference between the first end S and the control end G of the driving module 110 is the same or similar to the voltage difference between the first initialization stage and the light-emitting stage, so as to reduce the drift degree of the threshold voltage of the driving module 110, effectively reduce the hysteresis effect, and improve the problem of inconsistent brightness, thereby improving the display quality.

Fig. 10 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, referring to fig. 10, optionally, the pixel circuit further includes a first light emitting control unit 1801 and a second light emitting control unit 1802, the first light emitting control unit 1801 is connected between a first power line L1 and a first end S of the driving module 110, the second light emitting control unit 1802 is connected between a second end D of the driving module 110 and a first end of the light emitting module 170, a second end of the light emitting module 170 is connected with a second power line L2, and a control end of the first light emitting control unit 1801 and a control end of the second light emitting control unit 1802 are both connected with a light emitting control signal line.

Optionally, the control end of the first initialization module 161 is connected to the seventh scan line, the first end of the first initialization module 161 is connected to the first initialization signal line, and the second end of the first initialization module 161 is connected to the control end G of the driving module 110.

Optionally, the pixel circuit further includes a second initialization module 162, a control end of the second initialization module 162 is connected to the eighth scan line, a first end of the second initialization module 162 is connected to the second initialization signal line, and a second end of the second initialization module 162 is connected to the first end of the light emitting module 170.

Fig. 11 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, specifically, a schematic structural diagram of a pixel circuit of fig. 10, wherein the driving module 110 includes a fifth transistor M5, the first voltage writing module 120 includes a sixth transistor M6, the compensation module 190 includes a seventh transistor M7, the first initialization module 161 includes an eighth transistor M8, the first light emitting control unit 1801 includes a ninth transistor M9, the second light emitting control unit 1802 includes a tenth transistor M10, the second initialization module 162 includes an eleventh transistor M11, and the light emitting module 170 includes a light emitting diode D1.

Specifically, the gate of the sixth transistor M6 is connected to the sixth scan line to receive the sixth scan signal S6 transmitted on the sixth scan line, the first pole of the sixth transistor M6 is connected to the data line, and the second pole of the sixth transistor M6 is connected to the first pole of the fifth transistor M5; the gate of the seventh transistor M7 is connected to the fifth scan line to receive the fifth scan signal S5 transmitted on the fifth scan line, the first pole of the seventh transistor M7 is connected to the second pole of the fifth transistor M5, and the second pole of the seventh transistor M7 is connected to the gate of the fifth transistor M5; a gate of the eighth transistor M8 is connected to the seventh scan line to receive the seventh scan signal S7 transmitted on the seventh scan line, a first pole of the eighth transistor M8 is connected to the first initialization signal line to receive the first initialization voltage VREF1 transmitted on the first initialization signal line, and a second pole of the eighth transistor M8 is connected to the gate of the fifth transistor M5; the gate of the ninth transistor M9 and the gate of the tenth transistor M10 are both connected to the emission control signal line to receive the emission control signal EM transmitted on the emission control signal line, the first pole of the ninth transistor M9 is connected to the first power line L1, the second pole of the ninth transistor M9 is connected to the first pole of the fifth transistor M5, the first pole of the tenth transistor M10 is connected to the second pole of the fifth transistor M5, the second pole of the tenth transistor M10 is connected to the first pole (may be the anode) of the light emitting diode D1, and the second pole (may be the cathode) of the light emitting diode D1 is connected to the second power line L2; the gate of the eleventh transistor M11 is connected to the eighth scan line to receive the eighth scan signal S8 transmitted on the eighth scan line, the first pole of the eleventh transistor M11 is connected to the second initialization signal line to receive the second initialization voltage VREF2 transmitted on the second initialization signal line, and the second pole of the eleventh transistor M11 is connected to the first pole of the light emitting diode D1.

Optionally, fig. 12 is a driving timing chart of a pixel circuit according to an embodiment of the present invention, which is suitable for display driving when a display brightness value (Display Brightness Value, DBV) of a display panel is smaller than a preset value, for example, the pixel circuit shown in fig. 11, wherein the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8 shown in fig. 7 are all N-type transistors, and the other transistors are all P-type transistors. Fig. 7 schematically shows only one structure of the pixel circuit, and in other embodiments, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8 may be P-type transistors. With reference to fig. 11 and fig. 12, the specific working procedure of the pixel circuit provided by the embodiment of the invention is as follows:

in the precharge phase T1, the first transistor M1 is turned on in response to the first scan signal S1 at a high level, the second transistor M2 is turned on in response to the second scan signal S2 at a high level, and the remaining transistors are turned off. Therefore, the first transistor M1 transmits the data voltage Vdata to the first pole of the capacitor C through the turned-on voltage dividing module 210, the second transistor M2 transmits the first power voltage VDD to the second pole of the capacitor C to store the on-state voltage drop between the data voltage Vdata and the voltage dividing module 210, and the first power voltage VDD on the capacitor C, and the voltage difference across the capacitor C is VDD-vdata+vd. When the DBV is smaller than the preset value in low brightness, the data voltage Vdata is larger, and Vdata is larger than VDD.

In the first initialization stage T2, the eighth transistor M8 is turned on in response to the seventh scan signal S7 at a high level, the third transistor M3 is turned on in response to the third scan signal S3 at a high level, and the fourth transistor M4 is turned on in response to the fourth scan signal S4 at a high level. The eighth transistor M8 transmits the first initialization voltage VREF1 to the gate of the fifth transistor M5, and initializes the gate of the fifth transistor M5. Meanwhile, the fourth transistor M4 transmits the first initialization voltage VREF1 to the first pole of the capacitor C, the voltage of the first pole of the capacitor C is hopped from Vdata-VD to the first initialization voltage VREF1, under the coupling action of the capacitor C, the voltage variation of the first pole is coupled to the second pole, and the voltage of the second pole of the capacitor C is coupled to vdd+vref1-vdata+vd. Therefore, the voltage of the first pole of the fifth transistor M5 is vdd+vref1-vdata+vd, and the reset operation of the first pole of the fifth transistor M5 is realized. Optionally, in the first initialization phase T2, the eighth transistor M8 may also be turned off.

In the first initialization stage T2, the voltage difference between the first electrode and the gate of the fifth transistor M5 is VDD-Vdata+VD.

Optionally, in the first initialization period T2, the eleventh transistor M11 is turned on in response to the eighth scan signal S8 at a low level, and transmits the second initialization voltage VREF2 to the first electrode of the light emitting diode D1 to reset the potential of the first electrode of the light emitting diode D1.

In the data writing stage T3, the second transistor M2 is turned on in response to the high level second scan signal S2, the fourth transistor M4 is turned on in response to the high level fourth scan signal S4, the seventh transistor M7 is turned on in response to the high level fifth scan signal S5, and the sixth transistor M6 is turned on in response to the low level sixth scan signal S6, so that the gate voltage of the fifth transistor M5 is Vdata-VD in the initial stage, VD is greater than the absolute value of Vth5, and the voltage of the first electrode of the fifth transistor M5 is Vdata, so as to ensure that the gate-source voltage difference of the fifth transistor M5 is less than Vth5, so as to ensure that the fifth transistor M5 is turned on in the initial stage, and the threshold compensation can be realized; that is, the data voltage Vdata is written to the gate of the fifth transistor M5 through the sixth transistor M6, the fifth transistor M5 and the seventh transistor M7 until the gate voltage of the fifth transistor M5 is vdata+vth5, the fifth transistor M5 is turned off, and the gate voltage of the fifth transistor M5 is stored on the capacitor C. Wherein Vth5 is a threshold voltage of the fifth transistor M5, the fifth transistor M5 is a P-type transistor, vth5 is a negative value, and here, the fifth transistor M5 is a driving transistor.

In the light emitting stage T4, the second transistor M2 is turned on in response to the second scan signal S2 of the high level, the fourth transistor M4 is turned on in response to the fourth scan signal S4 of the high level, the ninth transistor M9 and the tenth transistor M10 are turned on in response to the light emission control signal EM, respectively, and the fifth transistor M5 generates a driving current according to the gate voltage and the voltage of the first electrode thereof to drive the light emitting diode D1 to emit light. Here, the first electrode voltage of the fifth transistor M5 is VDD, the gate voltage is vdata+vth5, and the voltage difference between the first electrode and the gate of the fifth transistor M5 is VDD-Vdata-Vth5. When the DBV is lower than the preset value in low brightness, the data voltage Vdata is higher, the fifth transistor M5 is in a sub-threshold on state, and the gate-source voltage difference of the fifth transistor M5 is slightly lower than the threshold voltage Vth5.

Since the voltage difference between the first electrode and the gate of the fifth transistor M5 in the first initialization stage T2 is VDD-vdata+vd, the voltage difference between the first electrode and the gate of the fifth transistor M4 in the light-emitting stage T4 is VDD-Vdata-Vth5, and VD is slightly larger than the absolute value of Vth5, the voltage difference between the first electrode and the gate of the fifth transistor M5 in the initialization stage T2 is the same as or similar to that in the light-emitting stage T4, so as to reduce the drift degree of the threshold voltage Vth5 of the fifth transistor M5, effectively reduce the hysteresis effect, and improve the flicker problem caused by the inconsistent brightness, thereby improving the display quality.

Alternatively, the combination of a plurality of scan lines may be achieved by setting the channel type of each transistor to reduce the number of scan lines. Alternatively, the second transistor M2 and the third transistor M3 may be connected to the same scan line with different channel types. Alternatively, the first transistor M1 and the fourth transistor M4 may be connected to the same scan line with different channel types.

Fig. 13 is a driving timing chart of another pixel circuit according to an embodiment of the invention, where there is no pre-charge phase when the display brightness value (Display Brightness Value, DBV) of the display panel is greater than the preset value, or the storage module 130 is not pre-charged during the pre-charge phase, for example, the first charging unit 1401 may be turned off, the second charging unit 1402 may be turned on or off, and the pixel circuit directly enters the second initialization phase T2', that is, when the display brightness value of the display panel is greater than the preset value, at least one display period (such as the second display period) includes the second initialization phase T2', the data writing phase T3 and the light emitting phase T4. In the second initialization phase T2', the first charging unit 1401 is turned off, the second charging unit 1402 is turned on, the first voltage writing unit 1501 is turned off, and the second voltage writing unit 1502 is turned on. The flicker phenomenon is likewise not perceived at this time. This is because: each DBV instruction can correspond to one display brightness of the maximum gray scale in the display panel, and when the display brightness corresponding to the maximum gray scale is changed, the display brightness corresponding to other gray scales is also changed. The larger the DBV is, the larger the display brightness of the display panel is; when the DBV exceeds a certain preset value, the display panel is in a highlight state, and when the screen is switched, the human eyes cannot easily perceive the change of brightness, and at this time, the driving time sequence shown in fig. 13 can be adopted to drive the pixel circuit to work. When the display brightness value of the display panel is larger than the preset value, vdata is smaller than VDD.

Fig. 14 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, and, with respect to the pixel circuit shown in fig. 11, the pixel circuit shown in fig. 14 does not have the second switch unit 1502, and the first end a of the storage module 130 is directly connected to the control end G of the driving module 110. Fig. 15 is a driving timing chart of another pixel circuit according to an embodiment of the invention, which is applicable to driving the pixel circuit shown in fig. 14 when the display brightness value of the display panel is smaller than a preset value, and referring to fig. 14 and 15, the eighth transistor M8 is always kept in an off state in response to the seventh scan signal S7 with a low level, and the working process of the pixel circuit includes:

in the precharge phase T1, the first transistor M1 is turned on in response to the first scan signal S1 at a high level, the second transistor M2 is turned on in response to the second scan signal S2 at a high level, and the remaining transistors are turned off. Therefore, the first transistor M1 transmits the data voltage Vdata to the first pole of the capacitor C and the gate of the fifth transistor M5 via the turned-on voltage dividing module 210, and the second transistor M2 transmits the first power voltage VDD to the second pole of the capacitor C, and the voltage difference across the capacitor C is VDD-Vdata+VD.

In the first initialization stage T2, the third transistor M3 is turned on in response to the high level third scan signal S3, the voltage of the second pole of the capacitor C is transmitted to the first pole of the fifth transistor M5, and the voltage difference between the first pole and the gate of the fifth transistor M5 is VDD-vdata+vd. Wherein Vdata is greater than VDD.

The operation of the data writing stage T3 and the light emitting stage T4 is the same as the operation of the driving timing shown in fig. 12, and will not be described again. When the DBV is lower than the preset value in low brightness, the data voltage Vdata is higher, the fifth transistor M5 is in a sub-threshold on state, and the gate-source voltage difference of the fifth transistor M5 is slightly lower than the threshold voltage Vth5.

Alternatively, fig. 16 is a driving timing chart of another pixel circuit according to the embodiment of the present invention, which is applicable to driving the pixel circuit shown in fig. 14 when the display brightness value of the display panel is greater than the preset value, and the working process of the driving timing chart is the same as that of the driving timing chart shown in fig. 13, and will not be repeated.

Optionally, the present invention further provides a method for driving a pixel circuit, which may be used to drive the pixel circuit provided in any embodiment of the present invention, and fig. 17 is a flowchart of a method for driving a pixel circuit provided in an embodiment of the present invention, and referring to fig. 2 and 17, the method for driving a pixel circuit includes:

s110, in the pre-charging stage, the pre-charging module is controlled to transmit the data voltage on the data line to the first end of the memory module, and transmit the first power voltage transmitted on the first power line to the second end of the memory module.

S120, in the first initialization stage, the second end of the storage module is communicated with the first end of the driving module, and the first end of the storage module is communicated with the control end of the driving module.

And S130, in the data writing stage, controlling the first voltage writing module to transmit the data voltage transmitted on the data line to the driving module so as to enable the data voltage to be written into the control end of the driving module.

And S140, in the light-emitting stage, controlling the driving module to drive the light-emitting module to emit light.

Alternatively, in combination with the pixel circuit shown in fig. 8, the precharge module 140 includes a first charging unit 1401 and a second charging unit 1402; the control end of the first charging unit 1401 is connected to the first scan line, the first end of the first charging unit 1401 is connected to the data line, the second end of the first charging unit 1401 is connected to the first end a of the memory module 130, the first end of the second charging unit 1402 is connected to the first power line L1, the second end of the second charging unit 1402 is connected to the second end b of the memory module 130, and the control end of the second charging unit 1402 is connected to the second scan line.

The second voltage writing module 150 includes a first voltage writing unit 1501, a first end of the first voltage writing unit 1501 is connected to the second end b of the memory module 130, a second end of the first voltage writing unit 1501 is connected to the first end S of the driving module 110, and a control end of the first voltage writing unit 1501 is connected to the third scan line;

the first terminal a of the memory module 130 is connected to the control terminal G of the driving module 110.

Or, the voltage writing module 150 further includes a second voltage writing unit 1502, a first end of the second voltage writing unit 1502 is connected to the first end a of the memory module 130, a second end of the second voltage writing unit 1502 is connected to the control end G of the driving module 110, and a control end of the second voltage writing unit 1502 is connected to the fourth scan line.

The step S110 specifically includes:

in the precharge phase, the first charging unit is controlled to be conducted in response to a first scanning signal on the first scanning line so as to transmit the data voltage on the data line to the first end of the memory module, and the second charging unit is controlled to be conducted in response to a second scanning signal on the second scanning line so as to transmit the first power voltage transmitted on the first power line to the second end of the memory module.

The step S120 specifically includes:

in the first initialization stage, controlling the second voltage writing unit to be conducted in response to a fourth scanning signal on a fourth scanning line so as to transmit a data voltage to a first end of the memory module; and simultaneously controlling the first voltage writing unit to be conducted in response to a third scanning signal on a third scanning line so as to write the voltage of the second end of the storage module into the first end of the driving module.

Optionally, the pixel circuit further includes a compensation module 190, where the compensation module 190 is connected between the second terminal D and the control terminal G of the driving module 110, and the connection path between the first charging unit 1401 and the data line further includes a voltage division module 210, where the voltage division module 210 includes at least one diode; the on-state voltage drop of the voltage dividing module 210 is greater than the absolute value of the threshold voltage of the driving module 110. The pixel circuit also comprises a first initialization module which is connected with the driving module; when the display brightness value of the display panel is smaller than the preset value, the step S110 includes:

In the precharge stage, the first charging unit is controlled to be conducted in response to a first scanning signal on the first scanning line so as to transmit the data voltage on the data line to the first end of the memory module through the voltage dividing module, and the second charging unit is controlled to be conducted in response to a second scanning signal on the second scanning line so as to transmit the first power voltage transmitted on the first power line to the second end of the memory module.

The step S120 includes:

in the first initialization stage, the first initialization module is controlled to transmit a first initialization voltage to a control end of the driving module, and the second voltage writing unit is controlled to respond to the conduction of a fourth scanning signal on a fourth scanning line to transmit the first initialization voltage to a first end of the storage module; and simultaneously controlling the first voltage writing unit to respond to the third scanning signal on the third scanning line to conduct, and writing the voltage of the second end of the storage module into the first end of the driving module.

The step S130 includes:

For the description of the precharge phase and the first initialization phase, reference may be made to the description in the above embodiments, and the description is not repeated here.

Optionally, the present invention further provides a display panel, where the display panel includes the pixel circuit provided by any embodiment of the present invention, so that the display panel also has the beneficial effects described in any embodiment above. Fig. 18 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and in this embodiment, the display panel 200 may be applied to a mobile phone panel as shown in fig. 18, and may also be applied to any electronic product with a display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interactive terminal, etc., which are not particularly limited in this embodiment of the invention.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. A pixel circuit, comprising: the device comprises a driving module, a first voltage writing module, a storage module, a precharge module, a second voltage writing module and a light emitting module;

the precharge module is connected with at least a data line and the storage module, and is used for transmitting the data voltage on the data line to a first end of the storage module in a precharge stage, and transmitting a first power voltage transmitted on a first power line to a second end of the storage module;

the first voltage writing module is used for transmitting the data voltage to the driving module in a data writing stage;

Wherein the precharge phase is located before the first initialization phase.

2. The pixel circuit of claim 1, wherein the precharge module comprises a first charging unit and a second charging unit;

the control end of the first charging unit is connected with a first scanning line, the first end of the first charging unit is connected with the data line, the second end of the first charging unit is connected with the first end of the storage module, the first end of the second charging unit is connected with the first power line, the second end of the second charging unit is connected with the second end of the storage module, and the control end of the second charging unit is connected with a second scanning line;

preferably, the first charging unit includes a first transistor, a gate of the first transistor is a control terminal of the first charging unit, a first pole of the first transistor is a first terminal of the first charging unit, and a second pole of the first transistor is a second terminal of the first charging unit;

the second charging unit comprises a second transistor, the gate of the second transistor is a control end of the second charging unit, the first pole of the second transistor is a first end of the second charging unit, and the second pole of the second transistor is a second end of the second charging unit;

Preferably, a voltage division module is further included on a connection path between the first charging unit and the data line, and the voltage division module includes at least one diode; the on-state voltage drop of the voltage dividing module is larger than the absolute value of the threshold voltage of the driving module; the voltage dividing module is conducted in the pre-charging stage;

preferably, the diode comprises a transistor with a gate and a first pole shorted;

preferably, the voltage dividing module comprises a first diode and a second diode connected in series.

3. The pixel circuit according to claim 2, wherein,

the second voltage writing module comprises a first voltage writing unit;

the first end of the first voltage writing unit is connected with the second end of the storage module, the second end of the first voltage writing unit is connected with the first end of the driving module, and the control end of the first voltage writing unit is connected with a third scanning line;

the first end of the storage module is connected with the control end of the driving module, or the second voltage writing module further comprises a second voltage writing unit, the first end of the second voltage writing unit is connected with the first end of the storage module, the second end of the second voltage writing unit is connected with the control end of the driving module, and the control end of the second voltage writing unit is connected with a fourth scanning line;

Preferably, the first voltage writing unit includes a third transistor, a gate of the third transistor is a control terminal of the first voltage writing unit, a first pole of the third transistor is a first terminal of the first voltage writing unit, and a second pole of the third transistor is a second terminal of the first voltage writing unit;

preferably, the memory module includes a capacitor, a first end of the capacitor being a first end of the memory module, and a second end of the capacitor being a second end of the memory module.

4. The pixel circuit according to claim 3, wherein the first scan line, the second scan line, the third scan line, and the fourth scan line are for transmitting scan signals,

in the precharge phase, the first charging unit and the second charging unit are turned on, the first voltage writing unit is turned off, and the second voltage writing unit is turned off;

in the data writing stage and the light emitting stage, the first charging unit is turned off, the second charging unit is turned on, the first voltage writing unit is turned off, and the second voltage writing unit is turned on;

preferably, at least one first display period includes the precharge phase, the first initialization phase, the data writing phase, and the light emitting phase when a display luminance value of the display panel is less than a preset value.

5. The pixel circuit according to claim 3 or 4, further comprising a first initialization module connected to the drive module,

the first initialization module is used for transmitting a first initialization voltage to a control end of the driving module in the first initialization stage when the display brightness value of the display panel is smaller than a preset value;

and/or the first initialization module is used for transmitting a first initialization voltage to the control end of the driving module in a second initialization stage when the display brightness value of the display panel is larger than a preset value;

Preferably, at least one second display period includes the second initialization phase, the data writing phase and the light emitting phase when a display luminance value of the display panel is greater than a preset value;

preferably, in a second initialization stage when the display brightness value of the display panel is greater than a preset value, the first charging unit is turned off, the second charging unit is turned on, the first voltage writing unit is turned off, and the second voltage writing unit is turned on;

preferably, the control end of the first initialization module is connected with the seventh scan line, the first end of the first initialization module is connected with the first initialization signal line, and the second end of the first initialization module is connected with the control end of the driving module.

6. The pixel circuit of claim 1, wherein the pixel circuit further comprises a compensation module; the compensation module is connected between the second end and the control end of the driving module, and the control end of the compensation module is connected with a fifth scanning line; the control end of the first voltage writing module is connected with a sixth scanning line, the first end of the first voltage writing module is connected with the data line, and the second end of the first voltage writing module is connected with the first end of the driving module;

Preferably, the pixel circuit further includes a first light emission control unit and a second light emission control unit;

the first light-emitting control unit is connected between the first power line and the first end of the driving module, the second light-emitting control unit is connected between the second end of the driving module and the first end of the light-emitting module, the second end of the light-emitting module is connected with the second power line, and the control end of the first light-emitting control unit and the control end of the second light-emitting control unit are both connected with a light-emitting control signal line;

preferably, the pixel circuit further includes a second initialization module, a control end of the second initialization module is connected to the eighth scan line, a first end of the second initialization module is connected to a second initialization signal line, and a second end of the second initialization module is connected to the first end of the light emitting module.

7. The driving method of the pixel circuit is characterized in that the pixel circuit comprises a driving module, a first voltage writing module, a storage module, a pre-charging module, a second voltage writing module and a light emitting module, wherein the pre-charging module is at least connected with a data line and the storage module, the second voltage writing module is at least connected with a first end of the driving module and the storage module, and the driving module and the light emitting module are connected between a first power line and a second power line;

The driving method of the pixel circuit comprises the following steps:

in a precharge phase, controlling the precharge module to transmit the data voltage on the data line to a first terminal of the memory module, and transmitting a first power voltage transmitted on the first power line to a second terminal of the memory module;

in a first initialization stage, the second end of the storage module is communicated with the first end of the driving module, and the first end of the storage module is communicated with the control end of the driving module;

in a data writing stage, controlling the first voltage writing module to transmit the data voltage transmitted on the data line to the driving module so that the data voltage is written into a control end of the driving module;

and in the light-emitting stage, controlling the driving module to drive the light-emitting module to emit light.

8. The method according to claim 7, wherein the precharge module includes a first charge unit and a second charge unit, a control terminal of the first charge unit is connected to a first scan line, a first terminal of the first charge unit is connected to the data line, a second terminal of the first charge unit is connected to a first terminal of the memory module, a first terminal of the second charge unit is connected to the first power line, a second terminal of the second charge unit is connected to a second terminal of the memory module, and a control terminal of the second charge unit is connected to a second scan line;

The second voltage writing module comprises a first voltage writing unit, a first end of the first voltage writing unit is connected with a second end of the storage module, a second end of the first voltage writing unit is connected with a first end of the driving module, and a control end of the first voltage writing unit is connected with a third scanning line;

in the precharge phase, the first charging unit is controlled to be conducted in response to a first scanning signal on the first scanning line so as to transmit the data voltage on the data line to the first end of the memory module, and the second charging unit is controlled to be conducted in response to a second scanning signal on the second scanning line so as to transmit the first power voltage transmitted on the first power line to the second end of the memory module;

In a first initialization phase, the step of communicating the second end of the storage module with the first end of the driving module, wherein the first end of the storage module is communicated with the control end of the driving module comprises the following steps:

in the first initialization stage, controlling the second voltage writing unit to respond to a fourth scanning signal on the fourth scanning line to conduct, and transmitting the data voltage to a first end of the memory module; and simultaneously controlling the first voltage writing unit to respond to the third scanning signal on the third scanning line to conduct, and writing the voltage of the second end of the storage module into the first end of the driving module.

9. The method according to claim 8, wherein the pixel circuit further comprises a compensation module connected between the second terminal and the control terminal of the driving module, the control terminal of the compensation module being connected to a fifth scan line; the connection path of the first charging unit and the data line further comprises a voltage division module, wherein the voltage division module comprises at least one diode; the on-state voltage drop of the voltage dividing module is larger than the absolute value of the threshold voltage of the driving module;

The pixel circuit further comprises a first initialization module connected with the driving module; when the display brightness value of the display panel is smaller than a preset value, in the precharge stage, the step of controlling the precharge module to transmit the data voltage on the data line to the first end of the memory module and to transmit the first power voltage transmitted on the first power line to the second end of the memory module includes:

in the pre-charging stage, the first charging unit is controlled to be conducted in response to a first scanning signal on the first scanning line so as to transmit the data voltage on the data line to the first end of the storage module through the voltage dividing module, and the second charging unit is controlled to be conducted in response to a second scanning signal on the second scanning line so as to transmit the first power voltage transmitted on the first power line to the second end of the storage module;

in the first initialization stage, the first initialization module is controlled to transmit a first initialization voltage to the control end of the driving module, the second voltage writing unit is controlled to respond to the conduction of a fourth scanning signal on the fourth scanning line, and the first initialization voltage is transmitted to the first end of the storage module; simultaneously controlling the first voltage writing unit to respond to a third scanning signal on the third scanning line to conduct, and writing the voltage of the second end of the storage module into the first end of the driving module;

and in the data writing stage, the first voltage writing module is controlled to transmit the data voltage transmitted on the data line to the control end of the driving module through the compensation module.

10. A display panel comprising a pixel circuit according to any one of claims 1-6.