CN116756073A - Method for improving read-write speed of SPI slave - Google Patents
Method for improving read-write speed of SPI slave Download PDFInfo
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- CN116756073A CN116756073A CN202310695276.5A CN202310695276A CN116756073A CN 116756073 A CN116756073 A CN 116756073A CN 202310695276 A CN202310695276 A CN 202310695276A CN 116756073 A CN116756073 A CN 116756073A
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- 230000005540 biological transmission Effects 0.000 claims description 19
- 230000001360 synchronised effect Effects 0.000 claims description 13
- 238000010586 diagram Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000005070 sampling Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30134—Register stacks; shift registers
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Abstract
The invention discloses a method for improving the read-write speed of SPI slave, which realizes the read-write operation of a register file with continuously distributed addresses by sending a control segment (read-write command and address) only once and automatically increasing the addresses of subsequent registers without independently sending a control segment to each register, thereby realizing burst operation and accelerating the read-write access speed.
Description
Technical Field
The invention relates to the technical field of communication methods of SPI serial peripheral interfaces, in particular to a method for improving the read-write speed of SPI slave.
Background
SPI (Serial Peripheral Interface ), is a high-speed full duplex serial communication bus. It uses 4 wires to perform data transmission between Master and slave devices, SCK (synchronous clock signal), MOSI (Master output/slave input), MISO (Master input/slave output), SS (slave chip select), and serial data transmission process is controlled by Master. Because SPI bus communication logic is simple, the wiring pin is few, is applicable to the configuration to the peripheral hardware.
When the peripheral internal register is configured by reading and writing through the SPI slave interface, the existing method generally defines a data frame transmitted by the SPI serial interface as 2 parts, and the data frame is divided into a control field and a data field. The control field comprises a read/write operation indicating bit and a register address bit, which are 1 byte; the data field contains the data to be read and written, typically 1-3 bytes, depending on the data length. And SCK clock signals are adopted between the master equipment and the slave equipment for synchronous transmission or sampling, the SPI slave analyzes the received control field, and the cross-clock domain signal processing from the SCK clock domain to the system clock domain is completed through an asynchronous processing circuit, so that the register read-write operation under the system clock domain is finally realized.
However, the above method has the defects that when the registers with different addresses are read and written, each time the registers need to receive and transmit a complete data frame, i.e. the control field is sent first and then the data field is received or received, and the addresses are fixed to 7 bits, so that the read and write speeds of the registers are slower, and the address range is beyond the addressing range when the address range of the registers exceeds 7 bits.
Disclosure of Invention
In order to solve the technical problems, the invention adopts a technical scheme that:
the method for improving the read-write speed of the SPI slave comprises the following steps:
(1) The SPI slave receives and analyzes the data transmitted by the master serial port to judge whether to perform read operation or write operation, and latches a read-write command and the first address of a register; the data frame transmitted by the SPI serial port comprises a control field and a data field, wherein the control field and the data field can be adjusted according to the address bit width of the register;
(2) When the SPI slave receives a write command to perform a write operation:
(2.1) after receiving write data of the 1 st byte, the SPI slave completes the synchronous processing of write enable signals from the SCK clock domain to the system clock domain, so that write operation does not occupy additional clocks beyond serial data transmission, data is written into a register of a corresponding address according to the synchronous signals, and meanwhile, the register address is automatically increased, and the register address after automatic increase is used as a register address corresponding to the next write data;
(2.2) after receiving the write data of the 2 nd byte, the SPI slave completes the write enabling signal synchronization processing from the SCK clock domain to the system clock domain, writes the write data into a register corresponding to the address after the automatic increment in the step (2.1) according to the synchronized signal, and simultaneously, the register address continues to be automatically incremented to be used as the register address corresponding to the next write data;
(2.3) repeating the above operations until all the data writing operations are completed;
(3) When SPI slave receives a read command to perform a read operation:
(3.1) SPI slave reads out the 1 st byte data from the register of the corresponding read address, and sends the 1 st byte data to the master through serial port shift, and simultaneously, the address of the read register is automatically increased;
(3.2) SPI slave reads out the 2 nd byte data from the register corresponding to the register address which is automatically increased in the step (3.1), and sends the data to the master through serial port shift, and simultaneously, the address of the read register is automatically increased;
(3.3) repeating the above operations until all the data reading operations are completed.
In a preferred embodiment of the present invention, the SPI slave module mainly includes a control module, a data frame parsing module, and a synchronization module.
In a preferred embodiment of the present invention, the parsing of the data frame includes read-write control parsing, address parsing, and data parsing.
In a preferred embodiment of the present invention, the data frame includes a control field and a data field 2 portion, wherein the control field is 1 or 2 bytes, the accessed register address bit width is selected to be 7 bits or 15 bits, the 1 st byte most significant bit is a read/write operation indicating bit, and the rest is the register address bit; the data field is in bytes, and the number of bytes which can be transceived is not limited.
In a preferred embodiment of the present invention, the first address of the register is received only, and the register address is incremented automatically after each byte of data is received or transmitted.
In a preferred embodiment of the present invention, the synchronization module is configured to synchronize the write enable signal Wr of the SCK clock domain, and the internal bus clock domain writes data into the register file RegFile according to the synchronized write command Wen signal.
In a preferred embodiment of the present invention, the control module generates a counter shift_cnt and a counter phase_cnt according to the input signal SS and the input signal SCK, wherein the counter shift_cnt is used for locating the bit of each currently transmitted byte, and when the value of shift_cnt is 0, it represents that 1 byte transmission is finished; the counter phase_cnt is used for positioning whether the field of the current transmission data is in the control field or the data field according to the bit width of the register address by calculating the number of bytes transmitted, so that the transmitted address and data can be conveniently latched.
The beneficial effects of the invention are as follows: the read-write operation of the register file with the addresses distributed continuously is realized by sending the control segment (read-write command and address) only once and automatically increasing the addresses of the subsequent registers, and each register does not need to send the control segment independently, so that the burst operation is realized, and the read-write access speed is accelerated.
Drawings
For a clearer description of the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the description below are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:
FIG. 1 is a schematic diagram of a data frame format of an SPI slave in a preferred embodiment of a method for improving the read/write speed of the SPI slave according to the present invention;
FIG. 2 is a data transmission line diagram of SPI slave in a preferred embodiment of a method for improving the read/write speed of SPI slave according to the present invention;
FIG. 3 is a timing diagram of the internal registers of the SPI slave in a preferred embodiment of a method for improving the read/write speed of the SPI slave according to the present invention;
fig. 4 is a timing diagram of internal registers of an SPI slave according to a preferred embodiment of a method for improving the read/write speed of the SPI slave.
Description of the embodiments
The following description of the technical solutions in the embodiments of the present invention will be clear and complete, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The data frame format of the method for improving the read-write access speed of the SPI slave to the internal register provided by the embodiment is shown in fig. 1. Each data frame transmitted by the SPI includes 2 parts, which are in turn a control field and a data field.
Wherein: the control field is 1 or 2 bytes, when the register address bit width is 15 bits, the control field is 2 bytes, the 1 st byte most significant bit is a read-write operation indicating bit, and the remaining 15 bits are register address bits; when the register address bit width is 7 bits, the control field only needs 1 byte.
The data field is in bytes, the byte length is not limited, and can be determined by the number of registers to be read and written.
The data path in this embodiment is shown in fig. 2. SPI slave determines the start and end of SPI data frame transmission by input signal SS, which is an active-low signal. The input signal SCK is used as a synchronous clock signal for data transmission, and the clock edges of data transmission and sampling are judged according to the CPOL and the CPHA. The slave latches the MOSI sent by the master to the register file rx_buffer at the sampling clock edge, and sends the data in the tx_shift shift register to the master through the MISO at the sending clock edge.
The Spi slave module mainly comprises a control module, a data frame analysis module and a synchronization module.
The control module generates 2 counters according to the SS signal and the SCK signal: a counter shift_cnt and a counter phase_cnt. The counter shift_cnt is used for locating the bit of each byte to be transmitted, and when shift_cnt is 0, the counter shift_cnt represents that 1 byte transmission is finished; the counter phase_cnt is used for locating whether the field for currently transmitting data is in the control field or the data field by calculating the number of bytes transmitted according to the bit width of the register address, so that the transmitted address and data can be conveniently latched. The 2 counters are reset when the system reset or SS signal is inactive.
The parsing of the data frame includes read-write control parsing, address parsing, and data parsing.
According to the data in the register file Rx_buffer, the highest bit of the 1 st byte is combined with the data frame format to judge the read or write operation, and a write command Wr and a read command Ren signal are generated. The lower 7 bits of the 1 st byte (the 2 nd byte is added if the address bit width is 15 bits) are used as the address of the read-write register, and the address is increased by 1 after the transmission of each data byte is finished, so as to generate Waddr and Raddr signals; wr_dat and Rd_dat are generated for data bits to be read and written starting from the 2 nd byte (from the 3 Rd byte if the address bit width is 15 bits). The data transfer may be ended by pulling the SS signal high.
The synchronization module is used for synchronizing the write enable signal Wr of the SCK clock domain. And the internal bus clock domain writes data into the RegFile according to the synchronized Wen signal.
Fig. 3 and 4 are timing diagrams of the SPI slave writing and reading, respectively, to the internal registers. In this embodiment, CPOL and CPHA are both 0, that is, clock rising edge sampling and falling edge sending; the register address bit width is 15 bits. The following further describes the read-write operation flow:
write register operation:
after receiving and analyzing data sent by a master, the SPI slave gives a write command Wr, synchronizes to the internal bus clock domain of Wen, gives a write address Waddr and 1 st byte write data Wdata0, writes Wdata0 into a register with the address Waddr by an internal module of the slave, and simultaneously, automatically increases the register address to Waddr+1; SPI slave receives the 2 nd byte data Wdata1, the synchronized write enable signal Wen is valid again, the data Wdata1 is written into a register with the address Waddr+1 by the slave device internal module, and meanwhile, the register address is automatically increased to Waddr+2; and repeating the last process, writing data into the registers with continuously increasing addresses until the SS signal is pulled high to finish transmission, and stopping writing operation.
Register read operation:
after receiving and analyzing data sent by a master, the SPI slave gives out a read command Ren, a read address Raddr, and a slave device internal module reads out 1 st byte data Rdata0 from a register with the address Raddr and assigns the 1 st byte data Rdata0 to a Tx_shift shift register and outputs the data through MISO serial output; after the transmission of the 1 st byte data Rdata0 is finished, the register address is automatically increased to Raddr+1, then the slave device internal module reads out the 2 nd byte data Rdata1 from the register with the slave address of Raddr+1, and assigns the 2 nd byte data Rdata1 to the Tx_shift shift register, and then the data is serially output through MISO; after the transmission of the 2 nd byte data Rdata1 is finished, the register address is automatically increased to Raddr+2; the last process is repeated, the data is read from the register with the address continuously increased until the SS pull-up transmission is finished, and the reading operation is stopped.
The method for improving the read-write speed of the SPI slave has the beneficial effects that:
1. under the condition that a control section (a read-write command and an address) is sent once, the subsequent register address is automatically increased to realize the read-write operation of the register file with continuously distributed addresses, so that the time of independently sending the control field for each time of reading and writing the register is saved, burst operation is realized, the access speed for reading and writing the register is greatly improved, and the access speed is more obvious especially when the number of the registers is more;
2. the wide address range of the register can be expanded, the address range is not limited to 7 bits, the wide address range is suitable for the condition that the address range of the register configured through the SPI bus is wide, and the universality is improved.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes or direct or indirect application in other related arts are included in the scope of the present invention.
Claims (7)
1. A method for improving the read-write speed of SPI slave is characterized by comprising the following steps:
(1) The SPI slave receives and analyzes the data transmitted by the master serial port to judge whether to perform read operation or write operation, and latches a read-write command and the first address of the register; the data frame transmitted by the SPI serial port comprises a control field and a data field, wherein the control field and the data field can be adjusted according to the address bit width of the register;
(2) When the SPI slave receives a write command to perform a write operation:
(2.1) after receiving write data of the 1 st byte, the SPI slave completes the synchronous processing of write enable signals from the SCK clock domain to the system clock domain, so that write operation does not occupy additional clocks beyond serial data transmission, data is written into a register of a corresponding address according to the synchronous signals, and meanwhile, the register address is automatically increased, and the register address after automatic increase is used as a register address corresponding to the next write data;
(2.2) after receiving the write data of the 2 nd byte, the SPI slave completes the write enabling signal synchronization processing from the SCK clock domain to the system clock domain, writes the write data into a register corresponding to the address after the automatic increment in the step (2.1) according to the synchronized signal, and simultaneously, the register address continues to be automatically incremented to be used as the register address corresponding to the next write data;
(2.3) repeating the above operations until all the data writing operations are completed;
(3) When SPI slave receives a read command to perform a read operation:
(3.1) SPI slave reads out the 1 st byte data from the register of the corresponding read address, and sends the 1 st byte data to the master through serial port shift, and simultaneously, the address of the read register is automatically increased;
(3.2) SPI slave reads out the 2 nd byte data from the register corresponding to the register address which is automatically increased in the step (3.1), and sends the data to the master through serial port shift, and simultaneously, the address of the read register is automatically increased;
(3.3) repeating the above operations until all the data reading operations are completed.
2. The method for improving the read-write speed of the SPI slave according to claim 1, wherein the SPI slave module mainly comprises a control module, a data frame parsing module, and a synchronization module.
3. The method for increasing the read-write speed of an SPI slave according to claim 1, wherein the parsing of the data frame includes read-write control parsing, address parsing, and data parsing.
4. A method for increasing the read-write speed of an SPI slave according to claim 3, wherein the data frame comprises a control field and a data field 2 portion, wherein the control field is 1 or 2 bytes, the accessed register address bit width is selectable to be 7 bits or 15 bits, the 1 st byte most significant bit is a read-write operation indication bit, and the remainder is a register address bit; the data field is in bytes, and the number of bytes which can be transceived is not limited.
5. A method for increasing the read-write speed of an SPI slave according to claim 1, wherein the register address is automatically incremented after each byte of data is received or transmitted only by receiving the first address of the register.
6. The method for increasing the read-write speed of an SPI slave according to claim 1, wherein the synchronization module is configured to synchronize a write enable signal Wr of the SCK clock domain, and the internal bus clock domain writes data into the register file RegFile according to the synchronized write command Wen signal.
7. The method for increasing the read-write speed of the SPI slave according to claim 1, wherein the control module generates a counter shift_cnt and a counter phase_cnt according to the input signal SS and the input signal SCK, wherein the counter shift_cnt is used for locating the bit of each current byte to be transmitted, and when the value of shift_cnt is 0, it represents that the transmission of 1 byte is completed; the counter phase_cnt is used for positioning whether the field of the current transmission data is in the control field or the data field according to the bit width of the register address by calculating the number of bytes transmitted, so that the transmitted address and data can be conveniently latched.
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| CN202310695276.5A CN116756073A (en) | 2023-06-13 | 2023-06-13 | Method for improving read-write speed of SPI slave |
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| CN202310695276.5A CN116756073A (en) | 2023-06-13 | 2023-06-13 | Method for improving read-write speed of SPI slave |
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