CN116754931A - Self-checking method and self-checking circuit for digital input loop - Google Patents
Self-checking method and self-checking circuit for digital input loop Download PDFInfo
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- 239000007924 injection Substances 0.000 claims description 35
- 238000005070 sampling Methods 0.000 claims description 12
- 238000012360 testing method Methods 0.000 claims description 8
- 238000012545 processing Methods 0.000 claims description 7
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- 238000004088 simulation Methods 0.000 description 2
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- 230000009471 action Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
Abstract
The invention relates to the technical field of digital input, in particular to a self-checking method and a self-checking circuit of a digital input loop, wherein the self-checking method comprises the following steps: acquiring an actual output signal of a digital input loop, and defining the actual input signal of the digital input loop as a first level signal according to the actual output signal; injecting a second level signal with a certain width into the digital input loop, wherein the second level signal is opposite to the first level signal in state; and collecting a feedback output signal of the digital input loop, and judging whether the digital input loop is normal or not according to the feedback output signal. The self-checking method and the self-checking circuit for the digital input loop can carry out self-checking judgment on the effectiveness of the digital input loop, expand the scene of the effectiveness judgment of the digital input loop, pre-judge the correctness and the reliability of the loop in advance under various working conditions, and reduce the occupation of GPIO resources of a controller.
Description
Technical Field
The invention relates to the technical field of digital input, in particular to a self-checking method and a self-checking circuit of a digital input loop.
Background
In the field of rail transit, in order to monitor the states of devices such as relays, switches, meters and the like of various control loops, a digital input loop is needed, monitoring signals are input into a controller through the digital input loop, and then the controller outputs control signals through a digital output loop to perform operations such as alarming, switching-off and the like.
Fig. 1 shows a digital input circuit isolated by an optocoupler in the prior art, wherein a switch S is connected to an input side of the optocoupler, when the switch S is turned off, a light emitting diode in the optocoupler is not energized, a phototransistor is turned off, and an output signal U0 of the optocoupler is kept at a high level; when the switch S is closed, the light emitting diode in the optocoupler is electrified, the phototriode is conducted, and the output signal U0 of the optocoupler is pulled down to be low level. Therefore, the state of the switch S can be judged by detecting the output signal U0 of the optocoupler through the controller, and the controller can be protected through optocoupler isolation, so that the anti-interference effect is good. However, the digital input circuit may malfunction, and if the digital input circuit malfunctions, the controller cannot accurately receive the signal of the switch state, and malfunction occurs, so that the digital input circuit needs to be self-checked during operation to ensure the effectiveness of the operation.
Disclosure of Invention
The invention provides a self-checking method and a self-checking circuit for a digital input loop, which can carry out self-checking on the effectiveness of the digital input loop, can carry out self-checking under various working conditions and ensure the accuracy and the reliability of the self-checking, and solves the technical problem that the digital input loop in the prior art can be faulty to cause misoperation.
The invention adopts the technical scheme that:
a self-checking method of a digital input loop comprises the following steps:
acquiring an actual output signal of a digital input loop, and defining the actual input signal of the digital input loop as a first level signal according to the actual output signal;
injecting a second level signal with a certain width into the digital input loop, wherein the second level signal is opposite to the first level signal in state;
and collecting a feedback output signal of the digital input loop, and judging whether the digital input loop is normal or not according to the feedback output signal.
Further, the first level signal is defined as an actual input signal when the digital input loop is operating normally.
Further, judging whether the digital input loop is normal according to the feedback output signal, specifically comprising the following steps:
if the feedback output signal is unchanged compared with the actual output signal, judging that the digital input loop is abnormal;
if the feedback output signal is changed compared with the actual output signal due to the injected second level signal, the digital input loop is judged to be normal.
Further, the long-term high-level signal/low-level signal in the feedback output signal is used as an actual sampling signal of the digital input loop.
In another aspect of the present invention, a self-test circuit for a digital input loop is provided, comprising a digital input loop and a controller, the controller comprising an acquisition module, a processing module, an injection module and a judgment module, wherein,
the acquisition module is used for acquiring an actual output signal of the digital input loop;
the processing module is used for defining an actual input signal of the digital input loop as a first level signal according to the actual output signal;
the injection module is used for injecting a second level signal with a certain width into the digital input loop, and the second level signal is opposite to the first level signal in state;
the judging module is used for judging whether the digital input loop is normal or not according to the feedback output signal after the acquisition module acquires the feedback output signal of the digital input loop.
Further, the self-checking circuit further comprises a high-level injection circuit and a low-level injection circuit, and when the first level signal is at a high level, the controller injects a low level with a certain width into the digital input loop through the low-level injection circuit; when the first level signal is at a low level, the controller injects a high level with a certain width into the digital input loop through the high level injection circuit;
the high-level injection circuit comprises a first photo MOS relay, wherein the input side of the first photo MOS relay is respectively connected with a power supply and the controller, and the output side of the first photo MOS relay is respectively connected with the power supply and the input end of the digital input loop; the low-level injection circuit comprises a second photo-MOS relay, wherein the input side of the second photo-MOS relay is respectively connected with a power supply and the controller, and the output side of the second photo-MOS relay is respectively connected with the ground and the input end of the digital input loop.
Further, the high-level injection circuit further comprises a first diode, wherein the anode of the first diode is connected with the output end of the first photo-MOS relay, and the cathode of the first diode is connected with the input end of the digital input loop; the low-level injection circuit comprises a second diode, wherein the anode of the second diode is connected with the input end of the digital input loop, and the cathode of the second diode is connected with the output end of the second photo-MOS relay.
Further, the digital input loop comprises an optocoupler and a third diode, wherein the anode of the third diode inputs the actual input signal, and the cathode of the third diode is connected with the input end of the optocoupler and simultaneously connected with the cathode of the first diode and the anode of the second diode.
Further, an anode of the third diode is further connected with an inductor, a parallel resistor is further arranged on the input side of the optocoupler, and filter capacitors are further arranged on the input side and the output side of the optocoupler respectively.
Further, a decoder is arranged between the controller and the input end of the digital input loop; the number of the digital input loops is at least two, and an encoder is arranged between the output end of the digital input loop and the controller.
The invention has the beneficial effects that: the self-checking method and the self-checking circuit for the digital input loop can perform self-checking on the effectiveness of the digital input loop, expand the scene of judging the effectiveness of the digital input loop, pre-judge the correctness and the reliability of the loop in advance under various working conditions, and reduce the occupation of GPIO resources of a controller by arranging a decoder.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a digital input circuit in the prior art;
FIG. 2 is a flow chart of a self-checking method of the digital input circuit of the present invention;
FIG. 3 is a schematic diagram of a self-checking circuit of the digital input circuit according to the present invention;
fig. 4 is a schematic diagram of signals input by the digital input circuit in self-test.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 2, the present embodiment provides a self-checking method of a digital input loop, which includes the following steps:
s1, acquiring an actual output signal of a digital input loop, and defining the actual input signal of the digital input loop as a first level signal according to the actual output signal;
when the digital input circuit works actually, the input end of the digital input circuit inputs an actual input signal, the output end outputs an actual output signal, and if the digital input circuit works normally, the actual input signal can be obtained to be in a high level or a low level according to the actual output signal combined with the specific structure of the digital input circuit.
For example, in the structure of the digital input loop shown in fig. 1, when the normal operation does not fail, it is assumed that the input end of the optocoupler is at a low level, the light emitting diode is not turned on, the phototransistor is also turned off, and the output end of the optocoupler is pulled up to a high level; assuming that the input end of the optocoupler is at a high level, the light emitting diode is conducted, the phototriode is also conducted, and the output end is pulled down to be at a low level, so that the signal of the input end in normal operation can be obtained according to the signal of the output end, namely if the output end is at the high level, the input end is at the low level; if the output is low, the input is high.
When the digital input loop is different from the structure shown in fig. 1, for example, the output end of the digital input loop is not provided with a pull-up resistor but provided with a pull-down resistor, namely, the collector electrode of the phototriode is connected with a power supply, the emitter electrode is grounded through the pull-down resistor, and the digital input loop is led out from the emitter electrode to be an output end, and when the digital input loop works normally, if the output end is at a low level, the input end is at a low level; if the output is high, the input is high.
That is, in combination with a specific digital input loop, an actual input signal of the input end of the digital input loop in normal operation can be obtained according to an actual output signal of the output end of the digital input loop, and the actual input signal is defined as a first level signal. The signal acquisition, processing, injection and judgment can be performed by controllers such as MCU, FPGA, singlechip and the like.
S2, injecting a second level signal with a certain width into the digital input loop, wherein the second level signal is opposite to the first level signal in state;
the controller is directly or indirectly connected to the input end of the digital input loop, and a second level signal with a certain width is injected into the input end of the digital input loop for a single time or periodically according to the first level signal, wherein the second level signal is opposite to the first level signal in state, specifically, when the first level signal is in a high level, a low level with a certain width is injected, so that the input end of the digital input loop is in a low level; when the second level signal is low level, a high level with a certain width is injected, so that the input end of the digital input loop is high level.
And S3, collecting a feedback output signal of the digital input loop, and judging whether the digital input loop is normal or not according to the feedback output signal.
The controller is used for collecting the feedback output signal of the output end of the digital input loop again, and as the second level signal with a certain width is injected into the input end of the digital input loop, that is to say, the actual input signal and the second level signal are simultaneously input into the input end of the digital input loop, when the digital input loop is normal, the signal of the output end of the digital input loop can change under the action of the second level signal, namely, the inversion level with a certain width appears once or periodically, and at the moment, whether the digital input loop is normal can be judged according to the factors such as the period width, the delay time and the like of the feedback output signal. Specifically, if the feedback output signal is unchanged from the actual output signal, that is, the injected second level signal is not active, it may be determined that the digital input loop is invalid, and faults such as open circuit, short circuit, etc. may exist; and if the feedback output signal is changed compared with the actual output signal by the injected second level signal, that is, an inverted level of a certain width is generated once or periodically, it can be judged that the digital input loop is normal.
In this way, according to the self-checking method for the digital input loop provided by the embodiment, the actual input signal of the digital input loop in normal operation is deduced to be the first level signal according to the actual output signal of the digital input loop, and the second level signal opposite to the first level signal is injected, so that whether the digital input loop is normal or not can be judged according to the feedback output signal. By the self-checking method, the self-checking can be completed no matter whether the actual input signal of the digital input loop is high level or low level, and the correctness and reliability of the loop can be pre-judged in advance under various working conditions of the digital input loop.
According to the self-checking method for the digital input loop, when the digital input loop is judged to be in fault, alarm prompt can be carried out, and when the digital loop is judged to be normal, long-term high-level signals/low-level signals in the feedback output signals can still be used as actual sampling signals of the digital input loop, and only high-level signals and low-level signals in a certain period in the feedback output signals are used as self-checking judging signals, namely the self-checking method does not influence the original sampling work of the digital input loop and does not generate the problems of misoperation and the like.
Correspondingly, the embodiment also provides a self-checking circuit of the digital input loop, the self-checking circuit comprises the digital input loop and a controller, the controller comprises an acquisition module, a processing module, an injection module and a judging module, wherein the acquisition module is used for acquiring an actual output signal of the digital input loop; the processing module is used for defining an actual input signal of the digital input loop as a first level signal according to the actual output signal; the injection module is used for injecting a second level signal with a certain width into the digital input loop, and the second level signal is opposite to the first level signal in state; the judging module is used for judging whether the digital input loop is normal or not according to the feedback output signal after the acquisition module acquires the feedback output signal of the digital input loop.
As shown in fig. 3, a specific embodiment of a self-checking circuit is provided, the self-checking circuit includes a digital input loop and a controller, the digital input loop includes an optocoupler U1, the optocoupler U1 includes a light emitting diode and an optocoupler triode, the cathode of the light emitting diode is grounded, and the anode is formed as an input end; the collector of the phototriode is connected with a power supply, the emitter is grounded through a resistor R4, and the collector is led out through a resistor R5 to form an output end.
When the digital input loop works normally, if the input end of the digital input loop is at a high level, the output end of the digital input loop is also at a high level; if the input end is low level, the output end is also low level, based on the digital input loop, as shown in fig. 4, when the digital input loop is in a low level state, a high level signal with a certain width is simulated and injected, so that accurate sampling can be ensured, specifically, the digital input loop is in a low level state, namely, the actual output signal is low level, but the actual input signal is not known to be high level or low level, at the moment, the simulation is injected into a high level with a certain width for testing, if the output signal of the digital input loop is unchanged, the sampling error is indicated, and the digital input loop has faults, such as the disconnection of a light emitting diode in an optical coupler U1; if the output signal of the digital input loop also changes to high level, then the sampling is correct when the high level is input; it is known from the back-extrapolation that if the actual input signal is at a high level, the output signal of the digital input loop changes to a high level as the analog injected high level, but the actual output signal is still at a low level, which means that the actual input signal is at a low level, i.e. the sampling is correct when the low level is input.
When the digital input loop is in a high level state, a low level signal with a certain width is simulated and injected so as to ensure correct sampling, specifically, the digital input loop is in a high level state, namely the actual output signal is in a high level state, but whether the actual input signal is in a high level or a low level is not known, at the moment, the simulation is injected into the low level with a certain width for testing, if the output signal of the digital input loop is unchanged, the sampling error is indicated, the digital input loop has faults, such as short circuit or insufficient insulation of a phototriode in an optocoupler U1, and the output is always in the high level; if the output signal of the digital input loop also changes to a low level, then the sampling is correct when the input signal is input at the low level; it is known from the back-extrapolation that if the actual input signal is low, the output signal of the digital input loop changes to low as the analog injected low, but the actual output signal is still high, which means that the actual input signal is high, i.e. the sampling is correct when the high input signal is inputted.
Further, the self-checking circuit further comprises a high-level injection circuit and a low-level injection circuit, when the controller collects that the actual output signal of the digital input circuit is high, the actual input signal of the digital input circuit is defined to be high, namely the first level signal is high, and at the moment, the controller injects low level with a certain width into the input end of the digital input circuit through the high-level injection circuit; when the controller collects that the actual output signal of the digital input loop is at a low level, the actual input signal of the digital input loop is defined to be at a low level, namely the first level signal is at a low level, and at the moment, the controller injects a high level with a certain width into the input end of the digital input loop through the high level injection circuit.
Specifically, the high-level injection circuit comprises a first photo-MOS relay V1, wherein the first photo-MOS relay V1 comprises a light emitting diode and an MOS tube, the light emitting diode is positioned at the input side, the anode of the light emitting diode is connected with a power supply through a resistor R1, the cathode of the light emitting diode is connected with a controller through a first tri-state device V3, the MOS tube is positioned at the output side, the source of the MOS tube is connected with the power supply, and the drain of the MOS tube is connected with the input end of a digital input loop, namely the input end of an optical coupler U1; the low-level injection circuit comprises a second photo MOS relay V2, the second photo MOS relay V2 comprises a light emitting diode and an MOS tube, wherein the light emitting diode is positioned at the input side, the anode of the light emitting diode is connected with a power supply through a resistor R2, the cathode of the light emitting diode is connected with the controller through a second tri-state device V4, the MOS tube is positioned at the output side, the source of the MOS tube is connected with the ground, and the drain of the MOS tube is connected with the input end of the digital input loop. In this embodiment, the photoMOS relay is used for isolation, and the power supplies at the input side and the output side of the photoMOS relay are not grounded together, so that the controller is protected. When the controller needs to inject high level, the controller sends low level to the first photo MOS relay V1 to enable the light emitting diode and the MOS tube to be conducted, and the controller injects high level to the input end of the digital input loop; when the controller needs to inject low level, the controller sends low level to the second photo MOS relay V2 to enable the light emitting diode MOS tube to be conducted, and the low level is injected to the input end of the digital input loop.
Further, the high-level injection circuit further comprises a first diode D1, wherein an anode of the first diode D1 is connected to an output end of the first photo MOS relay V1, namely a drain electrode of the MOS transistor thereof, and a cathode of the first diode D1 is connected to an input end of the digital input loop; the low-level injection circuit further comprises a second diode D2, the anode of the second diode D2 is connected to the input end of the digital input loop, the cathode of the second diode D2 is connected to the output end of the second photo MOS relay V2, namely the drain electrode of the MOS tube of the second photo MOS relay V, and the first diode D1 and the second diode D2 can play roles in inverse prevention and clamping. Further, the digital input circuit further includes a third diode D3, an anode of the third diode D3 inputs an actual input signal, a cathode of the third diode is connected to an input end of the optocoupler U1, and simultaneously connected to a cathode of the first diode D1 and an anode of the second diode D2, and the third triode D3 can play a role in preventing reverse.
Further, an inductor L1 is also arranged in the digital input loop, one end of the inductor L1 is connected with the anode of the third diode D3, and the other end of the inductor L1 is input with an actual input signal, so that the effect of stabilizing current can be achieved; the input side of the optical coupler U1 is also provided with a parallel resistor R3, which can play a role in resisting interference and preventing the optical coupler U1 from being turned on by mistake; filter capacitors C2 and C4 are also respectively disposed on the input side and the output side of the optocoupler U1. In addition, a current limiting resistor may be further disposed at the input end of the optocoupler U1 as required, for example, between the anode of the second diode D2 and the anode of the light emitting diode in the optocoupler U1.
Because the controller needs to be connected with the high-level injection circuit and the low-level injection circuit and occupies two GPIO ports, the decoder is arranged at the output end of the controller, the GPIO ports of the controller are expanded, and therefore the occupation of interface resources of the controller is reduced. In addition, when the number of the digital input loops is two or more, the controller needs to inject high level or low level into each digital input loop through a plurality of high level injection circuits and low level injection circuits respectively, so that more GPIO ports of the controller are needed to be occupied, and the output end of each digital input loop needs to be connected with different GPIO ports of the controller.
In summary, the self-checking method and the self-checking circuit for the digital input loop provided by the embodiment can perform self-checking on the validity of the digital input loop, expand the scene of validity judgment of the digital input loop, pre-judge the correctness and reliability of the loop in advance under various working conditions, and reduce the occupation of GPIO resources of a controller by arranging a decoder and an encoder.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing circuits, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above examples are only illustrative of the preferred embodiments of the present invention and are not intended to limit the scope of the present invention, and various modifications and improvements made by those skilled in the art to the technical solution of the present invention should fall within the scope of protection defined by the claims of the present invention without departing from the spirit of the design of the present invention.
Claims (10)
1. The self-checking method of the digital input loop is characterized by comprising the following steps of:
acquiring an actual output signal of a digital input loop, and defining the actual input signal of the digital input loop as a first level signal according to the actual output signal;
injecting a second level signal with a certain width into the digital input loop, wherein the second level signal is opposite to the first level signal in state;
and collecting a feedback output signal of the digital input loop, and judging whether the digital input loop is normal or not according to the feedback output signal.
2. The method of claim 1, wherein the first level signal is defined as an actual input signal of the digital input loop when the digital input loop is operating normally.
3. The method for self-checking a digital input loop according to claim 1, wherein determining whether the digital input loop is normal according to the feedback output signal comprises the steps of:
if the feedback output signal is unchanged compared with the actual output signal, judging that the digital input loop is abnormal;
if the feedback output signal is changed compared with the actual output signal due to the injected second level signal, the digital input loop is judged to be normal.
4. The method according to claim 1, wherein the long-term high-level signal/low-level signal in the feedback output signal is used as an actual sampling signal of the digital input loop.
5. A self-checking circuit of a digital input loop is characterized by comprising the digital input loop and a controller, wherein the controller comprises an acquisition module, a processing module, an injection module and a judging module,
the acquisition module is used for acquiring an actual output signal of the digital input loop;
the processing module is used for defining an actual input signal of the digital input loop as a first level signal according to the actual output signal;
the injection module is used for injecting a second level signal with a certain width into the digital input loop, and the second level signal is opposite to the first level signal in state;
the judging module is used for judging whether the digital input loop is normal or not according to the feedback output signal after the acquisition module acquires the feedback output signal of the digital input loop.
6. The self-test circuit of a digital input loop according to claim 5, further comprising a high level injection circuit and a low level injection circuit, wherein when the first level signal is high level, the controller injects a low level of a certain width into the digital input loop through the low level injection circuit; when the first level signal is at a low level, the controller injects a high level with a certain width into the digital input loop through the high level injection circuit;
the high-level injection circuit comprises a first photo MOS relay, wherein the input side of the first photo MOS relay is respectively connected with a power supply and the controller, and the output side of the first photo MOS relay is respectively connected with the power supply and the input end of the digital input loop; the low-level injection circuit comprises a second photo-MOS relay, wherein the input side of the second photo-MOS relay is respectively connected with a power supply and the controller, and the output side of the second photo-MOS relay is respectively connected with the ground and the input end of the digital input loop.
7. The self-test circuit of the digital input loop according to claim 6, wherein the high-level injection circuit further comprises a first diode, an anode of the first diode is connected to an output terminal of the first photo MOS relay, and a cathode of the first diode is connected to an input terminal of the digital input loop; the low-level injection circuit comprises a second diode, wherein the anode of the second diode is connected with the input end of the digital input loop, and the cathode of the second diode is connected with the output end of the second photo-MOS relay.
8. The self-test circuit of the digital input loop according to claim 7, wherein the digital input loop comprises an optocoupler and a third diode, an anode of the third diode inputs the actual input signal, and a cathode of the third diode is connected to an input terminal of the optocoupler, and simultaneously connected to a cathode of the first diode and an anode of the second diode.
9. The self-checking circuit of a digital input circuit according to claim 8, wherein the anode of the third diode is further connected with an inductor, the input side of the optocoupler is further provided with a parallel resistor, and the input side and the output side of the optocoupler are further provided with filter capacitors respectively.
10. The self-test circuit of a digital input loop according to claim 9, wherein a decoder is further provided between the controller and the input of the digital input loop; the number of the digital input loops is at least two, and an encoder is arranged between the output end of the digital input loop and the controller.
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| Publication number | Priority date | Publication date | Assignee | Title |
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