CN116742944A - H bridge driving circuit with single signal source - Google Patents
H bridge driving circuit with single signal source Download PDFInfo
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- CN116742944A CN116742944A CN202310622683.3A CN202310622683A CN116742944A CN 116742944 A CN116742944 A CN 116742944A CN 202310622683 A CN202310622683 A CN 202310622683A CN 116742944 A CN116742944 A CN 116742944A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
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- H02M1/385—Means for preventing simultaneous conduction of switches with means for correcting output voltage deviations introduced by the dead time
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Abstract
The invention discloses an H-bridge driving circuit with a single signal source, which comprises: the complementary PWM generating circuit, the first hardware dead zone control circuit and the second hardware dead zone control circuit; the complementary PWM generating circuit comprises a first exclusive OR gate circuit and a second exclusive OR gate circuit, and is used for converting a single PWM signal into two paths of complementary signals; the first hardware dead zone control circuit comprises a first inverter circuit, a first delay circuit, a second inverter circuit and a second delay circuit, and is used for outputting a first driving PWM signal and a second driving PWM signal to obtain a first dead zone control time; the second hardware dead zone control circuit comprises a third inverter circuit, a third delay circuit, a fourth inverter circuit and a fourth delay circuit, and is used for outputting a third driving PWM signal and a fourth driving PWM signal to obtain second dead zone control time. The invention can realize the work of a single PWM signal driving H bridge, and realizes the adjustable dead zone control time based on the cooperation of the inverter circuit and the delay circuit.
Description
Technical Field
The invention relates to the technical field of circuit design, in particular to an H-bridge driving circuit with a single signal source.
Background
The conventional H-bridge drive generally has the following schemes: firstly, the MCU or the DSP directly outputs four paths of PWM waveforms with complementary dead time, the scheme depends on the performance of the MCU or the DSP, at least occupies four IO ports, the MCU or the DSP has the least need to support 4 paths of PWM functions, the cost is high, and the risk of software running exists in the process of realizing based on software; secondly, the traditional hardware driving scheme generally needs an MCU or a DSP to directly output two paths of PWM waveforms, and the problem of high cost exists; thirdly, the integrated H-bridge driving scheme is low in working frequency, free change of dead time is impossible, and cost is high.
Disclosure of Invention
The invention aims to solve the technical problems that: the H-bridge driving circuit with the single signal source is provided, the work of a single PWM wave driving H-bridge is realized based on an exclusive OR gate circuit, an inverter circuit and a delay circuit, the hardware cost is reduced, and the dead time control is realized based on the inverter circuit matched with the delay circuit, so that the dead time control time is adjustable.
In order to solve the above technical problems, the present invention provides an H-bridge driving circuit with a single signal source, including: the complementary PWM generating circuit, the first hardware dead zone control circuit and the second hardware dead zone control circuit;
the complementary PWM generation circuit comprises a first exclusive-OR gate circuit and a second exclusive-OR gate circuit, and PWM signals are respectively input into the first exclusive-OR gate circuit and the second exclusive-OR gate circuit so as to obtain a first PWM signal and a second PWM signal, wherein the first PWM signal and the second PWM signal are complementary PWM signals;
the first hardware dead zone control circuit comprises a first inverter circuit, a first delay circuit, a second inverter circuit and a second delay circuit, wherein the first inverter circuit and the first delay circuit are used for carrying out inversion and delay processing on an input first PWM signal, outputting a first driving PWM signal, the second inverter circuit and the second delay circuit are used for carrying out inversion and delay processing on the input first PWM signal, outputting a second driving PWM signal, and the first dead zone control time is obtained based on the first delay time of the first driving PWM signal and the second delay time of the second driving PWM signal;
the second hardware dead zone control circuit comprises a third inverter circuit, a third delay circuit, a fourth inverter circuit and a fourth delay circuit, wherein the third inverter circuit and the third delay circuit are used for carrying out inversion and delay processing on an input second PWM signal, the third delay time is used for outputting a third driving PWM signal, the fourth inverter circuit and the fourth delay circuit are used for carrying out inversion and delay processing on the input second PWM signal, the fourth delay time is used for outputting a fourth driving PWM signal, and the third delay time of the third driving PWM signal and the fourth delay time of the fourth driving PWM signal are used for obtaining second dead zone control time.
In one embodiment, the first inverter circuit and the first delay circuit perform inversion and delay processing on the input first PWM signal, and output the first PWM signal to obtain a first driving PWM signal, which specifically includes:
and performing first inversion processing on the first PWM signal based on the first inverter circuit to obtain a first inversion PWM signal, performing delay processing on the first inversion PWM signal based on the first delay circuit to obtain a first delay PWM signal, and performing second inversion processing on the first delay PWM signal based on the first inverter circuit to obtain a first driving PWM signal.
In one embodiment, the first exclusive-or gate includes a first exclusive-or gate input terminal, a second exclusive-or gate input terminal, a first exclusive-or gate power supply terminal, a first exclusive-or gate output terminal, and a first resistor;
the first exclusive-or gate input end is connected with the PWM signal output end, the second exclusive-or gate input end is connected with the first end of the first resistor, and the second end of the first resistor and the first exclusive-or gate power end are respectively connected with a power supply.
In one embodiment, the second exclusive-or gate circuit includes a third exclusive-or gate input terminal, a fourth exclusive-or gate input terminal, a first exclusive-or gate ground terminal, and a second exclusive-or gate output terminal;
the third exclusive-or gate input end is connected with the PWM signal output end, and the fourth exclusive-or gate input end and the first exclusive-or gate grounding end are grounded.
In an embodiment, the first hardware dead zone control circuit includes a first inverter circuit and a first delay circuit, wherein the first inverter circuit includes a first inverter input terminal, a first inverter output terminal, a second inverter input terminal and a second inverter output terminal, and the first delay circuit includes a first diode, a second resistor and a first capacitor;
the first inverter input end is connected with the second exclusive-or gate output end, the first inverter output end is connected with the negative electrode of the first diode and the first end of the second resistor respectively, the positive electrode of the first diode is connected with the second end of the second resistor, the first end of the first capacitor is connected with the positive electrode of the first diode and the second end of the second resistor respectively, the second end of the first capacitor is grounded, and the second inverter input end is connected with the first end of the first capacitor, the positive electrode of the first diode and the second end of the second resistor respectively.
In an embodiment, the first hardware dead zone control circuit includes a second inverter circuit and a second delay circuit, where the second inverter circuit includes a third inverter input terminal, a third inverter output terminal, a fourth inverter input terminal, and a fourth inverter output terminal, and the second delay circuit includes a second diode, a third resistor, and a second capacitor;
the third inverter input end is connected with the second exclusive-or gate output end, the third inverter output end is connected with the positive electrode of the second diode and the first end of the third resistor respectively, the negative electrode of the second diode is connected with the second end of the third resistor, the first end of the second capacitor is connected with the negative electrode of the second diode and the second end of the third resistor respectively, the second end of the second capacitor is grounded, and the fourth inverter input end is connected with the first end of the second capacitor, the negative electrode of the second diode and the second end of the third resistor respectively.
In an embodiment, the second hardware dead zone control circuit includes a third inverter circuit and a third delay circuit, where the third inverter circuit includes a fifth inverter input terminal, a fifth inverter output terminal, a sixth inverter input terminal, and a sixth inverter output terminal, and the third delay circuit includes a third diode, a fourth resistor, and a third capacitor;
the input end of the fifth inverter is connected with the output end of the first exclusive-or gate, the output end of the fifth inverter is respectively connected with the negative electrode of the third diode and the first end of the fourth resistor, the positive electrode of the third diode is connected with the second end of the fourth resistor, the first end of the third capacitor is respectively connected with the positive electrode of the third diode and the second end of the fourth resistor, the second end of the third capacitor is grounded, and the input end of the sixth inverter is respectively connected with the first end of the third capacitor, the positive electrode of the third diode and the second end of the fourth resistor.
In an embodiment, the second hardware dead zone control circuit includes a fourth inverter circuit and a fourth delay circuit, where the fourth inverter circuit includes a seventh inverter input terminal, a seventh inverter output terminal, an eighth inverter input terminal, and an eighth inverter output terminal, and the fourth delay circuit includes a fourth diode, a fifth resistor, and a fourth capacitor;
the input end of the seventh inverter is connected with the output end of the first exclusive-or gate, the output end of the seventh inverter is respectively connected with the positive electrode of the fourth diode and the first end of the fifth resistor, the negative electrode of the fourth diode is connected with the second end of the fifth resistor, the first end of the fourth capacitor is respectively connected with the negative electrode of the fourth diode and the second end of the fifth resistor, the second end of the fourth capacitor is grounded, and the input end of the eighth inverter is respectively connected with the first end of the fourth capacitor, the negative electrode of the fourth diode and the second end of the fifth resistor.
In an embodiment, the invention provides an H-bridge driving circuit with a single signal source, which further comprises an H-bridge inverter circuit, wherein the H-bridge inverter circuit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor.
In an embodiment, the first driving PWM signal is used for driving the first MOS transistor, the second driving PWM signal is used for driving the second MOS transistor, the third driving PWM signal is used for driving the third MOS transistor, and the fourth driving PWM signal is used for driving the fourth MOS transistor.
Compared with the prior art, the H-bridge driving circuit with the single signal source has the following beneficial effects:
the H-bridge driving circuit comprises a complementary PWM generating circuit, a first hardware dead zone control circuit and a second hardware dead zone control circuit; the complementary PWM generating circuit comprises a first exclusive OR gate circuit and a second exclusive OR gate circuit, and is used for converting a single PWM signal into two paths of complementary signals; the first hardware dead zone control circuit comprises a first inverter circuit, a first delay circuit, a second inverter circuit and a second delay circuit, wherein the first inverter circuit and the first delay circuit are used for outputting a first driving PWM signal, the second inverter circuit and the second delay circuit are used for outputting a second driving PWM signal, and the first dead zone control time is obtained based on the first delay time of the first driving PWM signal and the second delay time of the second driving PWM signal; the second hardware dead zone control circuit comprises a third inverter circuit, a third delay circuit, a fourth inverter circuit and a fourth delay circuit, wherein the third inverter circuit and the third delay circuit are based on outputting a third driving PWM signal, the fourth inverter circuit and the fourth delay circuit are based on outputting a fourth driving PWM signal, and the fourth dead zone control time is obtained based on the third delay time of the third driving PWM signal and the fourth delay time of the fourth driving PWM signal. Compared with the prior art, the technical scheme of the invention realizes that a single PWM wave drives the H bridge to work based on the exclusive OR gate circuit, the inverter circuit and the delay circuit, reduces the hardware cost, and realizes that the dead time control time is adjustable based on the inverter circuit and the delay circuit.
Drawings
FIG. 1 is a schematic diagram of an embodiment of an H-bridge driving circuit with a single signal source according to the present invention;
FIG. 2 is a schematic diagram of a complementary PWM generation circuit according to one embodiment of the present invention;
FIG. 3 is an exclusive OR gate truth value representative intent of one embodiment provided by the present invention;
FIG. 4 is a schematic diagram of a first hardware dead zone control circuit configuration of one embodiment provided by the present invention;
FIG. 5 is a schematic diagram of a second hardware dead zone control circuit configuration of one embodiment provided by the present invention;
fig. 6 is a schematic diagram of inverter parameters according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a single-signal-source H-bridge driving circuit according to the present invention, and as shown in fig. 1, the circuit includes a complementary PWM generating circuit 11, a first hardware dead zone control circuit 12, and a second hardware dead zone control circuit 13, specifically as follows:
the complementary PWM generation circuit 11 includes a first exclusive or gate 111 and a second exclusive or gate 112, and inputs PWM signals into the first exclusive or gate 111 and the second exclusive or gate 112, respectively, so as to obtain a first PWM signal and a second PWM signal, where the first PWM signal and the second PWM signal are complementary PWM signals.
The first hardware dead zone control circuit 12 includes a first inverter circuit 121, a first delay circuit 122, a second inverter circuit 123, and a second delay circuit 124, performs inversion and delay processing on an input first PWM signal based on the first inverter circuit 121 and the first delay circuit 122, outputs a first driving PWM signal, performs inversion and delay processing on the input first PWM signal based on the second inverter circuit 123 and the second delay circuit 124, outputs a second driving PWM signal, and obtains a first dead zone control time based on a first delay time of the first driving PWM signal and a second delay time of the second driving PWM signal.
The second hardware dead zone control circuit 13 includes a third inverter circuit 131, a third delay circuit 132, a fourth inverter circuit 133, and a fourth delay circuit 134, performs inversion and delay processing on the input second PWM signal based on the third inverter circuit 131 and the third delay circuit 132, outputs a third driving PWM signal based on a third delay time, performs inversion and delay processing on the input second PWM signal based on the fourth inverter circuit 133 and the fourth delay circuit 134, outputs a fourth driving PWM signal based on a fourth delay time, and obtains a second dead zone control time based on the third delay time of the third driving PWM signal and the fourth delay time of the fourth driving PWM signal.
In one embodiment, the complementary PWM generating circuit 11 includes a first xor gate 111 and a second xor gate 112, as shown in fig. 2, and fig. 2 is a schematic structural diagram of the complementary PWM generating circuit.
In one embodiment, the complementary PWM generating circuit 11 further includes a PWM signal output terminal for outputting a PWM signal.
In one embodiment, the first exclusive-or circuit 111 includes a first exclusive-or gate input terminal 1A, a second exclusive-or gate input terminal 1B, a first exclusive-or gate power supply terminal VCC, a first exclusive-or gate output terminal 1Y, and the first resistor R1; the first exclusive-or gate input end 1A is connected with the PWM signal output end, the second exclusive-or gate input end 1B is connected with the first end of the first resistor R1, the second end of the first resistor R1 and the first exclusive-or gate power supply end VCC are respectively connected with a power supply, and the first exclusive-or gate output end 1Y is used for outputting a first PWM signal.
In one embodiment, the second exclusive-or gate 112 includes a third exclusive-or gate input 2A, a fourth exclusive-or gate input 2B, a first exclusive-or gate ground GND, and a second exclusive-or gate output 2Y; the third exclusive-or gate input end 2A is connected to the PWM signal output end, the fourth exclusive-or gate input end 2B is grounded to the first exclusive-or gate ground end GND, and the second exclusive-or gate output end 2Y is configured to output a second PWM signal.
In an embodiment, as can be seen from the schematic diagram of the complementary PWM generation circuit, since the PWM signals are input to the input terminals 1A and 2A of the two-way exclusive-or gate circuit respectively based on the PWM output terminals, and the other input terminals 1B and 2B of the two-way exclusive-or gate circuit are connected to the power supply and the ground respectively, the output terminals 1Y and 2Y of the two-way exclusive-or gate circuit can output two complementary PWM waveforms, as shown in fig. 3, fig. 3 is an exclusive-or gate true value indicating the intention; and because the two complementary PWM signals are converted by the exclusive-OR gate, the two complementary PWM signals have the same time delay and have small phase difference.
In one embodiment, two paths of first PWM signals and second PWM signals, which are complementary and phase-synchronized, are output by the complementary PWM generating circuit 11, wherein one path of signals enters the first hardware dead zone control circuit 12, and the other path of PWM signals enters the second hardware dead zone control circuit. Preferably, the first PWM signal may be set to enter the first hardware dead zone control circuit 12 and the second PWM signal may be set to perform the second hardware dead zone control circuit, or the first PWM signal may be set to enter the second hardware dead zone control circuit and the second PWM signal may be set to perform the first hardware control circuit.
In one embodiment, the first hardware dead zone control circuit 12 includes a first inverter circuit 121, a first delay circuit 122, a second inverter circuit 123, and a second delay circuit 124, as shown in fig. 4, and fig. 4 is a schematic diagram of the first hardware dead zone control circuit.
In one embodiment, the first inverter circuit 121 includes a first inverter input terminal 1211, a first inverter output terminal 1212, a second inverter input terminal 1213, and a second inverter output terminal 1214, and the first delay circuit 122 includes a first diode D1, a second resistor R2, and a first capacitor C1.
In an embodiment, the first inverter input terminal 1211 is connected to the second exclusive-or gate output terminal 2Y, the first inverter output terminal 1212 is connected to the negative electrode of the first diode D1 and the first end of the second resistor R2, the positive electrode of the first diode D1 is connected to the second end of the second resistor R2, the first end of the first capacitor C1 is connected to the positive electrode of the first diode D1 and the second end of the second resistor R2, the second end of the first capacitor C1 is grounded, and the second inverter input terminal 1213 is connected to the first end of the first capacitor C1, the positive electrode of the first diode D1, and the second end of the second resistor R2.
In an embodiment, the first inverter circuit 121 and the first delay circuit 122 perform inversion and delay processing on the input first PWM signal, and output the first PWM signal to obtain a first driving PWM signal, specifically, perform first inversion processing on the first PWM signal based on the first inverter circuit 121 to obtain a first inverted PWM signal, perform delay processing on the first inverted PWM signal based on the first delay circuit 122 to obtain a first delayed PWM signal, and perform second inversion processing on the first delayed PWM signal based on the first inverter circuit 121 to obtain the first driving PWM signal.
In one embodiment, the second inverter circuit 123 includes a third inverter input terminal 1231, a third inverter output terminal 1232, a fourth inverter input terminal 1233, and a fourth inverter output terminal 1234, and the second delay circuit 124 includes a second diode D2, a third resistor R3, and a second capacitor C2.
In an embodiment, the third inverter input end 1231 is connected to the second exclusive-or gate output end 2Y, the third inverter output end 1232 is connected to the positive electrode of the second diode D2 and the first end of the third resistor R3, the negative electrode of the second diode D2 is connected to the second end of the third resistor R3, the first end of the second capacitor C2 is connected to the negative electrode of the second diode D2 and the second end of the third resistor R3, the second end of the second capacitor C2 is grounded, and the fourth inverter input end 1233 is connected to the first end of the second capacitor C2, the negative electrode of the second diode D2, and the second end of the third resistor R3.
In an embodiment, the second inverter circuit 123 and the second delay circuit 124 perform inversion and delay processing on the input first PWM signal, and output the first PWM signal to obtain a second driving PWM signal, specifically, perform third inversion processing on the first PWM signal based on the second inverter circuit 123 to obtain a second inverted PWM signal, perform delay processing on the second inverted PWM signal based on the second delay circuit 124 to obtain a second delayed PWM signal, and perform fourth inversion processing on the second delayed PWM signal based on the second inverter circuit 123 to obtain the second driving PWM signal.
In one embodiment, the second hardware dead zone control circuit 13 includes a third inverter circuit 131, a third delay circuit 132, a fourth inverter circuit 133 and a fourth delay circuit 134, as shown in fig. 5, and fig. 5 is a schematic diagram of the second hardware dead zone control circuit.
In one embodiment, the third inverter circuit 131 includes a fifth inverter input 1311, a fifth inverter output 1312, a sixth inverter input 1313, and a sixth inverter output 1314, and the third delay circuit 132 includes a third diode D3, a fourth resistor R4, and a third capacitor C3.
In an embodiment, the fifth inverter input terminal 1311 is connected to the first exclusive-or gate output terminal 1Y, the fifth inverter output terminal 1312 is connected to the negative electrode of the third diode D3 and the first end of the fourth resistor R4, the positive electrode of the third diode D3 is connected to the second end of the fourth resistor R4, the first end of the third capacitor C3 is connected to the positive electrode of the third diode D3 and the second end of the fourth resistor R4, the second end of the third capacitor C3 is grounded, and the sixth inverter input terminal 1313 is connected to the first end of the third capacitor C3, the positive electrode of the third diode D3, and the second end of the fourth resistor R4.
In an embodiment, the third inverter circuit 131 and the third delay circuit 132 perform inversion and delay processing on the input second PWM signal, and output the second PWM signal to obtain a third driving PWM signal, specifically, perform fifth inversion processing on the second PWM signal based on the third inverter circuit 131 to obtain a third inverted PWM signal, perform delay processing on the third inverted PWM signal based on the third delay circuit 132 to obtain a third delayed PWM signal, and perform sixth inversion processing on the third delayed PWM signal based on the third inverter circuit 131 to obtain the third driving PWM signal.
In one embodiment, the fourth inverter circuit 133 includes a seventh inverter input 1331, a seventh inverter output 1332, an eighth inverter input 1333, and an eighth inverter output 1334, and the fourth delay circuit includes a fourth diode D4, a fifth resistor R5, and a fourth capacitor C4.
In an embodiment, the seventh inverter input end 1331 is connected to the first exclusive-or gate output end 1Y, the seventh inverter output end 1332 is connected to the positive electrode of the fourth diode D4 and the first end of the fifth resistor R5, the negative electrode of the fourth diode D4 is connected to the second end of the fifth resistor R5, the first end of the fourth capacitor C4 is connected to the negative electrode of the fourth diode D4 and the second end of the fifth resistor R5, the second end of the fourth capacitor C4 is grounded, and the eighth inverter input end 1333 is connected to the first end of the fourth capacitor C4, the negative electrode of the fourth diode D4, and the second end of the fifth resistor R5.
In an embodiment, the fourth inverter circuit 133 and the fourth delay circuit 134 perform inversion and delay processing on the input second PWM signal, and output the second PWM signal to obtain a fourth driving PWM signal, specifically, perform seventh inversion processing on the second PWM signal based on the fourth inverter circuit 133 to obtain a fourth inverted PWM signal, perform delay processing on the fourth inverted PWM signal based on the fourth delay circuit 134 to obtain a fourth delayed PWM signal, and perform fourth inversion processing on the fourth delayed PWM signal based on the fourth inverter circuit 133 to obtain a fourth driving PWM signal.
The first hardware dead zone control circuit 12 can be applied to a wireless charging function of a hearing aid charging bin, and the working process of the first hardware dead zone control circuit 12 is described as follows:
in one embodiment, for the first inverter circuit 121 and the first delay circuit 122: the first PWM signal output by the second exclusive or gate output end 2Y is input to the first inverter circuit 121 based on the first inverter input end 1211, the first inverted PWM signal is output based on the first inverter output end 1212, and the output first inverted PWM signal is connected to the second inverter circuit 123 through the first delay circuit 122 including the second resistor R2, the first capacitor C1, and the first diode D1, so that the second inverter circuit 123 shapes the waveform of the first inverted PWM signal into a square wave as the final first driving PWM signal, and the overshoot problem of the output waveform is avoided.
When the first PWM signal input by the first inverter input terminal 1211 is a low level signal, the first inverted PWM signal output by the first inverter circuit 121 is a high level signal, and at this time, the first capacitor C1 in the first delay circuit 122 needs to be charged, so the first capacitor C1 needs to be charged through the first inverter output terminal 1212, and the first inverter output terminal 1212 cannot be suddenly changed, and at this time, the voltage waveform of the first capacitor C1 is in a slow sine-wave-like rising curve.
When the first PWM signal input by the first inverter input terminal 1211 is a high level signal, the first inverted PWM signal output by the first inverter circuit 121 is a low level signal, and at this time, the first capacitor C1 in the first delay circuit 122 needs to be discharged, so the first inverter output terminal 1212 needs to be discharged through the first capacitor C1, and the first inverter output terminal 1212 cannot be suddenly changed, and at this time, the voltage waveform of the first capacitor C1 is in a slow sine-wave-like falling curve.
When the first inverter output terminal 1212 charges the first capacitor C1, the first diode D1 is turned off in an inverted state, and thus a current flows through the second resistor R2; when the first capacitor C1 discharges the first inverter output 1212, the first diode D1 flows forward, and thus a current flows through the first diode D1, and thus the voltage waveform of the capacitor thereof exhibits a characteristic of slow rise and fast fall for the first inverter circuit 121 and the first delay circuit 122.
As can be seen, in the first inverter circuit 121 and the first delay circuit 122, when the input first PWM signal is a high level signal, the output first driving PWM signal is turned over along with the first PWM signal while the signal is turned over based on the characteristic of slow rise and fast fall thereof; when the input first PWM signal is a low level signal, the output first driving PWM signal will generate a response of a first delay time to the inversion of the first PWM signal, where the first delay time is a rising edge delay time of the first driving PWM signal.
In one embodiment, the calculation formula of the first delay time is as follows:
in U tH High-level minimum input voltage U for inverter IHmin ，U t0 Low-level minimum output voltage U for inverter OLmin ，U O High-level minimum output voltage U of inverter OHmin The inverter parameters may be selected based on fig. 6, and fig. 6 is a schematic diagram of inverter parameters.
In one embodiment, for the second inverter circuit 123 and the second delay circuit 124: when the first PWM signal input from the third inverter input terminal 1231 is a low level signal, the second inverted PWM signal output from the second inverter circuit 123 is a high level signal, and at this time, the second capacitor C2 in the second delay circuit 124 needs to be charged, so the second capacitor C2 needs to be charged through the third inverter output terminal 1232, and the third inverter output terminal 1232 cannot be suddenly changed, and at this time, the voltage waveform of the second capacitor C2 is in a slow sine-wave-like rising curve.
When the first PWM signal input from the third inverter input terminal 1231 is a high level signal, the second inverted PWM signal output from the second inverter circuit 123 is a low level signal, and at this time, the second capacitor C2 in the second delay circuit 124 needs to be discharged, so the third inverter output terminal 1232 needs to be discharged through the second capacitor C2, and the second inverter output terminal 1232 cannot be suddenly changed, and at this time, the voltage waveform of the second capacitor C2 is in a slow sine-wave-like falling curve.
When the second capacitor C2 discharges the third inverter output 1232, the second diode D2 is turned off in reverse phase, and thus a current flows through the third resistor R3; when the third inverter output 1232 charges the second capacitor C2, the second diode D2 flows forward, and thus a current flows through the second diode D2, and thus the voltage waveform of the capacitor of the second inverter circuit 123 and the second delay circuit 124 is characterized by a fast-slow-rise characteristic.
As can be seen, in the second inverter circuit 123 and the second delay circuit 124, when the input first PWM signal is a low level signal, the output second driving PWM signal is turned over along with the first PWM signal while the signal is turned over based on the characteristic of the fast and slow of the fast; when the input first PWM signal is a high-level signal, the output second driving PWM signal can generate a response of a second delay time to the inversion of the first PWM signal along with the signal inversion of the first PWM signal, wherein the response of the second delay time is the falling edge delay time of the second driving PWM signal.
In one embodiment, the calculation formula of the second delay time is as follows:
in U tL Low-level highest input voltage U for inverter ILmax ，U t0 Low-level minimum output voltage U for inverter OLmin ，U I High-level minimum input voltage U for inverter IHmin The inverter parameters may be selected based on fig. 6, and fig. 6 is a schematic diagram of inverter parameters.
In one embodiment, the dead time of the first hardware dead time control circuit 12 is the sum of the first delay time and the second delay time; and based on the calculation formulas of the first delay time and the second delay time, the dead time can be adjusted by changing the parameters of the resistor and the capacitor in the circuit, so that the dead time can be controlled more conveniently.
In one embodiment, the two driving PWM signals output by the first hardware dead zone control circuit 12 can be controlled to have a fixed dead zone time by matching the difference of the threshold voltage limit value of the inverter and the rising and falling speed of the capacitor voltage.
In one embodiment, the second hardware dead zone control circuit has the same circuit structure as the first hardware dead zone control circuit 12, and the operation processes of the two are the same, so that detailed description thereof will not be provided here.
In an embodiment, the device further comprises an H-bridge inverter circuit, wherein the H-bridge inverter circuit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor, specifically, the first MOS transistor and the third MOS transistor are PMOS transistors, the second MOS transistor and the fourth MOS transistor are NMOS transistors, the PMOS transistors are low-level conduction, and the NMOS transistors are high-level conduction.
In an embodiment, the first driving PWM signal is used for driving the first MOS transistor, the second driving PWM signal is used for driving the second MOS transistor, the third driving PWM signal is used for driving the third MOS transistor, and the fourth driving PWM signal is used for driving the fourth MOS transistor; the single PWM signal is driven to open or close the multipath MOS tube through the H-bridge driving circuit.
In summary, the invention discloses an H-bridge driving circuit with a single signal source, a complementary PWM generating circuit, a first hardware dead zone control circuit and a second hardware dead zone control circuit; the complementary PWM generating circuit comprises a first exclusive OR gate circuit and a second exclusive OR gate circuit, and is used for converting a single PWM signal into two paths of complementary signals; the first hardware dead zone control circuit comprises a first inverter circuit, a first delay circuit, a second inverter circuit and a second delay circuit, and is used for outputting a first driving PWM signal and a second driving PWM signal to obtain a first dead zone control time; the second hardware dead zone control circuit comprises a third inverter circuit, a third delay circuit, a fourth inverter circuit and a fourth delay circuit, and is used for outputting a third driving PWM signal and a fourth driving PWM signal to obtain second dead zone control time. The invention can realize the work of a single PWM signal driving H bridge, and realizes the adjustable dead zone control time based on the cooperation of the inverter circuit and the delay circuit.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and substitutions can be made by those skilled in the art without departing from the technical principles of the present invention, and these modifications and substitutions should also be considered as being within the scope of the present invention.
Claims (10)
1. An H-bridge driver circuit of a single signal source, comprising: the complementary PWM generating circuit, the first hardware dead zone control circuit and the second hardware dead zone control circuit;
the complementary PWM generation circuit comprises a first exclusive-OR gate circuit and a second exclusive-OR gate circuit, and PWM signals are respectively input into the first exclusive-OR gate circuit and the second exclusive-OR gate circuit so as to obtain a first PWM signal and a second PWM signal, wherein the first PWM signal and the second PWM signal are complementary PWM signals;
the first hardware dead zone control circuit comprises a first inverter circuit, a first delay circuit, a second inverter circuit and a second delay circuit, wherein the first inverter circuit and the first delay circuit are used for carrying out inversion and delay processing on an input first PWM signal, outputting a first driving PWM signal, the second inverter circuit and the second delay circuit are used for carrying out inversion and delay processing on the input first PWM signal, outputting a second driving PWM signal, and the first dead zone control time is obtained based on the first delay time of the first driving PWM signal and the second delay time of the second driving PWM signal;
the second hardware dead zone control circuit comprises a third inverter circuit, a third delay circuit, a fourth inverter circuit and a fourth delay circuit, wherein the third inverter circuit and the third delay circuit are used for carrying out inversion and delay processing on an input second PWM signal, the third delay time is used for outputting a third driving PWM signal, the fourth inverter circuit and the fourth delay circuit are used for carrying out inversion and delay processing on the input second PWM signal, the fourth delay time is used for outputting a fourth driving PWM signal, and the third delay time of the third driving PWM signal and the fourth delay time of the fourth driving PWM signal are used for obtaining second dead zone control time.
2. The H-bridge driving circuit with single signal source according to claim 1, wherein the first inverter circuit and the first delay circuit perform inversion and delay processing on the input first PWM signal, and output the first PWM signal to obtain the first driving PWM signal, and the method specifically comprises:
and performing first inversion processing on the first PWM signal based on the first inverter circuit to obtain a first inversion PWM signal, performing delay processing on the first inversion PWM signal based on the first delay circuit to obtain a first delay PWM signal, and performing second inversion processing on the first delay PWM signal based on the first inverter circuit to obtain a first driving PWM signal.
3. The H-bridge driver circuit of claim 1, wherein the first exclusive-or gate circuit comprises a first exclusive-or gate input, a second exclusive-or gate input, a first exclusive-or gate power supply, a first exclusive-or gate output, and a first resistor;
the first exclusive-or gate input end is connected with the PWM signal output end, the second exclusive-or gate input end is connected with the first end of the first resistor, and the second end of the first resistor and the first exclusive-or gate power end are respectively connected with a power supply.
4. The H-bridge driver circuit of claim 1, wherein the second exclusive-or gate circuit comprises a third exclusive-or gate input, a fourth exclusive-or gate input, a first exclusive-or gate ground, and a second exclusive-or gate output;
the third exclusive-or gate input end is connected with the PWM signal output end, and the fourth exclusive-or gate input end and the first exclusive-or gate grounding end are grounded.
5. The single source H-bridge driver circuit of claim 4, wherein the first hardware dead zone control circuit comprises a first inverter circuit comprising a first inverter input, a first inverter output, a second inverter input, and a second inverter output, a first delay circuit comprising a first diode, a second resistor, a first capacitor;
the first inverter input end is connected with the second exclusive-or gate output end, the first inverter output end is connected with the negative electrode of the first diode and the first end of the second resistor respectively, the positive electrode of the first diode is connected with the second end of the second resistor, the first end of the first capacitor is connected with the positive electrode of the first diode and the second end of the second resistor respectively, the second end of the first capacitor is grounded, and the second inverter input end is connected with the first end of the first capacitor, the positive electrode of the first diode and the second end of the second resistor respectively.
6. The H-bridge driving circuit with single signal source according to claim 4, wherein the first hardware dead zone control circuit comprises a second inverter circuit and a second delay circuit, wherein the second inverter circuit comprises a third inverter input terminal, a third inverter output terminal, a fourth inverter input terminal and a fourth inverter output terminal, and the second delay circuit comprises a second diode, a third resistor and a second capacitor;
the third inverter input end is connected with the second exclusive-or gate output end, the third inverter output end is connected with the positive electrode of the second diode and the first end of the third resistor respectively, the negative electrode of the second diode is connected with the second end of the third resistor, the first end of the second capacitor is connected with the negative electrode of the second diode and the second end of the third resistor respectively, the second end of the second capacitor is grounded, and the fourth inverter input end is connected with the first end of the second capacitor, the negative electrode of the second diode and the second end of the third resistor respectively.
7. The single source H-bridge driver circuit of claim 3, wherein the second hardware dead zone control circuit comprises a third inverter circuit comprising a fifth inverter input, a fifth inverter output, a sixth inverter input, and a sixth inverter output, a third delay circuit comprising a third diode, a fourth resistor, a third capacitor;
the input end of the fifth inverter is connected with the output end of the first exclusive-or gate, the output end of the fifth inverter is respectively connected with the negative electrode of the third diode and the first end of the fourth resistor, the positive electrode of the third diode is connected with the second end of the fourth resistor, the first end of the third capacitor is respectively connected with the positive electrode of the third diode and the second end of the fourth resistor, the second end of the third capacitor is grounded, and the input end of the sixth inverter is respectively connected with the first end of the third capacitor, the positive electrode of the third diode and the second end of the fourth resistor.
8. The single source H-bridge driver circuit of claim 3, wherein the second hardware dead zone control circuit comprises a fourth inverter circuit and a fourth delay circuit, wherein the fourth inverter circuit comprises a seventh inverter input, a seventh inverter output, an eighth inverter input, and an eighth inverter output, and wherein the fourth delay circuit comprises a fourth diode, a fifth resistor, and a fourth capacitor;
the input end of the seventh inverter is connected with the output end of the first exclusive-or gate, the output end of the seventh inverter is respectively connected with the positive electrode of the fourth diode and the first end of the fifth resistor, the negative electrode of the fourth diode is connected with the second end of the fifth resistor, the first end of the fourth capacitor is respectively connected with the negative electrode of the fourth diode and the second end of the fifth resistor, the second end of the fourth capacitor is grounded, and the input end of the eighth inverter is respectively connected with the first end of the fourth capacitor, the negative electrode of the fourth diode and the second end of the fifth resistor.
9. The H-bridge driving circuit of claim 1, further comprising an H-bridge inverter circuit, wherein the H-bridge inverter circuit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor.
10. The H-bridge driving circuit of claim 9, wherein the first driving PWM signal is used to drive the first MOS transistor, the second driving PWM signal is used to drive the second MOS transistor, the third driving PWM signal is used to drive the third MOS transistor, and the fourth driving PWM signal is used to drive the fourth MOS transistor.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310622683.3A CN116742944A (en) | 2023-05-30 | 2023-05-30 | H bridge driving circuit with single signal source |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310622683.3A CN116742944A (en) | 2023-05-30 | 2023-05-30 | H bridge driving circuit with single signal source |
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| CN116742944A true CN116742944A (en) | 2023-09-12 |
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| CN202310622683.3A Pending CN116742944A (en) | 2023-05-30 | 2023-05-30 | H bridge driving circuit with single signal source |
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- 2023-05-30 CN CN202310622683.3A patent/CN116742944A/en active Pending
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