CN116741121A

CN116741121A - Display control system, electronic device and display method

Info

Publication number: CN116741121A
Application number: CN202310710143.0A
Authority: CN
Inventors: 文亮
Original assignee: Vivo Mobile Communication Co Ltd
Current assignee: Vivo Mobile Communication Co Ltd
Priority date: 2023-06-14
Filing date: 2023-06-14
Publication date: 2023-09-12

Abstract

The application discloses a display control system, electronic equipment and a display method. The system comprises a display screen and a DPU; the display screen comprises a DDIC, a control circuit, N display areas and N driving circuits; the DPU comprises a first processing module; the DDIC is connected between the first processing module and the N driving circuits; n driving circuits are in one-to-one correspondence with N display areas; the control circuit is respectively connected with the N driving circuits; the first processing module determines a first image according to the layer information and sends the first image to the DDIC, wherein the first image comprises N sub-areas, the N sub-areas are in one-to-one correspondence with the N display areas, and the frame rates of the sub-areas and the corresponding display areas are the same; the DDIC drives N driving circuits to refresh the corresponding sub-areas in the first image to the corresponding display areas, and the control circuit is used for controlling the target driving circuit to execute a first operation, wherein the first operation comprises the following steps: and refreshing the target display area according to a first frame rate, wherein the first frame rate is the frame rate of the target display area.

Description

Display control system, electronic device and display method

Technical Field

The application belongs to the technical field of display screen control, and particularly relates to a display control system, electronic equipment and a display method.

Background

In the related art, image contents of two different frame rates can be displayed on one electronic device, for example: 120hz refreshed image content a is displayed on the left side of the same display screen and 30hz refreshed image content B is displayed on the right side. However, since the display content on the same display screen is refreshed as a whole, that is, the image content a and the image content B are refreshed at 120hz, the image content B will generate a repeated frame rate, which results in an increase of power consumption of the electronic device.

Disclosure of Invention

The embodiment of the application aims to provide a display control system, electronic equipment and a display method, which can refresh different display areas on a display screen according to respective corresponding frame rates and can reduce the energy consumption of the electronic equipment.

In a first aspect, an embodiment of the present application provides a display control system, including: the display screen and the display processing unit DPU are connected with each other;

the display screen includes: the display driving chip DDIC, the control circuit, N display areas and N driving circuits, wherein N is an integer greater than 1;

the DPU comprises a first processing module;

The DDIC is connected between the first processing module and N driving circuits;

n driving circuits are in one-to-one correspondence with N display areas;

the control circuit is respectively connected with the N driving circuits;

the first processing module is used for determining a first image according to image layer information and sending the first image to the DDIC, the first image comprises N sub-areas, N sub-areas are in one-to-one correspondence with N display areas, and the frame rates of the sub-areas and the corresponding display areas are the same;

the DDIC is configured to drive N driving circuits to refresh respective corresponding sub-regions in the first image to corresponding display regions, and the control circuit is configured to control the target driving circuit to perform a first operation, where the first operation includes: and refreshing a target display area according to a first frame rate, wherein the first frame rate is the frame rate of the target display area, N driving circuits comprise the target driving circuits, N display areas comprise the target display area, and the target driving circuits correspond to the target display area.

In a second aspect, an embodiment of the present application provides a display control system, including: the display screen and the display processing unit DPU are connected with each other;

the DPU comprises M processing paths, wherein M is a positive integer;

the DDIC is connected between the processing path and the N driving circuits;

n driving circuits are in one-to-one correspondence with N display areas;

the control circuit is respectively connected with the N driving circuits;

the processing paths are used for acquiring layer information, processing the layer information in parallel to obtain N second images, and sending the N second images to the DDIC;

the DDIC is configured to send a target second image to a target driving circuit, and the control circuit is configured to control the target driving circuit to perform a first operation including: refreshing a target display area according to a first frame rate, wherein the first frame rate is the frame rate of the target display area, the frame rate of the target second image is the same as the frame rate of the target display area, N second images comprise the target second image, N driving circuits comprise the target driving circuits, N display areas comprise the target display area, and the target driving circuits correspond to the target display area.

In a third aspect, an embodiment of the present application provides a display control system, including: the display screen and the display processing unit DPU are connected with each other;

the DPU comprises M processing paths and a first processing module, wherein the M processing paths are connected with the first processing module, and M is a positive integer;

n driving circuits are in one-to-one correspondence with N display areas;

the control circuit is respectively connected with the N driving circuits;

the processing method comprises the steps that M processing paths are used for obtaining layer information, parallel processing or serial processing is carried out on the layer information, and a first processing module is used for carrying out first processing on output information of the M processing paths to obtain a first image and sending the first image to the DDIC;

In a fourth aspect, an embodiment of the present application provides an electronic device, including a display control system according to the first aspect, the second aspect, or the third aspect.

In a fifth aspect, an embodiment of the present application provides a display method, where the display method is applied to the display control system according to the first aspect, the second aspect, or the third aspect, and the method includes:

acquiring frame rates corresponding to at least two display areas on a display screen respectively;

and refreshing the image content in the at least two display areas according to the respective corresponding frame rates.

In a sixth aspect, an embodiment of the present application provides an electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the method according to the fifth aspect.

In a seventh aspect, embodiments of the present application provide a readable storage medium having stored thereon a program or instructions which when executed by a processor implement the steps of the method according to the fifth aspect.

In an eighth aspect, an embodiment of the present application provides a chip, where the chip includes a processor and a communication interface, where the communication interface is coupled to the processor, and the processor is configured to execute a program or instructions to implement a method according to the fifth aspect.

In a ninth aspect, embodiments of the present application provide a computer program product stored in a storage medium, the program product being executable by at least one processor to implement the method according to the fifth aspect.

In the embodiment of the application, the display areas on the display screen are divided into N, each display area is driven to display by the respective driving circuit, and the refresh frame rate of each driving circuit is respectively controlled by the control circuit, so that different display areas on the display screen can be refreshed according to different frame rates, and the energy consumption caused by refreshing display can be reduced. In addition, the second image with different frame rates can be processed through the processing path to be sent to the display area with corresponding frame rate through the DDIC for display, or one first image can be synthesized through the first processing module, and the refresh frame rate of different subareas in the first image can be different, so that each subarea on the first image is refreshed to the display area with corresponding frame rate through the DDIC.

Drawings

Fig. 1 is a schematic diagram of a structure of a display control system in the related art;

fig. 2 is a process view of a DPU in the related art to acquire a refresh frame in synchronization with a Tearing Effect (TE) signal;

FIG. 3 is a schematic diagram of a related art process of refreshing display regions of different frame rates;

FIG. 4a is one of the intentions of a process for refreshing display areas of different frame rates in an embodiment of the present application;

FIG. 4b is a diagram showing a second exemplary embodiment of a process for refreshing display regions with different frame rates;

FIG. 4c is a schematic diagram of a display control system according to an embodiment of the present application;

FIG. 4d is a third illustration of a process for refreshing display regions of different frame rates according to an embodiment of the present application;

FIG. 4e is a second schematic diagram of a display control system according to an embodiment of the application;

FIG. 5a is a diagram illustrating a fourth exemplary embodiment of a process for refreshing display regions of different frame rates;

FIG. 5b is a fifth illustration of a process for refreshing display regions of different frame rates in accordance with an embodiment of the present application;

FIG. 5c is a third schematic diagram of a display control system according to an embodiment of the application;

FIG. 5d is a schematic diagram of a display control system according to an embodiment of the present application;

FIG. 5e is a schematic diagram of a display control system according to an embodiment of the present application;

FIG. 6 is a diagram illustrating a sixth exemplary embodiment of a process for refreshing display regions of different frame rates;

FIG. 7a is a diagram of a seventh embodiment of a process for refreshing display regions of different frame rates;

FIG. 7b is an illustration of a process for refreshing display regions of different frame rates in an embodiment of the present application;

FIG. 7c is a schematic diagram of a display control system according to an embodiment of the present application;

FIG. 8 is a diagram of a process for refreshing display regions of different frame rates according to an embodiment of the present application;

FIG. 9 is a schematic diagram of TE signals in an embodiment of the present application;

FIG. 10 is a schematic diagram of a display method according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 12 is a schematic hardware structure of another electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions of the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the present application, fall within the scope of protection of the present application.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.

Current cell phone display technology is fast moving, with screen refresh rates evolving from the previous 60hz to 120hz, 144hz, and to current dynamic frame rate refresh. I.e. the screen may brush a number of gear frame rates, e.g. 10hz for still pictures, 24hz for 24 frame film, 60 frame game is screen brush 60, 120hz or 144hz for sliding the screen.

In some embodiments, for a scene of a folded screen, a large screen, a split screen application, or the like, at least two windows may be displayed on the display screen, where refresh frame rates for different windows may be different. For convenience of explanation, in the embodiment of the present application, an application to a folding screen mobile phone is exemplified, and the type of display screen in the display control system provided in the embodiment of the present application is not limited.

For a folding screen mobile phone, as shown in fig. 1, it may include 2 screens, where the screen 1 is a main screen and the screen 2 is a sub-screen, and of course, the folding screen mobile phone may also include only one foldable screen 1, and for convenience of explanation, in this embodiment of the present application, a folding screen mobile phone is generally exemplified by including the screen 1 and the screen 2.

An application processor (Application Processor, AP) on the folding screen mobile phone is a main control chip, and the AP comprises a display processing unit (Display Process Unit, DPU) which is used for processing the content to be displayed and then sending the image content to the screen 1 and the screen 2 for display. The DPU consists essentially of display content processing paths, one of which may include: the specific structure and function of the display content processing path can refer to the display content processing path in the DPU in the related art, and will not be described herein.

As shown in fig. 1, the DPU processes the content of a frame to be displayed by: the display content processing path 1 of the DPU takes the layers to be synthesized, such as layer 1, layer 2, layer 3 and layer 4, from the buffer, and synthesizes one frame of the content to be displayed after the processing of the display content processing path 1, stores the frame buffer in the frame buffer, and sends the content in the frame buffer to the screen 1 for display through the DSI port (port) 1 of the mobile industry processor interface (Mobile Industry Processor Interface, MIPI).

Based on the same principle, the content to be displayed on the screen 2 is processed by the display content processing path 0, specifically, the display content processing path 0 of the DPU takes the layer from the buffer memory, synthesizes a frame of the content to be displayed after the processing of the display content processing path 0, has a corresponding frame buffer memory position, and then sends the frame buffer memory position to the screen 2 for display through the MIPI DSI port0 interface.

As can be seen from the above, in the related art, although the two screens can refresh images at different frame rates, two independent display content processing paths are required, and the two independent display content processing paths are connected to the two screens in one-to-one correspondence through respective DSI ports, so that the two independent display content processing paths can respectively process the image content at the respective corresponding frame rates and send the image content to the respective corresponding screens.

Taking the example of processing the content to be displayed on the screen 1 by the display content processing path 1, when an Application is opened by a mobile phone, for example, an Application program (Application) is opened, a photo is recorded or a video is watched, etc., the content drawn by the graphics processor (Graphics Processing Unit, GPU) or the network content is downloaded and decoded, and then stored in a buffer memory in the form of a layer, for example, after the layer 1 and the layer 2 … in fig. 1 are acquired by the DPU, the layer overlapping processing is performed, so as to form the content to be displayed finally, and the content of the frame buffer memory is stored in a frame buffer memory, and the content of the frame buffer memory is sent to the screen 1 for display through a display serial interface (Display Serial Interface, DSI).

Specifically, as shown in fig. 2, a frame of content is formed by stacking multiple layers, and a frame buffer stores the content to be displayed, where a frame of content to be displayed is represented by a frame buffer, and the DPU fetches the relevant layer from a buffer, where the buffer type of the frame buffer is typically DDR Memory, that is, double Data Rate (DDR) synchronous dynamic random Access Memory (Synchronous Dynamic Random-Access Memory, SDRAM).

The specific refreshing process of the screen is as follows:

The pictures that the DPU feeds the screen consist of a line of content, for example: the Full High-Definition (FHD) screen has a resolution of 2520 x 1080, i.e. there is 2520 lines of data. The DPU processes and then sends the data to the DDIC, which drives the array gate driver (Gate Driver On Array, GOA) circuits of the screen to display a line of pictures on the screen.

For example: the display refreshing of the frame of content can be completed by refreshing the first line at the top of the picture, refreshing the second line and refreshing the second line to the last line in sequence.

For another example: assuming that 60hz content needs to be displayed, that is, 60 times of image content is refreshed in one second, the AP DPU extracts the content to be displayed from the frame buffer frame by frame according to synchronization of a Tearing Effect (TE) synchronization signal, processes the content frame by frame, and finally transmits the content frame by frame to the DDIC through the DSI interface, and the screen performs frame by frame refresh display.

It should be noted that, in the related art, different image contents may also be displayed in different display areas on the same screen, for example: for a folding screen mobile phone, a webpage is displayed on the left side, and a chat interface of a social application program is displayed on the right side, and at the moment, the refresh frame rate of different display contents can be different. Alternatively, the user may operate a partial region on the same screen, at which time the refresh frame rate of the region is higher than that of the region that is not operated.

However, in the related art, one screen corresponds to one display content processing path, and refresh frame rates of image contents processed by the display content processing path are the same, which causes contents displayed on the same screen to be refreshed only at the same frame rate.

For example: assuming that the folding screen displays a social application interface, the social application interface comprises a first display area on the left side and a second display area on the right side, if a user touches the first display area and the second display area displays a video chat interface, the refresh frame rate of the first display area may be 120hz, and the refresh frame rate of the second display area may be 30hz, but based on that the whole image displayed on the folding screen is completely refreshed according to one large image, the whole image needs to be refreshed according to 120hz, so that the video in the second display area is more than a lot of repeated frame rates, and the waste of the power of the mobile phone is caused.

That is, in a folding mobile phone or other conventional bar phone, particularly a folding screen, a split screen application, etc., where two contents with different refresh frame rates are included, two parts of the contents with different refresh frame rates are spliced together at the time of DPU output to output a complete large picture, and the complete large picture is refreshed onto the screen at the highest refresh frame rate thereof. For example: as shown in fig. 3, assuming that the refresh frame rate of the content a is 60hz and the refresh frame rate of the content B is 24hz, the content B of 24hz is repeated to fill up 60hz, so that the content a and the content B are refreshed together at the refresh frame rate of 60hz, that is, the content of the entire screen is refreshed at 60hz, and the refresh is repeated at a high frame rate from the content B resulting in a low frame rate, wasting power consumption.

In the embodiment of the application, the display control system can distinguish and process the picture contents with different frame rates through updating the display control system, and the picture contents are transmitted to the display screen according to the actual frame rates of the different picture contents so as to be refreshed on the display screen according to the actual frame rates of the picture contents. For example: assuming that the refresh frame rate of content A is 60hz and the refresh frame rate of content B is 24hz, in an embodiment of the present application, content A is refreshed on the display at 60hz and content B is refreshed on the display at 24 hz.

The display control system, the electronic device and the display method provided by the embodiment of the application are described in detail below through specific embodiments and application scenes thereof with reference to the accompanying drawings.

Embodiment one

Referring to fig. 4a, a display control system provided in an embodiment of the present application includes: a display screen 1 and a DPU 2;

the display screen 1 includes: a control circuit 11, N display areas 12, N driving circuits 13, and DDIC 14, N being an integer greater than 1;

DPU 2 comprises a first processing module 22;

the DDIC 14 is connected between the first processing module 22 and the N driving circuits 13;

the N driving circuits 13 are in one-to-one correspondence with the N display areas 12;

the control circuit 11 is connected to the N driving circuits 13, respectively;

The first processing module 22 is configured to determine a first image according to layer information, and send the first image to the DDIC 14, where the first image includes N sub-areas, N sub-areas are in one-to-one correspondence with N display areas 12, and the sub-areas have the same frame rate as the corresponding display areas 12;

the DDIC 14 is configured to drive N driving circuits 13 to refresh respective corresponding sub-areas in the first image to corresponding display areas 12, and the control circuit 11 is configured to control the target driving circuit to perform a first operation, where the first operation includes: the target display area is refreshed at a first frame rate, which is the frame rate of the target display area, wherein N driving circuits 13 include the target driving circuits, N display areas 12 include the target display area, and the target driving circuits correspond to the target display area.

For convenience of description, in the embodiment of the present application, the display screen 1 is taken as a folding screen, and the folding screen is divided into two display areas, that is, n=2, for example, and in other embodiments, the display screen 1 may be any at least one screen, and the display areas on the screen may be divided into 3, 4 or more, which is not particularly limited herein.

Alternatively, the driving circuit 13 may be a GOA circuit. For example: as shown in fig. 4a, the display area a corresponds to GOA, and the display area B corresponds to GOA 1, at this time GOA is used to refresh the image in the display area a, and GOA 1 is used to refresh the image in the display area B.

The N GOA circuits are arranged in parallel, and the DDIC controls the N GOA circuits to refresh through signals of the control lines, wherein at least one control signal line is arranged. The frequency of the TE signal may be determined according to the refresh frame rate corresponding to the N display areas 12, for example: the AP notifies the DDIC of the refresh frame rate, the timing module of the DDIC outputs a TE signal according to the refresh frame rate, under the synchronous action of the TE signal, the DDIC control line signal can be transmitted from the 1 st GOA circuit to the N th GOA circuit, in the process, the control circuit 11 can control to open each GOA circuit or to pinch off part of the GOA circuits, at the moment, the cut-off GOA circuits cannot refresh the corresponding display areas, and thus, the control circuit 11 controls each GOA circuit to be in an open state or a pinch-off state respectively, and the refresh frame rate of each GOA circuit is adjusted.

In one embodiment, the TE signals correspond to the frame rates of the display areas one by one, and at this time, the DDIC adjusts each GOA circuit to be in a pinching-off or opening state respectively through the control line driving control circuit 11, so as to control the GOA circuits to refresh according to the frame rates of the corresponding display areas.

Optionally, the display control system further includes:

a synchronization signal line, TE line, connected between the DPU 2 and the DDIC14, the DDIC14 for transmitting N kinds of synchronization signals to the DPU 2 through the synchronization signal line;

wherein the N synchronization signals are in one-to-one correspondence with the frame rates of the N display areas 12, and the DPU 2 is configured to synchronize the images with the corresponding frame rates to the DDIC14 according to the N synchronization signals.

In an implementation, the N kinds of synchronization signals may be N kinds of different shapes of synchronization signals, for example: one synchronization signal is 111, the other synchronization signal is 011, etc.

For example: as shown in fig. 9, assuming that N is equal to 2, two kinds of TE signals may be set, and when the DPU 2 detects the TE signal of the first kind of waveform at a specific frame time, it is determined to synchronize the image content of the display area 12 corresponding to the TE signal of the first kind of waveform with the DDIC 14; when the DPU 2 detects the TE signal of the second waveform at a specific frame timing, it is determined to synchronize the image content of the display area 12 corresponding to the TE signal of the second waveform to the DDIC 14.

Alternatively, at a specific frame time, when at least two TE signals are transmitted on the synchronization signal line, the at least two TE signals may be superimposed to generate a new-shape TE signal, and at this time, the DPU 2 may determine, based on receiving the new-shape TE signal, to synchronize the image contents of the display areas 12 corresponding to the two TE signals to the DDIC14 at the same time.

In this embodiment, at least two kinds of synchronization signals can be transmitted by multiplexing one synchronization signal line, and the number of synchronization signal lines and DDICs 14 can be reduced, thereby simplifying the structure of the display control system.

Of course, in another embodiment, N synchronization signal lines corresponding to the frame rates of the N display areas 12 one to one may be provided, so that each synchronization signal line only needs to transmit a TE signal of one frame rate.

For example: as shown in fig. 4e or fig. 5e, assuming that n=2, the number of display areas 12, DDIC 14, and TE lines is two, one DDIC 14 may be connected to the DPU 2 through the synchronization signal line TE1, so that the DPU 2 synchronously transmits the image content of the first frame rate to the DDIC 14 under the synchronization of the TE1 signal, and then the DDIC 14 drives to synchronize the received image content to the display area 12 of the first frame rate; while the other DDIC 14 may be connected to the DPU 2 via a synchronization signal line TE2 so that the DPU 2 synchronously transmits the image content of the second frame rate to the DDIC 14 in synchronization with the TE2 signal, and then the DDIC 14 drives the synchronization of the received image content to the display area 12 of the second frame rate.

In another embodiment, only one TE signal is provided, and the control circuit 11 may pinch off the GOA circuit corresponding to the display area 12 with a low frame rate, so that the display area 12 with a low frame rate is not refreshed repeatedly, for example: assuming that the frame rate of the display area a is 120Hz, the frame rate of the display area B is 30Hz, and the frequency of the te signal is 120Hz, the control circuit 11 may periodically pinch off the GOA circuit of the display area B, so that the GOA circuit corresponding to the display area B only refreshes the display area B at the frame rate of 30Hz, without repeating the refreshing of the display frame for the display area B.

The first image may be understood as integration of image contents that need to be refreshed in the N display areas.

It should be noted that, in addition to the first processing module 22, other processing modules may be further included in the DPU 2 for adjusting the layer information, such as synthesizing, brightness, chromaticity, resolution, etc., and for convenience of explanation, in the embodiment of the present application, the DPU 2 includes the processing path 21 for adjusting the layer information, such as synthesizing, brightness, chromaticity, resolution, etc., as an example.

In one embodiment, the DPU 2 may include a processing path 21 for performing serial processing on the layer information with different frame rates, that is, time-sharing processing on the layer information with different frame rates, and then sending the processed image data to the first processing module 22, so as to fuse the image data with different frame rates or the third image by the first processing module 22 to obtain a first image.

In another embodiment, the DPU 2 may include at least two processing paths 21, where the at least two processing paths 21 are configured to process the layer information with different frame rates in parallel, and then each processing path 21 sends the processed image data to the first processing module 22, so as to fuse the image data with different frame rates or the third image by the first processing module 22 to obtain a first image.

In one embodiment, the DPU 2 may acquire layer information from a cache, where the content stored in the cache may be downloaded from a network by an electronic device having the display control system, or may be captured by a camera of the electronic device, and the AP stores the content from different sources into a DDR buffer memory area of the mobile phone through encoding and decoding, after the DPU 2 acquires the content from the cache memory area, performs adjustment such as synthesis, brightness, chromaticity, resolution, and the like, and then fuses the image content with each frame rate by the first processing module 22 to obtain an image frame to be refreshed, and finally sends the image frame to the DDIC 14 of the display screen 1, and the DDIC 14 controls the driving circuit 13 to refresh each sub-area in the image frame to the corresponding display area 12.

In the case where the refresh frame rates of the N display areas 12 are different, at least a part of the display contents of the display areas 12 may be refreshed for a specific frame time, and at this time, there may be a partial sub-area in the first image and no image contents may be present. For the sub-region without image content, it is not necessary to drive the corresponding display region by the drive circuit 13 to refresh the display content.

For example: assuming that the refresh frame rate of the display area a is 60Hz and the refresh frame rate of the display area B is 24Hz, in a first image of a frame as shown in fig. 5a, image contents are in sub-areas corresponding to the display area a and the display area B respectively; in the other frame of the first image shown in fig. 5B, only the sub-area corresponding to the display area a with the high refresh frame rate has image content, and the sub-area corresponding to the display area B with the low refresh frame rate has no image content, so that when the driving circuit 13 refreshes the one frame of the first image shown in fig. 5B to the display screen for display, the driving circuit 13 corresponding to the display area a refreshes the display area a, and the driving circuit 13 corresponding to the display area B does not drive the display area B for refreshing.

In one embodiment, the DDIC 14 may store the first image in different storage spaces on the DDIC 14 according to the distribution of the sub-areas having the display contents, so that the driving circuit 13 may determine whether to drive the refresh of the corresponding display area 12 according to the storage space of the DDIC 14 storing the first image.

For example: assuming that N is equal to 2, the refresh frame rate of the display area a is 60Hz, and the refresh frame rate of the display area B is 24Hz, then in a first image of one frame as shown in fig. 5a, the display area a and the display area B each have image contents in a corresponding sub-area, and at this time, the DDIC 14 stores the first image in the storage space a; in the first image of the other frame shown in fig. 5B, only the sub-area corresponding to the display area a with the high refresh frame rate has image content, and the sub-area corresponding to the display area B with the low refresh frame rate has no image content, and the DDIC 14 stores the first image in the storage space B. Subsequently, the DDIC 14 may drive the driving circuits 13 corresponding to the display areas a and B so that the display areas a and B refresh the first image in the storage space a; alternatively, the DDIC 14 may drive the driving circuit 13 corresponding to the display area a so that the display area a refreshes the first image in the memory space B.

The number of memory spaces of the DDIC 14 may be adjusted according to the number of the display areas 12, the combination of the sub-areas having the image content in the first image, and the like, and is not particularly limited herein.

Of course, in other embodiments, the DDIC 14 may also use other manners to implement the refresh of the display area by the driving circuit 13 corresponding to the sub-area where the image content is driven, which is not limited herein. For example: the control circuit judges the subareas with the image content, so that the drive circuit 13 corresponding to the subareas with the image content is controlled to drive the display area to refresh.

In this embodiment, the first image is managed by taking the content of one frame displayed on the entire display screen 1 as a whole.

As an alternative embodiment, the first processing module 22 includes:

the synthesizing module is used for synthesizing the image data streams with N frame rates to obtain the first image, wherein the image data streams are data streams output by a processing path in the DPU; or alternatively, the first and second heat exchangers may be,

and the jigsaw module is used for carrying out jigsaw processing on third images with N frame rates to obtain the first image, wherein the third images are processed images of the processing paths in the DPU.

In one embodiment, where the first processing module 22 includes a synthesizing module, the first processing module 22 directly obtains the image data stream output by the processing path 21, and performs a synthesizing process on the image data stream to obtain image data of a first image of a frame.

In another embodiment, in the case that the first processing module 22 includes a mosaic module, the processing channels 21 output a third image, which may be an intermediate image corresponding to the display areas 12 one by one, and then the mosaic module performs a mosaic process on the third image output by each processing channel 21 to obtain the first image.

Optionally, in the case that the first processing module includes the jigsaw module, the display control system further includes:

the N second storage spaces are in one-to-one correspondence with the N display areas, and are used for iteratively storing image data to be transmitted to the jigsaw module, which corresponds to at least one row of the third image, wherein the refresh frame rate of the third image stored in each of the N second storage spaces is the same as the frame rate of the display area corresponding to each of the N second storage spaces;

The jigsaw module is used for acquiring the image data of the third image from the N second storage spaces.

The second storage space may be a buffer space with a specified size, such as DDR or SRAM, where the size of the storage space may be greater than or equal to or less than the image data size of a frame of the third image, where when the second storage space is less than the image data size of a frame of the third image, the image data of a part of the lines in the third image may be stored each time, and when the image data of a certain line is sent to the tile module, the image data of the line is deleted from the second storage space, so that the next line of the image data in the third image processed by the storage processing path 21 is added in the second storage space, and thus, each line of the data in the third image may be iteratively stored by using the second storage space with a smaller size until all the image data of the third image to be refreshed in the frame is sent to the tile module.

For convenience of explanation, in the embodiment of the present application, the size of the second storage space is generally taken as an example and is equal to the data size of a frame of the third image, where the second storage space may be referred to as a frame buffer, that is, a complete frame of the third image may be stored at a time.

For example: as shown in fig. 5e, the second storage space includes a frame buffer a 'for storing a 60Hz third image output by the processing path a and a frame buffer B' for storing a 24Hz third image output by the processing path B.

It should be noted that, at a specific frame time, only a part of the third images of the refresh frame may be stored in the N second storage spaces, and another part of the third images may not be stored in the second storage spaces, for example: at some frame time, only processing lane A generates a 60Hz third image, while processing lane B does not generate a 24Hz third image. At this time, the jigsaw module only reads the third image from the second storage space with the third image, and leaves the sub-area without the third image empty, that is, the first image is formed by carrying out jigsaw processing on the third image with the refresh frame only.

In this embodiment, the third image output by the processing path 21 is stored in the corresponding second storage space according to the refresh frame rate, so that the jigsaw module obtains the third image to be jigsaw processed from the second storage space.

In the case where the number of the processing paths 21 is at least two, for example: the synthesizing module is configured to synthesize the data streams output by the M processing paths 21 to obtain the first image; or, the jigsaw module is configured to perform a jigsaw process on the M third images processed by the M processing paths 21, so as to obtain the first image.

Further, in the case that the DPU 2 includes M processing lanes 21, in order for the mosaic module to learn which processing lanes 21 have new third images, the mosaic module may actively detect whether each processing lane 21 has new third images, or a first unit may be provided in the mosaic module, where the first unit is used to determine whether each processing lane 21 has the processed third images, or the first unit is used to receive the first information from each processing lane 21.

Optionally, the jigsaw module includes a first unit, where the first unit is configured to determine whether the M processing paths have the processed third image, or the first unit is configured to receive first information from the M processing paths;

and when the first unit receives the first information from the target processing path or judges that the target processing path has the processed third image, the jigsaw module reads the image data of the third image processed by the target processing path from a second storage space corresponding to the target processing path.

Wherein the processing path 21 in the DPU 2 comprises the above-mentioned target processing path.

In some embodiments, the first information is used to indicate that the processing path 21 that sends the first information has a new third image, and the processing path 21 may send the first information to the first unit when the third image is generated, or during the generation of the third image.

In this embodiment, the jigsaw module can learn which processing paths 21 have new third images based on the determination result of the first unit or the receiving condition of the first information, so as to acquire the new third images to perform the jigsaw processing.

It should be noted that, based on the difference of the display areas 12 to be refreshed at a specific frame time, that is, the difference of the distribution of the sub-areas in the first image processed by the DPU 2, at this time, the DPU 2 may store the first image processed in different frame buffers according to the difference of the display areas 12 to be refreshed. In other words, the reference frame rates in different frame buffers may be different.

As an alternative embodiment, the display control system further includes:

the first buffer memory 3 and the first storage space 4, the first buffer memory 3 is used for buffering layer information, the first storage space 4 is used for iteratively storing at least one line of image data to be transmitted to the DDIC 14 in the first image processed by the DPU 2;

The number of the first caches 3 is N, the N first caches 3 are in one-to-one correspondence with the frame rates of the N display areas 12, and the N first caches 3 are respectively used for caching layer information of the frame rates corresponding to the N first caches;

the number of the first storage spaces 4 is Y, and the Y first storage spaces 4 are respectively used for storing image data of first images with respective corresponding reference frame rates, where the reference frame rates are related to frame rates of sub-areas where image contents exist in the corresponding first images.

The first buffer 3 may be a buffer for buffering layer information of various frame rates in the AP, and the first storage space 4 may be a storage space of a specified size, for example: DDR or SRAM, etc., the size of the storage space may be greater than or equal to or less than the image data size of the first image of one frame, wherein, when the first storage space 4 is less than the image data size of the first image of one frame, the image data of a part of the lines in the first image may be stored each time, and when the image data of a certain line is completed to be transmitted to the DDIC 14, the image data of the line is deleted from the first storage space 4, so that the next line of the image data in the first image processed by the DPU 2 is additionally stored in the first storage space 4, and thus, each line of the data in the first image may be iteratively stored by using the first storage space 4 of a smaller size until all the image data of the first image to be refreshed of one frame is transmitted to the DDIC 14.

For convenience of explanation, in the embodiment of the present application, the size of the first storage space 4 is generally taken as an example and is equal to the data size of a first image of one frame, where the first storage space 4 may be referred to as a frame buffer, that is, a complete first image of one frame may be stored at a time.

For example: the first storage space 4 may be a frame buffer for storing a frame of image content to be refreshed after the processing of the DPU 2, and the frame of image content may be deleted from the first storage space 4 when the refreshing of the frame of image is completed or when the transmission of the frame of image content to the DDIC 14 is completed.

In this embodiment, the image contents of different reference frame rates obtained after the processing of the DPU 2 may be stored separately in at least two first storage spaces 4, so that when the image contents of a specified reference frame rate are transferred to the DDIC 14, the image contents to be transmitted may be acquired from the first storage spaces 4 corresponding to the reference frame rate.

For example: as shown in fig. 5c and 5d, when the display content processing path a is used for processing an image with a 60Hz frame rate, the display content processing path a acquires 60Hz layer information from the first buffer 3, performs processing such as stacking the 60Hz layer information, and outputs a data stream of the 60Hz image; the display content processing path B is configured to process an image at a 24Hz frame rate, and then the display content processing path B obtains 24Hz layer information from the first buffer 3, performs processing such as stacking the 24Hz layer information, and outputs a data stream of the 24Hz image, and then performs, by using the first processing module 22 (i.e., the synthesizing module), a synthesizing process on the data streams processed by the display content processing path a and the display content processing path B, so as to obtain a first image. For a specific frame time, there may be image contents of only a sub-region corresponding to 60Hz in the first image, or image contents of both a sub-region corresponding to 60Hz and a sub-region corresponding to 24Hz, based on which the first storage space 4 is divided into two: the frame buffer A is used for storing the first image with the image content in the subarea corresponding to 60Hz only, and the frame buffer A is used for storing the first image with the image content in the subarea corresponding to 60Hz and the subarea corresponding to 24 Hz.

Of course, in implementation, it may also occur that, in a case where only the sub-region corresponding to 24Hz has image content at a specific frame time, the number of the first storage spaces may be increased at this time, for storing the first image where only the sub-region corresponding to 24Hz has image content.

Also for example: as shown in fig. 5e, if the display content processing path a is used for processing an image with a frame rate of 60Hz, the display content processing path a obtains 60Hz layer information from the first buffer 3, and performs processing such as stacking the 60Hz layer information to obtain a third image with a frame rate of 60 Hz; the display content processing path B is configured to process an image at a 24Hz frame rate, and then the display content processing path B obtains 24Hz layer information from the first buffer 3, performs processing such as stacking the 24Hz layer information to obtain a third image at 24Hz, and then performs, by using the first processing module 22 (i.e., a jigsaw module), jigsaw processing on the third images processed by the display content processing path a and the display content processing path B, so as to obtain a first image. In this process, the first storage space 4 includes a frame buffer C and a frame buffer D, and the second storage space includes a frame buffer a 'and a frame buffer B', where the frame buffer a 'is used to store a third image with a 60Hz frame rate after being processed by the display content processing path a, and the frame buffer B' is used to store a third image with a 24Hz frame rate after being processed by the display content processing path B, and the first processing module 22 obtains the third image that needs to be tiled from the frame buffer a 'and the frame buffer B' respectively, and for a specific frame time, there may be a third image with only 60Hz, and at this time, only a sub-region corresponding to 60Hz in the synthesized first image has image content; alternatively, there are a 60Hz third image and a 24Hz third image, and at this time, the sub-region corresponding to 60Hz and the sub-region corresponding to 24Hz in the synthesized first image have image contents. Based on this, a frame buffer C and a frame buffer D may be further provided, where the frame buffer C is used to store a first image having image contents in only a sub-region corresponding to 60Hz, and the frame buffer D is used to store a first image having image contents in both a sub-region corresponding to 60Hz and a sub-region corresponding to 24 Hz.

It should be noted that, in one embodiment, the size of the first storage space 4 may be smaller than the size of the first image of one frame, and the size of the second storage space may be smaller than the size of the third image of one frame. At this time, the first storage space 4 is used for iteratively storing U-line data in a frame of the first image to be refreshed, U is an integer greater than or equal to 1, and the second storage space is used for iteratively storing V-line data in a frame of the third image to be tiled, and V is an integer greater than or equal to 1.

Specifically, the processing path 21 stores V-line data in the processed third image in the second storage space in an iterative manner, and the jigsaw module reads each line of data in the N third images from the second storage space in turn, wherein when a certain line of data in the third image is read by the jigsaw module, the line of data is deleted from the second storage space, so that the next line of data in the third image is newly stored in the second storage space until the jigsaw module reads a complete frame of third image to be jigsaw from the second storage space; similarly, the jigsaw module may store at least one row of data after the jigsaw process is completed in the first storage space 4 in an iterative manner, so that the DDIC 14 obtains each row of data of the first image from the first storage space 4, and after a certain row of data in the first image is sent to the DDIC 14, deletes the row of data from the first storage space 4, so as to newly store the next row of data in the first image in the first storage space 4 until the DDIC 14 reads a complete frame of the first image to be refreshed from the first storage space 4.

Also for example: as shown in fig. 7c, the display content processing path B is configured to serially process an image with a 60Hz frame rate and an image with a 24Hz frame rate, so that at a specific frame time, the display content processing path B may acquire layer information with a 60Hz frame rate from the first buffer 3, and perform processing such as stacking the layer information with the 60Hz frame rate to obtain a first image, where only a sub-region corresponding to the 60Hz region has image content, and the first image is stored in the frame buffer a; at another specific frame time, the display content processing path B may acquire layer information of 60Hz frame rate and 24Hz frame rate from the first buffer 3, and perform processing such as stacking the layer information of 60Hz and 24Hz respectively, so as to obtain a first image, where in the first image, both a sub-region corresponding to 60Hz and a sub-region corresponding to 24Hz have image contents, and then the first image is stored in the frame buffer B.

It should be noted that, in implementation, the DDIC 14 may also have at least two different buffer spaces, as shown in fig. 4a, where the DDIC 14 includes SRAM 1 and SRAM 2, so that the DDIC 14 may correspond the SRAM 1 to a display area corresponding to the image content to be refreshed, for example, store the image content corresponding to the display area a in the SRAM 1, and store the image content corresponding to the display area B in the SRAM 2; alternatively, the SRAM 1 stores image contents corresponding to the display area a and the display area B, and the SRAM 2 stores image contents corresponding to the display area a.

As an alternative embodiment, as shown in any one of fig. 4e, 5e, 6 and 8, the DPU 2 further includes:

x first interfaces 23, X being a positive integer, the DPU 2 sends the first image to the DDIC 14 via X first interfaces 23.

The first interface 23 may be a display serial interface (Display Serial Interface, DSI), among others. For example: the DPU 2 and DDIC 14 are connected by a display serial interface (Display Serial Interface, DSI), such as: as shown in fig. 4c, the two processing paths 21 of the DPU 2 are connected to the DDIC 14 via two mobile industry processor interface (Mobile Industry Processor Interface, MIPI) DSI interfaces.

Alternatively, as shown in fig. 4c, the MIPI DSI interface generally employs a MIPI D physical layer (Dphy) interface, which is composed of 4 data lines and 1 set of clock signal lines, clk_p+clk_n is 1 set of differential clock signal lines, P represents positive, and N represents negative. The data lines are also differential signals, d0_p and d0_n representing the first set of data lines, D0 representing data0, P representing positive, and N representing negative. The other three sets of data lines and so on.

Of course, the first interface 23 may also be another image data transmission interface, and for convenience of explanation, the embodiment of the present application is exemplified by taking the first interface 23 as a DSI interface, which is not specifically limited herein.

In the present embodiment, the first image processed by the DPU 2 is transmitted to the DDIC 14 through the DSI interface.

In the display control process, the picture content output by the DPU 2 may be sent to the storage space of the DDIC 14 through the MIPI DSI interface under the synchronization of the TE signal, for example: in a Static Random-Access Memory (SRAM) or a line buffer, the contents in the Memory space of the DDIC 14 are refreshed line by line onto the display 1 under the driving of the DDIC 14 controlling the display GOA and other circuits.

The progressive refresh may be a progressive refresh from above to below the display screen 1, or a progressive refresh from below to above the display screen 1, which is not particularly limited herein.

Second embodiment

As shown in fig. 4a and 4b, another display control system provided in an embodiment of the present application includes:

the display screen 1 and the DPU 2, wherein the display screen 1 is connected with the DPU 2;

the display screen 1 includes: DDIC 14, control circuit 11, N display areas 12, N driving circuits 13, N being an integer greater than 1;

DPU 2 includes M processing paths 21, M being a positive integer;

the DDIC 14 is connected between the processing path 21 and the N driving circuits 13;

the control circuit 11 is connected to the N driving circuits 13, respectively;

the M processing paths 21 are configured to acquire layer information, process the layer information in parallel to obtain N second images, and send the N second images to the DDIC 14;

the DDIC 14 is for transmitting a target second image to a target driving circuit, and the control circuit 11 is for controlling the target driving circuit to perform a first operation including: the target display area is refreshed according to a first frame rate, wherein the first frame rate is the frame rate of the target display area, the frame rate of the target second image is the same as the frame rate of the target display area, N pieces of second images comprise the target second image, N pieces of driving circuits 13 comprise the target driving circuits, N pieces of display areas 12 comprise the target display area, and the target driving circuits correspond to the target display area.

The second embodiment differs from the first embodiment in that it includes: in the present embodiment, the frame image refreshed for each display area 12 is taken as an independent second image, whereas in the previous embodiment, the frame image refreshed for all display areas 12 is taken as a first image of the whole, and in the present embodiment, the image contents with different frame rates are processed in parallel by using M processing paths 21, so that the efficiency of image processing can be improved. In the present embodiment, the DDIC 14 only needs to drive the display area 12 by the driving circuit 13 to refresh the respective corresponding second images.

When the refresh frame rates of the N display areas 12 are different, at least part of the display contents of the display areas 12 may be refreshed for a specific frame time, and at this time, some of the N second images may have no image contents. For the second image without image content, it is not necessary to drive the corresponding display area by the driving circuit 13 to refresh the display content.

For example: assuming that the refresh frame rate of the display area A is 60Hz and the refresh frame rate of the display area B is 24Hz, at a certain frame moment, image contents are respectively arranged in the subareas corresponding to the display area A and the display area B; in contrast, at the other frame time, only the second image corresponding to the display area a having the high refresh frame rate is generated, and the second image corresponding to the display area B having the low refresh frame rate is not generated, so that when the driving circuit 13 refreshes the second image at the other frame time to display on the display screen, the driving circuit 13 corresponding to the display area a drives the display area a to refresh, and the driving circuit 13 corresponding to the display area B does not drive the display area B to refresh.

Note that M may be less than or equal to N.

The processing path 21 in the embodiment of the present application may be referred to as a display content processing path, and the display content processing path may acquire layer information of a specified frame rate in the first buffer 3, and perform processing such as stacking on the layer information to obtain a frame image.

In one embodiment, at least two processing paths 21 in DPU 2 may be utilized to process refresh frame images of different display areas 12 in parallel, such as: as shown in fig. 5a and 5B, the refresh image content of the display area a is processed by a processing path a (referred to as "path a") in the DPU 2, and the refresh image content of the display area B is processed by a processing path B (referred to as "path B") in the DPU 2.

In this embodiment, M may be equal to N.

x first interfaces 23, X is a positive integer, and the DPU 2 sends N second images to the DDIC 14 through the X first interfaces 23.

Alternatively, as shown in fig. 6, in the case where the DPU 2 includes M processing paths 21, X is equal to M, and X first interfaces 23 are connected to M processing paths 21 in one-to-one correspondence;

The images processed by the M processing paths 21 are sent to the DDIC 14 through the corresponding first interfaces 23.

Of course, in the case where the DPU 2 includes M processing paths 21, X may be less than M or greater than M.

For example: in case X is smaller than M, at least two processing paths 21 may transmit the processed image content to the DDIC 14 using the same first interface 23 in a time-sharing manner.

For another example: in the case that X is greater than M, the same processing path 21 may send the processed image content to the DDIC 14 in parallel by using at least two first interfaces 23, or the number of the display screens 1 is at least two, where the first interfaces 23 are in one-to-one correspondence with the display screens 1, and the M processing paths 21 are connected to the X first interfaces through a switching module 24, where the switching module 24 may switch the on states between the two processing paths 21 and the two DSI interfaces of the DPU 2.

Optionally, X is equal to N, and X first interfaces 23 are in one-to-one correspondence with N display areas 12;

the X first interfaces 23 are respectively used for transmitting the second images of the respective corresponding display areas 12.

In this embodiment, the DDIC 14 may determine the display area 12 corresponding to the second image according to the first interface 23 for transmitting the second image, so as to drive the driving circuit 13 corresponding to the display area 12 to refresh the second image to the display area 12.

In the present embodiment, the first image or the second image processed by the DPU 2 is transmitted to the DDIC 14 through the DSI interface.

Alternatively, as shown in fig. 4c, a switching module 24 may be provided between at least two processing paths 21 and the DDIC 14, which switching module 24 may switch the on-state between the two processing paths 21 and the two DSI interfaces of the DPU 2.

For example: in case the DPU 2 comprises M processing paths 21, the M being greater than 1 and X being less than M, the DPU 2 further comprises:

the switching module 24 includes M first ends and X second ends, the M first ends are connected with the M processing paths 21 in a one-to-one correspondence, and the X second ends are connected with the X first interfaces 23 in a one-to-one correspondence;

the switching module 24 is configured to switch a conducting relationship between the X second ends and the M first ends, where, when the target first end is conducted with the target second end, the second image processed by the processing path 21 correspondingly connected to the target first end is sent to the DDIC 14 through the first interface 23 correspondingly connected to the target second end, the M first ends include the target first end, and the X second ends include the target second end.

In the present embodiment, the switching module 24 can switch the on state between the processing path 21 and the first interface 23, for example: the processing path 21 generating the refreshed image content may be changed at different frame moments, and the processing path 21 generating the second image may be switched on to the first interface 23 by the switching module 24, so that the processing path 21 generating the refreshed image frame may be able to send the refreshed image content to the DDIC 14 via the first interface 23.

It should be noted that, based on the difference of the display areas 12 to be refreshed at a specific frame time, that is, the difference of the display areas 12 corresponding to the second image, the DPU 2 may store the processed second image in different frame buffers according to the difference of the display areas 12 to be refreshed. In other words, the reference frame rates in different frame buffers may be different.

As an alternative embodiment, the display control system further includes:

a first buffer 3 and a first storage space 4, where the first buffer 3 is used to buffer layer information, and the first storage space 4 is used to iteratively store at least one line of image data to be transmitted to the DDIC in the second image processed by the DPU 2;

the number of the first storage spaces 4 is Y, and the Y first storage spaces 4 are respectively used for storing image data in second images with respective corresponding reference frame rates, where the reference frame rates are related to frame rates corresponding to the corresponding second images.

The first buffer 3 may be a buffer for buffering layer information of various frame rates in the AP, and the first storage space 4 may be a storage space of a designated size, such as DDR or SRAM, where the size of the storage space may be greater than or equal to or less than the image data size of a frame of the second image, where when the first storage space 4 is less than the image data size of a frame of the second image, image data of a part of the lines in the second image may be stored each time, and when the image data of a certain line is sent to the DDIC 14, the image data of the line is deleted from the first storage space 4, so that the next line of image data in the second image processed by the DPU 2 is added and stored in the first storage space 4, and thus, each line of data in the second image may be iteratively stored by using the first storage space 4 of a smaller size until all image data of the second image to be refreshed in the frame is sent to the DDIC 14.

For convenience of explanation, in the embodiment of the present application, the size of the first storage space 4 is generally taken as an example and is equal to the data size of one frame of the second image, where the first storage space 4 may be referred to as a frame buffer, that is, a complete frame of the second image may be stored at a time.

For example: as shown in fig. 4c and 4e, assuming that the first storage space 4 includes a frame buffer 3A and a frame buffer 3B, the display content processing path a is used for processing an image with a 60Hz frame rate, the display content processing path a acquires 60Hz layer information from the first buffer 3, performs processing such as stacking the 60Hz layer information to obtain a 60Hz second image, and stores the 60Hz second image in the frame buffer 3A. Thereafter, the DDIC 14 can acquire a 60Hz second image in the frame buffer 3A through the first interface 23 and drive the GOA to refresh the 60Hz second image into the display area 12 refreshed at 60 Hz. Similarly, if the display content processing path B is configured to process an image with a 24Hz frame rate, the display content processing path B obtains 24Hz layer information from the first buffer 3, performs processing such as stacking the 24Hz layer information, and stores the 24Hz second image in the frame buffer 3B. Thereafter, the DDIC 14 can acquire a 24Hz second image in the frame buffer 3B through the first interface 23 and drive the GOA 1 to refresh the 24Hz second image into the display area 12 refreshed at 24 Hz.

Embodiment III

The third display control system provided by the embodiment of the application may include:

the DPU 2 comprises M processing paths 21 and a first processing module 22, wherein the M processing paths 21 are connected with the first processing module 22, and M is a positive integer;

the control circuit 11 is connected to the N driving circuits 13, respectively;

The M processing paths 21 are configured to acquire layer information, perform parallel processing or serial processing on the layer information, and the first processing module 22 is configured to perform first processing on output information of the M processing paths 21 to obtain a first image, and send the first image to the DDIC 14;

the DDIC 14 is configured to drive the N driving circuits 13 to refresh respective corresponding sub-areas in the first image to the corresponding display areas 12, and the control circuit 11 is configured to control the target driving circuit to perform a first operation, where the first operation includes: the target display area is refreshed at a first frame rate, which is the frame rate of the target display area, wherein N driving circuits 13 include the target driving circuit, N display areas 12 include the target display area, and the target driving circuit corresponds to the target display area.

The third embodiment may be a combination of the first and second embodiments.

In one embodiment, M is equal to 1, at which time the refresh frame image of the different display areas 12 may be serially processed by one processing path 21 in the DPU 2, for example: as shown in fig. 7a and 7B, the same processing path 21 may be used to time-share the refreshed image content of display area a and display area B.

In another embodiment, M may be any integer greater than 1 and less than N, where the same processing path 21 may process the refreshed image content of at least two display regions 12 serially, and at least two processing paths 21 may process the refreshed image content in parallel.

In yet another embodiment, M may be equal to N, where M processing paths 21 are used to process image content at respective corresponding refresh frame rates in parallel.

In one embodiment, as shown in fig. 5c, the first processing module 22 includes a synthesizing module, configured to perform synthesizing processing on the data streams output by the M processing paths 21, so as to obtain the first image.

In this embodiment, the processing paths 21 respectively transmit the data streams to the synthesizing module, and the synthesizing module synthesizes the received data streams to obtain a data stream of a first image, and in this case, the first processing may be a synthesizing processing of the data streams.

In another embodiment, as shown in fig. 5d and fig. 5e, the first processing module 22 includes a jigsaw module, configured to perform a jigsaw process on M third images processed by M processing paths, so as to obtain the first image.

In this embodiment, the processing path 21 transmits the third images to the puzzle modules, and the M Zhang Disan images are synthesized into one first image by the synthesis module, and at this time, the first processing module is used to perform the synthesis processing on the images.

In yet another embodiment, as shown in fig. 7a, 7b and 7c, in the case that one processing path 21 processes image contents of at least two different frame rates in series, the first processing module 22 may integrate the image contents of the N display areas 12 processed by the processing path 21 into one first image.

It should be noted that, at a specific frame time, there may be a portion of the image of the display area 12 that is not refreshed, and as shown in fig. 7b, there is no image content in the sub-area corresponding to the display area 12 that is not refreshed in the first image synthesized by the first processing module 22.

By the display control system provided by the application, the contents with different frame rates can be separately processed when the DPU 2 of the AP processes the data, for example: for 60Hz content, the refresh image frames are generated at a frame rate of 60Hz, and for 24Hz content, the refresh image frames are generated at a frame rate of 24 Hz. In this way, the display screen 1 can be fed to the DDIC 14 according to the actual frame rate of different picture contents, so that the display screen 1 is refreshed according to the actual different display frame rates, and the situation that the 24Hz picture contents need to be repeatedly padded to 60Hz when different display areas of the display screen are refreshed according to 60Hz and 24Hz respectively and the 24Hz frame rate display contents need to be refreshed on the display screen according to the 60Hz frame rate is avoided.

In order to facilitate understanding of the display control system according to the embodiment of the present application, N is assumed to be equal to 2, and the display control system provided by the embodiment of the present application is illustrated by taking the following scenario as an example:

scene one: the processing paths 21 are in one-to-one correspondence with the frame rates, and each processing path 21 is configured to independently process the image content at the respective corresponding frame rate.

As shown in fig. 4B, DPU 2 takes content a, content B of different frame rates from different first buffers. Under the synchronization action of the same synchronization signal TE, the content a is processed through the independent path a of the DPU 2 and the content B is processed through the independent path B of the DPU 2. And then the processed B content is sent to the SRAM 2 and refreshed to a 24-frame display area of the display screen for display. And sending the processed A content to a corresponding SRAM 1, refreshing the processed A content to a 60-frame display area of the display screen for display.

In refreshing the display 1, the control circuit 11 may divide the display 1 into 2 display areas 12 that are refreshed at 60 frames and 24 frames, respectively, so that the GOA circuits that refresh the 24-frame display areas 12 are refreshed at 24hz and the GOA circuits that refresh the 60-frame display areas 12 are refreshed at 60 hz.

Alternatively, as shown in fig. 4c, the content with high frame rate (i.e. 60 frames) is processed by the display content processing path a and then sent to the MIPI DSI port (port) B to be sent to the DDIC 14 for screen-brushing display, and the content with low frame rate (i.e. 24 frames) is sent to the DDIC 14 for screen-brushing display by the MIPI DSI port B through the display content processing path B. In view of the fact that both the display content processing path a and the display content processing path B are connected to MIPI DSI port B, a switching module 24 may be provided, where the switching module 24 includes: the switch and arbitration module adjusts the switch state of the switch under the control of the arbitration module so that the display content processing path A and the display content processing path B are sequentially and orderly sent to the display screen 1 for display through the MIPI DSI port B.

Alternatively, for better synchronization, 2 sets of TE synchronization signals and above may be set. For example: as shown in fig. 4d, the data of the path B is sent to the SRAM 2 of the DDIC 14 under the synchronization of TE 2, and then sent to the 24-frame display area refresh display of the display screen 1; the data of the path a is sent to the SRAM 1 of the DDIC 14 in synchronization with TE1, and then sent to the 60-frame display area refresh display of the display panel 1.

Further, 2 DDICs 14 may be disposed on the display screen 1, and different DDICs 14 are responsible for controlling display areas with different frame rates on the display screen 1. For example: as shown in fig. 4e, 24Hz display content processed by the path a is sent to the 24 frame display area 12 through one DDIC 14 for display; the 60Hz display content processed by the path B is sent to the 60 frame display area 12 for display by the other DDIC 14. Wherein, the path A and the path B are respectively controlled by different TE synchronous signals.

Scene II: a first processing module 22 (which may also be referred to as a post-processing module, synthesis module, jigsaw module, etc.) is added.

As shown in fig. 5a and 5B, 60Hz content of the display area a in the DPU 2 is processed through the path a, 24Hz content of the display area B is processed through the path B, then a first processing module 22 is added, the path a and the processed content of the path B are combined into a large image (first image), and then sent to the storage space of the DDIC 14, and then the DDIC 14 brushes the first image onto the display screen 1. In this process, the DPU 2 may take metadata (metadata) such as frame rate information of the content in the first buffer 3, and assist the path a, the path B, and the first processing module 22 in cooperation according to the frame rate content after referencing.

Specifically, since the number of frames of the display content with a low frame rate is smaller than that of the display content with a high frame rate, for example: as shown in fig. 5B, in some cases, when the 60Hz content of the display area a is processed, the 24Hz content of the display area B is not content at this time, and at this time, the first processing module 22 may update only the 60Hz portion of the display content to be refreshed to the DDIC 14 with reference to metadata such as frame rate information, and then the DDIC 14 refreshes the updated portion of the display content to the corresponding display area a of the display screen 1.

Optionally, path a processes 60 frames of display content, path B processes 24 frames of display content, and the two paths of processed content are used as layers by the composition module to compose a display frame (i.e., a first image) in the frame buffer. As shown in fig. 5c, when the contents of 60 frames and 24 frames exist, the first image of the synthesized frame is stored in the frame buffer B and refreshed on the display screen 1 through the DDIC 14; in case of 24 frames missing, another block of frame buffer a is opened up, where only 60 frames of content are in the first image and refreshed by DDIC 14 onto the corresponding display area 12 on the display screen 1. In this way, refreshing of content at different frame rates is achieved by storing different content with two frame buffers.

Alternatively, the first processing module 22 may employ a jigsaw module, such as: as shown in fig. 5d or fig. 5e, the graphs processed by the display content processing path a and the display content processing path B and stored in the frame buffer are taken out for re-stitching, and the puzzle module may include a judging module or a receiving information module, for example: the method comprises the steps that data information from a display content processing path A and a display content processing path B can be received, the data information can be used for informing a jigsaw module whether new content is sent next, if the two display content processing paths are sent, image contents processed by the two display content processing paths are respectively extracted from a frame buffer A 'and a frame buffer B', and the image contents are spliced into a large image and stored in a frame buffer D; if only the display content processing path a has the processed high frame rate content, the image content processed by the display content processing path a extracted in the frame buffer a 'is stored in the frame buffer C, or the high frame rate display content in the frame buffer a' is directly transmitted to the DDIC 14.

Of course, in addition to the above manner of sending data information to the puzzle module via the display content processing path to inform the puzzle module of whether new content is next delivered, the puzzle module may also learn in other manners whether the display content processing path is next delivered, for example: the jigsaw module detects whether new content is delivered to the display content processing path by itself.

In addition, for the embodiment shown in fig. 5e, the frame buffer a 'and the frame buffer B' may not be provided, but the image content processed by the display content processing path may be directly spliced by the jigsaw module and then stored in the frame buffer D or the frame buffer C.

Scene III: the DPU 2 processed image content is transferred to DDIC 14 via at least two first interfaces 23.

In one embodiment, the at least two first interfaces 23 may be interfaces obtained after the MIPI interface is bifurcated, for example: as shown in fig. 6, the MIPI interface of DPU 2 is forked to obtain two DSI interfaces, such as: dsi_1 and dsi_2, wherein the contents of path a are sent to DDIC 14 through dsi_1, can be stored in a memory space designated by DDIC 14, such as SRAM 1, for more reliable system. The contents of path B are sent to DDIC 14 via dsi_2 and may be stored in another memory space designated by DDIC 14, such as SRAM 2, for the system to be more reliable. Then, the DDIC 14 can refresh the contents stored in the SRAM 1 and the SRAM 2 onto the corresponding display area 12.

The at least two first interfaces 23 can enable the image contents refreshed at different frame rates to be synchronously transmitted to the DDIC 14, so that the DDIC 14 can synchronously drive the at least two display areas 12 to refresh the display contents according to respective frame rates, and the smoothness of refreshing the at least two display areas 12 according to respective frame rates is improved.

Scene four: the same processing path 21 serially processes the image content of at least two frame rates.

As shown in fig. 7a, the DPU 2 may have only one processing path 21, and after the DPU 2 obtains the 60Hz content corresponding to the display area a and the 24Hz content corresponding to the display area B from the first buffer, the processing is performed on the processing path 21 of the DPU 2. Then combined in the first processing module 22 to obtain a first image of the display content comprising display area a and display area B, which is then sent via the DSI interface to the display screen 1 for display.

As shown in fig. 7b, since the number of 24Hz content frames is smaller than that of 60Hz content frames, in some cases, only 60Hz content is in the first buffer, the DPU 2 processes only 60Hz content after taking it, and sends the processed image content to the first processing module 22, and the first processing module 22 performs data alignment and other processing on the data to be sent to the display screen 1, where the data alignment processing may include adjustment of the sending position, the data sending timing, and so on, so as to avoid display errors.

Alternatively, to improve data reliability, the first processing module 22 may perform partition storage with reference to the frame rate of the image.

For example: as shown in fig. 7c, only the display content processing path B is used for serial processing, when both high frame rate (60 Hz) and low frame rate (24 Hz) contents are available, one frame of contents is synthesized and stored in the frame buffer B, and the image contents in the frame buffer B are sent to the DDIC 14 to be refreshed on the display screen 1; in case of a low frame rate content loss, another block frame buffer a is opened up, the image stored in the frame buffer a having only a high frame rate content, after which the image content in the frame buffer a is sent to the DDIC 14 to be refreshed to the corresponding display area 12 on the display screen 1.

In this way, the refresh at different frame rate contents is realized by storing different contents respectively through the two frame caches. Of course, only one frame buffer may be provided, or the first processing module 22 may determine the size of the image content processed by the display content processing path B by itself, and determine whether to store the display content in the frame buffer a or the frame buffer B according to the determination.

In this scenario, one processing path 21 can process image contents of different frame rates, so that the number of processing paths 21 can be reduced, and the structural complexity of the display control system can be reduced.

Scene five: the same processing path 21 serially processes the image contents of at least two frame rates and transmits the image contents processed by the DPU 2 to the DDIC 14 through at least two first interfaces 23.

The present scenario is a combination of the third scenario and the fourth scenario, and one processing path 21 may process image contents with different frame rates, and the processed data with different frame rates may be separately transmitted to the display screen 1. In this way, the display screen 1 can distinguish the display area 12 corresponding to the image content transmitted by the data interface according to the source of the data interface, so as to refresh the image frame received from a certain data interface onto the corresponding display area 12.

The embodiment of the application also provides electronic equipment, which can comprise any one of the display control systems shown in the embodiment of fig. 4a to 9.

By way of example, the electronic device may be a mobile phone, tablet computer, notebook computer, palm computer, vehicle-mounted electronic device, mobile internet appliance (Mobile Internet Device, MID), augmented reality (augmented reality, AR)/Virtual Reality (VR) device, robot, wearable device, ultra-mobile personal computer, UMPC, netbook or personal digital assistant (personal digital assistant, PDA), etc., but may also be a server, network attached storage (Network Attached Storage, NAS), personal computer (personal computer, PC), television (TV), teller machine or self-service machine, etc., and the embodiments of the present application are not limited in particular.

The electronic equipment provided by the embodiment of the application can realize refreshing on different display areas of the display screen according to the respective corresponding frame rates based on the display control system, thereby saving the energy consumption of the electronic equipment.

The embodiment of the application also provides a display method, which can be applied to any display control system in the embodiment shown in fig. 4a to 9, as shown in fig. 10, and the method includes:

Step 1001, obtaining frame rates corresponding to at least two display areas on a display screen.

Step 1002, refreshing image content in the at least two display areas according to respective corresponding frame rates.

The frame rate corresponding to each of the at least two display areas on the display screen may be obtained based on at least one of user setting, application scenario, system configuration, user operation trigger, etc., for example: in the case of the power saving mode being turned on, the refresh frame rate of the display screen is low.

For another example: the refresh frame rate may be different when different applications are opened, for example: the refresh frame rate of the chat interface is lower than the refresh frame rate of the game interface.

Also for example: the refresh frame rate of the display area operated by the user is higher than the refresh frame rate of the display area not operated by the user.

The at least two display areas may be display areas corresponding to interfaces of at least two applications, or the at least two display areas may be display areas of different windows in the same application, which is not limited herein specifically.

In the embodiment of the application, the GOA circuits corresponding to the at least two display areas can be controlled by the control circuit, and the display areas are refreshed according to the frame rates corresponding to the GOA circuits. The embodiment of the present application can achieve the same technical effects as any one of the display control systems shown in fig. 4a to 9, and is not repeated here.

Optionally, as shown in fig. 11, the embodiment of the present application further provides an electronic device 1100, including a processor 1101 and a memory 1102, where the memory 1102 stores a program or an instruction that can be executed on the processor 1101, and the program or the instruction implements each step of the embodiment of the display method when executed by the processor 1101, and the steps can achieve the same technical effect, so that repetition is avoided, and no further description is given here.

The electronic device in the embodiment of the application includes the mobile electronic device and the non-mobile electronic device.

Fig. 12 is a schematic hardware structure of an electronic device implementing an embodiment of the present application.

The electronic device 1200 includes, but is not limited to: radio frequency unit 1201, network module 1202, audio output unit 1203, input unit 1204, sensor 1205, display unit 1206, user input unit 1207, interface unit 1208, memory 1209, and processor 1210.

Those skilled in the art will appreciate that the electronic device 1200 may also include a power source (e.g., a battery) for powering the various components, which may be logically connected to the processor 1210 by a power management system, such as to perform functions such as managing charging, discharging, and power consumption by the power management system. The electronic device structure shown in fig. 12 does not constitute a limitation of the electronic device, and the electronic device may include more or less components than illustrated, or may combine certain components, or may be arranged in different components, which are not described in detail herein.

The processor 1210 is configured to obtain frame rates corresponding to at least two display areas on the display screen;

the processor 1210 is further configured to control the display unit 1206 to refresh image content in the at least two display areas at respective corresponding frame rates.

The electronic device provided by the embodiment of the present application can implement each process of the method embodiment shown in fig. 10, and can obtain the same beneficial effects, so that repetition is avoided, and no further description is given here.

It should be appreciated that in embodiments of the present application, the input unit 1204 may include a graphics processor (Graphics Processing Unit, GPU) 12041 and a microphone 12042, the graphics processor 12041 processing image data of still pictures or video obtained by an image capturing device (e.g., a camera) in a video capturing mode or an image capturing mode. The display unit 1206 may include a display panel 12061, and the display panel 12061 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 1207 includes at least one of a touch panel 12071 and other input devices 12072. The touch panel 12071 is also called a touch screen. The touch panel 12071 may include two parts, a touch detection device and a touch controller. Other input devices 12072 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and so forth, which are not described in detail herein.

Memory 1209 may be used to store software programs as well as various data. The memory 1209 may mainly include a first memory area storing programs or instructions and a second memory area storing data, wherein the first memory area may store an operating system, application programs or instructions (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like. Further, the memory 1209 may include volatile memory or nonvolatile memory, or the memory 1209 may include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash Memory. The volatile memory may be random access memory (Random Access Memory, RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (ddr SDRAM), enhanced SDRAM (Enhanced SDRAM), synchronous DRAM (SLDRAM), and Direct RAM (DRRAM). Memory 1209 in embodiments of the present application includes, but is not limited to, these and any other suitable types of memory.

Processor 1210 may include one or more processing units; optionally, processor 1210 integrates an application processor that primarily processes operations involving an operating system, user interface, application programs, and the like, and a modem processor that primarily processes wireless communication signals, such as a baseband processor. It will be appreciated that the modem processor described above may not be integrated into processor 1210.

The embodiment of the application also provides a readable storage medium, on which a program or an instruction is stored, which when executed by a processor, implements each process of the above-described embodiment of the display method, and can achieve the same technical effects, so that repetition is avoided, and no further description is given here.

Wherein the processor is a processor in the electronic device described in the above embodiment. The readable storage medium includes computer readable storage medium such as computer readable memory ROM, random access memory RAM, magnetic or optical disk, etc.

The embodiment of the application further provides a chip, which comprises a processor and a communication interface, wherein the communication interface is coupled with the processor, and the processor is used for running programs or instructions to realize the processes of the embodiment of the display method, and can achieve the same technical effects, so that repetition is avoided, and the description is omitted here.

It should be understood that the chips referred to in the embodiments of the present application may also be referred to as system-on-chip chips, chip systems, or system-on-chip chips, etc.

Embodiments of the present application provide a computer program product stored in a storage medium, where the program product is executed by at least one processor to implement the respective processes of the embodiments of the display method described above, and achieve the same technical effects, and for avoiding repetition, a detailed description is omitted herein.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a computer software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present application.

The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.

Claims

1. A display control system, comprising: the display screen and the display processing unit DPU are connected with each other;

the DPU comprises a first processing module;

n driving circuits are in one-to-one correspondence with N display areas;

the control circuit is respectively connected with the N driving circuits;

2. The system of claim 1, wherein the first processing module comprises:

3. The system of claim 1 or 2, wherein the display control system further comprises:

the first buffer is used for buffering layer information, and the first storage space is used for iteratively storing at least one line of image data to be transmitted to the DDIC in the first image processed by the DPU;

the number of the first caches is N, the N first caches are in one-to-one correspondence with the frame rates of the N display areas, and the N first caches are respectively used for caching layer information of the frame rates corresponding to the N first caches;

the number of the first storage spaces is Y, and the Y first storage spaces are respectively used for storing image data in first images with corresponding reference frame rates, wherein the reference frame rates are related to the frame rates of the corresponding sub-areas with image contents in the first images.

4. A display control system, comprising: the display screen and the display processing unit DPU are connected with each other;

the DPU comprises M processing paths, wherein M is a positive integer;

the DDIC is connected between the processing path and the N driving circuits;

n driving circuits are in one-to-one correspondence with N display areas;

the control circuit is respectively connected with the N driving circuits;

5. The system of claim 4, wherein the DPU further comprises:

and X first interfaces, wherein X is a positive integer, and the DPU transmits N second images to the DDIC through the X first interfaces.

6. The system of claim 5, wherein in the case where M is greater than 1 and X is less than M, the DPU further comprises:

the switching module comprises M first ends and X second ends, the M first ends are connected with the M processing channels in a one-to-one correspondence manner, and the X second ends are connected with the X first interfaces in a one-to-one correspondence manner;

the switching module is configured to switch a conducting relationship between the X second ends and the M first ends, where, when the target first end is conducted with the target second end, the second image processed by the processing path correspondingly connected to the target first end is sent to the DDIC through the first interface correspondingly connected to the target second end, the M first ends include the target first end, and the X second ends include the target second end.

7. The system of any one of claims 4 to 6, wherein the display control system further comprises:

A synchronization signal line connected between the DPU and the DDIC for transmitting N kinds of synchronization signals to the DPU through the synchronization signal line;

the DPU is used for synchronizing a second image with the corresponding frame rate to the DDIC according to the N synchronizing signals.

8. The system according to any one of claims 4 to 7, wherein the number of DDICs is N, the number of the synchronization signal lines is N, N of the synchronization signal lines are in one-to-one correspondence with N of the synchronization signals, and N of the DDICs are in one-to-one correspondence with N of the synchronization signal lines;

the target DDIC is configured to send a target synchronization signal to the DPU through a target synchronization signal line, where the N DDICs include the target DDIC, the N synchronization signal lines include the target synchronization signal line, the N synchronization signals include the target synchronization signal, and the target DDIC corresponds to the target synchronization signal line.

9. The system of any one of claims 4 to 8, wherein the display control system further comprises:

the first buffer is used for buffering layer information, and the first storage space is used for iteratively storing at least one line of image data to be transmitted to the DDIC in the second image processed by the DPU;

the number of the first storage spaces is Y, and the Y first storage spaces are respectively used for storing image data in the second images with the corresponding reference frame rates, wherein the reference frame rates are related to the frame rates of the corresponding second images.

10. A display control system, comprising: the display screen and the display processing unit DPU are connected with each other;

n driving circuits are in one-to-one correspondence with N display areas;

the control circuit is respectively connected with the N driving circuits;

11. The system of claim 10, wherein the first processing module comprises:

the synthesizing module is used for synthesizing the data streams output by the M processing paths to obtain the first image; or alternatively, the first and second heat exchangers may be,

and the jigsaw module is used for carrying out jigsaw processing on M third images processed by the M processing paths to obtain the first images.

12. The system of claim 10 or 11, wherein the display control system further comprises:

the number of the first storage spaces is Y, and the Y first storage spaces are respectively used for storing image data in the first images with the corresponding reference frame rates, wherein the reference frame rates are related to the frame rates of the corresponding sub-areas with image contents in the first images.

13. The system of claim 11 or 12, wherein in the case where the first processing module comprises the puzzle module, the display control system further comprises:

14. The system of claim 13, wherein the mosaic module comprises a first unit configured to determine whether M of the processing lanes have the processed third image, or the first unit is configured to receive first information from M of the processing lanes;

15. The system of any of claims 11 to 14, wherein M is less than N, at least some of the M processing lanes being used for serial processing of the layer information for at least two different frame rates.

16. The system according to any one of claims 11 to 15, wherein the DPU further comprises:

x first interfaces, X is a positive integer, and the first processing module sends the first image to the DDIC through the X first interfaces.

17. An electronic device comprising the display control system of any one of claims 1 to 16.

18. A display method applied to the display control system according to any one of claims 1 to 16, the method comprising:

19. An electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the display method of claim 18.

20. A readable storage medium having stored thereon a program or instructions which when executed by a processor perform the steps of the display method of claim 18.