CN116959374A - Frame rate control method, device, electronic equipment and storage medium - Google Patents
Frame rate control method, device, electronic equipment and storage medium Download PDFInfo
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
- G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
- G09G2340/0435—Change or adaptation of the frame rate of the video stream
Abstract
The application discloses a frame rate control method, a frame rate control device, electronic equipment and a storage medium, and belongs to the technical field of electronics. The method comprises the following steps: determining a target offset based on a window length of a data processing window corresponding to a second frame rate during the displaying at the first frame rate, the second frame rate being greater than the first frame rate; shifting the data processing window corresponding to the first frame rate based on the target offset to obtain a first data processing window; and processing first data in the first data processing window, wherein the first data is display data in the process of displaying at a first frame rate.
Description
Technical Field
The application belongs to the technical field of electronics, and particularly relates to a frame rate control method, a frame rate control device, electronic equipment and a storage medium.
Background
Currently, electronic devices can change the refresh rate of content displayed on a screen by changing different screen refresh rates to achieve the goal of frame rate conversion. In the related art, the electronic device may send a command to the screen driver, where the command includes a refresh rate to be updated, and related configuration parameters and timing corresponding to the refresh rate, so that the electronic device may perform frame rate conversion.
However, since the above command contains more information, the delay of the electronic device sending the command to the screen driver is larger, so that the user can feel that the electronic device is significantly stuck during the frame changing period, and thus, the smoothness of the frame rate conversion process of the electronic device is poor.
Disclosure of Invention
The embodiment of the application aims to provide a frame rate control method, a frame rate control device, electronic equipment and a storage medium, which can improve the fluency of the frame rate conversion process of the electronic equipment.
In a first aspect, an embodiment of the present application provides a frame rate control method, including: determining a target offset based on a window length of a data processing window corresponding to a second frame rate during the displaying at the first frame rate, the second frame rate being greater than the first frame rate; shifting the data processing window corresponding to the first frame rate based on the target offset to obtain a first data processing window; and processing the first data in the first data processing window, wherein the first data is display data in the process of displaying at the first frame rate.
In a second aspect, an embodiment of the present application provides a frame rate control apparatus, including: the device comprises a determining module, an offset module and a processing module. And the determining module is used for determining the target offset based on the window length of the data processing window corresponding to the second frame rate in the process of displaying by adopting the first frame rate, wherein the second frame rate is larger than the first frame rate. And the offset module is used for offsetting the data processing window corresponding to the first frame rate based on the target offset determined by the determination module to obtain a first data processing window. And the processing module is used for processing the first data in the first data processing window obtained based on the moving module, wherein the first data is display data in the process of displaying by adopting the first frame rate.
In a third aspect, an embodiment of the present application provides an electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the method as described in the first aspect.
In a fourth aspect, embodiments of the present application provide a readable storage medium having stored thereon a program or instructions which when executed by a processor perform the steps of the method according to the first aspect.
In a fifth aspect, an embodiment of the present application provides a chip, where the chip includes a processor and a communication interface, where the communication interface is coupled to the processor, and where the processor is configured to execute a program or instructions to implement a method according to the first aspect.
In a sixth aspect, embodiments of the present application provide a computer program product stored in a storage medium, the program product being executable by at least one processor to implement the method according to the first aspect.
In the embodiment of the application, in the process of displaying by adopting the first frame rate, the electronic equipment can determine the target offset based on the window length of the data processing window corresponding to the second frame rate, wherein the second frame rate is larger than the first frame rate; shifting the data processing window corresponding to the first frame rate based on the target offset to obtain a first data processing window; and processing the first data in the first data processing window, wherein the first data is display data in the process of displaying at the first frame rate. In the scheme, the target offset is determined through the window length of the data processing window corresponding to the second frame rate, so that the window length of the first data processing window obtained by the electronic device based on the target offset can be similar to the window length of the data processing window corresponding to the second frame rate, so that the rendering time and the synthesizing time corresponding to the first frame rate can be aligned with the rendering time and the synthesizing time corresponding to the second frame rate, and when the electronic device is switched from the first frame rate to the second frame rate, the data processing window corresponding to the second frame rate can be seamlessly connected to the back of the first data processing window, and the smoothness of the electronic device in the frame rate conversion process is improved.
Drawings
Fig. 1 is a diagram of an example of a vertical synchronization signal (vertical synchronizing signal, vsync) model in the related art;
FIG. 2 is one of the timing diagrams of a related art vsync model;
FIG. 3 is a second timing diagram of a related art vsync model;
fig. 4 is a flowchart of a frame rate control method according to an embodiment of the present application;
FIG. 5 is a second flowchart of a frame rate control method according to an embodiment of the present application;
FIG. 6 is a timing diagram of a vsync model provided by an embodiment of the present application;
FIG. 7 is a second timing diagram of a vsync model according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a frame rate control device according to an embodiment of the present application;
fig. 9 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present application;
fig. 10 is a second schematic diagram of a hardware structure of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions of the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the present application, fall within the scope of protection of the present application.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application are capable of operation in sequences other than those illustrated or otherwise described herein, and that the objects identified by "first," "second," etc. are generally of a type not limited to the number of objects, for example, the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
The terms "at least one," "at least one," and the like in the description and in the claims, mean that they encompass any one, any two, or a combination of two or more of the objects. For example, at least one of a, b, c (item) may represent: "a", "b", "c", "a and b", "a and c", "b and c" and "a, b and c", wherein a, b, c may be single or plural. Similarly, the term "at least two" means two or more, and the meaning of the expression is similar to the term "at least one".
The frame rate control method, the device, the electronic equipment and the storage medium method provided by the embodiment of the application are described in detail below through specific embodiments and application scenes thereof with reference to the accompanying drawings.
The frame rate control method, the frame rate control device, the electronic equipment and the storage medium provided by the embodiment of the application can be applied to a screen refreshing scene.
With the development of electronic devices, an organic light emitting display (Organic Light Emitting Display, OLED) screen is mostly used in the screen of the electronic device, and the OLED screen can support to switch between different screen refresh rates. For example, the electronic device may switch the screen refresh rate from 60HZ to 120HZ, or from 120HZ to 60HZ, and it is understood that the higher the refresh rate, the smoother the content displayed in the screen of the electronic device.
In the related art, when the electronic device performs frame rate switching, the frame rate switching in the electronic device may be initiated by a system end, and then a Display Driver in a screen is invoked, and the Display Driver may send a corresponding command code after processing a related flow, where the code includes a frame rate to be switched at the next moment, and parameter configuration and timing related to the frame rate; then, the electronic device may transmit the code to a display driver chip (Display Driver Integrated Circuit, DDIC) in the screen through a serial interface (MobileIndustry Processor Interface-Display Serial Interface, MIPI-DSI), and further, after the DDIC receives the code, the DDIC may change relevant parameter configuration and timing of the frame rate through the code at the next moment, so as to achieve the purpose of frame rate switching.
In general, a DDIC in a screen of an electronic device may send a hardware vertical synchronization signal (HardWork-vertical synchronizing signal, HW-vsync) to a processor decentralized processing unit (Data Processing Unit, DPU) and a graphics processor (Graphics Processing Unit, GPU) in the electronic device, the HW-vsync being used to synchronize a refresh cadence of a frame rate and a refresh rate. Then, the electronic device may display data under different frame rates through the Vsync model, for example, after obtaining the HW-Vsync, the DPU may obtain the Vsync-app and the Vsync-sf after sampling and calculating the HW-Vsync through the surfeflinger service; the Vsync-app is used for indicating the composition time of the display data in the screen of the electronic device, the Vsync-sf is used for indicating the rendering time of the display data after composition, then the GPU can render the display data after composition, and the DPU can compose the display data, namely, the display data after changing the frame rate, and send the display data to the screen for display.
It should be noted that, the refresh rate and the frame rate need to cooperate to enable the content of the application program in the electronic device to be displayed on the screen, that is, the GPU may acquire the image data and then render the image data, so that the rendered image data is presented on the screen, and the refresh rate refers to the number of times that the image on the screen is repeatedly scanned by the electron beam. It can be appreciated that the higher the refresh rate, the better the stability of the picture displayed on the screen of the electronic device; the Frame rate (Frame rate) is the frequency (rate) at which bitmap images in units of frames appear continuously on the display.
By way of example, FIG. 1 shows a model architecture diagram of a typical Vsync model, which includes Vsync-app, vsync-sf, and HW-Vsync layers, as shown in FIG. 1. The Vsync-app layer is used for rendering data, the Vsync-sf layer is used for synthesizing data, and the HW-Vsync layer is used for transmitting processed data to the display panel for display.
Taking a frame of data displayed in a display screen of an electronic device as an example, assuming that the frame of data includes image data of a status bar, image data of a navigation bar and image data of a setting application program, the electronic device may render the image data of the status bar, the image data of the navigation bar and the image data of the setting application program through a Vsync-app layer, then send all the image data after rendering to the Vsync-sf layer, and then send all the image data to a DPU or a GPU through a surfacef link service in the Vsync-sf layer for data synthesis to obtain a frame of image data, and then send the frame of image data to a HW-Vsync layer, and in case that HW-Vsync in the HW-Vsync layer is triggered, send the frame of image data to a Panel for display.
Illustratively, in connection with the above-described fig. 1, fig. 2 shows a vsync timing diagram of a vsync model. As shown in fig. 2, without considering the phase offset, it is assumed that the Vsync-app layer of the Vsync model includes a data processing window corresponding to Frame1 and a data processing window corresponding to Frame2, where the Frame1 corresponding Frame rate is the same as the Frame2 corresponding Frame rate.
Example 1: for Frame1, as shown in fig. 2, in the Vsync-app layer, the electronic device may render image data within a data processing window corresponding to Frame1, after rendering is completed, in the Vsync-sf layer, the electronic device may combine image data corresponding to Frame1 after the data processing window corresponding to Frame1 in the Vsync-app layer, and after combining is completed, in the HW-Vsync layer, the electronic device may display image data corresponding to Frame1 after the data processing window in the Vsync-sf layer. Thus, it can be seen that in this shifted state, one frame of layer data needs to be completed via 3 vsync timings, one for each level in the vsync model, each of the different layers in the vsync model being shifted back in turn by the length occupied by one data processing window.
Example 2: as shown in fig. 2, the Frame2 or the subsequent Frame n may be displayed sequentially at the processing sequence represented by this timing chart. However, if a Frame2 appears behind the Frame2, as shown in fig. 3, for example, when the current Frame1 and Frame2 are 60Hz, and then the Frame3 needs to be switched to 120Hz, based on the Vsync model shown in fig. 1, a delay is generated between 60Hz and 120Hz due to the longer window length of the data processing window corresponding to the Frame2, so that the data processing window corresponding to the Frame3 cannot be connected behind the Frame3 in the Vsync-sf layer, and similarly, the data processing window corresponding to the Frame3 cannot be connected behind the Frame3 in the HW-Vsync layer, and further, the delay is increased due to the more information contained in the code, so that the smoothness of the Frame rate conversion process of the electronic device is poor.
In the frame rate control method, the device, the electronic equipment and the storage medium provided by the application, because the target offset is determined by the window length of the data processing window corresponding to the second frame rate, the window length of the first data processing window obtained by the electronic equipment based on the target offset can be similar to the window length of the data processing window of the second frame rate, so that the rendering time and the synthesizing time corresponding to the first frame rate can be aligned with the rendering time and the synthesizing time corresponding to the second frame rate, and therefore, when the electronic equipment is switched from the first frame rate to the second frame rate, the data processing window corresponding to the second frame rate can be seamlessly connected to the back of the first data processing window, and the smoothness of the electronic equipment in the frame rate conversion process is improved.
The execution body of the frame rate control method provided by the embodiment of the application can be a frame rate control device, and the frame rate control device can be an electronic device or a functional module in the electronic device. The technical solution provided by the embodiment of the present application is described below by taking an electronic device as an example.
An embodiment of the present application provides a frame rate control method, and fig. 4 shows a flowchart of the frame rate control method provided by the embodiment of the present application. As shown in fig. 4, the frame rate control method provided by the embodiment of the present application may include the following steps 201 to 203.
In step 201, in the process of displaying at the first frame rate, the electronic device determines the target offset based on the window length of the data processing window corresponding to the second frame rate.
In the embodiment of the present application, the second frame rate is greater than the first frame rate.
In the embodiment of the application, in the process of displaying by adopting the first frame rate, the electronic device can set a fixed target offset for the window length of the data processing window corresponding to the first frame rate according to the window length of the data processing window corresponding to the second frame rate, so that the rendering time and the synthesizing time of the data processing corresponding to the first frame rate can be aligned with the rendering time and the synthesizing time of the data processing corresponding to the second frame rate, and the data processing window corresponding to the first frame rate can be connected with the data processing window corresponding to the second frame rate in a seamless manner.
In the above-described process of displaying at the first frame rate, it is understood that the use timing of the first frame rate in the present embodiment is before the use timing of the second frame rate.
By way of example, assuming that the current display content in the screen of the electronic device is news information, the frame rate of the display content may be 60HZ.
In an embodiment of the application, the second frame rate may be determined by the electronic device; or selected for the user.
In an embodiment of the present application, the data processing window corresponding to the second frame rate refers to a processing window for processing, by the electronic device, image data corresponding to the second frame rate.
For example, assuming that the frame rate is 60HZ, the window length of the data processing window corresponding to the frame rate is: the electronic device processes the processing window required for one frame of image data at 60HZ.
Optionally, in the embodiment of the present application, the electronic device may obtain, based on the first correspondence, a window length of the data processing window corresponding to the second frame rate and the second frame rate, that is, the electronic device may obtain, by knowing the second frame rate, the window length of the data processing window corresponding to the second frame rate.
For example, the first correspondence may be preset for the electronic device.
For example, if the second frame rate is 120HZ, the window length of the data processing window corresponding to 120HZ is 8.3ms, that is, the electronic device may directly obtain the window length of the data processing window corresponding to the second frame rate after obtaining the second frame rate.
Optionally, in the embodiment of the present application, the electronic device may pre-store a plurality of correspondence relationships, and then determine window lengths of data processing windows corresponding to different frame rates based on the plurality of correspondence relationships.
Illustratively, the plurality of correspondence relationships include correspondence relationships of a plurality of different frame rates, one frame rate corresponds to one correspondence relationship, and the correspondence relationship of any frame rate includes a mapping relationship between the frame rate and a window length of one data processing window.
For example, the above-mentioned correspondence relationships may be set according to actual requirements or industry standards, which is not limited by the present application.
Alternatively, in the embodiment of the present application, the target offset may be the same as the window length of the data processing window corresponding to the second frame rate, or the target offset may be different from the window length of the data processing window corresponding to the second frame rate.
Alternatively, in an embodiment of the present application, as shown in fig. 5 in conjunction with fig. 4, the above step 201 may be specifically implemented by the following step 201 a.
In step 201a, the electronic device uses the window length of the data processing window corresponding to the second frame rate as the target offset.
In the embodiment of the application, after the electronic device determines the second frame rate, the electronic device may obtain the window length of the data processing window corresponding to the second frame rate according to the first correspondence, so as to use the window length of the data processing window corresponding to the second frame rate as the target offset.
In the embodiment of the application, the electronic equipment takes the window length of the data processing window corresponding to the second frame rate as the target offset, so that the window length of the data processing window corresponding to the first frame rate after the offset can be consistent with the window length of the data processing window corresponding to the second frame rate, and further, the rendering time and the synthesizing time corresponding to the first frame rate are consistent with the rendering time and the synthesizing time corresponding to the second frame rate, and thus, the electronic equipment can avoid larger time delay of frame rate switching caused by inconsistent rendering time or synthesizing time when the first frame rate is switched to the second frame rate.
Step 202, the electronic device shifts the data processing window corresponding to the first frame rate based on the target offset, so as to obtain a first data processing window.
In the embodiment of the application, after the electronic device obtains the target offset, the electronic device can forward offset the data processing window corresponding to the first frame rate by the length corresponding to the target offset, and then obtain the first data processing window.
In an example, the electronic device may shift the data processing window corresponding to the first frame rate forward by a length corresponding to the target offset based on the target offset, so as to obtain the first data processing window, that is, the electronic device may change the starting position of the data processing window corresponding to the first frame rate in the time sequence, and not change the window length of the data processing window corresponding to the first frame rate.
Illustratively, assuming that the position of the data processing window corresponding to the first frame rate is 0 and the target offset is 8.3ms, the electronic device may offset the position of the data processing window corresponding to the first frame rate to minus 8.3 ms.
In one example, the electronic device may compress the window length of the data processing window corresponding to the first frame rate by the corresponding length of the target offset based on the target offset, so as to obtain the first data processing window, that is, the electronic device may not change the starting position of the data processing window corresponding to the first frame rate in the time sequence, but update the window length of the data processing window corresponding to the first frame rate.
By way of example, assuming that the window length of the data processing window corresponding to the first frame rate is 16.67ms and the target offset is 8.3ms, the electronic device may compress the window length of the data processing window corresponding to the first frame rate, that is, 16.67ms-8.3ms, to obtain a compressed first data processing window, that is, the window length of the compressed first data processing window is 8.37ms.
Alternatively, in the embodiment of the present application, the above step 202 may be specifically implemented by the following step 202 a.
Step 202a, the electronic device compresses the data processing window corresponding to the first frame rate according to the target offset and the parameter corresponding to the first frame rate, so as to obtain a first data processing window.
In the embodiment of the present application, the parameters corresponding to the first frame rate include:
a vertical synchronization signal rendering parameter, a vertical synchronization signal synthesis parameter, and a hardware vertical synchronization signal;
the vertical synchronization signal rendering parameter is used for indicating rendering time of display data in the process of displaying by adopting the first frame rate;
the vertical synchronizing signal synthesis parameter is used for indicating the synthesis time of the display data in the process of displaying by adopting the first frame rate;
the hardware vertical synchronization signal is used for indicating display time of display data in the process of displaying by adopting the first frame rate.
In the embodiment of the application, aiming at the rendering parameters of the vertical synchronization signal, the electronic equipment can offset the rendering time of the display data in the process of displaying by the electronic equipment by adopting the first frame rate based on the target offset, so that the rendering time corresponding to the rendering parameters of the vertical synchronization signal can be consistent with the rendering time corresponding to the second frame rate.
In the embodiment of the application, for the synthesis parameters of the vertical synchronization signal, the electronic device can use the synthesis time of the display data in the process of displaying the electronic device by adopting the first frame rate based on the target offset, so that the synthesis time corresponding to the synthesis parameters of the vertical synchronization signal can be consistent with the synthesis time corresponding to the second frame rate.
In the embodiment of the application, aiming at the hardware vertical synchronization signal, the electronic equipment can display the display time of the display data in the process of displaying the electronic equipment by adopting the first frame rate based on the target offset, so that the display time corresponding to the hardware vertical synchronization signal can be consistent with the display time corresponding to the second frame rate.
In the embodiment of the present application, the rendering parameters of the vertical synchronization signal may be parameters corresponding to Vsync-app, the synthesizing parameters of the vertical synchronization signal may be parameters corresponding to Vsync-sf, and the vertical synchronization signal of the hardware may be parameters corresponding to HW-Vsync.
It will be appreciated that the Vsync-app, vsync-sf, and HW-Vsync described above are different levels in the Vsync model, each level representing a data processing opportunity. For the Vsync-app level, assuming that the level includes two data processing windows corresponding to the first frame rate, the electronic device may perform compression processing on the data processing windows corresponding to the two first frame rates in the Vsync-app level, so as to obtain first data processing windows corresponding to the two first frame rates, and similarly, the Vsync-sf layer and the HW-Vsync layer may all obtain first data processing windows corresponding to the first frame rates in different levels.
For the Vsync-app layer, the electronic device may subtract the target offset from the window length of the data processing window corresponding to the first frame rate after determining the target offset, so as to obtain a first data processing window, that is, the data processing window corresponding to the compressed first frame rate, so as to obtain the first data processing window, where the window length of the first data processing window obtained by the electronic device at different levels may be consistent with the window length of the data processing window corresponding to the second frame rate at different levels.
For example, as shown in fig. 6, the electronic device may set a fixed target offset, that is, an offset of 8.3ms, for the Vsync-app layer, the Vsync-sf layer, and the HW-Vsync layer in the Vsync model, then, for each level, the electronic device may subtract 8.3ms from the 16.67ms data processing duration corresponding to 60HZ, and then obtain an updated data processing duration, that is, the first data processing window, so that the electronic device may align the Vsync-app actual rendering and the Vsync-sf synthesis time under 60HZ to 120HZ, thereby ensuring that seamless connection between 60HZ and 120HZ may be performed.
Therefore, the electronic device can make the data processing window corresponding to the first frame rate and the data processing window corresponding to the second frame rate be in seamless connection by performing offset adjustment on the rendering time, the synthesis time and the display time.
Optionally, in the embodiment of the present application, after the step 202, the frame rate control method provided in the embodiment of the present application further includes the following step 301.
Step 301, the electronic device reserves blank data processing windows except the first data processing window in the data processing windows corresponding to the first frame rate.
That is, the first data processing window is adjacent to the blank data processing window.
In the embodiment of the application, after the electronic equipment compresses the data processing windows corresponding to the first frame rate, the electronic equipment can reserve the data processing windows except the first data processing window in the data processing windows corresponding to the first frame rate, so that the time sequence of the data processing windows corresponding to the same frame rate can not be shifted forwards under the condition of unchanged frame, and the time sequence of the first frame rate can not be disordered.
Step 203, the electronic device processes the first data within the first data processing window.
In the embodiment of the present application, the first data is display data in a process of displaying at a first frame rate.
By way of example, assuming that the window length of the data processing window corresponding to the first frame rate is 16.67ms, the window length of the first data processing window is 8.37ms, i.e., 16.67ms-8.3ms, that is, the electronic device compresses the data processing window corresponding to the first frame rate such that the window length of the data processing window of the first frame rate approximates the window length of the data processing window corresponding to the second frame rate, that is, the electronic device may perform data processing at the first frame rate by the window length of the data processing window corresponding to the second frame rate.
In the frame rate control method provided by the embodiment of the application, in the process of adopting the first frame rate for display, the electronic equipment can determine the target offset based on the window length of the data processing window corresponding to the second frame rate, wherein the second frame rate is larger than the first frame rate; shifting the data processing window corresponding to the first frame rate based on the target offset to obtain a first data processing window; and processing the first data in the first data processing window, wherein the first data is display data in the process of displaying at the first frame rate. In the scheme, the target offset is determined by the window length of the data processing window corresponding to the second frame rate, so that the window length of the first data processing window obtained by the electronic device based on the target offset can be similar to the window length of the data processing window of the second frame rate, so that the rendering time and the synthesizing time corresponding to the first frame rate can be aligned with the rendering time and the synthesizing time corresponding to the second frame rate, and when the electronic device is switched from the first frame rate to the second frame rate, the data processing window corresponding to the second frame rate can be seamlessly connected to the back of the first data processing window, and the smoothness of the electronic device in the frame rate conversion process is improved.
Optionally, in the embodiment of the present application, after the step 202, the frame rate control method provided in the embodiment of the present application further includes a step 401 described below.
Step 401, the electronic device shifts the data processing window corresponding to the second frame rate based on the target offset.
In the embodiment of the present application, the data processing window corresponding to the shifted second frame rate is adjacent to the first data processing window.
It can be appreciated that, since the electronic device reserves a blank data processing window except for the first data processing window in the data processing window corresponding to the first frame rate, the electronic device may shift the position of the data processing window corresponding to the second frame rate forward entirely, so that the data processing window corresponding to the second frame rate may be adjacent to the rear of the first data processing window.
Illustratively, in connection with FIG. 6, as shown in FIG. 7, in the above-described Vsync-app layer, vsync-sf layer, and HW-Vsync layer, the electronic device may shift the positions of the data processing windows corresponding to 120HZ in each of the Vsync-sf layer, and HW-Vsync layer forward by 8.3ms, so that the data processing windows corresponding to 120HZ in each layer may be adjacent to the first data processing window corresponding to 60 HZ.
In the embodiment of the application, the electronic equipment forwards shifts the position of the data processing window corresponding to the second frame rate by the length corresponding to the target offset, so that the screen-on time corresponding to the second frame rate can be advanced after the electronic equipment is switched from the first frame rate to the second frame rate, and the display data corresponding to the second frame rate can be screen-on faster.
It can be understood that the above-mentioned on-screen timing is a timing at which the electronic device displays the image data at the second frame rate.
It should be noted that, in the frame rate control method provided by the embodiment of the present application, the execution body may be a frame rate control device, or an electronic device, or may also be a functional module or entity in the electronic device. In the embodiment of the present application, a frame rate control device is used as an example to execute a frame rate control method.
Fig. 8 is a schematic diagram showing a possible configuration of a frame rate control apparatus according to an embodiment of the present application. As shown in fig. 8, the frame rate control device 70 may include: a determination module 71, an offset module 72 and a processing module 73.
Wherein, the determining module 71 is configured to determine, during the displaying at the first frame rate, the target offset based on a window length of a data processing window corresponding to a second frame rate, where the second frame rate is greater than the first frame rate. And an offset module 72, configured to offset the data processing window corresponding to the first frame rate based on the target offset determined by the determining module 71, to obtain a first data processing window. The processing module 73 is configured to process, in the first data processing window obtained by the offset module 72, first data, which is display data in a process of displaying at the first frame rate.
In one possible implementation manner, the determining module 71 is specifically configured to use a window length of the data processing window corresponding to the second frame rate as the target offset.
In one possible implementation manner, the offset module 73 is specifically configured to compress the data processing window corresponding to the first frame rate according to the target offset and the parameter corresponding to the first frame rate, to obtain a first data processing window; the parameters corresponding to the first frame rate include: a vertical synchronization signal rendering parameter, a vertical synchronization signal synthesis parameter, and a hardware vertical synchronization signal; the vertical synchronization signal rendering parameter is used for indicating rendering time of display data in the process of displaying by adopting the first frame rate; the vertical synchronization signal synthesis parameter is used for indicating the synthesis time of the display data in the process of displaying by adopting the first frame rate; the hardware vertical synchronization signal is used for indicating display timing of display data in the process of displaying at the first frame rate.
In one possible implementation manner, the frame rate control device provided by the embodiment of the application further includes: a reservation module; and a reserving module, configured to, based on the target offset, perform offset on the data processing window corresponding to the first frame rate by using the offset module 72, and reserve a blank data processing window except for the first data processing window in the data processing window corresponding to the first frame rate after the first data processing window is obtained.
In a possible implementation manner, the offset module 73 is further configured to offset the data processing window corresponding to the first frame rate based on the target offset, and after obtaining the first data processing window, offset the data processing window corresponding to the second frame rate based on the target offset, where the data processing window corresponding to the second frame rate after the offset is adjacent to the first data processing window.
The embodiment of the application provides a frame rate control device, because a target offset is determined by the window length of a data processing window corresponding to a second frame rate, the window length of a first data processing window obtained by the frame rate control device based on the target offset can be similar to the window length of the data processing window corresponding to the second frame rate, so that the rendering time and the synthesizing time corresponding to the first frame rate can be aligned with the rendering time and the synthesizing time corresponding to the second frame rate, and therefore, when the frame rate control device is switched from the first frame rate to the second frame rate, the data processing window corresponding to the second frame rate can be seamlessly connected to the first data processing window, and the smoothness of the frame rate control device in the frame rate conversion process is improved.
The frame rate control device in the embodiment of the application can be an electronic device or a component in the electronic device, such as an integrated circuit or a chip. The electronic device may be a terminal, or may be other devices than a terminal. By way of example, the mobile electronic device may be a mobile phone, tablet computer, notebook computer, palm computer, vehicle-mounted electronic device, mobile internet appliance (Mobile Internet Device, MID), augmented reality (augmented reality, AR)/Virtual Reality (VR) device, robot, wearable device, ultra-mobile personal computer, UMPC, netbook or personal digital assistant (personal digital assistant, PDA), etc., and may also be a server, network attached storage (Network Attached Storage, NAS), personal computer (personal computer, PC), television (TV), teller machine or self-service machine, etc., without limitation of the embodiments of the present application.
The frame rate control device in the embodiment of the application can be a device with an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, and the embodiment of the present application is not limited specifically.
The frame rate control device provided by the embodiment of the application can realize each process realized by the embodiment of the method, and in order to avoid repetition, the description is omitted.
Optionally, as shown in fig. 9, the embodiment of the present application further provides an electronic device 90, which includes a processor 91 and a memory 92, where the memory 92 stores a program or an instruction that can be executed on the processor 91, and the program or the instruction implements each step of the embodiment of the frame rate control method when executed by the processor 91, and the steps achieve the same technical effects, so that repetition is avoided, and no further description is given here.
The electronic device in the embodiment of the application includes the mobile electronic device and the non-mobile electronic device.
Fig. 10 is a schematic diagram of a hardware structure of an electronic device implementing an embodiment of the present application.
The electronic device 100 includes, but is not limited to: radio frequency unit 101, network module 102, audio output unit 103, input unit 104, sensor 105, display unit 106, user input unit 107, interface unit 108, memory 109, and processor 110.
Those skilled in the art will appreciate that the electronic device 100 may further include a power source (e.g., a battery) for powering the various components, and that the power source may be logically coupled to the processor 110 via a power management system to perform functions such as managing charging, discharging, and power consumption via the power management system. The electronic device structure shown in fig. 10 does not constitute a limitation of the electronic device, and the electronic device may include more or less components than shown, or may combine certain components, or may be arranged in different components, which are not described in detail herein.
The processor 110 is configured to determine, during display at a first frame rate, a target offset based on a window length of a data processing window corresponding to a second frame rate, where the second frame rate is greater than the first frame rate; shifting the data processing window corresponding to the first frame rate based on the target offset to obtain a first data processing window; and processing first data in the first data processing window, wherein the first data is display data in the process of displaying at the first frame rate.
The embodiment of the application provides an electronic device, because a target offset is determined by the window length of a data processing window corresponding to a second frame rate, the window length of a first data processing window obtained by the electronic device based on the target offset can be similar to the window length of the data processing window corresponding to the second frame rate, so that the rendering time and the synthesizing time corresponding to the first frame rate can be aligned with the rendering time and the synthesizing time corresponding to the second frame rate, and therefore, when the electronic device is switched from the first frame rate to the second frame rate, the data processing window corresponding to the second frame rate can be seamlessly connected to the back of the first data processing window, and the smoothness of the electronic device in the frame rate conversion process is improved.
Optionally, in the embodiment of the present application, the processor 110 is specifically configured to use a window length of the data processing window corresponding to the second frame rate as the target offset.
Optionally, in the embodiment of the present application, the processor 110 is specifically configured to compress a data processing window corresponding to a first frame rate according to a target offset and a parameter corresponding to the first frame rate, to obtain a first data processing window; the parameters corresponding to the first frame rate include: a vertical synchronization signal rendering parameter, a vertical synchronization signal synthesis parameter, and a hardware vertical synchronization signal; the vertical synchronization signal rendering parameter is used for indicating rendering time of display data in the process of displaying by adopting a first frame rate; the vertical synchronizing signal synthesis parameter is used for indicating the synthesis time of display data in the process of displaying by adopting a first frame rate; the hardware vertical synchronization signal is used for indicating display timing of display data in the process of displaying at the first frame rate.
Optionally, in the embodiment of the present application, the processor 110 is further configured to offset the data processing window corresponding to the first frame rate based on the target offset, and after obtaining the first data processing window, reserve a blank data processing window except the first data processing window in the data processing window corresponding to the first frame rate.
Optionally, in the embodiment of the present application, the processor 110 is further configured to offset the data processing window corresponding to the first frame rate based on the target offset, after obtaining the first data processing window, offset the data processing window corresponding to the second frame rate based on the target offset, where the data processing window corresponding to the offset second frame rate is adjacent to the first data processing window.
The electronic device provided by the embodiment of the application can realize each process realized by the embodiment of the method and can achieve the same technical effect, and in order to avoid repetition, the description is omitted here.
The beneficial effects of the various implementation manners in this embodiment may be specifically referred to the beneficial effects of the corresponding implementation manners in the foregoing method embodiment, and in order to avoid repetition, the description is omitted here.
It should be appreciated that in embodiments of the present application, the input unit 104 may include a graphics processor (Graphics Processing Unit, GPU) 1041 and a microphone 1042, the graphics processor 1041 processing image data of still pictures or video obtained by an image capturing device (e.g., a camera) in a video capturing mode or an image capturing mode. The display unit 106 may include a display panel 1061, and the display panel 1061 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 107 includes at least one of a touch panel 1071 and other input devices 1072. The touch panel 1071 is also referred to as a touch screen. The touch panel 1071 may include two parts of a touch detection device and a touch controller. Other input devices 1072 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and so forth, which are not described in detail herein.
Memory 109 may be used to store software programs as well as various data. The memory 109 may mainly include a first memory area storing programs or instructions and a second memory area storing data, wherein the first memory area may store an operating system, application programs or instructions (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like. Further, the memory 109 may include volatile memory or nonvolatile memory, or the memory 109 may include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash Memory. The volatile memory may be random access memory (Random Access Memory, RAM), static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (ddr SDRAM), enhanced SDRAM (Enhanced SDRAM), synchronous DRAM (SLDRAM), and Direct RAM (DRRAM). Memory 109 in embodiments of the present application includes, but is not limited to, these and any other suitable types of memory.
Processor 110 may include one or more processing units; optionally, the processor 110 integrates an application processor that primarily processes operations involving an operating system, user interface, application programs, etc., and a modem processor that primarily processes wireless communication signals, such as a baseband processor. It will be appreciated that the modem processor described above may not be integrated into the processor 110.
The embodiment of the application also provides a readable storage medium, on which a program or an instruction is stored, which when executed by a processor, implements each process of the above method embodiment, and can achieve the same technical effects, and in order to avoid repetition, the description is omitted here.
Wherein the processor is a processor in the electronic device described in the above embodiment. The readable storage medium includes computer readable storage medium such as computer readable memory ROM, random access memory RAM, magnetic or optical disk, etc.
The embodiment of the application further provides a chip, which comprises a processor and a communication interface, wherein the communication interface is coupled with the processor, and the processor is used for running programs or instructions to realize the processes of the embodiment of the method, and can achieve the same technical effects, so that repetition is avoided, and the description is omitted here.
It should be understood that the chips referred to in the embodiments of the present application may also be referred to as system-on-chip chips, chip systems, or system-on-chip chips, etc.
Embodiments of the present application provide a computer program product stored in a storage medium, which is executed by at least one processor to implement the respective processes of the above-described frame rate control method embodiments, and achieve the same technical effects, and are not described herein in detail to avoid repetition.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a computer software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present application.
The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are to be protected by the present application.
Claims (12)
1. A frame rate control method, the method comprising:
determining a target offset based on a window length of a data processing window corresponding to a second frame rate during a display process using the first frame rate, the second frame rate being greater than the first frame rate;
shifting the data processing window corresponding to the first frame rate based on the target offset to obtain a first data processing window;
and processing first data in the first data processing window, wherein the first data is display data in the process of displaying by adopting the first frame rate.
2. The method of claim 1, wherein the determining the target offset based on the window length of the data processing window corresponding to the second frame rate comprises:
and taking the window length of the data processing window corresponding to the second frame rate as the target offset.
3. The method of claim 1, wherein the shifting the data processing window corresponding to the first frame rate based on the target offset, to obtain a first data processing window, includes:
compressing the data processing window corresponding to the first frame rate according to the target offset and the parameter corresponding to the first frame rate to obtain the first data processing window;
Wherein, the parameters corresponding to the first frame rate include:
a vertical synchronization signal rendering parameter, a vertical synchronization signal synthesis parameter, and a hardware vertical synchronization signal;
the vertical synchronization signal rendering parameter is used for indicating rendering time of display data in the process of displaying by adopting the first frame rate;
the vertical synchronization signal synthesis parameter is used for indicating the synthesis time of display data in the process of displaying by adopting the first frame rate;
the hardware vertical synchronization signal is used for indicating display time of display data in the process of displaying by adopting the first frame rate.
4. A method according to any one of claims 1 to 3, wherein the shifting the data processing window corresponding to the first frame rate based on the target offset, after obtaining a first data processing window, further comprises:
and reserving blank data processing windows except the first data processing window in the data processing windows corresponding to the first frame rate.
5. The method of claim 1, wherein the shifting the data processing window corresponding to the first frame rate based on the target offset, after obtaining a first data processing window, further comprises:
And shifting the data processing window corresponding to the second frame rate based on the target offset, wherein the data processing window corresponding to the shifted second frame rate is adjacent to the first data processing window.
6. A frame rate control apparatus, the apparatus comprising: the device comprises a determining module, an offset module and a processing module;
the determining module is used for determining a target offset based on the window length of a data processing window corresponding to a second frame rate in the process of displaying by adopting the first frame rate, wherein the second frame rate is larger than the first frame rate;
the offset module is configured to offset the data processing window corresponding to the first frame rate based on the target offset determined by the determining module, so as to obtain a first data processing window;
the processing module is configured to process first data in a first data processing window obtained based on the offset module, where the first data is display data in a process of displaying at the first frame rate.
7. The apparatus according to claim 6, wherein the determining module is specifically configured to use a window length of a data processing window corresponding to the second frame rate as the target offset.
8. The apparatus of claim 6, wherein the offset module is specifically configured to compress a data processing window corresponding to the first frame rate according to the target offset and a parameter corresponding to the first frame rate to obtain the first data processing window;
wherein, the parameters corresponding to the first frame rate include:
a vertical synchronization signal rendering parameter, a vertical synchronization signal synthesis parameter, and a hardware vertical synchronization signal;
the vertical synchronization signal rendering parameter is used for indicating rendering time of display data in the process of displaying by adopting the first frame rate;
the vertical synchronization signal synthesis parameter is used for indicating the synthesis time of display data in the process of displaying by adopting the first frame rate;
the hardware vertical synchronization signal is used for indicating display time of display data in the process of displaying by adopting the first frame rate.
9. The apparatus according to any one of claims 6 to 8, characterized in that the frame rate control apparatus further comprises: a reservation module;
the reservation module is configured to, based on the target offset, perform offset on the data processing window corresponding to the first frame rate, and reserve a blank data processing window except for the first data processing window in the data processing window corresponding to the first frame rate after the first data processing window is obtained.
10. The apparatus of claim 6, wherein the offset module is further configured to offset the data processing window corresponding to the first frame rate based on the target offset, and after obtaining a first data processing window, offset the data processing window corresponding to the second frame rate based on the target offset, where the data processing window corresponding to the second frame rate after the offset is adjacent to the first data processing window.
11. An electronic device comprising a processor, a memory and a program or instruction stored on the memory and executable on the processor, the program or instruction when executed by the processor implementing the steps of the frame rate control method according to any one of claims 1 to 5.
12. A readable storage medium, characterized in that the readable storage medium has stored thereon a program or instructions which, when executed by a processor, implement the steps of the frame rate control method according to any one of claims 1 to 5.
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