CN116721926A - Manufacturing method of packaging substrate, NAND Flash packaging substrate and storage particles - Google Patents

Manufacturing method of packaging substrate, NAND Flash packaging substrate and storage particles Download PDF

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Publication number
CN116721926A
CN116721926A CN202310628297.5A CN202310628297A CN116721926A CN 116721926 A CN116721926 A CN 116721926A CN 202310628297 A CN202310628297 A CN 202310628297A CN 116721926 A CN116721926 A CN 116721926A
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China
Prior art keywords
manufacturing
layer
metal layer
circuit pattern
copper block
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Pending
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CN202310628297.5A
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Chinese (zh)
Inventor
王闻师
胡秋勇
赖鼐
龚晖
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Zhuhai Miaocun Technology Co ltd
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Zhuhai Miaocun Technology Co ltd
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Priority to CN202310628297.5A priority Critical patent/CN116721926A/en
Publication of CN116721926A publication Critical patent/CN116721926A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

Abstract

The application provides a manufacturing method of a packaging substrate, a NAND Flash packaging substrate and storage particles, wherein the manufacturing method of the packaging substrate comprises the following steps: providing a first dielectric layer covered with a first metal layer, and manufacturing a first circuit pattern on the first metal layer; depositing a first circuit protection layer in a set area of the first metal layer, and depositing a first copper block on the first circuit protection layer; laminating a second dielectric layer on the first metal layer; forming a second metal layer on the second dielectric layer, and manufacturing a second circuit pattern on the second metal layer; manufacturing a via hole for communicating the first circuit pattern and the second circuit pattern; slotting on the second dielectric layer to expose the first copper block; covering a second dry film on the second metal layer, and etching the first copper block; and exposing and electroplating the first circuit pattern and the second circuit pattern which are positioned in the set area to form a first golden finger and a second golden finger. The manufacturing method of the packaging substrate can simplify the circuit pattern of the manufactured packaging substrate and simultaneously is beneficial to reducing the size of the packaging substrate.

Description

Manufacturing method of packaging substrate, NAND Flash packaging substrate and storage particles
Technical Field
The application relates to the field of semiconductor integrated circuit manufacturing, in particular to a manufacturing method of a packaging substrate, a NAND Flash packaging substrate and storage particles.
Background
The NAND Flash memory is one of Flash memories, and the NAND Flash has the characteristics of large capacity, high rewriting speed and the like, and provides a cheap and effective solution for realizing the solid-state large-capacity memory. According to the data quantity stored in each storage unit, the NAND Flash can be divided into SLC, MLC, TLC and QLC, and main manufacturers of the NAND Flash comprise three stars, armor, western numbers, beautiful lights and the like.
Because the functions of the pins of the NAND Flash produced by each manufacturer are different, in the related art, when the NAND Flash is packaged into the storage particle, a special packaging substrate needs to be designed for each type of NAND Flash. On one hand, the method leads to the need of repeatedly developing a plurality of packaging substrates, prolongs the product development time, and on the other hand, the method also brings trouble to the preparation of the packaging substrates on the production line, increases the management cost and even possibly affects the normal operation of the production line.
In some related technologies, a plurality of groups of golden fingers are arranged on the surface of a substrate, and each group of golden fingers is matched with NAND Flash of different types, so that the NAND Flash compatibility is realized, but the design can lead to complicated circuits, the design difficulty is increased, the minimum distance between the golden fingers is ensured, and the size of the substrate is increased.
Disclosure of Invention
The present application aims to solve at least one of the technical problems existing in the prior art. Therefore, the application provides a manufacturing method of the packaging substrate, the NAND Flash packaging substrate and the storage particles, wherein the manufacturing method of the packaging substrate is used for manufacturing the packaging substrate compatible with NAND Flash of different types, and the manufacturing method of the packaging substrate can simplify the circuit patterns of the packaging substrate and is beneficial to reducing the size of the packaging substrate.
The manufacturing method of the package substrate provided by the application comprises the following steps:
providing a first dielectric layer covered with a first metal layer, and manufacturing a first circuit pattern on the first metal layer;
depositing a first circuit protection layer in a set area of the first metal layer, and depositing a first copper block on the first circuit protection layer, wherein the set area refers to an area matched with a step groove to be formed;
laminating a second dielectric layer on the first metal layer, wherein the thickness of the second dielectric layer is larger than that of the first copper block, so that the first copper block is embedded in the second dielectric layer;
forming a second metal layer on the second dielectric layer, and manufacturing a second circuit pattern on the second metal layer;
manufacturing a via hole for communicating the first circuit pattern and the second circuit pattern;
slotting on the second dielectric layer to expose the first copper block;
covering a second dry film on the second metal layer, and etching the first copper block;
and exposing and electroplating the first circuit pattern and the second circuit pattern which are positioned in the setting area to form a first golden finger and a second golden finger.
The manufacturing method of the package substrate provided by the application has at least the following technical effects: the first golden finger and the second golden finger are respectively used for matching NAND Flash with different models, so that the packaging substrate manufacturing method can manufacture packaging substrates compatible with NAND Flash with different models, and the circuit patterns of the manufactured packaging substrate can be simplified by adopting a multi-layer design and exposing the first golden finger and the second golden finger in a stepped groove mode, and meanwhile, the size of the packaging substrate is reduced.
According to some embodiments of the application, the providing a first dielectric layer covered with a first metal layer, forming a first circuit pattern on the first metal layer includes: depositing a copper foil on the first metal layer; covering a first dry film on the copper foil, and exposing and developing to expose the set area; electroplating and depositing the first circuit protection layer in the set area; electroplating and depositing the first copper block on the first circuit protection layer; wherein the copper foil has a thickness of between 1 μm and 2 μm.
According to some embodiments of the application, after the first copper block is electrodeposited on the first circuit protection layer, the method further comprises: removing the first dry film; and (5) flashing to remove the copper foil.
According to some embodiments of the application, the exposing and plating the first and second circuit patterns in the set region includes: removing the first circuit protection layer; flashing to remove the copper foil; removing the second dry film; forming a second circuit protection layer on the second metal layer; and windowing on the second circuit protection layer to expose the set area.
According to some embodiments of the application, the boundary of the first copper block is at least 100 μm recessed relative to the boundary of the specific region.
According to some embodiments of the application, the first copper block has a thickness of greater than or equal to 30 μm, and the first copper block is a solid block or a hollow ring.
According to some embodiments of the application, a minimum distance between the second circuit pattern and the specific region is greater than or equal to 200 μm.
According to some embodiments of the application, a laser process is used to slot the second dielectric layer, and a desmear treatment is performed after the slot is completed.
The NAND Flash packaging substrate provided by the application is manufactured by the manufacturing method of the packaging substrate provided by the application.
The storage particles provided by the application comprise the NAND Flash packaging substrate provided by the application.
The NAND Flash packaging substrate and the storage particles provided by the application have the beneficial effects brought by the manufacturing method of the packaging substrate, and are not repeated herein.
Drawings
The foregoing and/or additional aspects and advantages of the application will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a schematic flow chart of a method for manufacturing a package substrate according to an embodiment of the application;
fig. 2 to 4 are schematic flow diagrams of a method for manufacturing a package substrate according to an embodiment of the application;
FIG. 5 is a schematic diagram of a memory granule according to an embodiment of the present application;
fig. 6 is a schematic diagram of a memory granule according to an embodiment of the present application.
Reference numerals:
the first dielectric layer 110, the first circuit pattern 120, the first gold finger 121, the second dielectric layer 130, the second circuit pattern 140, the second gold finger 141, the third dielectric layer 150, the third circuit pattern 160, the fourth circuit pattern 170, the solder mask 180, the first copper block 190 and the NAND flash900.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.
In the description of the present application, it should be understood that references to orientation descriptions such as upper, lower, front, rear, left, right, etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.
In the description of the present application, a number means one or more, a number means two or more, and greater than, less than, exceeding, etc. are understood to not include the present number, and above, below, within, etc. are understood to include the present number. The description of the first and second is for the purpose of distinguishing between technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present application, unless explicitly defined otherwise, terms such as arrangement, installation, connection, etc. should be construed broadly and the specific meaning of the terms in the present application can be reasonably determined by a person skilled in the art in combination with the specific contents of the technical scheme.
Referring to fig. 1 to 4, the method for manufacturing a package substrate according to the present application includes the following steps:
step S100: a first dielectric layer 110 is provided overlying a first metal layer on which a first circuit pattern 120 is formed.
In step S100, the source of the first dielectric layer 110 covered with the first metal layer is not particularly limited, and may be obtained by outsourcing, for example, purchasing a finished copper-clad plate meeting the requirements, or the first metal layer meeting the requirements may be manufactured on the surface of the substrate by electroplating or other conventional technical means in the art, and the substrate may have base copper or no base copper. For example, in some embodiments, first an electroplating deposition is performed on the copper-clad plate to obtain the first dielectric layer 110 covered with the first metal layer, and then etching is performed, so as to print the first circuit pattern 120 on the first metal layer.
At this time, the base copper of the copper-clad plate and the deposited copper foil together constitute the first metal layer. The first circuit pattern 120 of the present application may be configured according to design requirements, where the first circuit pattern 120 includes at least a first routing finger matching with a position of the step groove, and the first routing finger is used to form the first golden finger 121.
Step S200: a first circuit protection layer is deposited on a set area of the first metal layer, wherein the set area refers to an area matching the step groove to be formed, and a first copper block 190 is deposited on the first circuit protection layer.
Step S300: the second dielectric layer 130 is formed on the first metal layer in a laminated manner, and the thickness of the second dielectric layer 130 is greater than that of the first copper block 190, so that the first copper block 190 is buried in the second dielectric layer 130.
Step S400: a second metal layer is formed on the second dielectric layer 130, and a second circuit pattern 140 is formed on the second metal layer.
The second circuit pattern 140 of the present application may be set according to design requirements, where the second circuit pattern 140 includes at least a second routing finger matching with the position of the step groove, and the second routing finger is used to form a second golden finger 141.
Step S500: via holes are made to connect the first wiring pattern 120 and the second wiring pattern 140.
It is understood that in step S500, the first routing finger and the second routing finger are integrated into one and the same circuit network through rerouting.
Step S600: a slot is formed in the second dielectric layer 130 exposing the first copper block 190.
Step S700: the second dry film is covered on the second metal layer, and the first copper block 190 is etched.
Step S800: the first and second circuit patterns 120 and 140 located at the set region are exposed and plated to form the first and second gold fingers 121 and 141.
The first gold finger 121 and the second gold finger 141 are used for matching different types of NAND Flash respectively, so that the package substrate manufacturing method can manufacture package substrates compatible with different types of NAND Flash, and by adopting a multi-layer design and exposing the first gold finger 121 and the second gold finger 141 in a stepped groove manner, the circuit patterns of the manufactured package substrate can be simplified, and meanwhile, the size of the package substrate can be reduced.
The application also provides a NAND Flash packaging substrate and storage particles, wherein the NAND Flash packaging substrate is manufactured by the manufacturing method of the packaging substrate provided by the application, and the storage particles comprise the NAND Flash packaging substrate provided by the application.
It will be appreciated that steps S100 to S900 involve forming a stepped groove of the package substrate, and the method for manufacturing the package substrate may further include other steps according to design requirements, so as to manufacture a complete package substrate. The manufacturing method of the packaging substrate can be used for manufacturing the packaging substrate with two or more layers of golden fingers.
For example, fig. 2 to fig. 4 show a flow of manufacturing an embodiment of the NAND Flash package substrate provided by the present application according to the package substrate manufacturing method provided by the present application.
In this embodiment, the NAND Flash package substrate has four layers of wiring patterns, wherein two layers of wiring patterns have gold fingers, and fig. 5 and 6 are schematic structural diagrams of the NAND Flash package substrate with NAND Flash900 mounted thereon. Referring to fig. 2 to 6, in this embodiment, a third line pattern 160, a third dielectric layer 150, and a fourth line pattern 170 are sequentially formed on a side of the first dielectric layer 110 away from the first line pattern 120, surfaces of the second line pattern 140 and the fourth line pattern 170 are respectively covered with a solder resist layer 180, and contacts are also formed on the fourth line pattern 170.
For the embodiment with the golden finger on the multi-layer circuit pattern, after step S500, before step S600, step grooves may be formed in a segmented manner according to steps similar to steps S200 to S700, and finally the golden finger is formed by electroplating the circuit pattern on each layer.
Taking the example of the three-layer circuit pattern having the gold finger, after the step S500, before the step S600, a fifth dielectric layer with a second copper block embedded therein is first formed on the second circuit pattern 140, then a third circuit pattern is formed on the fifth dielectric layer, and then the second copper block is grooved and etched, and the second dielectric layer 130 and the second circuit pattern 140 located in the set region are exposed while forming the upper half of the stepped groove.
After the above steps are completed, steps S600 and S700 are continuously performed to form the lower half of the stepped groove. Finally, step S800 is executed to form the required golden fingers on the three layers of circuit patterns respectively.
In some embodiments, step S200 includes:
step S210: a copper foil is deposited over the first metal layer.
Step S220: the copper foil is covered with a first dry film, and the set area is exposed by exposure and development.
Step S230: electroplating and depositing a first circuit protection layer in the set area.
Step S240: a first copper block 190 is electrodeposited on the first line protection layer.
In step S210, a part of the copper foil is covered on the first circuit pattern 120, and a part of the copper foil is covered on the first dielectric layer 110, and the deposition may be performed by electroless copper deposition or magnetron sputtering, so as to be effectively attached to the surface of the first dielectric layer 110. The copper foil may serve as a substrate for a subsequently deposited first circuit protective layer, and in some embodiments, the thickness of the copper foil may be set between 1 μm and 2 μm.
The material of the first line protection layer is typically selected to be an inert metal, such as nickel, titanium, etc., to avoid corrosion of the first line image 120 in the set area during subsequent fabrication.
In some embodiments, the thickness of the first copper block 190 is greater than or equal to 30 μm, and for package substrates with two layers of gold fingers, the thickness of the first copper block 190 may be between 30 μm and 50 μm. The first copper block 190 may be a solid block or a hollow ring. In some embodiments, the boundary of the first copper block 190 is shrunk inwards with respect to the boundary of the specific region, in other words, the cross-sectional area of the first copper block 190 is smaller than that of the specific region, and the size of the shrinkage can be set to at least 100 μm.
In some embodiments, after step S240, further comprising:
step S250: and removing the film to remove the first dry film.
Step S260: and (5) flashing to remove the copper foil.
Referring to fig. 4, 5 and 6, in some embodiments, a portion of the second wiring pattern 140 for forming the second gold finger 141 (i.e., the second routing finger) abuts against an edge of the stepped groove, and is easily damaged when the second dielectric layer 130 is grooved. For this reason, in some embodiments, the minimum distance of the second line pattern from the specific region in step S400 is greater than or equal to 200 μm, thereby ensuring line quality.
It will be appreciated that the slotting in step S600 may be performed by a laser process, and in some embodiments, desmear treatment, that is, desmear treatment, is performed after slotting is completed, so as to remove residual resin and glass fibers, thereby ensuring clean and complete slotting positions.
In some embodiments, step S800 includes:
step S810: and removing the first circuit protection layer.
Step S820: and (5) flashing to remove the copper foil.
It is understood that a portion of the copper foil covered by the first line protective layer cannot be removed in step S260, and thus it is necessary to perform the flash removal again in step S820.
Step S830: and removing the film to remove the second dry film.
Step S840: and forming a second circuit protection layer on the second metal layer.
Step S850: and opening a window on the second circuit protection layer to expose the set area.
It can be understood that in the embodiment of the NAND Flash package substrate corresponding to fig. 2 to 6, the gold fingers have only two layers, so the solder resist layer 180 may be used as the second circuit protection layer, and in the embodiment with more layers of gold fingers, for example, in the embodiment with three layers of circuit patterns having gold fingers, the fifth dielectric layer covering the second circuit pattern 140 is used as the second circuit protection layer.
Step S860: the first and second circuit patterns 140 and 160 located in the set region are plated.
The nickel-gold layer may be applied in step S860, wherein the nickel layer has a thickness of 3 μm to 5 μm and the gold layer has a thickness of 0.3 μm to 0.5 μm.
The method for manufacturing the package substrate provided by the application is described in detail below with reference to fig. 2 to 6 in a specific NAND Flash package substrate embodiment. It is to be understood that the following description is exemplary only and is not intended to limit the application in any way. The present embodiment may also be replaced by or combined with the above-described corresponding technical features.
In this embodiment, the NAND Flash package substrate has four layers of circuit patterns, wherein two layers of circuit patterns have gold fingers. The four layers of circuit patterns are respectively a first circuit pattern 120, a second circuit pattern 140, a third circuit pattern 160 and a fourth circuit pattern 170, and the golden fingers are respectively a first golden finger 121 and a second golden finger 141.
The manufacturing method of the packaging substrate comprises the following steps:
on a double-sided copper-clad plate (including the first dielectric layer 110 and the base copper), a first circuit pattern 120 is formed on the upper surface by electroless copper deposition, electroplating deposition, pattern transfer, and circuit etching, and a third circuit pattern 160 is formed on the lower surface, and the first circuit pattern 120 and the third circuit pattern 160 are communicated through a via hole.
And forming a layer of thin copper foil on the upper surface in a chemical copper deposition or magnetron sputtering mode, wherein the thickness of the copper foil is 1-2 mu m, applying a first dry film, and performing exposure development to form a region corresponding to the step groove.
And forming a first circuit protection layer on the target area by electroplating deposition, wherein the thickness of the first circuit protection layer is 3-5 mu m.
And electroplating and depositing a layer of first copper block 190 on the area of the first circuit protection layer, wherein the thickness of the first copper block 190 is 30-50 mu m, removing the first dry film, and removing the thin copper foil formed by electroless copper deposition or magnetron sputtering through a flash etching process.
The second dielectric layer 130 is formed through a lamination process, the thickness of the second dielectric layer 130 is greater than that of the first copper block 190, the second circuit pattern 140 on the upper surface and the fourth circuit pattern 170 on the lower surface are formed on the second dielectric layer 130 through a substrate manufacturing process, and the second circuit pattern 140 and the fourth circuit pattern 170 are communicated with the internal circuit (i.e., the first circuit pattern 120 and the third circuit pattern 160) through via holes.
Drilling and slotting are carried out on the area corresponding to the step groove through a laser process, the slotting width is 100 mu m, the slotting depth reaches the surface of the first copper block 190, the first copper block 190 below is exposed, and residual resin and glass fibers are removed through desmear treatment after laser slotting.
And applying a second dry film to the surfaces of the second and fourth line patterns 140 and 170 to protect the line patterns on the upper and lower surfaces from corrosion, and pattern transfer exposing the laser-treated region corresponding to the stepped groove.
The etching process is used for etching the area corresponding to the step groove, the first copper block 190 is etched and removed, the step groove is formed, the first circuit protection layer is removed by using specific chemical liquid, the thin copper foil under the first circuit protection layer is removed by using the flash etching process, and finally the second dry film is removed by using film stripping liquid, so that the bare wire bonding finger is formed.
And applying a solder mask 180 on the upper surface and the lower surface of the NAND Flash packaging substrate, discharging air in the step groove by using a lamination leveling process, leveling the surface of the NAND Flash packaging substrate, and windowing the solder mask 180 by pattern transfer, wherein the step groove corresponds to the position of the solder mask 180. And covering the jig on the NAND Flash packaging substrate by utilizing a plasma etching jig, and removing the solder resist possibly remained in the window opening area through a plasma etching process.
Through a surface treatment process, a nickel gold layer is electroplated on the exposed wire bonding fingers by utilizing a lead electroplating method, so that a first gold finger 121 and a second gold finger 141 are formed, and the manufacturing of the NAND Flash packaging substrate is completed.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In some alternative embodiments, the functions/acts noted in the block diagrams may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Furthermore, the embodiments presented and described in the flowcharts of the present application are provided by way of example in order to provide a more thorough understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed, and in which sub-operations described as part of a larger operation are performed independently.
While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the application, the scope of which is defined by the claims and their equivalents.

Claims (10)

1. The manufacturing method of the packaging substrate is characterized by comprising the following steps of:
providing a first dielectric layer covered with a first metal layer, and manufacturing a first circuit pattern on the first metal layer;
depositing a first circuit protection layer in a set area of the first metal layer, and depositing a first copper block on the first circuit protection layer, wherein the set area refers to an area matched with a step groove to be formed;
laminating a second dielectric layer on the first metal layer, wherein the thickness of the second dielectric layer is larger than that of the first copper block, so that the first copper block is embedded in the second dielectric layer;
forming a second metal layer on the second dielectric layer, and manufacturing a second circuit pattern on the second metal layer;
manufacturing a via hole for communicating the first circuit pattern and the second circuit pattern;
slotting on the second dielectric layer to expose the first copper block;
covering a second dry film on the second metal layer, and etching the first copper block;
and exposing and electroplating the first circuit pattern and the second circuit pattern which are positioned in the setting area to form a first golden finger and a second golden finger.
2. The method of manufacturing a package substrate according to claim 1, wherein depositing a first circuit protection layer on the set region of the first metal layer comprises:
depositing a copper foil on the first metal layer;
covering a first dry film on the copper foil, and exposing and developing to expose the set area;
electroplating and depositing the first circuit protection layer in the set area;
electroplating and depositing the first copper block on the first circuit protection layer;
wherein the copper foil has a thickness of between 1 μm and 2 μm.
3. The method of manufacturing a package substrate according to claim 2, further comprising, after the electroplating deposition of the first copper block on the first circuit protection layer:
removing the first dry film;
and (5) flashing to remove the copper foil.
4. The package substrate manufacturing method according to claim 3, wherein the exposing and plating the first and second circuit patterns located in the set region comprises:
removing the first circuit protection layer;
flashing to remove the copper foil;
removing the second dry film;
forming a second circuit protection layer on the second metal layer;
and windowing on the second circuit protection layer to expose the set area.
5. The package substrate manufacturing method according to claim 1, wherein a boundary of the first copper block is shrunk by at least 100 μm with respect to a boundary of the specific region.
6. The method of manufacturing a package substrate according to claim 5, wherein the thickness of the first copper block is greater than or equal to 30 μm, and the first copper block is a solid block or a hollow ring.
7. The method of claim 1, wherein a minimum distance between the second circuit pattern and the specific region is greater than or equal to 200 μm.
8. The method of claim 1, wherein a laser process is used to slot the second dielectric layer, and desmear is performed after the slot is completed.
9. A NAND Flash package substrate, characterized in that it is made by the package substrate manufacturing method according to any one of claims 1 to 8.
10. A memory granule comprising the NAND Flash package substrate of claim 9.
CN202310628297.5A 2023-05-30 2023-05-30 Manufacturing method of packaging substrate, NAND Flash packaging substrate and storage particles Pending CN116721926A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310628297.5A CN116721926A (en) 2023-05-30 2023-05-30 Manufacturing method of packaging substrate, NAND Flash packaging substrate and storage particles

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Application Number Priority Date Filing Date Title
CN202310628297.5A CN116721926A (en) 2023-05-30 2023-05-30 Manufacturing method of packaging substrate, NAND Flash packaging substrate and storage particles

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CN116721926A true CN116721926A (en) 2023-09-08

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012248782A (en) * 2011-05-31 2012-12-13 Fujikura Ltd Manufacturing method of multilayer flexible printed wiring board
US20140082937A1 (en) * 2012-09-27 2014-03-27 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing rigid flexible printed circuit board
CN105792548A (en) * 2016-05-23 2016-07-20 上海美维科技有限公司 Method for manufacturing printed circuit board with stepped slot structure through electroplating and etching method
CN106231816A (en) * 2016-09-06 2016-12-14 深圳崇达多层线路板有限公司 A kind of manufacture method of golden fingerboard without lead wire
KR20220001183A (en) * 2020-06-29 2022-01-05 엘지이노텍 주식회사 Printed circuit board, package board and manufacturing method thereof
CN114679852A (en) * 2022-04-29 2022-06-28 广州广合科技股份有限公司 Manufacturing method of stepped golden finger

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012248782A (en) * 2011-05-31 2012-12-13 Fujikura Ltd Manufacturing method of multilayer flexible printed wiring board
US20140082937A1 (en) * 2012-09-27 2014-03-27 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing rigid flexible printed circuit board
CN105792548A (en) * 2016-05-23 2016-07-20 上海美维科技有限公司 Method for manufacturing printed circuit board with stepped slot structure through electroplating and etching method
CN106231816A (en) * 2016-09-06 2016-12-14 深圳崇达多层线路板有限公司 A kind of manufacture method of golden fingerboard without lead wire
KR20220001183A (en) * 2020-06-29 2022-01-05 엘지이노텍 주식회사 Printed circuit board, package board and manufacturing method thereof
CN114679852A (en) * 2022-04-29 2022-06-28 广州广合科技股份有限公司 Manufacturing method of stepped golden finger

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