CN116711198A

CN116711198A - Power converter control with snooze mode

Info

Publication number: CN116711198A
Application number: CN202280009599.8A
Authority: CN
Inventors: A·A·布兰科; M·罗
Original assignee: Texas Instruments Inc
Current assignee: Texas Instruments Inc
Priority date: 2021-01-12
Filing date: 2022-01-10
Publication date: 2023-09-05

Abstract

In an example, an apparatus (110) includes a control signal generator (202) and a snooze mode controller (204). The control signal generator includes: an error amplifier (208) having a first output, a first input, a second input, and a first snooze input; a first comparator (210) having a second output, a third input coupled to the first output, and a fourth input; and a second comparator (212) having a third output, a fifth input coupled to the third input, a sixth input, and a second snooze input. The control signal generator further includes: a logic circuit (218) having a fourth output and logic circuit inputs, a first logic circuit input of the logic circuit inputs being coupled to the second output; and a pulse generator (220) having a fifth output and a seventh input coupled to the fourth output. The snooze mode controller has a sixth output coupled to the first snooze input and the second snooze input.

Description

Power converter control with snooze mode

Background

A Switched Mode Power Supply (SMPS) transfers power from an input power supply to a load by switching one or more power transistors or other switching elements that are coupled through a switching node/terminal to an energy storage element (such as an inductor, an inductance of a transformer, and/or a capacitor) that is capable of being coupled to the load. The power transistor may be included in a power converter that includes or is capable of being coupled to an energy storage element. The SMPS may include an SMPS controller for providing one or more gate drive signals to the power transistor(s).

The input voltage to the converter may be greater than, less than, or equal to the output voltage. If the input voltage is greater than the output voltage, the converter may be referred to as a "buck" converter/regulator or a "buck converter". If the input voltage is less than the output voltage, the converter/regulator may be referred to as a "boost" converter/regulator or a "boost converter". A converter/regulator may be referred to as a "buck-boost converter" if it can perform both a boost function and a buck function.

Disclosure of Invention

In an example, an apparatus includes a control signal generator and a snooze mode controller. The control signal generator includes an error amplifier having a first output, a first input, a second input, and a first snooze input. The control signal generator also includes a first comparator having a second output, a third input coupled to the first output, and a fourth input. The control signal generator also includes a second comparator having a third output, a fifth input coupled to the third input, a sixth input, and a second snooze input. The control signal generator further includes a logic circuit having a fourth output and logic circuit inputs, a first of the logic circuit inputs coupled to the second output. The control signal generator also includes a pulse generator having a fifth output and a seventh input coupled to the fourth output. The snooze mode controller has a sixth output coupled to the first snooze input and the second snooze input.

In an example, an apparatus includes a control signal generator and a snooze mode controller. The control signal generator is configured to determine an error signal via the error amplifier, the error signal indicating a variance between the reference signal and a feedback signal representative of an output voltage of the power converter; determining whether the value of the error signal is greater than a signal representative of the current of the power converter to provide a comparison result; and providing a control signal for controlling the power converter based on the comparison result. The snooze mode controller is configured to disable at least a portion of the error amplifier in response to determining that the value of the reference voltage scaled by the scaling factor is greater than the feedback signal.

In an example, a system includes a load, a power converter, and a controller. The power converter is coupled to a load. The power converter is configured to switch power from the power source to the load. The controller is coupled to the power converter. The controller is configured to apply control to the power converter. The controller includes a control signal generator including an error amplifier. The control signal generator is configured to determine an error signal via the error amplifier, the error signal indicating a variance between the reference signal and a feedback signal representative of an output voltage of the power converter; determining whether the value of the error signal is greater than a signal representative of the current of the power converter to provide a comparison result; and providing a control signal for controlling the power converter based on the comparison result. The snooze mode controller is configured to disable at least a portion of the error amplifier in response to determining that the value of the reference voltage scaled by the scaling factor is greater than the feedback signal.

Drawings

FIG. 1 is a block diagram of an example system.

FIG. 2 is a block diagram of an example controller.

Fig. 3 is a schematic diagram of an example error amplifier.

Fig. 4 is a schematic diagram of an example fast-fall detection circuit.

Fig. 5A is a diagram of an example signal waveform.

Fig. 5B is a diagram of an example signal waveform.

Fig. 5C is a diagram of an example signal waveform.

Fig. 6 is a diagram of an example signal waveform.

Fig. 7 is a diagram of an example signal waveform.

Fig. 8 is a diagram of an example signal waveform.

Detailed Description

A Switched Mode Power Supply (SMPS) controller switches the power transistor(s) to form a circuit arrangement with the energy storage element(s) to provide load current to the load and/or output capacitor to maintain the regulated output voltage. Alternatively, although not shown herein, at least some of the power transistors may be implemented as passive switches, such as diodes. The power transistor may be coupled to the energy storage inductor through a switching node/terminal during charging and/or discharging switching states of the power converter. In at least some examples, the energy storage inductor is switched by the SMPS controller between a charging switch state and a discharging switch state to provide an inductor current (e.g., a current through the energy storage inductor) to the load and the output capacitor to maintain the regulated output voltage. As described above, in at least some examples, one or more of the power transistors are replaced by passive switches that react based on characteristics of the received input signal and are not switched by the SMPS controller. In some examples, the SMPS may be configured to operate as a constant current source with an energy storage element but without an output capacitor. The power converter periodically repeats a sequence of switching states (such as an "on" state and an "off state). A single on/off cycle may be referred to as a switching cycle.

The power transistor may be implemented as a Field Effect Transistor (FET), such as a metal oxide field effect transistor (MOSFET) or any other suitable solid state transistor device (e.g., a Bipolar Junction Transistor (BJT)). The power converter may have various architectures, each having specific functions such as buck, boost, buck-boost, etc. Herein, a power converter with a boost topology is described. However, the present disclosure is equally applicable to power converters having buck topologies and/or buck-boost (inverting and/or non-inverting) topologies. Further, this document may relate to other circuit architectures that provide a regulated output Voltage (VOUT).

To control the power converter, the SMPS controller provides control signals based on a control mode implemented by the SMPS controller. The control mode may be current mode control, voltage mode control, valley control, peak control, average control, or the like. Herein, valley control is described. However, the present disclosure is equally applicable to other control modes. The SMPS controller may provide a control signal to the driver or a logic circuit coupled to the driver and the driver provides a gate control signal to the gate of the power transistor to control the operation mode of the power converter. The gate control signal received by the power transistor controls the switching state of the power transistor, such as whether the power transistor is in a conductive state (e.g., on) or a non-conductive state (e.g., off). Each state of the power converter involves a specific combination of power transistors in a conducting state and power transistors in a non-conducting state. To change the mode of operation of the power converter, the SMPS controller modifies the sequence of switching states it commands the power transistors to take. In at least some examples, the SMPS controller includes a hardware component arrangement such that the value of the control signal is determined based on the hardware component arrangements.

Some use cases of SMPS benefit from reduced quiescent current. The quiescent current is the current consumed by the SMPS itself independent of the current supplied by the SMPS to the load. For example, the quiescent current may be the current consumed by the SMPS under no-load or light (e.g., low) load current conditions. If the power source from which the SMPS draws current is a depletable power source, such as a battery, reducing the quiescent current of the SMPS may reduce the power drawn from the power source and increase the usable life of the power source before it is recharged or replaced. If the power source from which the SMPS draws current is a non-depletable power source, such as a mains power source or power derived from a mains power source (e.g. output from a transformer, other power converter, etc.), reducing the quiescent current of the SMPS can reduce the costs associated with using the SMPS by consuming less energy by the SMPS.

Aspects herein relate to SMPS implementing sleep modes. The sleep mode may reduce the clock signal (SNOOZE_CLK) on which VOUT is monitored. For example, in response to VOUT remaining within a regulation range for a number of programming cycles or cycles, such as an oscillator signal (CLK), the SMPS may determine that the rate of decrease in the value of VOUT is such that snooze_clk may also slow down. By slowing down snooze_clk, the quiescent current of the SMPS will be reduced compared to an application that does not slow down snooze_clk.

In at least some examples, snooze_clk may be determined as a combination of multiple signals. For example, SNOOZE_CLK may be determined by performing a logical OR operation between a plurality of signals. These signals may include zero crossing detection signals (ZCD), CLK, and fast falling detection signals (FDD). In at least some examples, the ZCD is effective in a valley mode control system in response to a voltage representative of an inductor current of the power converter reaching zero before reaching a value of an error signal (Vea) provided by an error amplifier based on a reference signal (Vref) and a VOUT-based feedback signal (Vfb). CLK may be provided by an oscillator having an adjustable period that is programmed according to the application or use case of the SMPS. In at least some examples, FDD may be provided by a circuit that monitors the value of VOUT and provides a periodic signal having a frequency proportional to the rate at which the value of VOUT decreases. Conversely, in some systems, FDD may be provided by a circuit that monitors the value of VOUT and provides a periodic signal having a frequency proportional to the rate at which the value of VOUT increases. In such an example, FDD may be renamed as a fast rising detection signal. In response to snooze_clk being active, the SMPS may enter a SNOOZE mode or sleep mode.

In some examples, the error amplifier is configured to cause the SMPS to provide a current pulse in response to the error amplifier receiving a signal to cause the error amplifier to exit the snooze mode. The error amplifier may further comprise a compensated signal path and an uncompensated signal path, wherein the uncompensated signal path responds to signal value transients faster than the compensated signal path.

Fig. 1 is a block diagram of an example system 100. In at least some examples, the system 100 represents any electronic device that includes an SMPS 102 configured to switch power from the power supply 104 to the load 106. For example, the system 100 may be an internet of things (IoT) device, a sensor, or any other suitable electronic device. In at least some examples, the power source 104 is a battery. In some examples, SMPS 102 includes a power converter 108 and a controller 110. The controller 110 is configured to control the power converter 108 to switch power provided by the power source 104 to the load 106. For example, controller 110 may receive Vref and control power converter 108 to provide VOUT to load 106, where the value of VOUT is approximately equal to Vref when VOUT is in the regulation range.

In the example of system 100, power source 104 is coupled to a power converter 108 that is coupled to a load 106 and a controller 110. The power converter 108 is configured to receive VIN from the power source 104 and provide VOUT to the load 106 based on VIN and a control applied to the power converter 108 by the controller 110. The controller 110 may receive Vref and provide control signals to the power converter 108 to regulate VOUT to have a value approximately equal to Vref. In some examples, the controller 110 provides control signals to the power converter 108. In other examples, the controller 110 provides control signals to a driver (not shown) that drives the power converter 108 based on the control signals.

The controller 110 may include a snooze mode. In at least some examples, the snooze mode may reduce the quiescent current draw of the SMPS 102 to the power supply 104 compared to the SMPS 102 when the snooze mode is inactive. The snooze mode may be activated in response to SMPS 102 determining that VOUT is greater than a target voltage (which is represented, for example, by Vref) by a threshold amount and remains in the regulation range for the number of programming cycles of CLK. In at least some examples, when SMPS 102 is in a snooze mode, controller 110 does not monitor the value of VOUT to determine the value of VOUT or a signal representative of VOUT (e.g., vfb) relative to Vref. In response to expiration of SNOOZE_CLK, controller 110 may determine a value of VOUT (or Vfb) relative to Vref and control power converter 108 based on the determination. In at least some examples, snooze_clk may be programmable to have a value that is based on, for example, a rate of change of VOUT (e.g., a frequency proportional to the rate of change of VOUT), a fixed frequency, or a value of an inductor current of an inductor (not shown) of power converter 108. As described above, SNOOZE_CLK may be controlled to have a lower frequency in response to VOUT remaining in the regulated range for the number of programming cycles of CLK. In at least some examples, the number of programming cycles that VOUT maintains in the regulation range for CLK may indicate that the value of VOUT is slowly changing. In response to the value of VOUT changing at a rate exceeding the programming rate of change, SNOOZE_CLK may be controlled to have a higher frequency. In at least some examples, decreasing the frequency of snooze_clk in response to VOUT remaining in the regulation range for the number of programming cycles of CLK reduces the quiescent current draw of SMPS 102.

Fig. 2 is a block diagram of an example controller 110. Although shown as a component of SMPS 102, in various other examples controller 110 may be a component of another device, circuit, or system. In at least some examples, controller 110 includes a control signal generator 202, a snooze mode controller 204, and an FDD circuit 206. In at least some examples, controller 110 receives Vref, vfb, and a signal (IL) representative of the current of power converter 108, and provides a CONTROL signal (CONTROL) based at least in part on Vref, vfb, and IL. In at least some examples, the other CONTROL signals are derived based on the value of CONTROL (e.g., as a logical inverse of the value of CONTROL). In at least some examples, the control signal generator 202 includes an error amplifier 208, a comparator 210, a comparator 212, a timer 214, a timer 216, a logic circuit 218, and a pulse generator 220. In at least some examples, snooze mode controller 204 includes a clock combiner 222, a comparator 224, logic 226, and logic 228.

In at least some example architectures of control signal generator 202, error amplifier 208 is configured to receive Vref at a first input (e.g., a positive input or a non-inverting input) and Vfb at a second input (e.g., a negative input or an inverting input). In some examples, vfb has a value determined based on VOUT (e.g., such that Vfb is the output signal of a voltage divider having VOUT as the input signal). In other examples, vfb has substantially the same value as VOUT (e.g., VOUT is used as Vfb in some embodiments). An output of error amplifier 208 is coupled to a first input (e.g., a positive input or a non-inverting input) of comparator 210. In some examples, error amplifier 208 has a SNOOZE input configured to receive a SNOOZE control Signal (SNOOZE) and to be turned off (e.g., disabled) in response to SNOOZE being active. Comparator 210 is configured to receive IL at a second input (e.g., a negative input or an inverting input). Comparator 212 is configured to receive IL at a first input (e.g., a positive input or a non-inverting input) and a signal having a value of approximately 0 volts (V) at a second input (e.g., a negative input or an inverting input). In some examples, comparator 212 is a gated comparator having a SNOOZE input configured to receive SNOOZE and to be turned off (e.g., disabled) in response to SNOOZE being active. In at least some examples, one or both of error amplifier 208 and/or comparator 212 receives an inverse of SNOOZE (denoted snooze_z). The snooze_z may be provided according to any suitable process or hardware architecture. In at least one example, although not shown herein, snooze_z is provided by inverter circuit 230, which receives SNOOZE as an input. In such an example, an inverter circuit may be coupled between the output of the logic circuit 228 and the snooze input of the error amplifier 208. In at least some examples, timer 214 is configured to provide signal TOFF and timer 216 is configured to provide signal toff_max. In at least some examples, TOFF is enabled in response to expiration of a sum of any programming gap or delay time between the off time of power converter 108 and the control of the power transistors of power converter 108. In at least some examples, toff_max is enabled in response to expiration of a maximum off time of the power converter 108. Timer 214 has an input coupled to a second output of error amplifier 208. For example, in response to timer 214 receiving a ZCD with a valid value, timer 214 may count and provide a TOFF with a valid value for a programmed amount of time (in some examples, such as about 10 us) after receiving the ZCD with a valid value. Similarly, in response to timer 216 receiving a ZCD with a valid value, timer 216 may count and provide TOFF_MAX with a valid value for a programmed amount of time after receiving the ZCD with a valid value. In at least some examples, the provision of TOFF is further based on Vea, which is inversely proportional to the signal Vpfm provided by the error amplifier 208, described below, for example. Comparator 210, timer 214, and timer 216 each have an output coupled to an input of logic circuit 218. Logic circuit 218 has an output coupled to an input of a pulse generator 220 having an output that provides CONTROL. In at least some examples, the logic circuit 218 performs a logic or function between its input signals to provide an output signal that is valid in response to any one or more of the input signals of the logic circuit 218 being valid.

In at least some example architectures of snooze mode controller 204, clock combiner 222 has a first input coupled to an output of comparator 212 to receive the ZCD, a second input coupled to an output of an oscillator (not shown) to receive CLK, and a third input coupled to an output of FDD circuit 206. An output of SNOOZE mode controller 204 providing SNOOZE CLK is coupled to comparator 224. Comparator 224 is configured to receive Vref multiplied by a scaling factor at a first input (e.g., a positive input or a non-inverting input) and Vfb at a second input (e.g., a negative input or an inverting input). In at least some examples, the scaling factor is 1.01. In other examples, the scaling factor is any suitable value. An output of the comparator 224 is coupled to an input of the logic circuit 226. An output of logic circuit 226 is coupled to an input of logic circuit 228, which logic circuit 228 has another input coupled to an output of timer 216, and an output providing SNOOZE coupled to error amplifier 208. In at least some examples, logic circuit 226 is an inverter such that the value of the signal provided at the output of logic circuit 226 is a logical inverse of the value provided at the input of logic circuit 226. In at least some examples, the logic circuit 228 performs a logical AND function between its input signals to provide output signals that are valid in response to each of the input signals of the logic circuit 228.

In an example of operation of controller 110, error amplifier 208 amplifies the difference between the value of Vref and the value of Vfb to provide Vea. Comparator 210 compares Vea to IL and provides an output signal COMP having a valid value in response to the value of IL being less than Vea. In response to the assertion of COMP, logic circuit 218 provides an assertion signal to cause pulse generator 220 to provide CONTROL having an assertion value for the programming on-time determined by pulse generator 220. In at least some examples, in response to the assertion of CONTROL, the high-side power transistors (not shown) of the power converter 108 are controlled to be off and the low-side power transistors (not shown) in the power converter 108 are controlled to be on. In at least some examples, the comparator 212 enables ZCD in response to IL decreasing to zero before its increase reaches Vea. In at least some examples, the high-side power transistor of the power converter 108 is controlled to be off in response to the ZCD being active, such as via TOFF or TOFF_MAX being active. In response to the ZCD decreasing to zero before its increase reaches Vea, the controller 110 controls the power converter 108 to operate according to Pulse Frequency Modulation (PFM), wherein the off-time of the power converter 108 is controlled based on Vea.

When the power converter 108 operates according to PFM, the off-time of the power converter 108 may be a function of Vea. Timer 214 may determine the off time and provide TOFF according to any suitable procedure or using any suitable hardware architecture (the scope is not limited herein), based on Vea, and/or any other suitable signal or factor. In at least some examples, timer 214 may determine an off time based on Vea and determine a gap time that defines an amount of time to wait (e.g., a gap time) before the low-side power transistor of power converter 108 turns on after the high-side power transistor of power converter 108 turns off. In response to the sum of the gap time and the off time determined based on Vea expiring, timer 214 may provide TOFF with a valid value. In at least some examples, the value of the off-time is less than or equal to about 10 microseconds. In at least some examples, timer 216 may determine a maximum off time based at least in part on VIN and VOUT. In response to expiration of the maximum off time, the timer 216 may provide toff_max with a valid value. In at least one example, the maximum off time is approximately equal to VIN/l×t_hs×t_ls/i_out, where L is the inductance of the inductor of the power converter 108, t_hs is the time that the high side power transistor of the power converter 108 is on, t_ls is the time that the low side power transistor of the power converter 108 is on, and i_out is the load current of the power converter 108. In at least some examples, in response to the assertion of any of toff_max, TOFF, or COMP, logic circuit 218 CONTROLs pulse generator 220 to provide CONTROL with an assertion value.

In at least some examples, under heavy load conditions, the controller 110 may control the power converter 108 according to constant on-time valley current control using Pulse Width Modulation (PWM). As used herein, if the load 106 draws more than 100 milliamps (mA) of current from the power converter 108, a heavy load condition may exist. Under medium load conditions, the controller 110 may control the power converter 108 according to a constant on-time PFM with a variable off-time. As used herein, medium load conditions may exist if the current drawn by load 106 from power converter 108 is between about 15mA to about 100 mA. Under light load conditions, the controller 110 may control the power converter 108 to operate in a burst mode, wherein the snooze mode described herein is active between bursts. As used herein, a light load condition may exist if the current drawn by load 106 from power converter 108 is less than about 15 mA.

In an example of operation of SNOOZE mode controller 204, clock combiner 222 provides snooze_clk with a valid value that corresponds to a valid value in ZCD, CLK or FDD. For example, in at least one embodiment, clock combiner 222 performs a logical OR operation between ZCD, CLK and FDD to provide SNOOZE_CLK with a valid value in response to any one or more of ZCD, CLK or FDD having a valid value. In other examples, clock combiner 222 provides snooze_clk with a valid pulse whenever a rising edge is detected in ZCD, CLK, or FDD. Comparator 224 may be clocked by snooze_clk so that comparator 224 may compare its input signals and provide an output signal only when snooze_clk is active. In at least some examples, comparator 224 may be turned off and disabled when snooze_clk is inactive. In at least some examples, the comparator 224 may be referred to as a clocked dynamic comparator.

In response to snooze_clk becoming active, comparator 224 may compare its input signals (e.g., scaled Vref and Vfb) and provide an output signal. In some examples, vref is scaled to provide hysteresis to the snooze mode controller 204, preventing snooze mode controller 204 from causing controller 110 to enter and exit snooze mode frequency, such as due to transient signal noise. In at least some examples, the valid output signal provided by comparator 224 may indicate that the value of VOUT has fallen to within about one percent of the programmed value of VOUT, and that controller 110 should control power converter 108 to provide a burst of current to load 106. In at least some examples, SNOOZE may be disabled and SMPS 102 may be exited from SNOOZE mode in response to the output signal provided by comparator 224 being active. Conversely, in response to the output signal provided by the comparator 224 being inactive and toff_max being active, SNOOZE may be enabled and the SMPS 102 may be placed or maintained in SNOOZE mode. In response to SNOOZE being inactive, error amplifier 208 and comparator 212 may be turned on and become active to cause controller 110 to control power converter 108 to deliver current to load 106.

In an example of operation of FDD circuit 206, the rate of change of VOUT is monitored and FDD is provided based on the monitoring. For example, FDD circuit 206 may provide FDD as a clock signal having a frequency proportional to the rate of change of VOUT. In response to an increase in the rate of change of VOUT, the frequency of FDD may increase, and in response to a decrease in the rate of change of VOUT, the frequency of FDD may decrease until the rate of change of VOUT is too small to be detected by FDD circuit 206. In various examples, FDD circuit 206 may be implemented according to any suitable FDD circuit architecture, the scope of which is not limited herein.

Fig. 3 is a schematic diagram of an example error amplifier 208. Although shown as a component of the controller 110, in various other examples, the error amplifier 208 may be a component of another device, circuit, or system. In at least some examples, error amplifier 208 includes amplifier 302, resistor 304, switch 306, capacitor 308, transistor 310, transistor 312, current source 313, switch 314, transistor 316, resistor 317, transistor 318, resistor 319, current source 320, transistor 321, transistor 322, transistor 324, transistor 326, transistor 328, current source 329, resistor 330, capacitor 332, resistor 334, transistor 336, transistor 338, transistor 340, resistor 342, current source 344, transistor 346, resistor 348, comparator 350, offset voltage source 352, switch 354, and pulse generator 356.

In the example architecture of error amplifier 208, amplifier 302 has a first input (e.g., a positive input or a non-inverting input) configured to receive Vref and a second input (e.g., a negative input or an inverting input) configured to receive Vfb. The amplifier 302 further has a first output and a second output. In at least some examples, the amplifier 302 is a differential amplifier. Resistor 304 is coupled at a first terminal to a first output of amplifier 302 and at a second terminal to a top plate of capacitor 308 through switch 306. In at least some examples, switch 306 is a normally open switch configured to receive and be controlled by snooze_z. In other examples, switch 306 may be a normally closed switch configured to receive and be controlled by SNOOZE. The bottom plate of capacitor 308 is adapted to be coupled to ground 358. Transistor 310 has a source coupled to the top plate of capacitor 308, a drain adapted to be coupled to voltage source 360, and a gate. Transistor 312 has a gate coupled to the top plate of capacitor 308, a source adapted to be coupled to ground 358, and a drain coupled to the gate of transistor 310. Current source 313 is adapted to be coupled between voltage source 360 and the gate of transistor 310. Switch 314 has a first terminal coupled to the first output of amplifier 302, and a second terminal. In at least some examples, switch 314 is a normally open switch configured to receive and be controlled by snooze_z. In other examples, switch 314 may be a normally closed switch configured to receive and be controlled by SNOOZE. Transistor 316 has a gate coupled to the second terminal of switch 314, a source coupled to ground 358 through resistor 317, and a drain. Transistor 318 has a gate coupled to the second terminal of switch 314, a source coupled to ground 358 through resistor 319, and a drain providing Vea. Current source 320 is adapted to be coupled between voltage source 360 and the drain of transistor 316.

Transistor 321 has a gate coupled to the drain of transistor 316, a source coupled to the gate of transistor 316, and a drain. Transistor 322 has a drain and a gate coupled to the drain of transistor 321, and a source adapted to be coupled to voltage source 360. Transistor 324 has a gate coupled to the gate of transistor 322, a source adapted to be coupled to voltage source 360, and a drain. Transistor 326 has a drain and a gate coupled to the drain of transistor 324, and a source adapted to be coupled to ground 358. Transistor 328 has a gate coupled to the gate of transistor 326, a source adapted to be coupled to ground 358, and a drain. Current source 329 is adapted to be coupled between voltage source 360 and the drain of transistor 328. Resistor 330 is coupled between the drain of transistor 328 and the top plate of capacitor 332. The bottom plate of capacitor 332 is adapted to be coupled to ground 358. Resistor 334 is coupled between the drain of transistor 328 and the drain of transistor 336. Transistor 336 further has a source adapted to be coupled to ground 358, and a gate. Transistor 338 has a source coupled to the drain of transistor 328, a drain adapted to be coupled to voltage source 360, and a gate. Transistor 340 has a gate coupled to the drain of transistor 328, a source adapted to be coupled to ground 358 through resistor 342, and a drain coupled to the gate of transistor 338. Current source 344 is adapted to be coupled between voltage source 360 and the drain of transistor 340. Transistor 346 has a gate coupled to the drain of transistor 328, a source adapted to be coupled to ground 358 through resistor 348, and a drain providing the output of error amplifier 208. Comparator 350 has a first input (e.g., a positive input or a non-inverting input) configured to receive Vref, a second input (e.g., a negative input or an inverting input), and an output. Offset voltage source 352 is coupled to a second input of comparator 350 and provides an amount of voltage offset to Vfb. Switch 354 is adapted to be coupled between voltage source 360 and the drain of transistor 328. In at least some examples, the switch 354 is a normally open switch configured to receive and be controlled by the output signal of the comparator 350. Pulse generator 356 has an input configured to receive SNOOZE, and an output coupled to the gate of transistor 336.

In an example of operation of error amplifier 208, amplifier 302 receives Vref and Vfb and amplifies the difference between Vref and Vfb to provide an output signal COMP_PWM, which may be any suitable transconductance amplifier. Resistor 304 and capacitor 308 provide compensation to maintain stability in the PWM loop portion of error amplifier 208. Amplifier 302 drives transistor 318 to provide Vea at the drain of transistor 318. The clamp circuit, which includes transistor 316, resistor 317, current source 320, and transistor 321, maintains the value of COMP PWM at a minimum voltage or clamp voltage independent of the value of Vref or Vfb. Transistors 322, 324, 326 and 328 together mirror current from the source of transistor 321 to the drain of transistor 328 to provide comp_pfm while the clamp is engaged (e.g., if the value of comp_pwm would otherwise be less than the clamp voltage without the clamp). Resistor 330 and capacitor 332 provide compensation to maintain stability in the PFM loop portion of error amplifier 208. The clamp circuit, including transistor 338, transistor 340, resistor 342, and current source 344, maintains the value of COMP PFM at a minimum voltage or clamp voltage independent of the value of Vref or Vfb. Transistor 346 is driven based on the value of COMP PFM to provide an output signal Vpfm at the drain of transistor 346. When the error amplifier 208 is not in snooze mode, the capacitor 308, which may be a compensation capacitor, charges based on comp_pwm. In at least some examples, in response to error amplifier 208 entering the snooze mode, switch 306 is opened such that the voltage across capacitor 308 is maintained while in the snooze mode. The clamp formed by transistor 310, transistor 312, and current source 313 may maintain the voltage maintained on capacitor 308 at a minimum voltage or clamp voltage when in snooze mode. Also in response to error amplifier 208 entering snooze mode, switch 314 is opened, decoupling the output of amplifier 302 from the gates of transistors 316 and 318 and the source of transistor 321.

In at least some examples, PULSE generator 356 is configured to receive the SNOOZE and provide a voltage PULSE (SNOOZE_EXIT_PULSE) having a programming width in response to a falling edge of the SNOOZE. In at least some examples, the programming width is about 3 microseconds. In response to the snooze_exit_pulse being active for the duration of the PULSE and when snooze_exit_pulse is active, transistor 336 may become conductive, pulling down the gate of transistor 340 such that signal comp_pfm provided at the gate of transistor 340 is approximately equal to the voltage provided at ground 358. In at least some examples, in response to the gate of transistor 340 being pulled down, error amplifier 208 causes controller 110 to control power converter 108 in accordance with PFM control. In at least some examples, the transistor 336 of the gate of the pull-down transistor 340 may cause a single Discontinuous Conduction Mode (DCM) pulse to be provided as a gate control signal to the power converter 108. In some examples, the value of vout_comp_low may determine whether error amplifier 208 is to begin operation in PWM mode or PFM mode after snooze_exit_pulse is active. For example, in response to comparator 350 determining that the value of Vref is less than Vfb plus the amount of offset provided by offset voltage source 352, comparator 350 provides VOUT_COMP_LOW with an effective value. In at least some examples, the amount of offset is about one percent of Vref (e.g., such that VOUT_COMP_LOW is active if Vfb is reduced to less than ninety-nine percent of Vref). In response to vout_comp_low having an active value, switch 354 may be closed, thereby pulling up the gate of transistor 340 such that signal comp_pfm provided at the gate of transistor 340 is approximately equal to the voltage provided at voltage source 360, and error amplifier 208 provides Vea based on PWM control (e.g., entering a high current mode that skips PFM mode control). In other examples, such as if the value of Vref is not less than Vfb plus the amount of offset provided by offset voltage source 352, the DCM pulse may be provided by another circuit (such as logic circuitry as described above) that may receive the output of controller 110 and/or SNOOZE and provide a gate control signal for driving the power transistors of power converter 108. For example, in some embodiments, regardless of the output of error amplifier 208 or controller 110, the logic circuitry may provide a DCM pulse in response to the logic circuitry detecting a falling edge transition in SNOOZE.

Fig. 4 is a schematic diagram of an example FDD circuit 206. Although shown as a component of controller 110, in various other examples FDD circuit 206 may be a component of another device, circuit, or system. Likewise, although shown with a particular architecture, in various examples, FDD circuit 206 may have any architecture suitable for performing the functions described in this specification. In at least some examples, FDD circuit 206 includes a current source 402, a transistor 404, a transistor 406, a transistor 408, a capacitor 410, a switch 412, a capacitor 414, a transistor 416, a transistor 418, a resistor 420, a capacitor 422, a switch 424, a logic circuit 426, and a delay circuit 428.

In the example architecture of FDD circuit 206, current source 402 is adapted to be coupled between the output of power converter 108 and the drain of transistor 404. Transistor 404 has a gate coupled to the drain of transistor 404, and a source adapted to be coupled to ground 358. Transistor 406 has a gate coupled to the gate of transistor 404, a source adapted to be coupled to ground 358, and a drain. Transistor 408 has a drain and a gate coupled to the drain of transistor 406, and a source adapted to be coupled to the output of power converter 108. The capacitor 410 is adapted to be coupled between the output of the power converter 108 and the gate of the transistor 408. Switch 412 is coupled between the gate of transistor 408 and the gate of transistor 416. The capacitor 414 is adapted to be coupled between the gate of the transistor 416 and ground 358. Transistor 416 has a source adapted to be coupled to the output of power converter 108, and a gate. Transistor 418 has a drain coupled to the drain of transistor 416, a gate coupled to transistor 404, and a source adapted to be coupled to ground 358 through resistor 420. The capacitor 422 is adapted to be coupled between the output of the power converter 108 and the source of the transistor 418. Switch 424 is adapted to be coupled between the source of transistor 418 and ground 358. Logic circuit 426 has an input coupled to the drain of transistor 418 and an output. Delay circuit 428 has an input coupled to the output of logic circuit 426 and an output. In at least some examples, the output of delay circuit 428 is coupled to switch 412 and switch 424 such that the output signal of delay circuit 428 is provided to and configured to control switch 412 and switch 424.

In an example of operation of FDD circuit 206, VOUT is capacitively coupled to transistor 416 through capacitors 410 and 414 and to transistor 418 through capacitor 422. In at least some examples, the default output of FDD circuit 206 is a logic low signal or an inactive signal. As the value of VOUT decreases, more current flows through transistor 418 than through transistor 416. For example, the gate of transistor 416 remains connected to ground 358 through capacitor 414. As the value of VOUT as received at the source of transistor 416 decreases, the current through transistor 416 decreases. The source of transistor 418 remains connected to VOUT through capacitor 422. Thus, as the value of VOUT decreases, the voltage provided at the source of transistor 418 and the gate-source voltage (Vgs) of transistor 418 also increase. In response to the Vgs of transistor 418 increasing, the current through transistor 418 also increases and the value of the voltage provided at the input of logic circuit 426 begins to decrease from about VOUT to a value about equal to the value of the signal provided at ground 358. In response to the current through transistor 418 (which is also the current provided at the input of logic circuit 426) reaching the threshold of logic circuit 426, logic circuit 426 automatically turns off. In at least some examples, logic 426 implements logical inversion. Thus, logic circuit 426 may provide a logic high signal in response to an automatic turn-off occurring based on the current sunk through transistor 418. In at least some examples, the output signal of logic 426 is FDD. Thus, in at least some examples, an output of logic circuit 426 is coupled to an input of clock combiner 222. Delay circuit 428 may be any suitable delay circuit that receives FDD at an input of delay circuit 428 and provides a Reset Signal (RST) at an output of delay circuit 428 after a programmed amount of time. In at least some examples, RST has substantially the same value as FDD and is configured to control switch 412 and switch 424 to close, thereby resetting FDD circuit 206. In this way, FDD is provided as a PWM signal having a frequency proportional to the rate of change of VOUT while the rate of change of VOUT is within the sensitivity range of FDD circuit 206. In at least some examples, if the rate of change of VOUT is greater than about 100 picovolts (uV) per microsecond (us), FDD circuit 206 may be adapted to provide FDD with a frequency proportional to the rate of change of VOUT. In other examples, if the rate of change of VOUT is less than about 100uV/us, FDD circuit 206 may be modified to provide FDD with a frequency proportional to the rate of change of VOUT.

Fig. 5A is a graph 505 of an example signal waveform. In at least some examples, figure 505 shows a signal that may be provided in SMPS 102 as described with reference to the various figures herein. Figure 505 shows VOUT, FDD, and CLK of SMPS 102 as described above under a heavy subset of light load conditions (e.g., less than about 15 mA). Assuming that the inductance of the inductor of power converter 108 is about 10 microhenries (uH), the value of VOUT may decrease at a rate greater than about 100 uV/us. As shown in fig. 505, FDD is effective with repeated pulses whose frequency is proportional to the rate of change of VOUT when the value of VOUT decreases under heavy load conditions.

Fig. 5B is a graph 510 of an example signal waveform. In at least some examples, diagram 510 illustrates signals that may be provided in SMPS 102 as described with reference to the various figures herein. As described above, diagram 510 shows VOUT, FDD, and CLK for SMPS 102 under a medium load subset of light load conditions (e.g., less than about 15 mA). Assuming that the inductance of the inductor of power converter 108 is about 10uH, the value of VOUT may decrease at a rate greater than about 10uV/us but less than about 100 uV/us. As shown in graph 510, when the value of VOUT decreases under medium load conditions, the rate of change of VOUT is insufficient to trigger FDD, such that FDD has and maintains a logic low or invalid value. To provide the controller 110 with a clock signal that instructs the controller 110 to compare the value of Vfb to the value of Vref, the controller 110 receives CLK from the oscillator. In at least some examples, the period of CLK is about 50us. In various examples, the period of CLK may be programmed to any value that provides suitable accuracy in detecting the variance of Vfb and Vref.

Fig. 5C is a graph 515 of an example signal waveform. In at least some examples, the diagram 515 illustrates signals that may be provided in the SMPS 102 as described with reference to the various figures herein. As described above, diagram 515 shows VOUT, FDD, and CLK for SMPS 102 under a light load subset of light load conditions (e.g., less than about 15 mA). Assuming that the inductance of the inductor of power converter 108 is about 10uH, the value of VOUT may decrease at a rate of less than about 10 uV/us. As shown in graph 515, when the value of VOUT decreases under light load conditions, the rate of change of VOUT is insufficient to trigger FDD so that FDD has and maintains a logic low or invalid value. To provide the controller 110 with a clock signal that instructs the controller 110 to compare the value of Vfb to the value of Vref, the controller 110 receives CLK from the oscillator. In at least some examples, the period of CLK is about 50us. However, if VOUT remains in the regulation range for the number of programming cycles of CLK (e.g., about 32 times or any other value suitable for the application of SMPS 102), the CLK period may increase. For example, the period of CLK may increase from about 50us to about 200us. In various examples, the period of CLK may be programmed to any value that provides suitable accuracy in detecting the variance of Vfb and Vref. In at least some examples, the component that provides CLK may track the number of cycles VOUT maintains in the regulated range and provide CLK at a frequency determined based on the tracking.

Fig. 6 is a diagram 600 of an example signal waveform. In at least some examples, the diagram 600 illustrates signals that may be provided in the SMPS 102 as described with reference to the various figures herein. Diagram 600 shows VOUT, snooze_clk, the frequency of snooze_clk (shown as snooze_clk_freq in diagram 600), the output of comparator 224 (shown as snooze_comp in diagram 600), and the current of the inductor of power converter 108 (shown as I in diagram 600). VOUT, snooze_clk, and snooze_comp are each shown as having a vertical axis representing voltage in volts (V). Snooze_clk_freq is shown as having a vertical axis representing frequency in kilohertz (kHz). I is shown as having a vertical axis representing current in mA. Each signal is shown with a horizontal axis in milliseconds (ms).

As shown in graph 600, the power converter 108 operates in a light load condition, wherein the load current of the power converter 108 is approximately equal to 10 microamps (uA). Under light load conditions, SNOOZE_CLK is controlled according to CLK. As further shown in diagram 600, in response to SNOOZE_COMP not becoming active for a programming cycle number of CLK (e.g., 32 times), the frequency of CLK is reduced from about 20kHz to about 3.3kHz. In various examples, other frequencies may be used, as described above. As further shown in diagram 600, when the frequency of CLK (and thus snooze_clk) is approximately 20kHz, the quiescent current (IQ) of SMPS 102 may be approximately equal to 400 nanoamperes (nA). However, after the frequency of CLK (and thus snooze_clk) is reduced, IQ of SMPS 102 may be reduced to less than about 100nA. As further shown in diagram 600, in response to the assertion of SNOOZE_COMP, the SMPS 102 exits the SNOOZE mode and provides a current pulse via the power converter 108. In at least some examples, as described above, snooze_comp is enabled in response to the value of Vfb becoming greater than the value of scaled Vref. After snooze_comp is active, CLK returns to the original programming frequency until the number of programming cycles of CLK has passed again without snooze_comp becoming active, after which the frequency of CLK may be lowered again to reduce IQ.

Fig. 7 is a diagram 700 of an example signal waveform. In at least some examples, diagram 700 illustrates signals that may be provided in SMPS 102 as described with reference to the various figures herein. Graph 700 shows VOUT, CLK, FDD, ZCD, SNOOZE _clk, the output of comparator 224 (shown as snooze_comp in graph 700), the current drawn by load 106 (shown as i_out in graph 700), and the current of the inductor of power converter 108 (shown as I in graph 700). VOUT, CLK, FDD, SNOOZE _CLK and SNOOZE_COMP are each shown as having a vertical axis representing voltage in units of V. I_out and I are shown with the vertical axis representing current, where I_out is in mA and I is in amperes (A). Each signal is shown with a horizontal axis in ms.

As shown in diagram 700, for each rising edge in CLK FDD or ZCD, a corresponding pulse occurs in snooze_clk. When the value of I_out suddenly increases, the value of VOUT decreases, thereby enabling SNOOZE_COMP. In response to the validity of snooze_comp, SMPS 102 exits SNOOZE mode and the value of I increases to service the increased i_out. As further illustrated in diagram 700, in at least some examples, the rate of change of VOUT caused by the increased I_out causes FDD circuit 206 to enable FDD, thereby sending additional SNOOZE_CLK clock pulses.

Fig. 8 is a diagram 800 of an example signal waveform. In at least some examples, the diagram 800 illustrates signals that may be provided in the SMPS 102 as described with reference to the various figures herein. Diagram 800 shows VOUT, vout_comp_low, PWM Error, PFM Error, current drawn by load 106 (shown as i_out in diagram 800), and current of the inductor of power converter 108 (shown as I in diagram 800). VOUT, vout_comp_low, PWM Error, and PFM Error are each shown as having a vertical axis representing voltage in V units. I_out and I are shown with the vertical axis representing current, where I_out is in mA and I is in A. Each signal is shown with a horizontal axis in ms.

As shown in graph 800, vout_comp_low becomes active in response to a rapid decrease in the value of VOUT, such as caused by a rapid increase in i_out. In response to the assertion of VOUT_COMP_LOW, SMPS 102 exits the snooze mode and the value of I increases to service the increased I_out. For example, in response to the assertion of VOUT_COMP_LOW, PFM_Error is asserted. In response to the pfm_error being active, the value of TOFF may be zero and the controller 110 may control the power converter 108 according to the PWM operating mode. This control may cause the value of IL to increase rapidly to service the increased i_out, thereby maintaining VOUT in the regulated range.

The term "coupled," as used herein, may encompass a connection, communication, or signal path that enables a functional relationship consistent with the disclosure. For example, if device a provides a signal to control device B to perform an action: (a) in a first example, device a is directly coupled to device B; or (B) in a second example, device a is indirectly coupled to device B through intermediate component C, provided that intermediate component C does not substantially change the functional relationship between device a and device B, and device B is therefore controlled by device a via the control signals provided by device a.

A device "configured to" perform a task or function may be configured (e.g., programmed and/or hardwired) by a manufacturer at the time of manufacture to perform the function, and/or may be configured (or reconfigurable) by a user after manufacture to perform the function and/or other additional or alternative functions. The configuration may be performed by firmware and/or software programming the device, by constructing and/or laying out hardware components and interconnections of the device, or a combination thereof.

Circuits or devices described herein as including certain components may be adapted to be coupled to those components to form the described circuitry or devices. For example, structures described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and/or inductors), and/or one or more power sources (e.g., voltage and/or current sources) may include only semiconductor elements within a single physical device (e.g., a semiconductor die and/or Integrated Circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and/or power sources at the time of manufacture or after manufacture (e.g., by an end user and/or a third party) to form the described structures.

Although certain components may be described herein as components of a particular process technology, these components may be replaced with components of other process technologies. The circuits described herein may be reconfigured to include replaced components to provide functions at least partially similar to those available prior to component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and/or parallel to provide the amount of impedance represented by the illustrated resistors. For example, the resistors or capacitors shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in series or parallel, respectively, between the same two nodes as a single resistor or capacitor.

The use of the term "ground voltage potential" herein includes housing ground, ground, floating ground, virtual ground, digital ground, common ground, and/or any other form of ground connection suitable or adapted for the teachings herein. Unless otherwise indicated, "about," "about," or "substantially" preceding a value refers to +/-10% of the value.

Modifications to the described examples are possible within the scope of the claims, and other examples are also possible.

Claims

1. An apparatus, comprising:

a control signal generator, the control signal generator comprising:

an error amplifier having a first output, a first input, a second input, and a first snooze input;

a first comparator having a second output, a third input coupled to the first output, and a fourth input;

a second comparator having a third output, a fifth input coupled to the third input, a sixth input, and a second snooze input;

a logic circuit having a fourth output and a logic circuit input, a first of the logic circuit inputs coupled to the second output; and

a pulse generator having a fifth output and a seventh input, the seventh input coupled to the fourth output; and

a snooze mode controller having a sixth output coupled to the first snooze input and the second snooze input.

2. The apparatus of claim 1, wherein the error amplifier has a seventh output, and the control signal generator comprises:

A first timer having an eighth output and an eighth input, the eighth input coupled to the third output and the eighth output coupled to a second one of the logic circuit inputs; and

a second timer having a ninth output, a ninth input, and a tenth input, the ninth input coupled to the third output, the tenth input coupled to the seventh output, and the ninth output coupled to a third one of the logic circuit inputs, wherein the logic circuit performs a logical OR operation between signals received via the logic circuit inputs.

3. The apparatus of claim 1, wherein the snooze mode controller comprises:

a clock combiner having an eleventh output and a clock combiner input;

a third comparator having a twelfth output, an eleventh input, a twelfth input, and a thirteenth input, the thirteenth input coupled to the eleventh output;

A second logic circuit having a thirteenth output and a fourteenth input coupled to the twelfth output; and

a third logic circuit having a fourteenth output and a third logic circuit input, a first logic circuit input of the third logic circuit input coupled to the thirteenth output and the fourteenth output coupled to the first snooze input and the second snooze input.

4. The apparatus of claim 3, wherein the snooze mode controller is configured to:

receiving a reference voltage scaled according to a scaling factor at the eleventh input;

receiving a feedback voltage at the twelfth input;

receiving a zero crossing detection signal, a clock signal and a fast falling detection signal at the clock combiner input;

providing a snooze clock having an active pulse responsive to detecting a rising edge of any one of the zero crossing detection signal, the clock signal, or the fast falling detection signal;

comparing the scaled reference voltage to the feedback voltage in response to a rising edge of the snooze clock; and

A snooze mode control signal is provided based on a comparison between the scaled reference voltage and the feedback voltage.

5. The apparatus of claim 4, wherein a quiescent current of the apparatus decreases in response to assertion of the snooze mode control signal.

6. The apparatus of claim 1, wherein the snooze mode controller is configured to:

providing a snooze clock signal based on a zero crossing detection signal, a clock signal, and a fast-falling detection signal, the snooze clock signal including a valid pulse responsive to a rising edge of any one of the zero crossing detection signal, the clock signal, or the fast-falling detection signal;

determining, in response to a rising edge in the snooze clock signal, whether the scaled reference voltage is greater than a feedback voltage representative of an output voltage of the power converter to provide a snooze mode control signal; and

disabling at least a portion of the error amplifier and the second comparator in response to a change in the value of the snooze mode control signal, the quiescent current of the apparatus being reduced by disabling the error amplifier and the second comparator in response to a change in the value of the snooze mode control signal and determining whether the scaled reference voltage is greater than the feedback voltage only in response to a rising edge in the snooze clock signal.

7. The apparatus of claim 1, wherein the first comparator is configured to receive a signal at the fourth input indicative of a current of a power converter, the second comparator is configured to receive a signal at the sixth input having a voltage of approximately zero, and operation of the second comparator is enabled based on a value of an output signal of the snooze mode controller.

8. An apparatus, comprising:

a control signal generator comprising an error amplifier, the control signal generator configured to:

determining, by the error amplifier, an error signal indicative of a variance between a reference signal and a feedback signal representative of an output voltage of the power converter;

determining whether the value of the error signal is greater than a signal representative of the current of the power converter to provide a comparison result;

providing a control signal for controlling the power converter based on the comparison result; and a snooze mode controller configured to disable at least a portion of the error amplifier in response to determining that the value of the reference voltage scaled by the scaling factor is greater than the feedback signal.

9. The apparatus of claim 8, wherein the snooze mode controller is configured to provide a snooze clock comprising signal pulses responsive to each of:

a rising edge of a zero-crossing detection signal, said zero-crossing detection signal being active in response to a decrease in current of said power converter reaching zero,

a rising edge of a clock signal, the clock signal having a fixed frequency, an

A rising edge of a fast-falling detection signal having a frequency proportional to a rate of change of a value of an output voltage of the power converter.

10. The apparatus of claim 9, wherein the snooze mode controller is configured to compare a scaled reference voltage to the feedback signal in response to a rising edge in the snooze clock to provide a snooze comparison result.

11. The apparatus of claim 10, wherein the value of the fixed frequency is reduced in response to the snooze comparison result not becoming active for a programming period number of the clock signal.

12. The apparatus of claim 10, wherein the snooze mode controller is configured to provide a snooze mode control signal based on the snooze comparison result, the snooze mode control signal configured to disable at least the portion of the error amplifier responsive to a change in a value of the snooze mode control signal.

13. The apparatus of claim 12, wherein the control signal generator is configured to control the power converter to provide a burst of current in response to the deassertion of the snooze mode control signal.

14. The apparatus of claim 9, wherein a frequency of the snooze clock is variable based on a rate of change of an output voltage of the power converter.

15. A system, comprising:

a load;

a power converter coupled to the load, the power converter configured to switch power from a power source to the load; and

a controller coupled to the power converter, the controller configured to apply control to the power converter, the controller comprising:

Providing a control signal for controlling the power converter based on the comparison result; and

a snooze mode controller configured to disable at least a portion of the error amplifier in response to determining that a value of a reference voltage scaled by a scaling factor is greater than the feedback signal.

16. The system of claim 15, wherein the snooze mode controller is configured to provide a snooze clock comprising signal pulses responsive to each of:

a rising edge of a clock signal having a fixed frequency determined based on an amount of time an output voltage of the power converter remains in a regulation range, and

17. The system of claim 16, wherein the snooze mode controller is configured to compare the scaled reference voltage to the feedback signal in response to a rising edge in the snooze clock to provide a snooze comparison result.

18. The system of claim 17, wherein the snooze mode controller is configured to provide a snooze mode control signal based on the snooze comparison result, the snooze mode control signal configured to disable at least the portion of the error amplifier.

19. The system of claim 18, wherein the snooze mode control signal is effective to reduce quiescent current consumed by the controller.

20. The system of claim 18, wherein the control signal generator is configured to control the power converter to provide a burst of current in response to the deassertion of the snooze mode control signal.