CN116709045A - Line scanning image sensor, control method and line camera - Google Patents

Abstract

A line scanning image sensor, a control method and a line camera are provided. The line scan image sensor includes: a control unit; n pixel arrays, wherein N is more than or equal to 2 and N is an integer; n ADC arrays; the N pixel arrays are connected with the N ADC arrays in a one-to-one correspondence manner; the control unit is suitable for controlling the N pixel arrays to be sequentially exposed in the working period of one ADC array, and controlling other pixel arrays to be in a charge reset state when the pixel arrays are exposed; the ADC array is suitable for quantifying the image acquisition result of the corresponding pixel array; the duty cycle of the ADC array is equal to N times the row period. By adopting the scheme, the line frequency of the line scanning image sensor can be effectively improved.

Description

Line scanning image sensor, control method and line camera

Technical Field

The present invention relates to the field of image sensors, and in particular, to a line scan image sensor, a control method thereof, and a line camera.

Background

A linear array camera is a camera using a line scanning image sensor as a photosensitive device. Unlike the conventional area camera, which obtains a rectangular area with a known length and width by one-time exposure shooting, the linear camera can only obtain a long and narrow linear area with a known length by one-time exposure shooting, which is called a line of images. Therefore, a line camera is often used to photograph a moving object.

In the line camera, the photosensitive element in the line scanning image sensor can be a line image sensor or a time delay integral (TimeDelayIntegration, TDI) image sensor. In a linear array image sensor, pixels are arranged in a linear array. In a TDI image sensor, pixels are arranged in a two-dimensional area array. Either the line image sensor or the TDI image sensor exposes pixels through which a photographed object passes row by row. The difference is that the linear array image sensor can directly output the exposure result after each exposure, and the TDI image sensor needs to accumulate the exposure result of the same scene of the photographed object and output the accumulated exposure result.

The line frequency represents an important parameter of the line scanning image sensor and is used for representing the frequency of the line scanning image sensor for acquiring images, wherein the unit is lines/s, namely the line number capable of acquiring images per second. The higher the line frequency, the faster the acquisition speed of the line scan image sensor, and the higher the resolution of the line scan image sensor.

High-speed line scanning image sensors, i.e. line scanning image sensors with higher line frequency, are currently being used more and more widely in many industrial application fields, especially in the fields of semiconductors and the like.

However, the line frequency of the existing line scan image sensor still has difficulty in meeting the high-speed application requirements.

Disclosure of Invention

The invention solves the technical problems that: how to increase the line frequency of a line scan image sensor.

To solve the above technical problem, an embodiment of the present invention provides a line scan image sensor, including:

a control unit;

n pixel arrays, wherein N is more than or equal to 2 and N is an integer;

n ADC arrays;

the N pixel arrays are connected with the N ADC arrays in a one-to-one correspondence manner; the control unit is suitable for controlling the N pixel arrays to be sequentially exposed in the working period of one ADC array, and controlling other pixel arrays to be in a charge reset state when the pixel arrays are exposed; the ADC array is suitable for quantifying the image acquisition result of the corresponding pixel array; the duty cycle of the ADC array is equal to N times the row period.

Optionally, each pixel array is a linear array sensor.

Optionally, each of the pixel arrays is a TDI sensor.

Optionally, the value of N matches the pitch between adjacent pixel arrays.

Optionally, in the N pixel arrays, the pitch between adjacent pixel arrays is m×n rows, and M is any positive integer.

Optionally, the ADC array is adapted to perform correlated double sampling quantization on the image acquisition result of the corresponding pixel array.

Optionally, the line frequency of the line scanning image sensor is n×f, and F is the working period of the ADC array.

Optionally, the N pixel arrays are arranged along a scanning direction.

The embodiment of the invention also provides a linear array camera, which comprises the line scanning image sensor.

The embodiment of the invention also provides a control method of the line scanning image sensor, wherein the line scanning image sensor is as described in any one of the above. The method comprises the following steps:

and controlling the N pixel arrays to sequentially expose, and controlling other pixel arrays to be in a charge reset state when one pixel array is exposed.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

by adopting the scheme, the line scanning image sensor comprises N pixel arrays and N ADC arrays, the N pixel arrays are connected with the N ADC arrays in a one-to-one correspondence manner, under the control of the control unit, the N pixel arrays are sequentially exposed in the working period of one ADC array, and the working period of the ADC array is equal to N times of the line period, so that each pixel array is respectively exposed once in the working period of one ADC array, the N pixel arrays are exposed for N times, and the line frequency is extended to N times relative to the one-time exposure in the working period of one ADC array, thereby effectively improving the line frequency of the line scanning image sensor.

Drawings

FIG. 1 is a schematic diagram of a line scan image sensor according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a pixel structure in a linear array sensor;

FIG. 3 is a basic timing diagram for operation of the pixel of FIG. 2;

FIG. 4 is a schematic diagram illustrating an operation timing of a pixel array according to an embodiment of the invention.

Detailed Description

Existing line scan image sensors typically include only one linear array sensor array or one TDI image sensor whose output is quantized by an analog-to-digital converter (ADC) array.

Taking a photosensitive element of the line scanning image sensor as a line array sensor array as an example, exposing the line array sensor array once in a working period of one ADC array, wherein the exposure time of the line array sensor array is equal to the working period of the ADC array, and the line frequency of the line scanning image sensor is the working period of the unique ADC array in the line scanning image sensor.

Because the working period of the ADC array is difficult to improve, the line frequency of the traditional line scanning image sensor is limited, and the high-speed application requirement is difficult to meet.

In view of the above problems, the embodiment of the invention provides a line scanning image sensor, in which N pixel arrays and N ADC arrays are provided, the N pixel arrays are connected to the N ADC arrays in a one-to-one correspondence manner, under the control of a control unit, the N pixel arrays are sequentially exposed in a working period of one ADC array, and the working period of the ADC array is equal to N times of a line period, so that in the working period of one ADC array, the N pixel arrays respectively perform one exposure, and the N pixel arrays perform N times of exposure in total, and the line frequency is extended to N times in comparison with the working period of one ADC array, thereby effectively improving the line frequency of the line scanning image sensor.

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Embodiments of the present invention provide a line scan image sensor, which may include:

a control unit;

n pixel arrays, wherein N is more than or equal to 2 and N is an integer;

n ADC arrays;

the N pixel arrays are connected with the N ADC arrays in a one-to-one correspondence manner; the control unit is suitable for controlling the N pixel arrays to be sequentially exposed in the working period of one ADC array, and controlling other pixel arrays to be in a charge reset state when the pixel arrays are exposed; the ADC array is suitable for quantifying the image acquisition result of the corresponding pixel array; the duty cycle of the ADC array is equal to N times the row period.

In a specific implementation, the so-called line period, i.e. the line scanning period, is the time required to scan a line of an image for a pixel array. The exposure time of each pixel array is one row period, and because the working period of the ADC array is equal to N times of the row period, when N pixel arrays are sequentially exposed in turn in the working period of one ADC array, the N pixel arrays are exposed for N times in the working period of one ADC array, so that the row frequency is expanded to be N times of the original row frequency. Therefore, by increasing the number of the pixel arrays and the ADC arrays, the line frequency can be continuously expanded, and thus the high-speed application requirement can be met.

In a specific implementation, the value of N may be set according to the actual chip area requirement and the line frequency requirement. For example, N may be 2, 3, 4, 5, 6, etc., as long as the chip area allows. The number of the pixel arrays is the same as that of the ADC arrays and are connected in a one-to-one correspondence.

Fig. 1 is a schematic diagram of a connection between N pixel arrays and the N ADC arrays according to an embodiment of the invention. Referring to fig. 1, the n Pixel arrays are Pixel array1, pixel array2, pixel array3, … …, pixel array n-1, pixel array n, respectively. The N ADC arrays are respectively an ADC array1, an ADC array2, an ADC array3, … …, an ADC array N-1 and an ADC quantization array N.

The Pixel array1 is connected with the ADC array1, the Pixel array2 is connected with the ADC array2, the Pixel array3 is connected with the ADC array3, the … … is connected with the ADC array N-1, and the Pixel array N is connected with the ADC array N. The output of each pixel array is quantized by the corresponding ADC array.

In other embodiments, each pixel array is connected to the ADC array1 limited to the above, so long as N pixel arrays are connected to the ADC arrays in a one-to-one correspondence. For example, pixel array1 may be connected to ADC array N-1.

In a specific implementation, the N pixel arrays are sequentially exposed in a working period of one ADC array, which can be understood as that the N pixel arrays work in a pipelined manner. For example, pixel array1 is exposed to the first row period in the duty cycle of an ADC array, pixel array2 is exposed to the second row period in the duty cycle of the ADC array, … …, and Pixel array N is exposed to the nth row period in the duty cycle of the ADC array. When the Pixel array1 is exposed, the Pixel arrays Pixel array2 to Pixel array n are in a charge reset state … …, and when the Pixel arrays Pixel array n are exposed, the Pixel arrays Pixel array1 to Pixel array n-1 are in a charge reset state.

In the implementation, in the sequential exposure process, the Pixel array that is exposed first is not limited to the Pixel array1, but may be other Pixel arrays. The exposure sequence is not limited to the Pixel array1 to the Pixel array n, and may be any sequence as long as there is one Pixel array exposure per line period and each Pixel array is exposed only once.

In a specific implementation, the number of ADCs included in one ADC array is the same as the number of pixels included in one pixel array, and the ADCs in the ADC array are connected to corresponding pixels of the pixel array one by one, so that the exposure results of the corresponding ADCs can be quantized. The set of quantization results of all ADCs of the ADC array is the quantization result of the ADC array to the pixel array.

In a specific implementation, the N pixel arrays may be arranged along the scanning direction (i.e., the direction perpendicular to the row direction). The N ADC arrays work according to a certain time sequence, and no space limitation relation exists. The N ADC arrays form an interleaved ADC array. Each pixel array corresponds to one ADC array, and a single ADC array comprises the same number of columns as the pixel arrays, namely, each column of pixels corresponds to one column of ADC, and the column of ADCs in the ADC arrays can simultaneously quantize an output image of one pixel array (the working mode is column parallel ADCs).

In a specific implementation, the pixel array is exposed once, meaning that all pixels in the pixel array are exposed once respectively. Specifically, the one-time exposure time of the pixel array is a line period, the start time of the line period is the exposure start time of the pixel array, and the end time of the line period is the exposure end time of the pixel array. Each pixel array is used to acquire a line of image information.

In one embodiment of the present invention, each pixel array may be a linear array sensor. In the linear array sensor, pixels are arranged in a linear array, and each linear array sensor is composed of only one row and a plurality of columns of pixels. The linear array sensor can acquire one line of image information each time it is exposed. By moving relative to the shot object, the results of the multi-line scanning exposure can be spliced to obtain complete two-dimensional image information. At this time, the linear array sensor has one exposure time, i.e., one line period.

In another embodiment of the invention, each pixel array may be a TDI sensor. In the TDI sensor, the same column of pixels exposes the same position of the object to be photographed, each row of pixels exposes each row of pixels, and finally, the exposure results of the pixels in the same column are accumulated to be the final exposure result of the pixels in the column. The TDI sensor acquires one line of image information for one exposure time, i.e., one line period.

In other embodiments, the pixel array may be other types of line scan image sensing devices, and is not illustrated herein.

In a specific implementation, in order to ensure that the output of each ADC array can obtain a correct image after being rearranged, the value of N should be matched with the interval between adjacent pixel arrays. Therefore, based on the value of N, the physical distance between adjacent pixel arrays can be adjusted, so that each ADC array can stably acquire images of the same position of a shot object, and after the images acquired by the ADC arrays are aligned and arranged, a complete two-dimensional image is formed. Wherein, the distance between adjacent pixel arrays refers to the physical distance between the last row of the previous pixel array and the first row of the next pixel array.

In an embodiment of the present invention, in the N pixel arrays, a pitch between adjacent pixel arrays is m×n rows, and M is any positive integer. Therefore, the interval between the adjacent pixel arrays is an integer multiple of the number of the pixel arrays, because in the first line period, the pixel array1 acquires the 1 st line of image data, in the second line period, the pixel array2 acquires the Mth n+2 th line of image data, and so on, in the Nth line of pixels, the Nth pixel array acquires the (N-1) Mth n+N line of image data, and the N lines of image data are sequentially spaced by Mth n+1, after the data processing delay alignment is performed through the outside, the image information cannot be overlapped, and the overlapping between the image information acquired by the adjacent pixel arrays can be avoided. For example, M may be 1, and in this case, the pitch between adjacent pixel arrays is N rows. M may be 2, where the pitch between adjacent pixel arrays is 2N rows. M may also be 3, where the spacing between adjacent pixel arrays is 3N rows.

In a specific implementation, the pitches between each adjacent pixel array are the same in the N pixel arrays, for example, the pitches between each adjacent pixel array are all (3N) rows. This allows the ADC array1 to always quantize the first line of an image, and the ADC array N always quantizes the nth line of an image, and the data is output to the off-chip for realignment arrangement, so that a correct image can be obtained.

In an embodiment of the invention, the ADC array is adapted to perform correlated double sampling (Correlated Double Sampling, CDS) quantization of the image acquisition results of the respective pixel array.

The following describes in detail a control procedure of a line scanning image sensor in an embodiment of the present invention, taking a line sensor as an example:

fig. 2 is a schematic diagram of a pixel structure in a linear array sensor. FIG. 3 is a basic timing diagram of the operation of the pixel of FIG. 2.

Referring to fig. 2, the pixel structure is composed of a photodiode PD, a charge reset tube N1, a transfer tube N2, a gain switching tube N3, a pixel reset tube N4, an amplifying tube N5, a row selection tube N6, and a tail current source I0. The charge reset tube N1, the transmission tube N2, the gain switching tube N3, the pixel reset tube N4, the amplifying tube N5 and the row selecting tube N6 are NMOS tubes.

The cathode of the photodiode PD is connected to the source of the charge reset tube N1 and the source of the transfer tube N2. The control end of the charge reset tube N1 is connected with a charge reset signal AB. The drain of the charge reset tube N1 is connected to the pixel reset voltage VRST. The control end of the transmission tube N2 is connected with a transmission control signal TG. The drain of the transmission tube N2 is connected with the source of the gain switching tube N3 and the control end of the amplifying tube N5. The control end of the gain switching tube N3 is connected with a gain switching signal DCG. The drain of the gain switching tube N3 is connected to the source of the pixel reset tube N4. The control end of the pixel reset tube N4 is connected with a pixel reset signal RST. The drain of the pixel reset tube N4 is connected to the pixel reset voltage VRST. The control end of the amplifying tube N5 is connected with the amplifying signal SF. The drain electrode of the amplifying tube N5 is connected with the power supply voltage VDDPIX, and the source electrode is connected with the source electrode of the row selecting tube N6. The control end of the row selection tube N6 is connected with a row selection signal RS. The drain of the row select transistor N6 is connected to the bit line BL and the tail current source I0.

When the charge reset signal AB is at a high level, the charge reset transistor N1 is turned on, and the photo-charge on the photodiode PD is cleared. When the transfer control signal TG is at a high level, the photo charge on the photodiode PD is introduced to the node FD.

The gain switching tube N3 is a conversion gain switching switch of the pixel for switching the capacitance value of the node FD, specifically, when the gain switching signal DCG is at a high level, the capacitance of the node FD becomes large and the conversion gain of the pixel becomes small. When the gain switching signal DCG is low, the capacitance of the node FD becomes small, and the conversion gain of the pixel becomes large.

The pixel reset transistor N4 is a reset transistor of the pixel for performing a reset operation on the capacitance of the node FD. The amplifying tube N5 is matched with the row selecting tube N6 and the tail current source I0 to form a source electrode following amplifier, and the pixel signal of the node FD is output to the outside of the pixel array.

Referring to fig. 2 and 3, when the charge reset signal AB is at a high level, the photodiode PD is reset, and the photo charge on the photodiode PD is cleared. At time T0, the photodiode PD reset operation is ended, and the pixel starts exposure. At time T1, the row select signal RS is high, the row select transistor N6 is turned on, the read operation is started, and the exposure is ended.

Before the read operation starts, the FD node is reset. Specifically, in the low conversion gain mode, the gain switching signal DCG is constantly at a high level, so that the capacitance of the node FD becomes small, and the reset of the node FD is realized. In the high conversion gain mode, when the node FD is reset, the pixel reset transistor N4 and the gain switching transistor N3 are required to be turned on simultaneously, and turned off simultaneously after the reset is completed (no excessive mode is performed).

After the reset of the node FD, the voltage output from the pixel to the bit line BL is the pixel reset voltage VRST, and at this time, the corresponding ADC array starts the first quantization, that is, rmp1 operation, to quantize the pixel reset signal RST. After the rmp1 operation is completed, the transfer tube N2 is turned on to conduct the photo-charges to the node FD, and at this time, the voltage output from the pixel to the bit line BL is the signal level VSIG of the pixel, and then the corresponding ADC array starts the second quantization, that is, the rmp2 operation, to quantize the SIG signal of the pixel. And finishing CDS operation by making difference between the two quantization results, and finishing the quantization of the photosensitive information of the pixels.

In the above pixel structure, the charge reset signal AB controls the charge reset tube N1, thereby realizing the charge reset operation of the pixel. The capacitance value of node FD may remain unchanged during the charge reset. Therefore, in the implementation, the operation of rmp1 can be performed after FD reset, without waiting for the end of exposure.

Taking the Pixel array1 of fig. 1 as an example, the Pixel array1 is composed of a row of pixels shown in fig. 2. The ADC array corresponding to the Pixel array1 is ADC array1, the ADC array1 is quantized once every N time, each quantization has two actions, namely rmp1 operation and rmp2 operation, so that CDS operation is convenient, and the photoelectric charges generated in the rest time are reset through a charge reset tube N1. The operation timing of the Pixel array1 is shown in fig. 4.

Referring to fig. 4, RST indicates a Pixel reset signal RST of each Pixel in the Pixel array1 corresponding to the Pixel array. TG denotes a transfer control signal of each Pixel in the Pixel array1, and AB denotes a charge reset signal of each Pixel in the Pixel array 1. ADC1timing represents the timing of the ADC array1 corresponding to Pixel array 1. ADC2timing to ADCNtiming represent the timing of the corresponding ADC array for other pixel arrays.

In fig. 4, each unit time length is one line period. Before the K+1st exposure starts, the Pixel array1 is in a charge reset state through a charge reset signal AB, at this time, photo charges generated by photodiodes in pixels are all reset through charge reset tubes until the charge reset tubes are closed at the moment T0, the Pixel array starts exposure, and the exposure ends at the moment T1. The time of T0 to T1 is the line period T.

Before the k+1st exposure starts, the pixel reset signal RST is at a high level, and the ADC array1 can perform the first quantization operation, i.e. quantize the reset level. After the k+1th exposure is completed, the Pixel array1 is in a charge reset state, and the ADC array1 starts to perform a second quantization operation, that is, quantizes the signal level. The duty cycle of the ADC array1 is from the k+1th exposure start time (i.e., time T0) to the k+1th exposure start time of the Pixel array 1.

As can be seen from fig. 4, the pixel arrays are sequentially exposed, each pixel array having an exposure time of one line period. Each pixel array is respectively exposed once and N pixel arrays are exposed for N times in a working period of one ADC array. One ADC array only needs to be read and quantized once in N row time, and the corresponding readout time of a single ADC array is N times of the row period, that is, n×t (T is the row period), so that the operating speed of the ADC array is 1/N of the operating speed of the ADC array in the prior art.

There are N quantization result outputs in one ADC array duty cycle. If a single ADC can only meet the requirement of a linear array sensor with a line frequency F, after expansion, the line frequency of the sensor can be expanded to n×f. The line frequency can be extended continuously as long as the chip has sufficient area.

From the above, it can be seen that the line scanning image sensor in the embodiment of the present invention adopts a multi-array pipeline mode to extend the line frequency of the line scanning image sensor, and uses the chip area to replace the sufficient speed, so as to better satisfy the high-speed application requirement.

The embodiment of the invention also provides a linear array camera which comprises the line scanning image sensor.

The embodiment of the invention also provides a control method of the line scanning image sensor, wherein the line scanning image sensor can be implemented with reference to the description in the above embodiment, and the description is omitted herein.

The method comprises the following steps:

and controlling the N pixel arrays to sequentially expose, and controlling other pixel arrays to be in a charge reset state when one pixel array is exposed.

The N pixel arrays are controlled to sequentially expose in sequence, namely the N pixel arrays are controlled to work in a pipeline mode, so that the N pixel arrays are respectively exposed once in one ADC working period, the line frequency can be effectively improved, and the high-speed application requirement is met.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (10)

1. A line scan image sensor, comprising:

a control unit;

n pixel arrays, wherein N is more than or equal to 2 and N is an integer;

n ADC arrays;

the N pixel arrays are connected with the N ADC arrays in a one-to-one correspondence manner; the control unit is suitable for controlling the N pixel arrays to be sequentially exposed in the working period of one ADC array, and controlling other pixel arrays to be in a charge reset state when the pixel arrays are exposed; the ADC array is suitable for quantifying the image acquisition result of the corresponding pixel array; the duty cycle of the ADC array is equal to N times the row period.

2. The line scan image sensor of claim 1 wherein each of the pixel arrays is a line sensor.

3. The line scan image sensor of claim 1 wherein each of said pixel arrays is a TDI sensor.

4. A line scan image sensor as claimed in claim 2 or 3, wherein the value of N matches the spacing between adjacent pixel arrays.

5. A line scan image sensor as claimed in claim 2 or 3, wherein the pitch between adjacent pixel arrays is M x N rows, M is any positive integer, N is the number of pixel arrays.

6. The line scan image sensor of claim 1 wherein the ADC array is adapted to perform correlated double sampling quantization of the image acquisition results of the corresponding pixel array.

7. The line scan image sensor of claim 1 wherein the line scan image sensor has a line frequency of N x F, F being the ADC array duty cycle.

8. The line scan image sensor of claim 1 wherein the N pixel arrays are arranged along a scan direction.

9. A line camera comprising the line scan image sensor of any one of claims 1 to 8.

10. A control method of a line scanning image sensor, characterized in that the line scanning image sensor is as claimed in any one of claims 1 to 8, the method comprising:

and controlling the N pixel arrays to sequentially expose, and controlling other pixel arrays to be in a charge reset state when one pixel array is exposed.