CN116707469A - Digital Automatic Gain Controller (AGC) circuit structure with adjustable logarithmic parameters - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3089—Control of digital or coded signals
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention relates to a digital Automatic Gain Controller (AGC) circuit structure with adjustable logarithmic parameters, which is provided with a logarithmic and anti-logarithmic operation circuit, and utilizes a nonlinear function to control the output power of an AGC loop, so that the whole loop can reach a stable state in a shorter time and the stable time of signal loops aiming at different input amplitudes is basically consistent. The use of an n-multiplied clock in the subsequent stage circuit enables the circuit to converge more quickly in iteration (n has a value in the range of 3-6). In addition, the invention can realize that the dynamic range index of AGC is more than or equal to 69.5dB and the convergence threshold and the loop stability time parameter are adjustable.
Description
Technical Field
The invention relates to radio frequency technology and digital integrated circuit technology, in particular to a logarithmic digital automatic gain controller circuit structure.
Background
In a communication system, signals of different sensitivity ranges need to be processed. Because of the limited number of bits in the ADC, a larger signal needs to be attenuated and a smaller signal needs to be amplified, which can be achieved by adjusting the gain to adjust the signal to a suitable range, so as to achieve the best demodulation effect. As the input signal changes, the gain will also change accordingly. Such automatic gain control algorithms are commonly referred to as AGC.
With the continuous development of digital signal processing technology, the analog circuit adopted by the traditional AGC is gradually replaced by a digital circuit. Digital AGC has been widely studied by researchers in recent years due to its unique advantages.
The setup time of the conventional AGC structure is affected by the amplitude of the input signal, and when the input signal deviates from the target threshold too much, the convergence time is too long, and a method of adding a logarithmic operation link and improving the loop filter structure is proposed in reference 1 [1] . However, the introduction of logarithmic operation in AGC complicates loop operation and increases cost, based on which researchers have proposed using linear amplifiers to implement AGC loops of constant settling time, which omits the conventional exponential operation unit in digital implementation, reduces implementation complexity and cost, and demonstrates the correctness of the design method through simulink simulation [2] 。
One problem that has also existed in digital AGC is iterative convergence, for which researchers have pointed out that gain control words can be accurately calculated by employing digital synchronous floating point calculations to achieve high stable output [3] . In general, however, the digital automatic gain control uses fixed point arithmetic devices such as a programmable logic chip and a signal processor, and in order to solve the error problem caused by the truncated valid bit, researchers have proposed an algorithm for compensating the oscillation of the control signal by correcting the reference level of the digital automatic gain control [4] . Digital AGC algorithms using logarithmic mixing have also been proposed in AGC implementations [5] The final simulation result shows that the hybrid AGC algorithm realizes the compromise of tracking rate and sensitivity to noise, and has certain advantages in performance and algorithm implementation complexity. In recent years, aiming at the requirement of the AGC design of a software radio receiver, a closed-loop negative feedback AGC structure is designed, and the structure realizes AGC adjustment by comparing the obtained power of a baseband signal with a threshold value, and has the characteristics of simple realization, less occupied resources and quick adjustment convergence [6] . In addition, researchers also realize a large dynamic high-speed response digital AGC which takes a large dynamic high-linearity logarithmic detector and a high-precision digital control attenuator as cores, and realizes the dynamic response range of the AGC to single-factor signals62dB, a fastest response time of 22.6 mu s [7] 。
The patent comprehensively considers research results, uses a logarithmic closed loop AGC structure, realizes a digital AGC circuit in a logarithmic mode, and has a larger dynamic range and faster convergence time. The structure has a logarithmic and anti-logarithmic operation circuit, and uses a nonlinear function to control the output power of the AGC loop, so that the whole loop can reach a stable state in a shorter time. Compared with the traditional AGC, the structure can control the signal strength more effectively, thereby improving the system performance.
Reference to the literature
[1] Ding Dan, liu Fengliang zero intermediate frequency receiver and its AGC method are disclosed and implemented by [ J ]. Telecommunication technique, 2010,50 (06): 46-49.
[2] Wednesday, lu Manhong, huang Jianguo. Constant settling time digital AGC Loop design [ J ]. Aircraft measurement and control theory, 2013,32 (04): 316-320.
[3] Shen Haiwei digital automatic gain control FPGA design [ J ]. Modern navigation 2019,10 (01): 51-55.
[4] Prasolov A.A. CHARACTERISTICS OF DIGITAL AGC IN FIXED-Point OPERATIONS [ J ]. Journal of the Russian universities. Radio electronics,2019,22 (2) [5] Song, jin Huiqin, tian Wei, etc. logarithmic hybrid short wave channel digital AGC algorithm [ J ]. Weapon Automation, 2018,37 (04): 18-22.
[6] Shi Yangxi, zhao Li, liang Yiqing, etc. design and implementation of AGC signal processing algorithms and control models for software defined radio receivers [ J ]. Modern computers 2020, no.693 (21): 3-7.
[7] Implementation of the large dynamic high speed response digital AGC functional circuit [ J ]. Solid state electronics research and development, 2022,42 (06): 467-472.doi:10.19623/j.cnki.rpsse.2022.06.008.
Disclosure of Invention
Aiming at the problem of I/O signal input fluctuation in a zero intermediate frequency receiving and transmitting circuit, the patent provides a digital Automatic Gain Controller (AGC) circuit structure with adjustable logarithmic parameters in a radio frequency receiving and transmitting circuit.
The technical scheme of the invention is a brand new logarithmic closed loop AGC structure, the AGC structure is provided with a logarithmic and anti-logarithmic operation circuit, and the output power of an AGC loop is controlled by utilizing a nonlinear function, so that the whole loop can reach a stable state in a shorter time, and the stable time of signal loops aiming at different input amplitudes is basically consistent. The use of an n-multiplied clock in the subsequent stage circuit enables the circuit to converge more quickly in iteration (n has a value in the range of 3-6). In addition, the invention can realize that the dynamic range index of AGC is more than or equal to 69.5dB and the convergence threshold and the loop stability time parameter are adjustable.
The control loop of the structure consists of four main parts: an input stage, a logarithmic converter, control logic and an output stage. The input stage receives the input signal and amplifies it to within an appropriate range. The logarithmic converter converts the amplified signal into logarithmic values, making it easier to process. The control logic calculates a gain control signal based on the logarithmic value for controlling the generation of the gain value in the feedback circuit. The output stage receives the signal output by the feedback circuit and outputs the signal to the post-stage processing circuit. The more specific connection structure is: the input signal sequentially passes through a digital operational amplifier, signal module calculation, average value calculation, signal power calculation, threshold comparison and gain control, as shown in the structure of fig. 1.
The basic principle of the invention is shown in figure 1, wherein x (n 2), x (n 1) is an input IQ two-path signal, the signal firstly calculates the signal modulus value through a modulus value calculation module, namelyA signal of one frame data length (128 as used herein) is then sampled and the average of its signal modulus values, ave=average (mod), is calculated. The signal power calculation is responsible for converting the average analog value of the signal into the power of the signal, i.e. performing a logarithmic transformation, and since the power of the signal is in dBm, the calculation implemented in this section is power=20×log 10 ave-30。
Comparing the calculated power with a target threshold power to obtain a power difference value between the power and the target threshold power, inputting the power difference value into a gain coefficient control module, and adjusting the threshold and the gain step according to the settingThe gain coefficient coef needed in the AGC adjustment process is acquired. The gain coefficient obtained is multiplied by a loop factor delta, and is input to an anti-logarithmic operation module, and the loop factor is used for adjusting the loop stabilization time. The function implemented by the anti-logarithmic operation is to transform the gain coef into the linear domain for obtaining the gain value output to the digital operational amplifier, i.e
The hardware schematic diagram of the invention is shown in fig. 2, and a DSP multiplier, a cordic module value calculation module, a shift register, a power calculation module, a threshold comparison and gain control module and a cordic index calculation module are respectively realized on an FPGA. The data running state is controlled by a state machine in the whole process. The workflow of the digital automatic gain controller is shown in fig. 3.
The state machine of the circuit internal design of the invention is shown in fig. 4, wherein the state description and the state transition conditions are shown in the following table:
fig. 5 shows a circuit structure of a digital automatic gain controller with adjustable logarithmic parameters according to the present invention. Where block 102 is a PLL (phase locked loop) for generating the multiplied clocks required by the pre-stage and post-stage circuits. The module 101 is an ADC (analog-to-digital converter) at the front stage of the circuit, and signals of two paths of IQ generated are used as input of the whole circuit, and 16-bit signed fixed-point data are adopted for data of each path. The data is then first passed through a digital operational amplifier module 103, the gain value of which is provided by the factor output from the antilog operation module 109, with an initial value of 1, and the output result is taken as the output of the whole circuit and the input of the post signal module 104. The module value calculation module 104 outputs 16-bit fixed-point data as an input to the post-stage average value calculation module 105. The average value calculation module 105 outputs the average value calculated by 128 data, that is, 16-bit fixed-point data avemod, as an input to the post-stage signal power calculation module 106 after sampling the data. The signal power calculation module 106 outputs 16-bit, fixed-point power data as input to the post-threshold comparison and gain control module 107. The threshold comparison and gain control module 107 outputs 16-bit fixed-point gain data as the input of the secondary synchronizer module 108, the output of the secondary synchronizer module 108 is the synchronized input to the post-stage anti-logarithmic operation module 109, the anti-logarithmic operation module 109 calculates 16-bit fixed-point data factor and outputs the 16-bit fixed-point data factor to the digital operational amplifier module 103, and the finite state machine 110 in the circuit controls the data flow in the whole process, so that the whole AGC loop is formed.
The invention has the advantages that:
1. the invention has the characteristic of adjustable parameters, and can configure the signal target convergence power and the loop stabilizing time through the register.
2. The post-stage anti-logarithmic operation module uses an n-frequency multiplication clock, and the value range of n is 3-6, so that the digital automatic gain controller can realize faster iteration convergence.
3. Compared with a general digital automatic gain controller, the digital automatic gain controller has the advantages of higher dynamic range and faster loop stabilization time, and consistent loop stabilization time for input signals with different amplitudes.
Drawings
FIG. 1 is a schematic diagram of a digital automatic gain controller circuit with adjustable logarithmic parameters according to the present invention;
FIG. 2 is a hardware architecture diagram of a digital AGC circuit with logarithmic parameter adjustment according to the present invention;
FIG. 3 is a diagram showing the operation of a digital AGC circuit with adjustable logarithmic parameters according to the present invention;
FIG. 4 is a state jump diagram of a finite state machine within a digital AGC circuit configuration with logarithmic parameter adjustment according to the present invention;
FIG. 5 shows a circuit structure of a digital automatic gain controller with adjustable logarithmic parameters according to the present invention;
FIG. 6 is a diagram of matlab simulation input/output signals in example 1;
FIG. 7 is a graph of matlab simulated output signal power and final adjusted gain values in example 1;
FIG. 8 is a diagram of simulation results of the hardware implemented input/output signals in example 2;
FIG. 9 is a graph of the simulation results of the output power of the hardware implementation of example 2;
fig. 10 is a graph of input signal power versus output signal power for a hardware implementation of example 2.
Detailed Description
Example 1: MATLAB simulation and results for a digital automatic gain controller with adjustable logarithmic parameters.
In the embodiment, MATLAB simulation is performed on the digital automatic gain controller algorithm, input signals are sine waves with amplitudes of 1.5V, 0.5V, 0.1V and 0.0005V respectively, and discretization of data is achieved after sampling at a certain frequency, so that input data are obtained. The set target power for adjustment is 10dBm, and the threshold value for adjustment is divided into 4 grades, which are respectively: the gain steps are divided into 5dB, 2dB, 0.5dB and 0.1dB, wherein the minimum gain step is the adjustment precision of the digital automatic gain controller. The simulation results are shown in fig. 6, which shows the input signal and the output signal tested, and the amplitude of the output signal is converged within the target range after the automatic gain control.
Fig. 7 shows that the power of the output signal is regulated by the digital automatic gain controller, and the power of the signals with different magnitudes are all stabilized around the target value of 10 dBm.
Example 2: FPGA hardware implementation and simulation results of a digital automatic gain controller with adjustable logarithmic parameters.
In this embodiment, RTL simulation is performed by using a vivado simulator, and excitation data required for testing is generated by MATLAB, wherein the maximum amplitude of the input signal is 1.5V, 0.1V and 0.0005V, respectively. The set target power threshold is 10dBm, and the simulation result is as follows:
fig. 8 shows that the input signal is gradually stabilized around the target power value after being adjusted by the digital automatic gain controller, and the output finally reaches a steady state after being adjusted a plurality of times. At a frequency of 140MHZ, the loop settling times were 10.58 mus, 6.47 mus and 15.56 mus, respectively. In addition, according to the actual situation, the loop stability factor register can be configured, so that the loop stability time is further prolonged.
Fig. 9 shows the variation of signal power and gain values during digital automatic gain adjustment, with gain_line indicating the output gain value in the current linear domain, which is valid when ready_getgain is pulled high. Power_fixed represents the power value of the AGC adjusted signal, and it can be seen that the signal eventually settles near the target threshold.
Fig. 10 shows a graph of the input signal power and the output signal power in a hardware implementation.
Claims (2)
1. A digital Automatic Gain Controller (AGC) circuit structure with adjustable parameters, wherein the module 102 is a PLL (phase locked loop) for generating a multiplied clock required by a pre-stage circuit and a post-stage circuit. The module 101 is an ADC (analog-to-digital converter) at the front stage of the circuit, and signals of two paths of IQ generated are used as input of the whole circuit, and 16-bit signed fixed-point data are adopted for data of each path. The data is then first passed through a digital operational amplifier module 103, the gain value of which is provided by the factor output from the antilog operation module 109, with an initial value of 1, and the output result is taken as the output of the whole circuit and the input of the post signal module 104. The module value calculation module 104 outputs 16-bit fixed-point data as an input to the post-stage average value calculation module 105. The average value calculation module 105 outputs the average value calculated by 128 data, that is, 16-bit fixed-point data avemod, as an input to the post-stage signal power calculation module 106 after sampling the data. The signal power calculation module 106 outputs 16-bit, fixed-point power data as input to the post-threshold comparison and gain control module 107. The threshold comparison and gain control module 107 outputs 16-bit fixed-point gain data as the input of the secondary synchronizer module 108, the output of the secondary synchronizer module 108 is the synchronized input to the post-stage anti-logarithmic operation module 109, the anti-logarithmic operation module 109 calculates 16-bit fixed-point data factor and outputs the 16-bit fixed-point data factor to the digital operational amplifier module 103, and the finite state machine 110 in the circuit controls the data flow in the whole process, so that the whole digital Automatic Gain Controller (AGC) loop is formed.
2. The circuit structure of claim 1, wherein the clock frequencies required by the front and rear stages are different, and the rear anti-logarithmic operation circuit module 109 uses an n-frequency multiplication clock, and the value of n ranges from 3 to 6.
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