CN116705935A - Flip normal-pressure LED chip and preparation method thereof - Google Patents
Flip normal-pressure LED chip and preparation method thereof Download PDFInfo
- Publication number
- CN116705935A CN116705935A CN202310817590.6A CN202310817590A CN116705935A CN 116705935 A CN116705935 A CN 116705935A CN 202310817590 A CN202310817590 A CN 202310817590A CN 116705935 A CN116705935 A CN 116705935A
- Authority
- CN
- China
- Prior art keywords
- layer
- type semiconductor
- semiconductor layer
- flip
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 128
- 238000000034 method Methods 0.000 claims abstract description 58
- 230000008569 process Effects 0.000 claims abstract description 36
- 239000010410 layer Substances 0.000 claims description 355
- 239000000758 substrate Substances 0.000 claims description 85
- 238000000231 atomic layer deposition Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 230000000903 blocking effect Effects 0.000 claims description 8
- 238000009413 insulation Methods 0.000 claims description 6
- 238000012545 processing Methods 0.000 claims description 6
- 239000002356 single layer Substances 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 abstract description 5
- 238000004806 packaging method and process Methods 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 3
- 238000003466 welding Methods 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract 2
- 229910002601 GaN Inorganic materials 0.000 description 20
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 20
- 239000000463 material Substances 0.000 description 19
- 238000010586 diagram Methods 0.000 description 11
- 238000005530 etching Methods 0.000 description 5
- 238000002834 transmittance Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 239000007771 core particle Substances 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
- H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
Abstract
The application provides a flip normal-pressure LED chip and a preparation method thereof, wherein the flip normal-pressure LED chip fully surrounds the flip normal-pressure LED chip by utilizing an insulating film layer, only two grooves are reserved for arranging a P electrode and an N electrode, solder can be prevented from overflowing during subsequent welding, and the flip normal-pressure LED chip is communicated with an N type semiconductor layer and a P type semiconductor layer to cause the problems of electric leakage and the like, and can achieve the same effect as the conventional DE process, so the DE process is not needed in the application, the area of the P type semiconductor layer is not required to be reduced, and the light-emitting area of the flip normal-pressure LED chip is improved; the cost for forming the insulating film layer is lower than the cost of the DE procedure, so that the preparation cost is further reduced; the insulating film layer can also isolate water vapor from entering after packaging, so that the reliability of the flip normal-pressure LED chip is improved; in addition, the edge MESA is subjected to patterning treatment, and the light which is originally emitted from the side surface of the light path is changed into back surface emitted light after passing through the patterning DBR, so that the back surface light intensity is improved.
Description
Technical Field
The application relates to the technical field of manufacturing of semiconductor LED chips, in particular to a flip normal-pressure LED chip and a preparation method thereof.
Background
With the continuous development of science and technology, as a novel light emitting device, an LED (Light Emitting Diode ) has the advantages of energy saving, environmental protection, good color rendering property, good response speed and the like compared with the traditional light emitting device, is widely applied to the life and work of people, and brings great convenience to the daily life of people.
In the prior art, in the preparation process of the flip normal pressure LED chip, the MESA photoetching process is generally carried out on the P-type gallium nitride layer to form an MESA platform, then the DE process (DEEP etching technology) is carried out on the N-type gallium nitride layer to expose the substrate, and then the DBR layer is deposited to cover the exposed surfaces of the N-type gallium nitride layer and the P-type gallium nitride layer, so that the problems of leakage and the like caused by the communication between the solder overflow and the N-type gallium nitride layer and the P-type gallium nitride layer during die bonding can be prevented, and the reliability of the LED chip is improved.
However, in the existing preparation process of the flip-chip normal-pressure LED chip, the DE process etches the MESA platform by 2-5 μm, the areas of the MESA platform and the transparent conductive layer on the MESA platform are reduced by 4-10 μm, so that the LED light-emitting area is greatly reduced, the brightness is reduced, and the cost of the DE process is higher.
Therefore, how to improve the reliability of the flip normal pressure LED chip and to improve the light emitting area and reduce the cost is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present application provides a flip normal pressure LED chip and a method for manufacturing the same, which comprises the following steps:
a flip-chip normal pressure LED chip, the flip-chip normal pressure LED chip comprising:
a substrate;
the epitaxial layer is positioned on one side of the substrate and comprises an N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer which are sequentially positioned on one side of the substrate in a first direction, wherein the first direction is perpendicular to a plane where the substrate is positioned and is directed to the epitaxial layer by the substrate;
the epitaxial layer is provided with a first groove, and the first groove penetrates through part of the P-type semiconductor layer and part of the multiple quantum well layer in the first direction to expose part of the N-type semiconductor layer;
the insulating film layer covers the side wall of the inverted normal-pressure LED chip, the surface of the substrate on the side away from the epitaxial layer and the surface of the epitaxial layer on the side away from the substrate;
the insulation film layer comprises a second groove and a third groove, the flip normal-pressure LED chip further comprises a P electrode and an N electrode, the P electrode is located in the second groove and connected with the P-type semiconductor layer, and the N electrode is located in the third groove and connected with the N-type semiconductor layer.
Preferably, in the above flip normal pressure LED chip, the insulating film layer is a single layer structure or a stacked layer structure;
when the insulating film layers are of laminated structures, the refractive index of each insulating film layer is 1-1.67;
the refractive index of the insulating film layers in the stacked structure sequentially decreases in a second direction, which is directed from the epitaxial layer to the insulating film layers.
Preferably, in the flip normal pressure LED chip, the first groove divides the P-type semiconductor layer into a middle region and an edge region;
the P-type semiconductor layer positioned in the edge area comprises a plurality of independent P-type semiconductor layer units.
Preferably, in the above flip-chip normal pressure LED chip, the epitaxial layer further includes:
the current blocking layer, the transparent conductive layer and the DBR layer are sequentially positioned on one side, away from the multi-quantum well layer, of the P-type semiconductor layer in the first direction;
the DBR layer covers the side walls of the transparent conductive layer and the P-type semiconductor layer, the surface of the transparent conductive layer on the side away from the substrate, and the surface of the exposed part of the N-type semiconductor layer;
the DBR layer includes a first via hole and a second via hole, the P electrode is connected with the transparent conductive layer through the second groove and the first via hole, and the N electrode is connected with the N-type semiconductor layer through the third groove and the second via hole.
Preferably, in the above flip normal pressure LED chip, the flip normal pressure LED chip further includes:
the first bonding pad is positioned at one side of the P electrode away from the substrate;
and the second bonding pad is positioned on one side of the N electrode away from the substrate.
The application also provides a preparation method of the flip normal-pressure LED chip, which is used for preparing the flip normal-pressure LED chip, and comprises the following steps:
providing a substrate;
forming an epitaxial layer on one side of the substrate, wherein the epitaxial layer comprises an N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer which are sequentially positioned on one side of the substrate in a first direction, and the first direction is perpendicular to a plane where the substrate is positioned and is directed to the epitaxial layer by the substrate;
processing the epitaxial layer to form a first groove, wherein the first groove penetrates through part of the P-type semiconductor layer and part of the multiple quantum well layer in the first direction to expose part of the N-type semiconductor layer;
forming an insulating film layer, wherein the insulating film layer covers the side wall of the flip normal-pressure LED chip, the surface of the substrate on the side away from the epitaxial layer and the surface of the epitaxial layer on the side away from the substrate;
the insulation film layer is processed to form a second groove and a third groove, the flip normal-pressure LED chip further comprises a P electrode and an N electrode, the P electrode is located in the second groove and connected with the P-type semiconductor layer, and the N electrode is located in the third groove and connected with the N-type semiconductor layer.
Preferably, in the above method for manufacturing a flip normal pressure LED chip, the forming the insulating film layer includes: forming the insulating film layer by using an ALD (atomic layer deposition) device;
wherein, the process temperature of forming the insulating film layer by adopting the ALD equipment is 25-300 ℃, and the deposition rate of forming the insulating film layer by adopting the ALD equipment is 0.05A/s-5A/s.
Preferably, in the above method for manufacturing a flip normal-pressure LED chip, the first groove divides the P-type semiconductor layer into a middle region and an edge region, and the manufacturing method further includes:
and processing the P-type semiconductor layer in the edge area to form a plurality of independent P-type semiconductor layer units.
Preferably, in the above method for manufacturing a flip normal pressure LED chip, after forming the first groove and before forming the insulating film layer, the method further includes:
forming a current blocking layer, a transparent conductive layer and a DBR layer on one side of the P-type semiconductor layer, which is away from the multiple quantum well layer, in sequence in the first direction, wherein the DBR layer covers the side walls of the transparent conductive layer and the P-type semiconductor layer, the surface of the transparent conductive layer, which is away from one side of the substrate, and the surface of the exposed part of the N-type semiconductor layer;
and the DBR layer is processed to form a first through hole and a second through hole, the P electrode is connected with the transparent conductive layer through the second groove and the first through hole, and the N electrode is connected with the N-type semiconductor layer through the third groove and the second through hole.
Preferably, in the preparation method of the flip normal-pressure LED chip, the preparation method further includes:
forming a first bonding pad on one side of the P electrode, which is away from the substrate;
and forming a second bonding pad on one side of the N electrode, which is away from the substrate.
Compared with the prior art, the application has the following beneficial effects:
the application provides a flip normal-pressure LED chip and a preparation method thereof, wherein the flip normal-pressure LED chip comprises: the LED comprises a substrate, an epitaxial layer positioned on one side of the substrate, and an insulating film layer covering the side wall of the flip normal-pressure LED chip, the surface of the substrate on one side away from the epitaxial layer and the surface of the epitaxial layer on one side away from the substrate, wherein the epitaxial layer comprises an N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer; according to the flip normal-pressure LED chip provided by the application, the insulation film layer is utilized to fully enclose the flip normal-pressure LED chip, only the second groove and the third groove are reserved for arranging the P electrode and the N electrode, the solder can be prevented from overflowing during subsequent welding, the problems of electric leakage and the like caused by communication between the N-type semiconductor layer and the P-type semiconductor layer can be solved, and the same effect as the conventional DE process can be achieved, so that the DE process is not needed in the application; the insulating film layer can also isolate the entry of water vapor after packaging, so that the reliability of the flip normal-pressure LED chip is improved; in addition, the application does not adopt the DE procedure, so the area of the P-type semiconductor layer is not reduced, the light-emitting area of the flip normal-pressure LED chip is improved, and the cost for forming the insulating film layer is lower than the cost of the DE procedure, so that the preparation cost of the flip normal-pressure LED chip is further reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a flip normal pressure LED chip provided in the prior art;
fig. 2 is a schematic structural diagram of a flip normal-pressure LED chip according to an embodiment of the present application;
FIG. 3 is a schematic diagram showing the transmittance of a flip-chip normal-pressure LED chip according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of another flip normal-pressure LED chip according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a comparison structure of a flip-chip normal-pressure LED chip according to an embodiment of the present application, wherein the flip-chip normal-pressure LED chip is fabricated by a DE process and a non-DE process;
fig. 6 is a schematic flow chart of a preparation method of a flip normal-pressure LED chip according to an embodiment of the present application;
fig. 7 is a schematic top view of a P-type semiconductor layer unit according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Based on the description of the background technology, the inventor finds that in the process of preparing the conventional flip-chip normal-pressure LED chip, as shown in fig. 1, fig. 1 is a schematic structural diagram of the flip-chip normal-pressure LED chip provided in the prior art, an N-type gallium nitride layer 2, an active layer 3 and a P-type gallium nitride layer 4 are usually formed on a substrate 1 in sequence, then a MESA lithography process is performed on the P-type gallium nitride layer 4 to form a MESA, so that part of the N-type gallium nitride layer 2 is exposed, then the N-type gallium nitride layer 2 is etched through a DE process to expose part of the substrate 1, and then a DBR reflecting layer 5 is deposited to cover the exposed surfaces of the N-type gallium nitride layer 2 and the P-type gallium nitride layer 4, so that the problems of solder overflow, electric leakage caused by communication with the N-type gallium nitride layer 2 and the P-type gallium nitride layer 4 during die bonding can be prevented, and the reliability of the LED chip is improved; however, in the existing preparation process of the flip-chip normal-pressure LED chip, the DE process etches the MESA platform by 2-5 mu m, the size of the MESA platform and the size of the ITO transparent conducting layer 6 positioned on the MESA platform are single-sided and are shrunk by 4-10 mu m, so that the LED luminous area is greatly reduced, the brightness is reduced, and the cost of the DE process is higher; therefore, how to improve the reliability of the flip normal pressure LED chip and to improve the light emitting area and reduce the cost is a technical problem to be solved by those skilled in the art.
The application provides the flip normal-pressure LED chip and the preparation method thereof, which can improve the reliability of the flip normal-pressure LED chip and the luminous area and reduce the cost.
In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description.
The embodiment of the application provides a flip normal-pressure LED chip, referring to FIG. 2, FIG. 2 is a schematic structural diagram of the flip normal-pressure LED chip provided by the embodiment of the application, and in combination with FIG. 2, the flip normal-pressure LED chip comprises:
a substrate 7; the epitaxial layer 8 is located on one side of the substrate 7, the epitaxial layer 8 comprises an N-type semiconductor layer 9, a multiple quantum well layer 10 and a P-type semiconductor layer 11 which are sequentially located on one side of the substrate 7 in a first direction A, and the first direction A is perpendicular to the plane of the substrate 7 and is directed to the epitaxial layer 8 by the substrate 7.
Specifically, in the embodiment of the present application, the substrate 7 includes, but is not limited to, a sapphire substrate, the material of the N-type semiconductor layer 9 includes, but is not limited to, a gallium nitride material, and the like, and the material of the P-type semiconductor layer 11 includes, but is not limited to, a gallium nitride material, and the like.
The epitaxial layer 8 has a first groove penetrating a portion of the P-type semiconductor layer 11 and a portion of the multiple quantum well layer 10 in the first direction a, exposing a portion of the N-type semiconductor layer 9.
The insulating film layer 12, the insulating film layer 12 covers the side wall of the flip normal pressure LED chip, the surface of the substrate 7 on the side away from the epitaxial layer 8, and the surface of the epitaxial layer 8 on the side away from the substrate 7.
The insulating film layer 12 includes a second groove and a third groove, the flip normal-pressure LED chip further includes a P electrode 13 and an N electrode 14, the P electrode 13 is located in the second groove and connected to the P-type semiconductor layer 11, and the N electrode 14 is located in the third groove and connected to the N-type semiconductor layer 9.
Specifically, in the embodiment of the present application, the epitaxial layer 8 further includes a current blocking layer 16 and a transparent conductive layer 17 sequentially located on a side of the P-type semiconductor layer 11 facing away from the multiple quantum well layer 10 in the first direction a; the second groove penetrates through the insulating film layer 12 in the first direction a to expose part of the transparent conductive layer 17, and the P electrode 13 is located on the transparent conductive layer 17 in the second groove to connect with the P-type semiconductor layer 11; the third groove penetrates through the insulating film layer 12 in the first direction A to expose part of the N-type semiconductor layer 9, and the N electrode 14 is positioned on the N-type semiconductor layer 9 in the third groove; the material of the insulating film layer 12 includes, but is not limited to, al 2 O 3 Materials or AlN materials or SiO 2 A material, a SiN material, or the like.
As can be seen from the above description, the flip normal-pressure LED chip provided by the present application comprises: a substrate 7, an epitaxial layer 8 located at one side of the substrate 7, and an insulating film layer 12 covering the sidewall of the flip-chip normal-pressure LED chip, the surface of the substrate 7 facing away from the epitaxial layer 8, and the surface of the epitaxial layer 8 facing away from the substrate 7, wherein the epitaxial layer 8 includes an N-type semiconductor layer 9, a multiple quantum well layer 10, and a P-type semiconductor layer 11; according to the flip normal-pressure LED chip provided by the application, the insulation film layer 12 is utilized to fully enclose the flip normal-pressure LED chip, only the second groove and the third groove are reserved for arranging the P electrode 13 and the N electrode 14, the solder can be prevented from overflowing during subsequent welding, the flip normal-pressure LED chip is communicated with the N-type semiconductor layer 9 and the P-type semiconductor layer 11 to cause the problems of electric leakage and the like, and the same effect as the conventional DE process can be achieved, so that the DE process is not needed in the application; the insulating film layer 12 can also isolate the entry of water vapor after packaging, so that the reliability of the flip normal-pressure LED chip is improved; in addition, the application does not adopt the DE process, so the area of the P-type semiconductor layer 11 is not reduced, the light emitting area of the flip normal-pressure LED chip is improved, and the cost for forming the insulating film layer 12 is lower than the cost of the DE process, so that the preparation cost of the flip normal-pressure LED chip is further reduced.
Optionally, in another embodiment provided by the present application, the insulating film layer 12 in the foregoing flip-chip normal-pressure LED chip is further described, and with reference to fig. 2, the following details are described:
the insulating film layer 12 has a single-layer structure or a laminated structure; when the insulating film layers 12 are of a laminated structure, the refractive index of each insulating film layer 12 is in a range of 1-1.67; the refractive index of the insulating film layer 12 in the stacked structure sequentially decreases in a second direction, which is directed from the epitaxial layer 8 to the insulating film layer 12.
Specifically, in the embodiment of the present application, when the insulating film layer 12 has a single-layer structure, the refractive index of the insulating film layer 12 may take any value in the range of 1 to 1.67, and the insulating film layer 12 includes, but is not limited to, al 2 O 3 Material layer or AlN material layer or SiO 2 A material layer, a SiN material layer, or the like, and the thickness of the insulating film layer 12 in the second direction may take any value in the range of 50 angstroms to 5000 angstroms; when the insulating film layers 12 are laminated structures, the refractive index of each insulating film layer 12 can be set to any value in the range of 1-1.67, the laminated structures include but are not limited to laminated structures made of the same material or laminated structures made of multiple material layers, the number of layers of the insulating film layers 12 can be set to any value in the range of 1-10 layers, and the thickness of each insulating film layer 12 in the second direction can be set to any value in the range of 50-5000 angstroms; referring to FIG. 3, FIG. 3 is a schematic diagram showing the transmittance of a flip-chip normal-pressure LED chip according to an embodiment of the present application, wherein the abscissa in FIG. 3 shows the wavelength in the spectrum, and the ordinate shows the transmittance of the flip-chip normal-pressure LED chip, and the flip-chip normal-pressure LED chip with an insulating film layer 12 can be obtained from FIG. 3The transmittance of the LED chip is higher than that of the flip-chip normal-pressure LED chip not provided with the insulating film layer 12.
Optionally, in another embodiment of the present application, the structure of the above-mentioned flip-chip normal-pressure LED chip is further described, and referring to fig. 4, fig. 4 is a schematic structural diagram of another flip-chip normal-pressure LED chip provided in the embodiment of the present application, and in conjunction with fig. 4, the following details are described:
the first groove divides the P-type semiconductor layer 11 into a middle region and an edge region; the P-type semiconductor layer 11 located at the edge region includes a plurality of individual P-type semiconductor layer units 15.
Specifically, in the embodiment of the present application, the first groove surrounds the P-type semiconductor layer 11 in the middle area, and the P-type semiconductor layer 11 in the edge area surrounds the first groove; the shape of the P-type semiconductor layer unit 15 includes, but is not limited to, a cylindrical shape, a polygonal column shape, a stepped shape, etc.; the dimension of the P-type semiconductor layer unit 15 may take any value in the range of 3 μm to 100 μm, the thickness of the P-type semiconductor layer unit 15 in the first direction a may take any value in the range of 3 μm to 100 μm, and the width of the P-type semiconductor layer unit 15 in the third direction may take any value in the range of 3 μm to 100 μm, wherein the third direction is parallel to the plane of the substrate 7; the pitch between two adjacent P-type semiconductor layer units 15 may take any value in the range of 10 μm to 100 μm.
The epitaxial layer 8 further includes a current blocking layer 16, a transparent conductive layer 17, and a DBR layer 18, which are sequentially located on a side of the P-type semiconductor layer 11 facing away from the multiple quantum well layer 10 in the first direction a.
Specifically, in the embodiment of the present application, as shown in fig. 5, fig. 5 is a schematic diagram of a comparison structure of a flip-chip normal-pressure LED chip provided in the embodiment of the present application, in which a is a schematic top view of a flip-chip normal-pressure LED chip using a DE process and a non-DE process are illustrated in fig. 5, b is a schematic top view of a flip-chip normal-pressure LED chip not using a DE process, and as compared with the schematic top views in fig. 5, a and b, the present application reduces the DE process, no etching is required for the N-type semiconductor layer 9, the area of the N-type semiconductor layer 9 is larger than that of the N-type gallium nitride layer 2 after the DE process, the area of the P-type semiconductor layer 11 is not required to be reduced, and the area of the transparent conductive layer 17 is not required to be reduced, so that the light emitting area of the flip-chip normal-pressure LED chip can be increased by 5% -30%; in addition, the increasing proportion of the light emitting area of the flip-chip normal-pressure LED chip is related to the size of the flip-chip normal-pressure LED chip, for example, the flip-chip normal-pressure LED chip with the size of 150×250, which is not adopted in the DE process, can increase the light emitting area by 15% compared with the flip-chip normal-pressure LED chip with the DE process.
The DBR layer 18 covers the sidewalls of the transparent conductive layer 17 and the P-type semiconductor layer 11, the surface of the transparent conductive layer 17 on the side facing away from the substrate 7, and the surface of the exposed portion of the N-type semiconductor layer 9; the DBR layer 18 includes a first via hole and a second via hole, the P electrode 13 is connected to the transparent conductive layer 17 through the second groove and the first via hole, and the N electrode 14 is connected to the N-type semiconductor layer 9 through the third groove and the second via hole.
Specifically, in the embodiment of the present application, since the P-type semiconductor layer 11 in the edge region is a plurality of independent P-type semiconductor layer units 15, the DBR layer 18 covers the P-type semiconductor layer units 15 to obtain an edge DBR mirror; in the flip normal-pressure LED chip adopting the DE process, as shown in fig. 1, light is emitted from the side after being reflected by the DBR reflective layer 5, and after the P-type semiconductor layer unit 15 is provided, as shown in fig. 3, light is emitted from the surface of the substrate 7, which is far away from the N-type semiconductor layer 9, after being reflected by the DBR layer 18 in the P-type semiconductor layer unit 15, so that the side light-emitting rate is reduced, the back light intensity is improved, and the flip normal-pressure LED chip is very suitable for product applications requiring high back light efficiency, such as car lights and the like.
The flip normal pressure LED chip further comprises: a first pad 19 located on a side of the P electrode 13 facing away from the substrate 7; and a second bonding pad 20 positioned on the side of the N electrode 14 facing away from the substrate 7.
Specifically, in the embodiment of the application, because the reliability in packaging is considered in the prior art, the distance between the bonding pad and the DE etching position is generally 8-20 μm, but the application does not adopt the DE procedure, the area of the bonding pad can be enlarged according to the size of the flip normal pressure LED chip, and the heat dissipation and the thrust of the flip normal pressure LED chip can be improved due to the enlarged area of the bonding pad, so that the reliability of the chip is improved.
Optionally, based on the foregoing embodiment of the present application, in another embodiment of the present application, a method for preparing a flipped normal-pressure LED chip is further provided, which is used to prepare the flipped normal-pressure LED chip described in the foregoing embodiment, and referring to fig. 6, fig. 6 is a schematic flow diagram of a method for preparing a flipped normal-pressure LED chip provided in the embodiment of the present application, and in combination with fig. 6, the method includes:
s100: a substrate 7 is provided.
Specifically, in this step S100, the substrate 7 includes, but is not limited to, a sapphire substrate.
S200: an epitaxial layer 8 is formed on one side of the substrate 7, and the epitaxial layer 8 includes an N-type semiconductor layer 9, a multiple quantum well layer 10, and a P-type semiconductor layer 11 sequentially located on one side of the substrate 7 in a first direction a, wherein the first direction a is perpendicular to a plane of the substrate 7 and is directed from the substrate 7 to the epitaxial layer 8.
Specifically, in this step S200, the material of the N-type semiconductor layer 9 includes, but is not limited to, a gallium nitride material, etc., and the material of the P-type semiconductor layer 11 includes, but is not limited to, a gallium nitride material, etc.
S300: the epitaxial layer 8 is processed to form a first groove, and the first groove penetrates through part of the P-type semiconductor layer 11 and part of the multiple quantum well layer 10 in the first direction a to expose part of the N-type semiconductor layer 9.
Specifically, in the step S300, including but not limited to etching the P-type semiconductor layer 11 by using a MESA photolithography process to form a first groove, the first groove penetrates a portion of the P-type semiconductor layer 11 and a portion of the multiple quantum well layer 10 in the first direction a to expose a portion of the N-type semiconductor layer 9, and the first groove further divides the P-type semiconductor layer 11 into a middle region and an edge region; while etching the P-type semiconductor layer 11 by using a MESA photolithography process to form a first groove, processing the P-type semiconductor layer 11 in an edge region to form a plurality of independent P-type semiconductor layer units 15, as shown in fig. 7, fig. 7 is a schematic top view structure after forming the P-type semiconductor layer units, when forming the P-type semiconductor layer units 15 by using a MESA photolithography process, using a MESA photomask to define a pattern in the edge region of the P-type semiconductor layer 11, transferring the pattern onto the P-type semiconductor layer 11 by using a positive photoresist and an etching program, thereby forming the P-type semiconductor layer units 15, wherein the pattern can be in any shape such as a circle, a square or a trapezoid, the aperture and the line width of the pattern can be in any value within a range of 3 μm-100 μm, and the interval between two adjacent patterns can be in any value within a range of 10 μm-100 μm.
S400: in the first direction a, a current blocking layer 16, a transparent conductive layer 17, and a DBR layer 18 are sequentially formed on a side of the P-type semiconductor layer 11 facing away from the multiple quantum well layer 10, the DBR layer 18 covering the transparent conductive layer 17 and the side wall of the P-type semiconductor layer 11, a surface of the transparent conductive layer 17 facing away from the substrate 7, and a surface of the exposed portion of the N-type semiconductor layer 9.
Specifically, since the first recess divides the P-type semiconductor layer 11 into the middle region and the edge region in step S300, in step S400, the current blocking layer 16 and the transparent conductive layer 17 are sequentially formed on the side of the P-type semiconductor layer 11 in the middle region facing away from the substrate 7; in addition, before forming the DBR layer 18, forming the P electrode 13 on the side of the transparent conductive layer 17 facing away from the substrate 7, forming the N electrode 14 on the surface of the N-type semiconductor layer 9 exposed in the first groove facing away from the substrate 7, and then forming the DBR layer 18, wherein the DBR layer 18 covers the exposed surface of the P electrode 13, the exposed surface of the N electrode 14, the sidewalls of the transparent conductive layer 17 and the P-type semiconductor layer 11, the surface of the transparent conductive layer 17 facing away from the substrate 7, and the exposed portion of the surface of the N-type semiconductor layer 9.
S500: processing the DBR layer 18 to form a first via hole exposing the P electrode 13 and a second via hole exposing the N electrode 14; forming a first bonding pad 19 on a side of the P electrode 13 facing away from the substrate 7; a second pad 20 is formed on the side of the N-electrode 14 facing away from the substrate 7.
Specifically, in this step S500, the first pad 19 covers the surface of the P electrode 13 on the side facing away from the substrate 7, and covers a part of the surface of the DBR layer 18 on the side facing away from the substrate 7; the second pad 20 covers a surface of the N electrode 14 on a side facing away from the substrate 7, and covers a portion of a surface of the DBR layer 18 on a side facing away from the substrate 7.
S600: an insulating film layer 12 is formed, and the insulating film layer 12 covers the side wall of the flip normal-pressure LED chip, the surface of the substrate 7 on the side away from the epitaxial layer 8, and the surface of the epitaxial layer 8 on the side away from the substrate 7.
Specifically, after the first bonding pad 19 and the second bonding pad 20 are formed in the step S500, grinding and cutting are required to form core particles, the cut core particles are turned over onto a high-temperature film or a normal-temperature blue film, the side provided with the first bonding pad 19 and the second bonding pad 20 faces the high-temperature film or the normal-temperature blue film, and then the insulating film layer 12 is formed; in the step S600, including but not limited to, forming the insulating film layer 12 by using an ALD apparatus, the process temperature of forming the insulating film layer 12 by using the ALD apparatus may take any value in the range of 25 ℃ to 300 ℃, and the deposition rate of forming the insulating film layer 12 by using the ALD apparatus may take any value in the range of 0.05A/S to 5A/S; in addition, the insulating film 12 needs to be processed to form a second groove and a third groove, where the second groove exposes the first pad 19 and the second groove exposes the second pad 20.
The application provides a flip normal-pressure LED chip and a preparation method thereof, and specific examples are applied to the description of the principle and the implementation mode of the application, and the description of the examples is only used for helping to understand the method and the core idea of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include, or is intended to include, elements inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A flip-chip normal-pressure LED chip, comprising:
a substrate;
the epitaxial layer is positioned on one side of the substrate and comprises an N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer which are sequentially positioned on one side of the substrate in a first direction, wherein the first direction is perpendicular to a plane where the substrate is positioned and is directed to the epitaxial layer by the substrate;
the epitaxial layer is provided with a first groove, and the first groove penetrates through part of the P-type semiconductor layer and part of the multiple quantum well layer in the first direction to expose part of the N-type semiconductor layer;
the insulating film layer covers the side wall of the inverted normal-pressure LED chip, the surface of the substrate on the side away from the epitaxial layer and the surface of the epitaxial layer on the side away from the substrate;
the insulation film layer comprises a second groove and a third groove, the flip normal-pressure LED chip further comprises a P electrode and an N electrode, the P electrode is located in the second groove and connected with the P-type semiconductor layer, and the N electrode is located in the third groove and connected with the N-type semiconductor layer.
2. The flip-chip normal pressure LED chip of claim 1, wherein said insulating film layer is of a single-layer structure or a laminated structure;
when the insulating film layers are of laminated structures, the refractive index of each insulating film layer is 1-1.67;
the refractive index of the insulating film layers in the stacked structure sequentially decreases in a second direction, which is directed from the epitaxial layer to the insulating film layers.
3. The flip-chip normal pressure LED chip of claim 1, wherein said first grooves divide said P-type semiconductor layer into a middle region and an edge region;
the P-type semiconductor layer positioned in the edge area comprises a plurality of independent P-type semiconductor layer units.
4. The flip-chip normal pressure LED chip of claim 1, wherein said epitaxial layer further comprises:
the current blocking layer, the transparent conductive layer and the DBR layer are sequentially positioned on one side, away from the multi-quantum well layer, of the P-type semiconductor layer in the first direction;
the DBR layer covers the side walls of the transparent conductive layer and the P-type semiconductor layer, the surface of the transparent conductive layer on the side away from the substrate, and the surface of the exposed part of the N-type semiconductor layer;
the DBR layer includes a first via hole and a second via hole, the P electrode is connected with the transparent conductive layer through the second groove and the first via hole, and the N electrode is connected with the N-type semiconductor layer through the third groove and the second via hole.
5. The flip-chip normal-pressure LED chip of claim 1, further comprising:
the first bonding pad is positioned at one side of the P electrode away from the substrate;
and the second bonding pad is positioned on one side of the N electrode away from the substrate.
6. A method for preparing a flip-chip normal-pressure LED chip, wherein the method is used for preparing the flip-chip normal-pressure LED chip according to any one of claims 1 to 5, and the method comprises:
providing a substrate;
forming an epitaxial layer on one side of the substrate, wherein the epitaxial layer comprises an N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer which are sequentially positioned on one side of the substrate in a first direction, and the first direction is perpendicular to a plane where the substrate is positioned and is directed to the epitaxial layer by the substrate;
processing the epitaxial layer to form a first groove, wherein the first groove penetrates through part of the P-type semiconductor layer and part of the multiple quantum well layer in the first direction to expose part of the N-type semiconductor layer;
forming an insulating film layer, wherein the insulating film layer covers the side wall of the flip normal-pressure LED chip, the surface of the substrate on the side away from the epitaxial layer and the surface of the epitaxial layer on the side away from the substrate;
the insulation film layer is processed to form a second groove and a third groove, the flip normal-pressure LED chip further comprises a P electrode and an N electrode, the P electrode is located in the second groove and connected with the P-type semiconductor layer, and the N electrode is located in the third groove and connected with the N-type semiconductor layer.
7. The method of manufacturing according to claim 6, wherein the forming the insulating film layer includes: forming the insulating film layer by using an ALD (atomic layer deposition) device;
wherein, the process temperature of forming the insulating film layer by adopting the ALD equipment is 25-300 ℃, and the deposition rate of forming the insulating film layer by adopting the ALD equipment is 0.05A/s-5A/s.
8. The method of manufacturing according to claim 6, wherein the first groove divides the P-type semiconductor layer into a middle region and an edge region, the method further comprising:
and processing the P-type semiconductor layer in the edge area to form a plurality of independent P-type semiconductor layer units.
9. The manufacturing method according to claim 6, wherein after forming the first groove and before forming the insulating film layer, the manufacturing method further comprises:
forming a current blocking layer, a transparent conductive layer and a DBR layer on one side of the P-type semiconductor layer, which is away from the multiple quantum well layer, in sequence in the first direction, wherein the DBR layer covers the side walls of the transparent conductive layer and the P-type semiconductor layer, the surface of the transparent conductive layer, which is away from one side of the substrate, and the surface of the exposed part of the N-type semiconductor layer;
and the DBR layer is processed to form a first through hole and a second through hole, the P electrode is connected with the transparent conductive layer through the second groove and the first through hole, and the N electrode is connected with the N-type semiconductor layer through the third groove and the second through hole.
10. The method of manufacturing according to claim 6, further comprising:
forming a first bonding pad on one side of the P electrode, which is away from the substrate;
and forming a second bonding pad on one side of the N electrode, which is away from the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310817590.6A CN116705935A (en) | 2023-07-05 | 2023-07-05 | Flip normal-pressure LED chip and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310817590.6A CN116705935A (en) | 2023-07-05 | 2023-07-05 | Flip normal-pressure LED chip and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116705935A true CN116705935A (en) | 2023-09-05 |
Family
ID=87832290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310817590.6A Pending CN116705935A (en) | 2023-07-05 | 2023-07-05 | Flip normal-pressure LED chip and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116705935A (en) |
-
2023
- 2023-07-05 CN CN202310817590.6A patent/CN116705935A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102641239B1 (en) | Light emitting diode, method of fabricating the same, and light emitting device module having the same | |
| TWI819258B (en) | Light emitting diode chip | |
| US8138518B2 (en) | Light emitting diode, package structure and manufacturing method thereof | |
| CA2470095C (en) | Light-emitting diode with planar omni-directional reflector | |
| US8895329B2 (en) | Patterned substrate for light emitting diode and light emitting diode employing the same | |
| CN110459660B (en) | Light-emitting diode, manufacturing process and light-emitting device | |
| KR20120053571A (en) | Light emitting diode chip having plurality of mesa structures | |
| KR20120053570A (en) | Light emitting diode chip having electrode pad | |
| JP2012513681A (en) | Optoelectronic semiconductor chip and method of manufacturing optoelectronic semiconductor chip | |
| TW202029533A (en) | Light-emitting device and manufacturing method thereof | |
| US9991425B2 (en) | Light emitting device having wide beam angle and method of fabricating the same | |
| CN113555484B (en) | High-luminous-efficiency flip LED chip and preparation method thereof | |
| JP2013540365A (en) | Optoelectronic device and manufacturing method thereof | |
| KR20080027584A (en) | Vertical light emitting diode and method of fabricating the same | |
| KR101203138B1 (en) | Luminous device and the method therefor | |
| JP2010206133A (en) | Light emitting element, method of manufacturing the same, and electronic apparatus | |
| US20230092504A1 (en) | Light Emitting Diode and Fabrication Method Thereof | |
| KR100809508B1 (en) | Light emitting device having plane fresnel lens and fabrication method thereof | |
| CN113488569B (en) | Light-emitting diode chip with flip-chip structure and preparation method thereof | |
| CN116705935A (en) | Flip normal-pressure LED chip and preparation method thereof | |
| CN116093213A (en) | Manufacturing method of DBR flip chip | |
| TWI455377B (en) | Light emitting diode structure and fabrication method thereof | |
| KR100413435B1 (en) | Light Emitting Diode and Fabrication Method for the same | |
| US11239392B2 (en) | Optoelectronic semiconductor chip, high-voltage semiconductor chip and method for producing an optoelectronic semiconductor chip | |
| JPH0697498A (en) | Semiconductor light emitting element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |