CN116705831A - Silicon carbide floating junction power device containing columnar P channel - Google Patents

Silicon carbide floating junction power device containing columnar P channel Download PDF

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Publication number
CN116705831A
CN116705831A CN202310601313.1A CN202310601313A CN116705831A CN 116705831 A CN116705831 A CN 116705831A CN 202310601313 A CN202310601313 A CN 202310601313A CN 116705831 A CN116705831 A CN 116705831A
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silicon carbide
floating junction
power device
channel
columnar
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宋庆文
李靖域
袁昊
汤晓燕
张玉明
梁姝璇
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The application discloses a silicon carbide floating junction power device containing a columnar P channel, which at least comprises: an N-type silicon carbide substrate and an N-epitaxial layer; at least one P-type doped region is formed on the surface of the N-epitaxial layer through P-type doping; an active drift region is formed by an N-epitaxial layer between the P-type doped region and the N-type silicon carbide substrate; the active drift region is provided with a plurality of floating junctions, each floating junction is electrically connected with one P-type doped region through a plurality of columnar P-channels, and each P-type doped region is electrically connected with at least one floating junction through a plurality of columnar P-channels; both the floating junction and the columnar P channel are formed by performing ion implantation on the growing N-epitaxial layer for a plurality of times in the process of epitaxially growing the N-epitaxial layer. The application improves the switching characteristic of the silicon carbide floating junction power device, solves the problem that the silicon carbide floating junction power device is difficult to be applied to a high-frequency scene, and the reverse voltage resistance of the device is not reduced due to the introduction of a P channel.

Description

Silicon carbide floating junction power device containing columnar P channel
Technical Field
The application belongs to the field of microelectronics, and particularly relates to a silicon carbide floating junction power device comprising a columnar P channel.
Background
In recent years, the demands for energy conservation and emission reduction and low carbon development are increasing. Power semiconductor devices are an important element in the energy generation-storage-distribution cycle. The performance of the semiconductor power device is improved to become a feasible method for improving the energy conversion efficiency. Silicon carbide power semiconductor devices are expected to become the next generation mainstream high-power devices because of the high-voltage blocking capability, high-frequency switching characteristics and high-temperature working characteristics, and are widely favored by semiconductor manufacturers and researchers.
By introducing the floating junction structure into the silicon carbide floating junction power device, the advantages of the floating junction and the silicon carbide can be exerted, the one-dimensional limit of the silicon carbide unipolar device is broken, the dynamic loss of the device is reduced, and the voltage-resistant performance of the device is improved. However, since the floating junction is greatly widened toward the drift region under the reverse withstand voltage, when the bias voltage is changed from the reverse direction to the forward direction, the depletion region of the floating junction widened under the reverse bias is difficult to rapidly extract and deplete due to lack of a channel, the switching characteristics of the floating junction device are greatly affected, and the floating junction device is difficult to apply to high-frequency application.
Disclosure of Invention
In order to solve the problems in the prior art, the application provides a silicon carbide floating junction power device comprising a columnar P channel.
The technical problems to be solved by the application are realized by the following technical scheme:
a silicon carbide floating junction power device comprising a columnar P-channel, the silicon carbide floating junction power device comprising at least: an N-type silicon carbide substrate and an N-epitaxial layer;
wherein, the surface of the N-epitaxial layer is formed with at least one P-type doped region through P-type doping; an N-epitaxial layer between the P-type doped region and the N-type silicon carbide substrate forms an active drift region of the silicon carbide floating junction power device; the active drift region is internally provided with a plurality of floating junctions, each floating junction is electrically connected with one P-type doped region through a plurality of columnar P-channels, and each P-type doped region is electrically connected with at least one floating junction through a plurality of columnar P-channels; the floating junction and the columnar P channel are formed by carrying out ion implantation for a plurality of times on the growing N-epitaxial layer in the process of epitaxially growing the N-epitaxial layer.
Preferably, each floating junction is electrically connected to one P-type doped region by two columnar P-channels.
Preferably, the silicon carbide floating junction power device comprises: silicon carbide JBS diode.
Preferably, the plurality of floating junctions are arranged in parallel, the P-type doped region comprises a plurality of floating junctions, and the plurality of floating junctions are in one-to-one correspondence with the plurality of P-type doped regions.
Preferably, the silicon carbide floating junction power device comprises: silicon carbide MOSFETs.
Preferably, the silicon carbide MOSFET specifically includes:
the N-type silicon carbide substrate;
the N-epitaxial layer is overlapped on the N-type silicon carbide substrate;
the two P-type doped regions are formed by P-type doping the two side regions of the surface of the N-epitaxial layer;
the two N+ injection regions are formed by respectively carrying out N+ ion injection on the middle regions of the two P-type doped regions;
a drain electrode superimposed on the bottom surface of the N-type silicon carbide substrate;
a source electrode which is overlapped on the source region on the surface of the N-epitaxial layer;
a gate electrode which is overlapped on the gate region of the surface of the N-epitaxial layer;
the source electrode region and the gate electrode region partially cover the P-type doped region and the N+ injection region, and the source electrode region and the gate electrode region are not overlapped and are spaced at a certain distance.
Preferably, the implanted ions of the floating junction and the columnar P channel are both Al, and the Al doping concentration of the floating junction ranges from 1X 10 16 cm -3 ～1×10 19 cm -3 The Al doping concentration of the columnar P channel ranges from 1X 10 15 cm -3 ～1×10 17 cm -3 。
Preferably, the implantation energy of the floating junction ranges from 50Kev to 650Kev, and the implantation energy of the sheet-shaped P channel ranges from 10Kev to 500Kev.
Preferably, the thickness of the N-epitaxial layer is 10-70 μm.
Preferably, the thickness of the N-type silicon carbide substrate is 300-700 μm.
According to the silicon carbide floating junction power device comprising the columnar P-channel, the columnar P-channels are introduced between the floating junction and the P-type doped region, so that the floating junction and the P-type doped region are electrically connected through the columnar P-channels, and the columnar P-channels introduce a carrier extraction channel, so that the minority carrier extraction speed can be increased, the depletion region vanishing time is reduced, the overcharging voltage is reduced, the problem of opening speed when the silicon carbide floating junction power device is opened after being closed is solved, and the problem that the silicon carbide floating junction power device is difficult to be applied to a high-frequency scene due to the lack of the channel in the stretched floating junction depletion region under reverse bias in the background art is solved. In addition, the columnar P channel has a narrower width, so that the actually introduced P-type ions are not much, and the influence of the introduced P-type ions on the charge balance of the device can be reduced, so that the reverse electric field distribution of the original silicon carbide floating junction power device is hardly influenced, the reverse voltage-resistant performance of the silicon carbide floating junction power device is ensured, and the silicon carbide floating junction diode realizing high-frequency high voltage resistance is possible.
The present application will be described in further detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic diagram of a silicon carbide JBS (schottky) diode including a pillar-shaped P-channel and a floating junction provided by the inventive concept according to an embodiment of the present application;
FIG. 2 is a side view of the silicon carbide JBS diode shown in FIG. 1;
FIG. 3 is a bottom view of the silicon carbide JBS diode shown in FIG. 1;
fig. 4 is a schematic structural view of a silicon carbide MOSFET (metal-oxide semiconductor field effect transistor) including a pillar-shaped P-channel and a floating junction provided by the inventive concept according to an embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to specific examples, but embodiments of the present application are not limited thereto.
In order to solve the problems set forth in the background art, an embodiment of the present application provides a silicon carbide floating junction power device including a columnar P-channel, the silicon carbide floating junction power device at least including: an N-type silicon carbide substrate and an N-epitaxial layer.
Here, the reason why silicon carbide is selected as the substrate is that: the production technology of the silicon carbide substrate is mature, and the device quality is good; in addition, the silicon carbide substrate has higher heat conductivity and good stability, and can be applied to the high-temperature growth process; the silicon carbide substrate also has excellent physicochemical properties, and can realize high-power electronic devices with high performance.
Preferably, the thickness of the N-type silicon carbide substrate may be 300 μm to 700 μm.
The N-epitaxial layer is prepared on an N-type silicon carbide substrate by an epitaxial growth process.
Preferably, the N-epitaxial layer is made of silicon carbide and has a thickness of 10-70 μm.
Wherein, the surface of the N-epitaxial layer is formed with at least one P-type doped region by P-type doping.
Preferably, the implantation ion of the P type doping is Al, and the doping concentration range is 1 multiplied by 10 18 cm -3 ～1×10 20 cm -3 The implantation energy ranges from 10Kev to 1000Kev.
An N-epitaxial layer between the P-type doped region and the N-type silicon carbide substrate forms an active drift region of the silicon carbide floating junction power device; the active drift region is internally provided with a plurality of floating junctions, each floating junction is electrically connected with one P-type doped region through a plurality of columnar P-channels, and each P-type doped region is electrically connected with at least one floating junction through a plurality of (for example two) columnar P-channels; the floating junction and the columnar P channel are formed by carrying out ion implantation on the growing N-epitaxial layer for a plurality of times in the process of epitaxially growing the N-epitaxial layer.
Specifically, specific doping concentrations and parameters of the floating junction and the columnar P channel are determined according to a charge balance theory, so that the aims of improving the voltage withstanding characteristic and the switching characteristic of the MOSFET are fulfilled.
Preferably, the implanted ions of the floating junction and the columnar P channel are both Al; the Al doping concentration of the floating junction ranges from 1X 10 16 cm -3 ～1×10 19 cm -3 Al doping concentration of columnar P channel is 1×10 15 cm -3 ～1×10 17 cm -3 。
Preferably, the implantation energy of the floating junction ranges from 50Kev to 650Kev, and the implantation energy of the sheet-shaped P channel ranges from 10Kev to 500Kev.
In one embodiment, the silicon carbide floating junction power device including a columnar P-channel provided by the embodiment of the application may include: silicon carbide JBS diode.
Specifically, referring to fig. 1, a plurality of floating junctions 2 in an active drift region 5 of the silicon carbide JBS diode are arranged in parallel, a P-type doped region 1 includes a plurality of floating junctions 2 and P-type doped regions 1, which are vertically corresponding one by one, and an electrical connection between the floating junctions 2 and the P-type doped regions 1 is realized through a plurality of columnar P-channels 4 in the middle. In addition, the structure labeled 3 in fig. 1 is an N-type silicon carbide substrate, and the structure labeled 5 is an active drift region.
Referring to fig. 2 for a side view of the silicon carbide JBS diode shown in fig. 1, the active drift region 5 is not shown in fig. 2; referring to fig. 3, which is a bottom view of the JBS diode of fig. 1, fig. 3 is drawn through an N-type silicon carbide substrate 3.
It should be noted that fig. 1 only shows an example in which the plurality of floating junctions 2 in the active drift region are arranged in parallel in the same horizontal plane, and in practice, the plurality of floating junctions 2 in the active drift region 5 may be arranged horizontally in different planes, for example, in a step shape.
In another embodiment, the silicon carbide floating junction power device including a columnar P-channel provided by the embodiment of the present application may include: silicon carbide MOSFETs.
Specifically, referring to fig. 4, the silicon carbide MOSFET specifically includes:
an N-type silicon carbide substrate 3;
an N-epitaxial layer superimposed on the N-type silicon carbide substrate 3;
the two P-type doped regions 1 are formed by P-type doping the two side regions of the surface of the N-epitaxial layer;
two n+ implantation regions (denoted by n+ in fig. 4) formed by n+ ion implantation of the intermediate regions of the two P-type doped regions 1, respectively;
a drain electrode D which is overlapped on the bottom surface of the N-type silicon carbide substrate 3;
a source electrode S which is overlapped on the source region on the surface of the N-epitaxial layer;
a gate electrode G which is overlapped on the gate region of the surface of the N-epitaxial layer;
the source region and the gate region partially cover the P-type doped region 1 and the n+ implantation region, and the source region and the gate region do not overlap each other and are spaced apart from each other by a certain distance.
In addition, in MOSFET devices, the P-type doped region in fig. 4 is also called a P-well.
Fig. 4 is a cross-sectional view of a front view of a silicon carbide MOSFET, so that only one columnar P-channel 4 is drawn between each floating junction and the P-doped region 1 above the floating junction, and actually, a plurality of columnar P-channels 4 are arranged between each floating junction and the P-doped region 1 above the floating junction, so that the floating junction and the P-doped region 1 above the floating junction are electrically connected by using the plurality of columnar P-channels 4.
According to the silicon carbide floating junction power device comprising the columnar P-channel, the plurality of columnar P-channels are introduced between the floating junction and the P-type doped region, so that the floating junction and the P-type doped region are electrically connected through the columnar P-channels, and the columnar P-channels introduce a carrier extraction channel, so that the minority carrier extraction speed can be increased, the depletion region vanishing time is reduced, the overcharging voltage is reduced, the problem of opening speed when the silicon carbide floating junction power device is opened after being closed is solved, and the problem that the silicon carbide floating junction power device is difficult to be applied to a high-frequency scene due to the lack of the channel in the stretched floating junction depletion region under reverse bias in the background art is solved. In addition, the columnar P channel has a narrower width, so that the actually introduced P-type ions are not much, and the influence of the introduced P-type ions on the charge balance of the device can be reduced, so that the reverse electric field distribution of the original silicon carbide floating junction power device is hardly influenced, the reverse voltage resistance of the silicon carbide floating junction power device is ensured, and the silicon carbide floating junction diode realizing high-frequency high voltage resistance is possible.
The process of preparing a floating junction and a columnar P-channel during the epitaxial growth of an N-epitaxial layer is described in detail below, including the steps of:
(a) And growing a layer of N-epitaxial material on the surface of the N-type silicon carbide substrate by using a CVD (chemical vapor deposition) method, wherein the growth temperature is 1600-1900 ℃.
(b) And selecting a plurality of areas on the surface of the layer of the N-epitaxial material which is grown at present as the area where the floating junction is located.
(c) Ion implantation is carried out on the area where the floating junction is located, the implanted ions are Al, and the doping concentration range of Al is 1 multiplied by 10 16 cm -3 ～11×10 19 cm -3 The implantation energy ranges from 50Kev to 650Kev, thereby forming a plurality of floating junctions.
(d) Continuing to grow the N-epitaxial material with reference to step (a).
(e) Selecting a plurality of areas as areas where the P channels are located on the surface of a layer of N-epitaxial material which grows well at present, ensuring that the projections of the areas where the P channels are located in the vertical direction fall into the areas where the floating junctions are located, and enabling the vertical projections of at least two P channels to fall into each area where each floating junction is located;
(f) The region where the P channel is located is separatedImplanting Al with doping concentration of 1×10 15 cm -3 ～1×10 17 cm -3 The implantation energy ranges from 10Kev to 500Kev so that the P-channel makes surface contact with the floating junction directly below it.
(f) Repeating the steps (d) - (f) to continuously increase the height of the P channel and form a columnar P channel;
(e) And (3) continuing to grow a layer of N-epitaxial material according to the step (a) to obtain a grown N-epitaxial layer.
And then P doping can be carried out on the surface of the grown N-epitaxial layer, so that each P-type doped region is contacted with a plurality of columnar P-channel forming surfaces projected onto the same floating junction, and the P-type doped regions are electrically connected with the floating junction by utilizing the columnar P communication.
The implantation ion of the P-type doping is Al, and the doping concentration range is 1 multiplied by 10 18 cm -3 ～1×10 20 cm -3 The implantation energy ranges from 10Kev to 1000Kev.
In summary, the silicon carbide floating junction power device containing the columnar P channel provided by the embodiment of the application reduces the influence of the introduction of the P channel on the reverse voltage resistance of the diode while optimizing the switching performance of the diode, and breaks through the one-dimensional limit of the silicon carbide device.
The embodiment of the application can greatly widen the application range of the silicon carbide floating junction device in the future power semiconductor device field, and meanwhile, the novel structure can also be applied to a plurality of silicon carbide floating junction power device fields, so that the novel structure has great significance for the application of the future silicon carbide floating junction device in the high-temperature high-frequency environment of a power electronic device.
It should be noted that the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the disclosed embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with aspects of the present disclosure.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
Although the application is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings and the disclosure. In the description of the present application, the word "comprising" does not exclude other elements or steps, the "a" or "an" does not exclude a plurality, and the "a" or "an" means two or more, unless specifically defined otherwise. Moreover, some measures are described in mutually different embodiments, but this does not mean that these measures cannot be combined to produce a good effect.
In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.
In the present application, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present application, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
The foregoing is a further detailed description of the application in connection with the preferred embodiments, and it is not intended that the application be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the application, and these should be considered to be within the scope of the application.

Claims (10)

1. A silicon carbide floating junction power device comprising a columnar P-channel, the silicon carbide floating junction power device comprising at least: an N-type silicon carbide substrate and an N-epitaxial layer;
wherein, the surface of the N-epitaxial layer is formed with at least one P-type doped region through P-type doping; an N-epitaxial layer between the P-type doped region and the N-type silicon carbide substrate forms an active drift region of the silicon carbide floating junction power device; the active drift region is internally provided with a plurality of floating junctions, each floating junction is electrically connected with one P-type doped region through a plurality of columnar P-channels, and each P-type doped region is electrically connected with at least one floating junction through a plurality of columnar P-channels; the floating junction and the columnar P channel are formed by carrying out ion implantation for a plurality of times on the growing N-epitaxial layer in the process of epitaxially growing the N-epitaxial layer.
2. The floating junction power device of claim 1 wherein each floating junction is electrically connected to a P-type doped region by two columnar P-channels.
3. The silicon carbide floating junction power device containing a pillar P-channel of claim 1, wherein the silicon carbide floating junction power device comprises: silicon carbide JBS diode.
4. The floating junction power device of claim 3, wherein said plurality of floating junctions are arranged in parallel, said P-type doped region comprising a plurality, said plurality of floating junctions being in one-to-one correspondence with said plurality of P-type doped regions.
5. The silicon carbide floating junction power device containing a pillar P-channel of claim 1, wherein the silicon carbide floating junction power device comprises: silicon carbide MOSFETs.
6. The silicon carbide floating junction power device containing a pillar P-channel of claim 5, wherein said silicon carbide MOSFET comprises in particular:
the N-type silicon carbide substrate;
the N-epitaxial layer is overlapped on the N-type silicon carbide substrate;
the two P-type doped regions are formed by P-type doping the two side regions of the surface of the N-epitaxial layer;
the two N+ injection regions are formed by respectively carrying out N+ ion injection on the middle regions of the two P-type doped regions;
a drain electrode superimposed on the bottom surface of the N-type silicon carbide substrate;
a source electrode which is overlapped on the source region on the surface of the N-epitaxial layer;
a gate electrode which is overlapped on the gate region of the surface of the N-epitaxial layer;
the source electrode region and the gate electrode region partially cover the P-type doped region and the N+ injection region, and the source electrode region and the gate electrode region are not overlapped and are spaced at a certain distance.
7. The silicon carbide floating junction power device of claim 1 wherein said floating junction and said columnar P-channel are both implanted with ions of Al, said floating junction having an Al doping concentration in the range of 1 x 10 16 cm -3 ～1×10 19 cm -3 The Al doping concentration of the columnar P channel ranges from 1X 10 15 cm -3 ～1×10 17 cm -3 。
8. The floating junction power device of claim 7 wherein said floating junction has an implantation energy in the range of 50Kev to 650Kev and said plate-like P-channel has an implantation energy in the range of 10Kev to 500Kev.
9. The silicon carbide floating junction power device comprising a columnar P-channel of claim 1, wherein the N-epitaxial layer has a thickness of 10 μιη to 70 μιη.
10. The silicon carbide floating junction power device comprising a columnar P-channel of claim 1, wherein the N-type silicon carbide substrate has a thickness of 300 μιη to 700 μιη.
CN202310601313.1A 2023-05-25 2023-05-25 Silicon carbide floating junction power device containing columnar P channel Pending CN116705831A (en)

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