CN116705114A - Data writing method and device of memory - Google Patents

Abstract

The application discloses a data writing method and device of a memory, and belongs to the technical field of memories. The method comprises the following steps: a memory receiving controller instructs a write instruction to write data of a specified length to the memory; the memory writes data of a specified length to a storage medium of the memory based on the write instruction. Because the write instruction can specify the length of the data to be written, when the data with the specified length is required to be written, the number of write instructions required to be sent can be reduced, and the cost of the write instructions is reduced.

Description

Data writing method and device of memory

Technical Field

The present application relates to the field of storage technologies, and in particular, to a method and an apparatus for writing data into a memory.

Background

In the field of storage technology, when a controller writes data to a storage medium of a memory, the controller needs to send a write instruction and data to be written to the memory to instruct to write the data to be written to the storage medium of the memory.

Typically, the length of data to be written that the write instruction sent by the controller to the same memory can indicate is the same and is a fixed value.

However, when the same data (e.g., 0 or 1) needs to be continuously written, if the total length of the data is greater than the length of the data to be written that can be written by one write command, the controller needs to send multiple write commands and data, resulting in a large overhead for writing the data.

Disclosure of Invention

The application provides a data writing method and device of a memory. The application reduces the overhead of writing instructions. The technical scheme provided by the application is as follows:

in a first aspect, the present application provides a data writing method of a memory, the data writing method including: a memory receiving controller instructs a write instruction to write data of a specified length to the memory; the memory writes data of a specified length to a storage medium of the memory based on the write instruction.

In the data writing method of the memory, the memory receives a writing instruction of writing data with a specified length into the memory, and the memory writes the data with the specified length into a storage medium of the memory based on the writing instruction. Because the write instruction can specify the length of the data to be written, when the data with the specified length is required to be written, the number of write instructions required to be sent can be reduced, and the cost of the write instructions is reduced. In addition, because the number of write instructions to be sent is reduced, the instruction interval to be waited by the memory is shortened, and other data can be written by using the saved time, so that the write time delay of the memory is reduced, and the write bandwidth of the memory is effectively improved.

In one implementation, since the memory includes a plurality of memory arrays, the data access processes between the plurality of memory arrays do not affect each other, writing data to the memory arrays is accomplished by controlling the bit lines and word lines of the memory arrays. And each bit line corresponds to a section of address range, the address ranges corresponding to different bit lines are different, and the addresses corresponding to a plurality of bit lines connected with the same memory array form a section of address in the address range of the memory array. Each word line corresponds to a section of address range, the address ranges corresponding to different word lines are different, and the addresses corresponding to a plurality of word lines connected with the same memory array form a section of address in the address range of the memory array. And each storage array corresponds to a section of address range, the address ranges corresponding to different storage arrays are different, and the same storage array stores a section of addresses in the address range of the memory, wherein the addresses corresponding to the storage arrays form the section of addresses in the address range of the memory. Thus, the specified length is reflected by any one or more of: the total number of bit lines whose addresses need to be controlled based on the write instruction to write data, the total number of word lines whose addresses need to be controlled based on the write instruction to write data, and the total number of memory arrays whose addresses need to be controlled based on the write instruction to write data.

In one implementation, the bit lines with consecutive addresses may be a plurality of bit lines to which an electrical signal is sequentially applied when the memory is bit line scanned. Typically, a plurality of bit lines with consecutive addresses are sequentially disposed on a memory array. Similarly, the word lines having consecutive addresses may be a plurality of word lines to which electric signals are sequentially applied when the memory is subjected to the word line scanning. And a plurality of word lines with consecutive addresses are typically disposed sequentially on the memory array. The memory array with consecutive addresses may be a plurality of memory arrays to which data is sequentially written when data is required to be written to the plurality of memory arrays in the memory. And a plurality of memory arrays with consecutive addresses are typically deployed sequentially on the memory.

In one possible implementation scenario, the write instruction further indicates that a current value of a current signal used to perform a write operation indicated by the write instruction is less than a reference value, the reference value being a current value of a current signal used to perform a write operation indicated by the write instruction that is not indicative of a current value.

By the write instruction indicating that the current value of the current signal used to perform the write operation is smaller than the reference value, the power consumption of the write operation can be reduced. And, because the write operation has lower power consumption, for the memory comprising a plurality of memory arrays, the controller can concurrently access instructions to the plurality of memory arrays of the memory according to the power consumption condition of the memory, so as to perform flexible bandwidth allocation and power consumption allocation among the plurality of memory arrays, thereby meeting more application requirements.

In another possible implementation scenario, the write instruction also indicates that the specified length of data is allowed to be written in one or more periods according to the power consumption of the memory.

When the write instruction indicates that the data with the specified length is allowed to be written in a plurality of time periods according to the power consumption of the memory, the memory can select partial data in the data with the specified length to be written in each time period in the plurality of time periods according to the whole power consumption of the memory, so as to achieve the aim of reducing the whole power consumption of the memory.

In yet another possible implementation scenario, the write instruction further indicates: for any one of the storage addresses indicated by the write instruction, when the data stored in the storage address is different from the data indicated by the write instruction to be written to the storage address, the write operation is performed on the storage address based on the write instruction, and when the data stored in the storage address is the same as the data indicated by the write instruction to be written to the storage address, the write operation is not performed on the storage address.

When the data stored in the storage address is the same as the data written in the storage address by the writing instruction, the writing operation is not executed on the storage address, so that the operation time of the writing operation indicated by the writing instruction can be effectively reduced, the quick writing of the memory is realized, the instruction interval corresponding to the writing instruction can be shortened, other data can be written in by using the saved time, the writing time delay of the memory is reduced, and the writing bandwidth of the memory is improved.

Further, the data of the specified length may include a plurality of identical data. For example, when the data is represented by a binary value, the data of the specified length is data composed of a plurality of binary values 1, or the data of the specified length is data composed of a plurality of binary values 0.

At this time, by designating the length in the write instruction, it is possible to instruct writing of the data of the designated length by transmitting one write instruction, and it is unnecessary to transmit a plurality of write instructions to instruct writing, compared with the write instruction of the related art in which the length of the data to be written is the same and is a fixed value, so that the number of write instructions to be transmitted is reduced.

In a second aspect, the present application provides a data writing apparatus of a memory, the data writing apparatus comprising: the receiving module is used for receiving a write instruction of the controller for indicating to write data with specified length into the memory; and the access module is used for writing the data with the specified length into the storage medium of the memory based on the write instruction.

Optionally, the memory includes a plurality of memory arrays, the data access processes among the plurality of memory arrays do not affect each other, writing data to the memory arrays is achieved by controlling bit lines and word lines connected to the memory arrays, and the specified length is reflected by any one or more of: the total number of bit lines whose addresses need to be controlled based on the write instruction to write data, the total number of word lines whose addresses need to be controlled based on the write instruction to write data, and the total number of memory arrays whose addresses need to be controlled based on the write instruction to write data.

Optionally, the write instruction further indicates that a current value of a current signal used to perform a write operation indicated by the write instruction is smaller than a reference value, the reference value being a current value of a current signal used to perform a write operation indicated by the write instruction that does not indicate the current value.

Optionally, the write instruction further indicates that the specified length of data is allowed to be written in one or more periods according to the power consumption of the memory.

Optionally, the write instruction further indicates: for any one of the storage addresses indicated by the write instruction, when the data stored in the storage address is different from the data indicated by the write instruction to be written to the storage address, the write operation is performed on the storage address based on the write instruction, and when the data stored in the storage address is the same as the data indicated by the write instruction to be written to the storage address, the write operation is not performed on the storage address.

Alternatively, the data of the specified length is data composed of a plurality of binary values 1, or the data of the specified length is data composed of a plurality of binary values 0.

In a third aspect, the application provides a computer device comprising a memory storing program instructions and a processor executing the program instructions to perform the method provided in the first aspect of the application and any one of its possible implementations.

In a fourth aspect, the present application provides a computer readable storage medium, the computer readable storage medium being a non-volatile computer readable storage medium comprising program instructions which, when run on a computer device, cause the computer device to perform the method provided in the first aspect of the application and any one of its possible implementations.

In a fifth aspect, the application provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method provided in the first aspect of the application and any one of its possible implementations.

Drawings

Fig. 1 is a schematic diagram of an application scenario involved in a data writing method of a memory according to an embodiment of the present application;

FIG. 2 is a schematic diagram of transmitting a write command and data to be written according to an embodiment of the present application;

FIG. 3 is a schematic diagram of still another embodiment of the present application for transmitting a write command and data to be written;

FIG. 4 is a schematic diagram of a memory according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a storage component according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a memory array according to an embodiment of the present application;

FIG. 7 is a flowchart of a method for writing data into a memory according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a data writing device of a memory according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a computer device according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

Currently, in the field of storage technology, when a controller writes data to a storage medium of a memory, the controller needs to send a write instruction and data to be written to the memory to instruct to write the data to be written to the storage medium of the memory. The length of the data to be written, which can be indicated by the write command sent by the controller to the same memory, is the same and is a fixed value. Therefore, when the same data (e.g. 0 or 1) needs to be continuously written, if the total length of the data is greater than the length of the data to be written that can be written by one write command, the controller needs to send multiple write commands and data, resulting in a large overhead of writing the data. Further, since the increase of the memory write bandwidth (especially, the write bandwidth for continuously writing to the same memory array) is restricted by the instruction interval (time write to write, tW 2W), when a large number of instructions need to be transmitted, the execution interval to wait is long, and the write bandwidth of the memory is affected. Wherein the memory comprises one or more memory arrays (banks), and the data access processes among the memory arrays are not mutually influenced.

The embodiment of the application provides a data writing method of a memory. The method comprises the following steps: the memory receives a write instruction that the controller instructs to write data of a specified length to the memory, and the memory writes the data of the specified length to a storage medium of the memory based on the write instruction. Because the write instruction can specify the length of the data to be written, when the data with the specified length is required to be written, the number of write instructions required to be sent can be reduced, and the cost of the write instructions is reduced. In addition, because the number of write instructions to be sent is reduced, the instruction interval to be waited by the memory is shortened, and other data can be written by using the saved time, so that the write time delay of the memory is reduced, and the write bandwidth of the memory is effectively improved.

Fig. 1 is a schematic structural diagram of an implementation environment related to a data writing method of a memory according to an embodiment of the present application. As shown in fig. 1, the implementation environment includes: a processor 01 and a memory system 02. Alternatively, the memory system 02 may be a memory chip. Also, the storage system 02 includes a controller 021 and a memory 022. A communication connection is established between the processor 01 and the controller 021, and a communication connection is established between the controller 021 and the memory 022. The processor 01 is configured to indicate a write request to the controller 021, i.e. notify the controller 021 of a logical address of data to be written that needs to be written. The controller 021 is used for determining a physical address for writing data to be written according to an instruction of the processor 01, and sending a write instruction to the memory 022 according to the physical address and the data to be written. The memory 022 is used for writing data to be written into a corresponding physical address according to a writing instruction.

Alternatively, the processor 01 may be a hardware chip, which may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), general-purpose array logic (generic array logic, GAL), or any combination thereof. Alternatively, the processor 01 may be a general purpose processor, such as a central processing unit (central processing unit, CPU), a network processor (network processor, NP), or a combination of CPU and NP.

The memory 022 may be a nonvolatile memory (NVM) such as a phase change memory (phase change memory, PCM), spin transfer torque memory (shared transistor technology random access memory, STT-RAM), and a resistive random-access memory (RRAM). The embodiment of the application is described taking the memory 022 as a phase change memory as an example. The phase change memory is a novel nonvolatile semiconductor memory based on a chalcogenide compound. The memory 022 includes a plurality of memory cells. The storage medium of each memory cell is implemented using a phase change material, which stores 0/1 bit information using a difference in electrical characteristics of crystalline and amorphous states of the phase change material. Wherein the high-resistance amorphous state is defined as a write 0 state (i.e., RESET (0) state), and the low-resistance crystalline state is defined as a write 1 state (i.e., SET (1) state, also referred to as erase 1 state). The write 0 state is obtained by performing a write operation to the memory cell. The write operation is performed by applying a high amplitude and narrow width electrical pulse to the memory cell. Under the action of this electric pulse, the temperature of the phase change material is rapidly raised above the melting temperature and then quenched, and the phase change material remains in a highly resistive amorphous state because the microscopic atoms of the phase change material do not have sufficient time to crystallize during the process. The erase 1 state is obtained by performing an erase operation on the memory cell. The erase operation is accomplished by applying an electrical pulse to the memory cell that is of a lower amplitude than the electrical pulse of the write operation, but of a relatively longer duration. Under the action of this electric pulse, the temperature of the phase change material is raised to a temperature below the melting temperature above the crystallization temperature, during which the phase change material can be transformed into a low-resistance state by a thermally induced crystallization process. The read operation of phase change memory 022 is accomplished by applying an electrical pulse to the memory cell that is lower in amplitude than both the electrical pulse of the write operation and the electrical pulse of the erase operation. Under the action of the electric pulse, the resistance information of the phase change material is sensed by the reading circuit in the form of current or voltage, so that the reading operation of the memory cell is realized. Since both the write operation and the erase operation write data to the memory cell, the write operation in the embodiment of the present application does not distinguish between the write operation and the erase operation.

In an embodiment of the present application, the memory 022 may be used as a memory for temporarily storing data required for the operation of the processor 01. Accordingly, the controller 021 may be a memory controller. And an application scenario of the data writing method of the memory 022 provided by the embodiment of the application may be: the processor 01 generates operational data during operation, which is required to be stored in the memory. In this application scenario, the cooperative process between the processor 01, the controller 021 and the memory includes: the processor 01 indicates to the controller 021 that the operation data needs to be stored, the controller 021 obtains the operation data, determines a storage address for storing the operation data in a storage space of the memory, then sends a write instruction and the operation data to the memory according to the operation data and the storage address, and the memory stores the operation data on the corresponding storage address according to the write instruction.

Wherein the write command and the data to be written may be sent through different ports. For example, when it is necessary to send a write instruction and operation data to a memory, as shown in fig. 2 and 3, the write instruction may be sent to the memory by using the port 1, and the operation data may be sent to the memory by using the port 2. And, the write instruction may include the write instruction itself for indicating the write operation and a storage address for storing the data to be written. In one implementation, the write instruction itself and the memory address may be sent to memory through the same port. For example, as shown in FIG. 2, port 1 may be used to send the write instruction itself and the memory address to memory. Alternatively, the write instruction itself and the memory address may be sent to the memory through different ports. For example, as shown in fig. 3, the port 1 may be used to send a write command itself to the memory, and the port 3 may be used to send a memory address to the memory.

In one implementation, as shown in fig. 4, memory 022 includes: a storage component 0221, a driving circuit 0222, a control component 0223, and an input/output (I/O) port 0224. The implementation procedure of the data writing method of the memory 022 provided by the embodiment of the application can be cooperatively implemented through the control component 0223, the driving circuit 0222, the storage component 0221 and the I/O port 0224. Wherein the control component 0223 is configured to determine control parameters required for performing the access operation indicated by the write instruction, and instruct the drive circuit 0222 to supply the drive signal to the storage component 0221 in accordance with the control parameters. The storage component 0221 is used for writing data under the drive of a drive signal.

As shown in fig. 5, the storage component 0221 includes one or more storage arrays (banks) 0221a, and the data access processes among the plurality of storage arrays 0221a are not mutually influenced, that is, each storage array 0221a can independently or parallelly accept read-write instructions and complete corresponding operations. Each memory array 0221a includes a plurality of memory cells a1. Each memory cell a1 is connected to a Word Line (WL) and a Bit Line (BL), and at least one of the word line and the bit line to which a different memory cell a1 is connected is different. The read/write operation for the different memory cells a1 can be performed by applying an electrical signal to the word line and the bit line connected to the corresponding memory cell a1. And when at least one of the word line and the bit line to which the electric signal is applied during the read-write operation is different, the memory cell a1 to which the read-write operation is applied is different. For example, as shown in fig. 6, a plurality of bit lines BL and a plurality of word lines WL are arranged in a crisscross manner on the memory array 0221a, the plurality of word lines WL are arranged in sequence in a column direction, each word line WL extends in a row direction, the plurality of bit lines BL are arranged in sequence in the row direction, and each bit line BL extends in the column direction. Each memory cell a1 is connected to one bit line BL and one word line WL, respectively, and at least one of the word line WL and the bit line BL connected to the different memory cells a1 is different.

In one implementation, as shown in FIG. 6, memory cell a1 includes a variable resistor R and a gating device T in series. The variable resistor R serves as a storage medium of the memory cell a1 for storing information. And, the manufacturing material of the variable resistor R includes a phase change material. One end of the variable resistor R is connected with the bit line BL, the other end of the variable resistor R is connected with the first port of the gating device T, and the word line WL is connected with the second port of the gating device T. The voltage difference between the word line WL and the bit line BL determines the turn-on and turn-off of the loop between the bit line and the word line, e.g., the loop between the word line WL and the bit line BL is turned on when the voltage difference between them is greater than a certain threshold voltage. When the loop between the bit line and the word line is turned on, the electric signal applied to the bit line BL can be transmitted to the variable resistor R, and the data writing and reading of the variable resistor R can be realized under the control of the electric signal.

It should be understood that the foregoing is an exemplary description of an application scenario of the data writing method of the memory provided by the embodiment of the present application, and does not constitute a limitation on the application scenario of the event analysis method, and those skilled in the art can know that, as the service requirement changes, the application scenario can be adjusted according to the application requirement, which is not specifically recited in the embodiment of the present application.

The implementation process of the data writing method of the memory provided in the embodiment of the present application is described below by taking the application scenario shown in fig. 1 as an example. As shown in fig. 7, the implementation process of the data writing method of the memory may include the following steps:

step 701, the memory receiving controller instructs to write a write instruction of data of a specified length into the memory.

In accordance with the foregoing, a memory system includes a controller and a memory, the controller configured to send a write command to the memory. For example, when the memory is used as the memory, the processor is configured to indicate to the controller that the operation data needs to be stored, after the controller obtains the operation data, a storage address for storing the operation data may be determined in a storage space of the memory, and then a write instruction and the operation data are sent to the memory according to the operation data and the storage address, so that the memory stores the operation data on a corresponding storage address according to the write instruction.

Since the memory includes a plurality of memory arrays, the data access processes between the plurality of memory arrays do not affect each other, and writing data to the memory arrays is performed by controlling bit lines and word lines of the memory arrays. And each bit line corresponds to a section of address range, the address ranges corresponding to different bit lines are different, and the addresses corresponding to a plurality of bit lines connected with the same memory array form a section of address in the address range of the memory array. Each word line corresponds to a section of address range, the address ranges corresponding to different word lines are different, and the addresses corresponding to a plurality of word lines connected with the same memory array form a section of address in the address range of the memory array. And each storage array corresponds to a section of address range, the address ranges corresponding to different storage arrays are different, and the same storage array stores a section of addresses in the address range of the memory, wherein the addresses corresponding to the storage arrays form the section of addresses in the address range of the memory. Thus, the specified length may be reflected by any one or more of the following: the total number of bit lines whose addresses need to be controlled based on the write instruction to write data, the total number of word lines whose addresses need to be controlled based on the write instruction to write data, and the total number of memory arrays whose addresses need to be controlled based on the write instruction to write data.

In one implementation, the bit lines with consecutive addresses may be a plurality of bit lines to which an electrical signal is sequentially applied when the memory is bit line scanned. Typically, a plurality of bit lines with consecutive addresses are sequentially disposed on a memory array. Also, for every two adjacent bit lines, the head address of the next bit line may be equal to the maximum address +1 of the previous bit line. For example, as shown in fig. 6, the bit lines BL (1), BL (2) and BL (3) on the memory array are bit lines arranged in succession, and when the memory is scanned for a bit line, an electric signal is sequentially applied to the bit lines BL (1), BL (2) and BL (3), so that the bit lines BL (1), BL (2) and BL (3) are bit lines with consecutive addresses.

In one implementation, the word lines with consecutive addresses may be a plurality of word lines to which electrical signals are sequentially applied when the memory is scanned. Typically, a plurality of word lines with consecutive addresses are sequentially disposed on a memory array. Also, for every two adjacent word lines, the first address of the next word line may be equal to the maximum address +1 of the previous word line. For example, as shown in fig. 6, the word lines WL (1), WL (2), and WL (3) on the memory array are word lines arranged in succession, and when the memory is scanned, an electric signal is sequentially applied to the word lines WL (1), WL (2), and WL (3), so that the word lines WL (1), WL (2), and WL (3) are word lines with continuous addresses.

In one implementation, the memory array with consecutive addresses may be a plurality of memory arrays that are sequentially written with data when it is desired to sequentially write data to the plurality of memory arrays in the memory. Typically, a plurality of memory arrays with consecutive addresses are sequentially deployed on a memory. Also, for each two adjacent memory arrays of logical addresses, the head address of the next memory array may be equal to the maximum address +1 of the previous memory array. For example, as shown in fig. 5, when the memory 0221 includes a plurality of memory arrays 0221a arranged in sequence and data is written continuously to the plurality of memory arrays 0221a in the memory 0221, data is written sequentially to the memory arrays 0221a (1) and the memory arrays 0221a (2), and therefore the memory arrays 0221a (1) and 0221a (2) are memory arrays having continuous addresses.

In an embodiment of the present application, the data of the specified length may include a plurality of identical data. For example, when the data is represented by a binary value, the data of the specified length may be data composed of a plurality of binary values 1, or the data of the specified length may be data composed of a plurality of binary values 0. At this time, by designating the length in the write instruction, it is possible to instruct writing of the data of the designated length by transmitting one write instruction, and it is unnecessary to transmit a plurality of write instructions to instruct writing, compared with the write instruction of the related art in which the length of the data to be written is the same and is a fixed value, so that the number of write instructions to be transmitted is reduced.

In one implementation, the write instruction may also indicate that a write operation indicated by the write instruction is performed using a current signal having a current value less than the reference value. Wherein the reference value is a current value of a current signal used to perform a write operation indicated by a write instruction that does not indicate a current value. When writing operation is performed to a certain memory cell, a current pulse signal is required to be applied to a bit line connected with the memory cell, and a gating enable voltage signal is required to be applied to a word line connected with the memory cell, so that the electrical characteristics of a storage medium of the memory cell change under the action of the signal, and information can be stored through the changed electrical characteristics. Therefore, when the write command does not indicate a current value, the current values of the current pulse signals applied to the bit lines connected to all the memory cells in the same memory array may be the same, and the current value is the reference value. When the write command indicates that the current value of the current signal used to perform the write operation indicated by the write command is smaller than the reference value, it is equivalent to the write command indicating that the write operation is performed using a smaller current or transient operation current. In one implementation, performing the write operation using a smaller current or transient operating current may be accomplished by reducing the number of bits that the write operation operates at the same time.

By the write instruction indicating that the current value of the current signal used to perform the write operation is smaller than the reference value, the power consumption of the write operation can be reduced. And, because the write operation has lower power consumption, for the memory comprising a plurality of memory arrays, the controller can concurrently access instructions to the plurality of memory arrays of the memory according to the power consumption condition of the memory, so as to perform flexible bandwidth allocation and power consumption allocation among the plurality of memory arrays, thereby meeting more application requirements. Since the write instruction indicates that performing a write operation using a smaller current or transient operation current can reduce the power consumption of the write operation, the write instruction may also be referred to as a low power write instruction.

In another implementation, the write instruction may also indicate that the specified length of data is allowed to be written in one or more periods of time according to the power consumption of the memory. Wherein the power consumption of the memory comprises a sum of power consumption of a plurality of memory arrays in the memory. When the write instruction indicates that the data with the specified length is allowed to be written in a plurality of time periods according to the power consumption of the memory, the memory can select partial data in the data with the specified length to be written in each time period in the plurality of time periods according to the whole power consumption of the memory, so as to achieve the aim of reducing the whole power consumption of the memory. Since writing data as instructed by the write instruction can also reduce the power consumption of the memory, the write instruction can also be referred to as a low-power-consumption write instruction.

In yet another implementation, the write instruction may further indicate: for any storage address indicated by the write instruction, when the data stored in the storage address is different from the data indicated by the write instruction to be written into the storage address, writing operation is performed on the storage address based on the write instruction, and when the data stored in the storage address is the same as the data indicated by the write instruction to be written into the storage address, writing operation is not performed on the storage address. For example, assume that data already stored at a certain memory address are all 1, and the write instruction indicates that when the data already stored at the memory address is different from the data that the write instruction indicates to write to the memory address, a write operation is performed on the memory address based on the write instruction, and when the data already stored at the memory address is the same as the data that the write instruction indicates to write to the memory address, no write operation is performed on the memory address. Then, when the write operation indicated by the write instruction is performed, when the data of the bit to be written to the memory address is 0, the data stored in the bit needs to be refreshed to 0, and when the data of the bit to be written to the memory address is 1, no operation is performed on the bit. Since no operation is performed on the bit at this time, fast writing to the memory can be achieved.

When the data stored in the storage address is the same as the data written in the storage address by the writing instruction, the writing operation is not executed on the storage address, so that the operation time of the writing operation indicated by the writing instruction can be effectively reduced, the quick writing of the memory is realized, the instruction interval corresponding to the writing instruction can be shortened, other data can be written in by using the saved time, the writing time delay of the memory is reduced, and the writing bandwidth of the memory is improved. Since the write instruction can reduce the operation time for performing the write operation, the write instruction may be referred to as a fast write instruction.

Corresponding to the fast write instruction, one possible application scenario may be: before writing operation is performed on the continuous addresses of the memory, the controller instructs the memory to write all the continuous addresses to a unified value in advance, so that when the memory performs writing operation according to a subsequently received writing instruction, only bits, which are different from the data indicated by the writing instruction, of the data stored in the continuous addresses are required to be operated. For example, during a certain memory array idle period of the memory, the controller may control the memory to write bits of consecutive addresses of a specified length of the memory array to a uniform value by a write instruction or a low power write instruction that instructs to write the specified length of data, so that when the controller receives an urgent data write request, a fast write instruction can be used to perform a write operation in the consecutive addresses. The unified value may be set according to the performance of the memory, for example, when the write 0 speed of the memory is fast and the write 1 speed is slow, the unified value may be 1.

In addition, the write instruction may also directly specify the data to be written, such as specifying a write binary value of 1 or 0. The write command is used for indicating to write the binary number value 1 with the specified length or writing the binary number value 0 with the specified length, so that data to be written do not need to be transmitted through a data bus, and the power consumption of data transmission can be reduced. In this case, the write instruction may be referred to as a write 1 instruction or a write 0 instruction, or may be referred to as an instruction to write a specified length 0 or an instruction to write a specified length 1. Similarly, the low power write instruction may also be referred to as a low power write 1 instruction or a low power write 0 instruction, or may also be referred to as a low power write length 0 instruction or a low power write length 1 instruction. The above-described fast write instruction may also be referred to as a fast write 1 instruction or a fast write 0 instruction, or may also be referred to as a fast write instruction specifying length 0 or a fast write instruction specifying length 1.

Step 702, the memory writes data of a specified length to a storage medium of the memory based on the write instruction.

After the memory receives the write command sent by the controller, the write operation can be executed according to the write command, and the data to be written can be written on the storage medium of the memory. When the contents of the write operation instruction are different, the implementation manner of executing the write operation is slightly different, and the implementation manner of executing the corresponding write operation will be described in various cases for various implementations of the write instruction in step 701.

In the first case, when the designated length of the write instruction is reflected based on the total number of the bit lines whose addresses to be controlled by the write instruction to write data are consecutive, the memory may find the first memory address indicated by the write instruction in order according to the hierarchy of the memory array, the word line, and the bit line according to the write instruction, then perform the write operation on the first memory address, then add one to the address of the bit line, find the second memory address indicated by the write instruction, then perform the write operation on the second memory address, and so on to perform the traversal according to the hierarchy of the bit line, the word line, and the memory array and perform the write operation until the write operation indicated by the write instruction is completed.

In the second case, when the designated length of the write instruction is reflected based on the total number of the word lines whose addresses to be controlled by the write instruction to write data are consecutive, the memory may find the first memory address indicated by the write instruction in order according to the hierarchy of the memory array, the word line, and the bit line according to the write instruction, then perform the write operation on the first memory address, then add one to the address of the word line, find the second memory address indicated by the write instruction, then perform the write operation on the second memory address, and so on to perform the traversal according to the hierarchy of the word line, the bit line, and the memory array and perform the write operation until the write operation indicated by the write instruction is completed.

In the third case, when the specified length of the write instruction is reflected based on the total number of the memory arrays whose addresses to be controlled by the write instruction to write data are consecutive, the memory may find the first memory address indicated by the write instruction in order according to the hierarchy of the memory array, the bit line and the word line according to the write instruction, then perform the write operation on the first memory address, then add one to the address of the memory array, find the second memory address indicated by the write instruction, then perform the write operation on the second memory address, and so on to perform the traversal according to the hierarchy of the memory array, the bit line and the word line and perform the write operation until the write operation indicated by the write instruction is completed. For example, arrow b1 in fig. 5 is the direction in which the memory address of memory array 0021a increases, arrow b2 in fig. 6 is the direction in which bit line BL on memory array 0221a is scanned, i.e., the direction in which the memory address of bit line BL increases, and arrow b3 in fig. 6 is the direction in which word line WL on memory array 0221a is scanned, i.e., the direction in which the memory address of word line WL increases, then the memory array, bit line, and word line may be traversed in that order.

In the fourth case, when the data of the specified length in the write instruction includes a plurality of identical data, the memory may directly refresh bits of the storage address of the specified length indicated by the write instruction into the identical data according to the write instruction in the course of executing the write operation indicated by the write instruction.

In the fifth case, when the write instruction also instructs the write operation instructed by the write instruction to be performed using a current signal having a current value smaller than the reference value, the memory may apply a current pulse signal to the bit line to which the memory cell indicated by the write instruction is connected and a current value smaller than the reference value, and apply a gate enable voltage signal to the word line to which the memory cell is connected, in the course of performing the write operation instructed by the write instruction, to complete the write operation instructed by the write instruction.

In the sixth case, when the write instruction also indicates that the data of the specified length is allowed to be written in one or more periods according to the power consumption of the memory, the memory can predict the overall power consumption of the memory in the course of executing the write operation indicated by the write instruction, and write the data indicated by the write instruction in one or more periods lower in the overall power consumption of the memory, thereby achieving the purpose of reducing the overall power consumption of the memory.

In the seventh case, when the write instruction is the above-described fast write instruction, the memory may perform the write operation on the memory address based on the write instruction when the data stored in the memory address is different from the data indicated by the write instruction to be written to the memory address, and may not perform the write operation on the memory address when the data stored in the memory address is the same as the data indicated by the write instruction to be written to the memory address, for any memory address indicated by the write instruction in the process of performing the write operation indicated by the write instruction.

It should be noted that, in the actual application process of the memory, the write instruction may be a combination of some or all of the above multiple implementations, and when the write instruction is a combination of the above multiple implementations, the memory may execute the write operation according to the combination of the write instruction implementations, and the write operation is comprehensively executed by using the situation corresponding to the write instruction implementation in the above situations, which is not described herein.

Step 703, the memory feeds back a write response to the write instruction to the controller.

After the memory responds to the write instruction, the write response to the write instruction may be fed back to the controller to feed back to the controller whether the write operation indicated by the write instruction is completed. It should be noted that, the memory may not feed back the write response to the controller, and the controller may determine the execution result of the write instruction in other manners. For example, an instruction latency may be defined that determines that a write operation is not completed when feedback from the memory is not received within a specified period of time after the controller sends a write instruction.

In summary, in the method for writing data into a memory according to the embodiment of the present application, the memory receives a write command indicating to write data of a specified length into the memory, and the memory writes data of the specified length into the storage medium of the memory based on the write command. Because the write instruction can specify the length of the data to be written, when the data with the specified length is required to be written, the number of write instructions required to be sent can be reduced, and the cost of the write instructions is reduced. In addition, because the number of write instructions to be sent is reduced, the instruction interval to be waited by the memory is shortened, and other data can be written by using the saved time, so that the write time delay of the memory is reduced, and the write bandwidth of the memory is effectively improved.

It should be noted that, the sequence of the steps of the data writing method of the memory provided by the embodiment of the application can be properly adjusted, and the steps can be correspondingly increased or decreased according to the situation. Any method that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered in the protection scope of the present application, and thus will not be repeated.

The embodiment of the application also provides a data writing device of the memory. As shown in fig. 8, the data writing device 80 of the memory includes:

a receiving module 801, configured to receive a write instruction that instructs a controller to write data of a specified length to a memory.

An access module 802 for writing data of a specified length to a storage medium of the memory based on the write instruction.

Optionally, the memory includes a plurality of memory arrays, the data access processes among the plurality of memory arrays do not affect each other, writing data to the memory arrays is achieved by controlling bit lines and word lines connected to the memory arrays, and the specified length is reflected by any one or more of: the total number of bit lines whose addresses need to be controlled based on the write instruction to write data, the total number of word lines whose addresses need to be controlled based on the write instruction to write data, and the total number of memory arrays whose addresses need to be controlled based on the write instruction to write data.

Optionally, the write instruction further indicates that a current value of a current signal used to perform a write operation indicated by the write instruction is smaller than a reference value, the reference value being a current value of a current signal used to perform a write operation indicated by the write instruction that does not indicate the current value.

Optionally, the write instruction further indicates that the specified length of data is allowed to be written in one or more periods according to the power consumption of the memory.

Optionally, the write instruction further indicates: for any one of the storage addresses indicated by the write instruction, when the data stored in the storage address is different from the data indicated by the write instruction to be written to the storage address, the write operation is performed on the storage address based on the write instruction, and when the data stored in the storage address is the same as the data indicated by the write instruction to be written to the storage address, the write operation is not performed on the storage address.

Alternatively, the data of the specified length is data composed of a plurality of binary values 1, or the data of the specified length is data composed of a plurality of binary values 0.

In summary, in the data writing device of the memory provided in the embodiment of the application, the receiving module receives the write command of the controller for writing the data with the specified length into the memory, and the writing module writes the data with the specified length into the storage medium of the memory based on the write command. Because the write instruction can specify the length of the data to be written, when the data with the specified length is required to be written, the number of write instructions required to be sent can be reduced, and the cost of the write instructions is reduced. In addition, because the number of write instructions to be sent is reduced, the instruction interval to be waited by the memory is shortened, and other data can be written by using the saved time, so that the write time delay of the memory is reduced, and the write bandwidth of the memory is effectively improved.

It will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working process of the apparatus and modules described above may refer to the corresponding content in the foregoing method embodiment, which is not described herein again.

The embodiment of the application provides computer equipment. The storage system shown in fig. 1 may be deployed in the computing device. The computer device includes a memory storing program instructions and a processor executing the program instructions to perform the data writing method of the memory provided by the present application or to perform any step of the data writing method of the memory provided by the present application.

Fig. 9 is a schematic structural diagram of a computer device 90 according to an embodiment of the present application. As shown in fig. 9, the computer device 90 includes a memory 901, a processor 902, a communication interface 903, and a bus 904. The memory 901, the processor 902, and the communication interface 903 are communicatively connected to each other via a bus 904. Also, the computer device 90 may include a plurality of processors 902 to facilitate the implementation of the functions of the different functional modules described above by different processors.

The memory 901 may be a Read Only Memory (ROM), a static storage device, a dynamic storage device, or a random access memory (random access memory, RAM). The memory 901 may store an executable code sequence, and when the executable code stored in the memory 901 is executed by the processor 902, the processor 902 and the communication interface 903 are used to perform the data writing method of the memory provided by the embodiment of the present application. The memory 901 may also include software modules and data necessary for other running processes, such as an operating system.

The processor 902 may employ a general-purpose central processing unit (central processing unit, CPU), microprocessor, application specific integrated circuit (application specific integrated circuit, ASIC), graphics processor (graphics processing unit, GPU) or one or more integrated circuits.

The processor 902 may also be an integrated circuit chip with signal processing capabilities. In implementation, some or all of the functions of the data writing method of the memory of the present application may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 902. The processor 902 described above may also be a general purpose processor, a digital signal processor (digital signal processing, DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (field programmable gate array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be embodied directly in the execution of a hardware decoding processor, or in the execution of a combination of hardware and software modules in a decoding processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in the memory 901, and the processor 902 reads information in the memory 901, and combines with hardware to implement the data writing method of the memory according to the embodiment of the application.

The communication interface 903 enables communication between the computer device 90 and other devices or communication networks using a transceiver module such as, but not limited to, a transceiver. For example, the communication interface 903 may be any one or any combination of the following devices: network interfaces (e.g., ethernet interfaces), wireless network cards, and the like having network access functionality.

The bus 904 may include a path for transferring information between various components of the computer device 90 (e.g., the memory 901, the processor 902, the communication interface 903).

It should be noted that, when the computer device is a client, the computer device further includes a display screen, where the display screen is used to display a graphical user interface of the program development platform.

The descriptions of the processes corresponding to the drawings have emphasis, and the descriptions of other processes may be referred to for the parts of a certain process that are not described in detail.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product providing the program development platform includes one or more computer instructions that, when loaded and executed on a computer device, implement, in whole or in part, the processes or functions of the data writing method of the memory provided by the embodiments of the present application.

The computer device may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital subscriber line, or wireless (e.g., infrared, wireless, microwave, etc.) means from one website, computer, server, or data center.

The embodiment of the application also provides a computer readable storage medium, which is a nonvolatile computer readable storage medium, and the computer readable storage medium comprises program instructions, when the program instructions run on a computer device, the computer device is caused to execute the data writing method of the memory provided by the embodiment of the application.

The embodiment of the application also provides a computer program product containing instructions, which when run on a computer, cause the computer to execute the data writing method of the memory provided by the embodiment of the application.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, where the program may be stored in a computer readable storage medium, and the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

It should be noted that, the information (including but not limited to user equipment information, user personal information, etc.), data (including but not limited to data for analysis, stored data, presented data, etc.), and signals related to the present application are all authorized by the user or are fully authorized by the parties, and the collection, use, and processing of the related data is required to comply with the relevant laws and regulations and standards of the relevant countries and regions. For example, the resistance information related to the application is obtained under the condition of full authorization.

In embodiments of the present application, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The term "at least one" means one or more, the term "plurality" means two or more, unless expressly defined otherwise.

The term "and/or" in the present application is merely an association relation describing the association object, and indicates that three kinds of relations may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

The foregoing description of the preferred embodiments of the present application is not intended to limit the application, but is intended to cover any modifications, equivalents, alternatives, and improvements within the spirit and principles of the application.

Claims (15)

1. A method of writing data to a memory, the method comprising:

a memory receiving controller instructs a write instruction to write data of a specified length to the memory;

the memory writes the data of the specified length to a storage medium of the memory based on the write instruction.

2. The method of claim 1, wherein the memory comprises a plurality of memory arrays, the data access processes between the plurality of memory arrays do not affect each other, writing data to the memory arrays is achieved by controlling bit lines and word lines connected to the memory arrays, and the specified length is reflected by any one or more of: the method includes writing data based on the write instruction, writing the total number of address-consecutive bit lines that the data needs to control based on the write instruction, writing the total number of address-consecutive word lines that the data needs to control based on the write instruction, and writing the total number of address-consecutive storage arrays of the data based on the write instruction.

3. The method according to claim 1 or 2, wherein the write instruction further indicates that a current value of a current signal used to perform a write operation indicated by the write instruction is smaller than a reference value, the reference value being a current value of a current signal used to perform a write operation indicated by a write instruction that does not indicate a current value.

4. A method according to any one of claims 1 to 3, wherein the write instruction further indicates that the specified length of data is allowed to be written in one or more periods in accordance with the power consumption of the memory.

5. The method of any of claims 1 to 4, wherein the write instruction further indicates: for any storage address indicated by the write instruction, when the data stored in the storage address is different from the data indicated by the write instruction to be written into the storage address, writing operation is performed on the storage address based on the write instruction, and when the data stored in the storage address is the same as the data indicated by the write instruction to be written into the storage address, writing operation is not performed on the storage address.

6. The method according to any one of claims 1 to 5, wherein the data of the specified length is data composed of a plurality of binary values 1, or the data of the specified length is data composed of a plurality of binary values 0.

7. A data writing device of a memory, the device comprising:

the receiving module is used for receiving a write instruction of the controller for indicating to write data with specified length into the memory;

and the access module is used for writing the data with the specified length into the storage medium of the memory based on the write instruction.

8. The apparatus of claim 7, wherein the memory comprises a plurality of memory arrays, the data access processes between the plurality of memory arrays do not affect each other, writing data to the memory arrays is achieved by controlling bit lines and word lines connected to the memory arrays, and the specified length is reflected by any one or more of: the method includes writing data based on the write instruction, writing the total number of address-consecutive bit lines that the data needs to control based on the write instruction, writing the total number of address-consecutive word lines that the data needs to control based on the write instruction, and writing the total number of address-consecutive storage arrays of the data based on the write instruction.

9. The apparatus according to claim 7 or 8, wherein the write instruction further instructs a current value of a current signal used for performing a write operation instructed by the write instruction to be smaller than a reference value, the reference value being a current value of a current signal used for performing a write operation instructed by a write instruction not to be instructed by the current value.

10. The apparatus of any of claims 7 to 9, wherein the write instruction further indicates that the specified length of data is allowed to be written in one or more periods of time based on power consumption of the memory.

11. The apparatus of any of claims 7 to 10, wherein the write instruction further instructs: for any storage address indicated by the write instruction, when the data stored in the storage address is different from the data indicated by the write instruction to be written into the storage address, writing operation is performed on the storage address based on the write instruction, and when the data stored in the storage address is the same as the data indicated by the write instruction to be written into the storage address, writing operation is not performed on the storage address.

12. The apparatus according to any one of claims 7 to 11, wherein the data of the specified length is data composed of a plurality of binary values 1, or the data of the specified length is data composed of a plurality of binary values 0.

13. A computer device comprising a memory storing program instructions and a processor executing the program instructions to perform the method of any one of claims 1 to 6.

14. A computer readable storage medium comprising program instructions which, when run on a computer device, cause the computer device to perform the method of any of claims 1 to 6.

15. A computer program product, characterized in that the computer program product, when run on a computer, causes the computer to perform the method according to any of claims 1 to 6.