CN116705114A - Memory data writing method and device - Google Patents
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- G—PHYSICS
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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Abstract
本申请公开了一种存储器的数据写入方法及装置,属于存储器技术领域。该方法包括:存储器接收控制器指示向存储器写入指定长度的数据的写指令;存储器基于写指令向存储器的存储介质写入指定长度的数据。由于写指令能够指定待写入数据的长度,使得在需要写入指定长度的数据时,能够减少需要发送的写指令的条数,减小了写指令的开销。
The application discloses a method and device for writing data into a memory, belonging to the technical field of memory. The method includes: the memory receives a write instruction from the controller indicating to write data of a specified length into the memory; and the memory writes the data of the specified length to a storage medium of the memory based on the write instruction. Since the write command can specify the length of the data to be written, when the data of the specified length needs to be written, the number of write commands to be sent can be reduced, reducing the overhead of the write command.
Description
技术领域technical field
本申请涉及存储技术领域,特别涉及一种存储器的数据写入方法及装置。The present application relates to the technical field of storage, and in particular to a method and device for writing data into a storage.
背景技术Background technique
在存储技术领域中,控制器在向存储器的存储介质写入数据时,控制器需要向存储器发送写指令和待写入数据,以指示向存储器的存储介质写入该待写入数据。In the field of storage technology, when the controller writes data to the storage medium of the memory, the controller needs to send a write instruction and the data to be written to the memory, so as to instruct writing the data to be written into the storage medium of the memory.
通常地,控制器向同一存储器发送的写指令能够指示的待写入数据的长度相同且为固定值。Generally, the length of the data to be written that can be indicated by the write command sent by the controller to the same memory is the same and a fixed value.
但是,当需要连续写入同一数据(例如0或者1)时,若该数据的总长度大于一条写指令能够写入的待写入数据的长度,控制器需要发送多条写指令和数据,导致写数据的开销较大。However, when the same data (such as 0 or 1) needs to be written continuously, if the total length of the data is greater than the length of the data to be written that can be written by one write command, the controller needs to send multiple write commands and data, resulting in Writing data is expensive.
发明内容Contents of the invention
本申请提供了一种存储器的数据写入方法及装置。本申请减小了写指令的开销。本申请提供的技术方案如下:The present application provides a data writing method and device for a memory. The present application reduces the overhead of writing instructions. The technical scheme that this application provides is as follows:
第一方面,本申请提供了一种存储器的数据写入方法,该数据写入方法包括:存储器接收控制器指示向存储器写入指定长度的数据的写指令;存储器基于写指令向存储器的存储介质写入指定长度的数据。In a first aspect, the present application provides a data writing method of a memory, the data writing method includes: the memory receives a write instruction from the controller indicating to write data of a specified length to the memory; the memory writes data to the storage medium of the memory based on the write instruction Write data of the specified length.
在本申请提供的存储器的数据写入方法中,存储器接收控制器指示向存储器写入指定长度的数据的写指令,存储器基于写指令向存储器的存储介质写入指定长度的数据。由于写指令能够指定待写入数据的长度,使得在需要写入指定长度的数据时,能够减少需要发送的写指令的条数,减小了写指令的开销。并且,由于需要发送的写指令的条数减少了,存储器需要等待的指令间隔随之减短,能够利用节省出的时间写入其他数据,从而降低了存储器的写时延,并有效提升存储器的写带宽。In the data writing method of the memory provided by the present application, the memory receives a write instruction from the controller indicating to write data of a specified length to the memory, and the memory writes data of the specified length to the storage medium of the memory based on the write instruction. Since the write command can specify the length of the data to be written, when the data of the specified length needs to be written, the number of write commands to be sent can be reduced, reducing the overhead of the write command. Moreover, since the number of write instructions that need to be sent is reduced, the instruction interval that the memory needs to wait for is shortened accordingly, and the saved time can be used to write other data, thereby reducing the write delay of the memory and effectively improving the performance of the memory. Write bandwidth.
在一种可实现方式中,由于存储器包括多个存储阵列,多个存储阵列之间的数据访问过程互不影响,向存储阵列写入数据通过控制存储阵列的位线和字线实现。并且,每条位线均对应一段地址范围,不同位线对应的地址范围不同,同一存储阵列连接的多条位线对应的地址组成存储阵列的地址范围内的一段地址。每条字线均对应一段地址范围,不同字线对应的地址范围不同,同一存储阵列连接的多条字线对应的地址组成存储阵列的地址范围内的一段地址。以及,每个存储阵列均对应一段地址范围,不同存储阵列对应的地址范围不同,同一存储其中多个存储阵列对应的地址组成存储器的地址范围内的一段地址。因此,指定长度通过以下任一种或多种反映:基于写指令写入数据需要控制的地址连续的位线的总数,基于写指令写入数据需要控制的地址连续的字线的总数,以及,基于写指令被写入数据的地址连续的存储阵列的总数。In a practicable manner, since the memory includes multiple storage arrays, the data access process among the multiple storage arrays does not affect each other, and writing data to the storage arrays is realized by controlling bit lines and word lines of the storage arrays. Moreover, each bit line corresponds to an address range, and different bit lines correspond to different address ranges, and the addresses corresponding to multiple bit lines connected to the same storage array constitute a segment of addresses within the address range of the storage array. Each word line corresponds to an address range, and different word lines correspond to different address ranges, and the addresses corresponding to multiple word lines connected to the same memory array constitute a segment of addresses within the address range of the memory array. And, each storage array corresponds to a range of addresses, and different storage arrays correspond to different address ranges, and addresses corresponding to multiple storage arrays in the same storage form a range of addresses within the address range of the memory. Therefore, the specified length is reflected by any one or more of the following: the total number of bit lines whose addresses need to be controlled to write data based on the write command, the total number of word lines whose addresses need to be controlled to write data based on the write command, and, The total number of memory arrays whose addresses are contiguous to which data is written based on the write command.
在一种可实现方式中,地址连续的位线可以为在对存储器进行位线扫描时,会被依次施加电信号的多条位线。通常地,地址连续的多条位线在存储阵列上依次部署。类似的,地址连续的字线可以为在对存储器进行字线扫描时,会被依次施加电信号的多条字线。且地址连续的多条字线在存储阵列上通常会依次部署。地址连续的存储阵列可以为在需要向存储器中多个存储阵列连续写入数据时,会被依次写入数据的多个存储阵列。且地址连续的多个存储阵列在存储器上通常依次部署。In a practicable manner, the bit lines with consecutive addresses may be a plurality of bit lines to which electrical signals are sequentially applied when bit line scanning is performed on the memory. Usually, multiple bit lines with consecutive addresses are arranged sequentially on the memory array. Similarly, the word lines with consecutive addresses may be a plurality of word lines to which electrical signals are sequentially applied when the memory is scanned for the word lines. And multiple word lines with consecutive addresses are usually deployed in sequence on the memory array. The storage arrays with continuous addresses may be multiple storage arrays into which data is sequentially written when data needs to be continuously written into multiple storage arrays in the memory. And multiple storage arrays with consecutive addresses are usually deployed sequentially on the memory.
在一种可能的实现场景中,写指令还指示执行写指令指示的写入操作使用的电流信号的电流值小于参考值,参考值为执行未指示电流值的写指令所指示的写入操作使用的电流信号的电流值。In a possible implementation scenario, the write instruction also indicates that the current value of the current signal used to execute the write operation indicated by the write instruction is less than a reference value, and the reference value is used for the write operation indicated by the write instruction that does not indicate the current value. The current value of the current signal.
通过写指令指示执行写入操作使用的电流信号的电流值小于参考值,能够降低写入操作的功耗。并且,由于该写入操作的功耗较低,对于包括多个存储阵列的存储器,控制器能够根据存储器的功耗情况,向该存储器的多个存储阵列并发访问指令,以在该多个存储阵列之间进行灵活的带宽分配和功耗分配,从而满足更多应用需求。The write instruction indicates that the current value of the current signal used to perform the write operation is smaller than the reference value, so that the power consumption of the write operation can be reduced. Moreover, since the power consumption of the write operation is relatively low, for a memory including multiple storage arrays, the controller can concurrently send access instructions to the multiple storage arrays of the memory according to the power consumption of the memory, so as to store data in the multiple storage arrays. Flexible bandwidth allocation and power consumption allocation between arrays to meet more application requirements.
在另一种可能的实现场景中,写指令还指示允许根据存储器的功耗分一个或多个时段写入指定长度的数据。In another possible implementation scenario, the write instruction further indicates that data of a specified length is allowed to be written in one or more periods according to the power consumption of the memory.
当写指令指示允许根据存储器的功耗分多个时段写入指定长度的数据时,存储器可以根据存储器的整体功耗,选择在该多个时段中每个时段分别写入指定长度的数据中的部分数据,以达到降低存储器的整体功耗的目的。When the write instruction indicates that data of a specified length is allowed to be written in multiple time periods according to the power consumption of the memory, the memory can select the data of the specified length to be written in each of the multiple time periods according to the overall power consumption of the memory. Part of the data, in order to achieve the purpose of reducing the overall power consumption of the memory.
在再一种可能的实现场景中,写指令还指示:对于写指令指示的任一存储地址,当存储地址已存储的数据与写入指令指示写入存储地址的数据不同时,基于写指令对存储地址执行写入操作,当存储地址已存储的数据与写入指令指示写入存储地址的数据相同时,不对存储地址执行写入操作。In yet another possible implementation scenario, the write instruction also indicates: for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data written to the storage address indicated by the write instruction, based on the write instruction, the A write operation is performed on the storage address, and when the data stored at the storage address is the same as the data written to the storage address indicated by the write instruction, no write operation is performed on the storage address.
当存储地址已存储的数据与写入指令指示写入该存储地址的数据相同时,通过不对该存储地址执行写入操作,能够有效减少该写指令指示的写入操作的操作时间,实现对存储器的快速写,能够使该写指令对应的指令间隔变短,从而能够利用节省出的时间写入其他数据,降低了存储器的写时延,并提高了存储器的写带宽。When the data stored at the storage address is the same as the data written to the storage address indicated by the write instruction, by not performing a write operation on the storage address, the operation time of the write operation indicated by the write instruction can be effectively reduced, and the memory The fast write can shorten the command interval corresponding to the write command, so that other data can be written in the saved time, the write delay of the memory is reduced, and the write bandwidth of the memory is improved.
进一步的,指定长度的数据可以包括多个相同的数据。例如,当数据采用二进制数值表示时,指定长度的数据为多个二进制数值1组成的数据,或者,指定长度的数据为多个二进制数值0组成的数据。Further, the data of the specified length may include multiple pieces of the same data. For example, when the data is represented by a binary value, the data of the specified length is data composed of a plurality of binary values 1, or the data of the specified length is data composed of a plurality of binary values 0.
此时,通过在写指令中指定长度,能够通过发送一条写指令指示写入该指定长度的数据,相对于相关技术中指示待写入数据的长度相同且为固定值的写指令,无需发送多条写指令指示写入,减少了需要发送的写指令的条数。At this time, by specifying the length in the write command, it is possible to send a write command to indicate to write the data of the specified length. Compared with the write command indicating that the data to be written has the same length and is a fixed value in the related art, there is no need to send multiple write commands. The number of write instructions indicates writing, reducing the number of write instructions that need to be sent.
第二方面,本申请提供了一种存储器的数据写入装置,该数据写入装置包括:接收模块,用于接收控制器指示向存储器写入指定长度的数据的写指令;访问模块,用于基于写指令向存储器的存储介质写入指定长度的数据。In a second aspect, the present application provides a data writing device for a memory, the data writing device includes: a receiving module, used to receive a write instruction from the controller indicating to write data of a specified length to the memory; an access module, used to Writing data of a specified length to the storage medium of the memory based on the write command.
可选地,存储器包括多个存储阵列,多个存储阵列之间的数据访问过程互不影响,向存储阵列写入数据通过对存储阵列连接的位线和字线进行控制实现,指定长度通过以下任一种或多种反映:基于写指令写入数据需要控制的地址连续的位线的总数,基于写指令写入数据需要控制的地址连续的字线的总数,以及,基于写指令被写入数据的地址连续的存储阵列的总数。Optionally, the memory includes multiple storage arrays, and the data access process between the multiple storage arrays does not affect each other. Writing data to the storage arrays is realized by controlling the bit lines and word lines connected to the storage arrays. The specified length is as follows Any one or more reflections: the total number of address continuous bit lines that need to be controlled based on the write command to write data, the total number of address continuous word lines that need to be controlled based on the write command to write data, and, based on the write command to be written The total number of memory arrays whose data addresses are contiguous.
可选地,写指令还指示执行写指令指示的写入操作使用的电流信号的电流值小于参考值,参考值为执行未指示电流值的写指令所指示的写入操作使用的电流信号的电流值。Optionally, the write instruction also indicates that the current value of the current signal used to execute the write operation indicated by the write instruction is less than a reference value, and the reference value is the current of the current signal used by the write operation indicated by the write instruction that does not indicate the current value. value.
可选地,写指令还指示允许根据存储器的功耗分一个或多个时段写入指定长度的数据。Optionally, the write instruction also indicates that data of a specified length is allowed to be written in one or more periods according to the power consumption of the memory.
可选地,写指令还指示:对于写指令指示的任一存储地址,当存储地址已存储的数据与写入指令指示写入存储地址的数据不同时,基于写指令对存储地址执行写入操作,当存储地址已存储的数据与写入指令指示写入存储地址的数据相同时,不对存储地址执行写入操作。Optionally, the write instruction also indicates: for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data written to the storage address indicated by the write instruction, perform a write operation on the storage address based on the write instruction , when the stored data at the storage address is the same as the data written to the storage address indicated by the write instruction, no write operation is performed on the storage address.
可选地,指定长度的数据为多个二进制数值1组成的数据,或者,指定长度的数据为多个二进制数值0组成的数据。Optionally, the data of the specified length is data composed of multiple binary values 1, or the data of the specified length is data composed of multiple binary values 0.
第三方面,本申请提供了一种计算机设备,包括存储器和处理器,存储器存储有程序指令,处理器运行程序指令以执行本申请第一方面以及其任一种可能的实现方式中提供的方法。In a third aspect, the present application provides a computer device, including a memory and a processor, the memory stores program instructions, and the processor executes the program instructions to perform the method provided in the first aspect of the present application and any possible implementation thereof .
第四方面,本申请提供了一种计算机可读存储介质,该计算机可读存储介质为非易失性计算机可读存储介质,该计算机可读存储介质包括程序指令,当程序指令在计算机设备上运行时,使得计算机设备执行本申请第一方面以及其任一种可能的实现方式中提供的方法。In a fourth aspect, the present application provides a computer-readable storage medium. The computer-readable storage medium is a non-volatile computer-readable storage medium. The computer-readable storage medium includes program instructions. When the program instructions are stored on a computer device During operation, the computer device is made to execute the method provided in the first aspect of the present application and any possible implementation manner thereof.
第五方面,本申请提供了一种包含指令的计算机程序产品,当计算机程序产品在计算机上运行时,使得计算机执行本申请第一方面以及其任一种可能的实现方式中提供的方法。In a fifth aspect, the present application provides a computer program product containing instructions, which, when the computer program product is run on a computer, cause the computer to execute the method provided in the first aspect of the present application and any possible implementation thereof.
附图说明Description of drawings
图1是本申请实施例提供的一种存储器的数据写入方法涉及的应用场景的示意图;FIG. 1 is a schematic diagram of an application scenario involved in a data writing method of a memory provided by an embodiment of the present application;
图2是本申请实施例提供的一种传输写指令和待写入数据的示意图;FIG. 2 is a schematic diagram of a transmission write instruction and data to be written provided by an embodiment of the present application;
图3是本申请实施例提供的又一种传输写指令和待写入数据的的示意图;Fig. 3 is a schematic diagram of another transmission of write instructions and data to be written provided by the embodiment of the present application;
图4是本申请实施例提供的一种存储器的结构示意图;FIG. 4 is a schematic structural diagram of a memory provided by an embodiment of the present application;
图5是本申请实施例提供的一种存储组件的结构示意图;Fig. 5 is a schematic structural diagram of a storage component provided by an embodiment of the present application;
图6是本申请实施例提供的一种存储阵列的示意图;FIG. 6 is a schematic diagram of a storage array provided by an embodiment of the present application;
图7是本申请实施例提供的一种存储器的数据写入方法的流程图;FIG. 7 is a flow chart of a method for writing data into a memory according to an embodiment of the present application;
图8是本申请实施例提供的一种存储器的数据写入装置的结构示意图;FIG. 8 is a schematic structural diagram of a device for writing data into a memory according to an embodiment of the present application;
图9是本申请实施例提供的一种计算机设备的结构示意图。FIG. 9 is a schematic structural diagram of a computer device provided by an embodiment of the present application.
具体实施方式Detailed ways
为使本申请的目的、技术方案和优点更加清楚,下面将结合附图对本申请实施方式作进一步地详细描述。In order to make the purpose, technical solution and advantages of the present application clearer, the implementation manners of the present application will be further described in detail below in conjunction with the accompanying drawings.
目前,在存储技术领域中,控制器在向存储器的存储介质写入数据时,控制器需要向存储器发送写指令和待写入数据,以指示向存储器的存储介质写入该待写入数据。并且,控制器向同一存储器发送的写指令能够指示的待写入数据的长度相同且为固定值。因此,当需要连续写入同一数据(例如0或者1)时,若该数据的总长度大于一条写指令能够写入的待写入数据的长度,控制器需要发送多条写指令和数据,导致写数据的开销较大。并且,由于存储器写带宽(尤其是连续写同一存储阵列的写带宽)的提升受指令间隔(time writeto write,tW2W)制约,当需要发送大量指令时,需要等待的执行间隔较长,导致存储器的写带宽会受到影响。其中,存储器包括一个或多个存储阵列(bank),该多个存储阵列之间的数据访问过程互不影响。Currently, in the field of storage technology, when the controller writes data to the storage medium of the memory, the controller needs to send a write instruction and the data to be written to the memory to instruct writing the data to be written into the storage medium of the memory. Moreover, the length of the data to be written that can be indicated by the write command sent by the controller to the same memory is the same and a fixed value. Therefore, when the same data (such as 0 or 1) needs to be written continuously, if the total length of the data is greater than the length of the data to be written that can be written by one write command, the controller needs to send multiple write commands and data, resulting in Writing data is expensive. Moreover, since the improvement of the memory write bandwidth (especially the write bandwidth of continuous writing to the same storage array) is restricted by the instruction interval (time write to write, tW2W), when a large number of instructions need to be sent, the execution interval that needs to be waited for is longer, resulting in memory Write bandwidth will be affected. Wherein, the memory includes one or more storage arrays (banks), and the data access process among the multiple storage arrays does not affect each other.
本申请实施例提供了一种存储器的数据写入方法。该方法包括:存储器接收控制器指示向存储器写入指定长度的数据的写指令,存储器基于写指令向存储器的存储介质写入指定长度的数据。由于写指令能够指定待写入数据的长度,使得在需要写入指定长度的数据时,能够减少需要发送的写指令的条数,减小了写指令的开销。并且,由于需要发送的写指令的条数减少了,存储器需要等待的指令间隔随之减短,能够利用节省出的时间写入其他数据,从而降低了存储器的写时延,并有效提升存储器的写带宽。An embodiment of the present application provides a method for writing data into a memory. The method includes: the memory receives a write instruction from the controller indicating to write data of a specified length into the memory, and the memory writes the data of the specified length to a storage medium of the memory based on the write instruction. Since the write command can specify the length of the data to be written, when the data of the specified length needs to be written, the number of write commands to be sent can be reduced, reducing the overhead of the write command. Moreover, since the number of write instructions that need to be sent is reduced, the instruction interval that the memory needs to wait for is shortened accordingly, and the saved time can be used to write other data, thereby reducing the write delay of the memory and effectively improving the performance of the memory. Write bandwidth.
图1是本申请实施例提供的存储器的数据写入方法涉及的实施环境的结构示意图。如图1所示,该实施环境包括:处理器01和存储系统02。可选地,存储系统02可以为存储芯片。并且,存储系统02包括控制器021和存储器022。处理器01和控制器021之间建立有通信连接,控制器021和存储器022之间建立有通信连接。处理器01用于向控制器021指示写入需求,即通知控制器021需要写入的待写入数据的逻辑地址。控制器021用于根据处理器01的指示,确定用于写入待写入数据的物理地址,并根据物理地址和待写入数据向存储器022发送写指令。存储器022用于根据写指令将待写入数据写入对应的物理地址。FIG. 1 is a schematic structural diagram of an implementation environment involved in a method for writing data into a memory provided by an embodiment of the present application. As shown in FIG. 1 , the implementation environment includes: a processor 01 and a storage system 02 . Optionally, the storage system 02 may be a storage chip. Also, the storage system 02 includes a controller 021 and a memory 022 . A communication connection is established between the processor 01 and the controller 021 , and a communication connection is established between the controller 021 and the memory 022 . The processor 01 is used to indicate the write requirement to the controller 021 , that is, to notify the controller 021 of the logical address of the data to be written that needs to be written. The controller 021 is configured to determine a physical address for writing data to be written according to an instruction of the processor 01, and send a write instruction to the memory 022 according to the physical address and the data to be written. The memory 022 is used to write the data to be written into the corresponding physical address according to the write instruction.
可选地,该处理器01可以是硬件芯片,该硬件芯片可以是专用集成电路(application-specific integrated circuit,ASIC),可编程逻辑器件(programmablelogic device,PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complexprogrammable logic device,CPLD),现场可编程逻辑门阵列(field-programmable gatearray,FPGA),通用阵列逻辑(generic array logic,GAL)或其任意组合。或者,该处理器01可以是通用处理器,例如,中央处理器(central processing unit,CPU),网络处理器(network processor,NP),或者,CPU和NP的组合。Optionally, the processor 01 may be a hardware chip, and the hardware chip may be an application-specific integrated circuit (application-specific integrated circuit, ASIC), a programmable logic device (programmablelogic device, PLD) or a combination thereof. The aforementioned PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), a general array logic (generic array logic, GAL) or any combination thereof. Alternatively, the processor 01 may be a general processor, for example, a central processing unit (central processing unit, CPU), a network processor (network processor, NP), or a combination of a CPU and an NP.
存储器022可以是相变存储器(phase change memory,PCM)、自旋转移力矩存储器(shared transistor technology random access memory,STT-RAM)、可变电阻式存储器(resistive random-access memory,RRAM)等非易失存储器(non-volatile memory,NVM)。本申请实施例以存储器022为相变存储器为例进行说明。相变存储器是一种基于硫系化合物的新型非易失性半导体存储器。该存储器022包括多个存储单元。每个存储单元的存储介质均采用相变材料实现,其利用相变材料的晶态和非晶态的电学特性差异存储0/1的比特信息。其中,高阻的非晶态被定义为写0态(即RESET(0)态),低阻的晶态被定义为写1态(即SET(1)态,也称为擦1态)。写0态通过对存储单元执行写操作得到。写操作通过对存储单元施加一个高幅度且窄宽度的电脉冲实现。在这一电脉冲作用下,相变材料的温度被迅速提升至融化温度以上然后骤冷,由于相变材料的微观原子在该过程中没有充分的时间进行结晶,因而相变材料保持在了高阻的非晶状态。擦1态通过对存储单元执行擦操作得到。擦操作通过对存储单元施加一个幅度相对写操作的电脉冲较低,但持续时间相对较长的电脉冲实现。在这一电脉冲作用下,相变材料的温度被提升至结晶温度之上熔化温度之下,相变材料在该过程中可以通过热致结晶过程转变成低阻的状态。相变存储器022的读操作通过对存储单元施加一个幅度相对写操作的电脉冲和擦操作的电脉冲都更低的电脉冲实现。在这一电脉冲作用下,相变材料的阻值信息以电流或者电压的形式被读电路感知,从而实现对存储单元的读操作。其中,由于写操作和擦操作都是向存储单元写入数据,因此,本申请实施例中的写入操作不区分是写操作还是擦操作。The memory 022 can be a nonvolatile memory such as a phase change memory (phase change memory, PCM), a spin transfer torque memory (shared transistor technology random access memory, STT-RAM), or a variable resistance memory (resistive random-access memory, RRAM). Lost memory (non-volatile memory, NVM). The embodiment of the present application is described by taking the memory 022 as a phase change memory as an example. Phase change memory is a new type of non-volatile semiconductor memory based on chalcogenides. The memory 022 includes a plurality of storage units. The storage medium of each storage unit is realized by phase-change material, which stores 0/1 bit information by utilizing the difference in electrical characteristics between the crystalline state and the amorphous state of the phase-change material. Among them, the high-resistance amorphous state is defined as the write 0 state (ie, the RESET (0) state), and the low-resistance crystalline state is defined as the write 1 state (ie, the SET (1) state, also called the erase 1 state). The write 0 state is obtained by performing a write operation on the memory cell. The write operation is realized by applying a high-amplitude and narrow-width electrical pulse to the memory cell. Under the action of this electric pulse, the temperature of the phase change material is rapidly raised above the melting temperature and then quenched. Since the microscopic atoms of the phase change material do not have sufficient time to crystallize during this process, the phase change material remains at a high temperature. Resistant amorphous state. The erase 1 state is obtained by performing an erase operation on a memory cell. The erasing operation is realized by applying an electrical pulse with a lower amplitude than that of the write operation to the memory cell, but with a relatively longer duration. Under the action of this electric pulse, the temperature of the phase change material is raised above the crystallization temperature and below the melting temperature, during which the phase change material can be transformed into a low-resistance state through a thermally induced crystallization process. The read operation of the phase change memory 022 is realized by applying an electric pulse with a lower magnitude than that of the write operation and the erase operation to the memory cell. Under the action of this electric pulse, the resistance value information of the phase change material is sensed by the read circuit in the form of current or voltage, thereby realizing the read operation of the memory cell. Wherein, since the writing operation and the erasing operation both write data to the storage unit, the writing operation in the embodiment of the present application does not distinguish whether it is a writing operation or an erasing operation.
在本申请实施例中,存储器022可用作内存,用于暂时存放处理器01运行所需的数据。相应的,控制器021可以是内存控制器。且本申请实施例提供的存储器022的数据写入方法的一种应用场景可以为:处理器01在运行过程中产生了运算数据,需要将运算数据存储在内存中。在该应用场景中,处理器01、控制器021和内存之间的协同过程包括:处理器01向控制器021指示需要将运算数据进行存储,控制器021获取该运算数据,并在内存的存储空间中确定用于存储该运算数据的存储地址,然后根据该运算数据和存储地址向内存发送写指令和运算数据,内存根据该写指令将运算数据存储在对应的存储地址上。In the embodiment of the present application, the storage 022 can be used as a memory for temporarily storing data required for the operation of the processor 01 . Correspondingly, the controller 021 may be a memory controller. Moreover, an application scenario of the data writing method of the memory 022 provided in the embodiment of the present application may be: the processor 01 generates calculation data during operation, and the calculation data needs to be stored in the memory. In this application scenario, the cooperative process between the processor 01, the controller 021, and the memory includes: the processor 01 indicates to the controller 021 that the operation data needs to be stored, and the controller 021 acquires the operation data and stores them in the memory. Determine the storage address for storing the operation data in the space, and then send the write instruction and operation data to the memory according to the operation data and storage address, and the memory stores the operation data at the corresponding storage address according to the write instruction.
其中,写指令和待写入数据可以通过不同的端口发送。例如,当需要向内存发送写指令和运算数据时,如图2和图3所示,可以采用端口1向内存发送写指令,采用端口2向内存发送运算数据。并且,写指令可以包括用于指示写入操作的写指令本身和用于存储待写入数据的存储地址。在一种可实现方式中,该写指令本身和存储地址可以通过同一端口发送至内存。例如,如图2所示,可以采用端口1向内存发送写指令本身和存储地址。或者,写指令本身和存储地址可以通过不同的端口发送至内存。例如,如图3所示,可以采用端口1向内存发送写指令本身,采用端口3向内存发送存储地址。Wherein, the write command and the data to be written can be sent through different ports. For example, when it is necessary to send write instructions and operation data to the memory, as shown in Figure 2 and Figure 3, port 1 can be used to send write instructions to the memory, and port 2 can be used to send operation data to the memory. Also, the write command may include the write command itself for instructing the write operation and a storage address for storing the data to be written. In a practicable manner, the write instruction itself and the storage address can be sent to the memory through the same port. For example, as shown in Figure 2, port 1 can be used to send the write command itself and the storage address to the memory. Alternatively, the write command itself and the store address can be sent to memory through separate ports. For example, as shown in FIG. 3 , port 1 may be used to send the write command itself to the memory, and port 3 may be used to send the storage address to the memory.
在一种可实现方式中,如图4所示,存储器022包括:存储组件0221、驱动电路0222、控制组件0223和输入/输出(input/output,I/O)端口0224。本申请实施例提供的存储器022的数据写入方法的实现过程可以通过该控制组件0223、驱动电路0222、存储组件0221和I/O端口0224协同实现。其中,控制组件0223用于确定执行写指令指示的访问操作所需的控制参数,并指示驱动电路0222按照控制参数向存储组件0221提供驱动信号。存储组件0221用于在驱动信号的驱动下写入数据。In one implementable manner, as shown in FIG. 4 , the memory 022 includes: a storage component 0221 , a drive circuit 0222 , a control component 0223 and an input/output (input/output, I/O) port 0224 . The implementation process of the method for writing data to the memory 022 provided in the embodiment of the present application can be implemented through the cooperation of the control component 0223 , the driving circuit 0222 , the storage component 0221 and the I/O port 0224 . Wherein, the control component 0223 is configured to determine the control parameters required to execute the access operation indicated by the write instruction, and instruct the drive circuit 0222 to provide a drive signal to the storage component 0221 according to the control parameters. The storage component 0221 is used for writing data under the driving signal.
如图5所示,存储组件0221包括一个或多个存储阵列(bank)0221a,该多个存储阵列0221a之间的数据访问过程互不影响,即每个存储阵列0221a可以独立或并行接受读写指令并完成相应的操作。每个存储阵列0221a包括多个存储单元a1。每个存储单元a1均与字线(word line,WL)和位线(bit line,BL)连接,且不同存储单元a1连接的字线和位线中的至少一个不同。对不同存储单元a1的读写操作可以通过对对应存储单元a1连接的字线和位线施加电信号实现。且当读写操作过程中施加电信号的字线和位线中的至少一个不同时,读写操作所作用的存储单元a1不同。示例地,如图6所示,存储阵列0221a上纵横交错地排列着多条位线BL和多条字线WL,多条字线WL沿列方向依次排布,每条字线WL沿行方向延伸,多条位线BL沿行方向依次排布,每条位线BL沿列方向延伸。每个存储单元a1分别于一条位线BL和一条字线WL连接,且不同存储单元a1连接的字线WL和位线BL中的至少一个不同。As shown in Figure 5, the storage component 0221 includes one or more storage arrays (bank) 0221a, and the data access process between the multiple storage arrays 0221a does not affect each other, that is, each storage array 0221a can accept reads and writes independently or in parallel instruction and complete the corresponding operation. Each memory array 0221a includes a plurality of memory cells a1. Each memory cell a1 is connected to a word line (word line, WL) and a bit line (bit line, BL), and at least one of the word line and the bit line connected to different memory cells a1 is different. The read and write operations on different memory cells a1 can be implemented by applying electrical signals to the word lines and bit lines connected to the corresponding memory cells a1. And when at least one of the word line and the bit line to which the electrical signal is applied during the read and write operations is different, the memory cells a1 affected by the read and write operations are different. For example, as shown in FIG. 6, a plurality of bit lines BL and a plurality of word lines WL are arranged in a criss-cross pattern on the memory array 0221a, and the plurality of word lines WL are arranged in sequence along the column direction, and each word line WL is arranged along the row direction. Extending, a plurality of bit lines BL are arranged in sequence along the row direction, and each bit line BL extends along the column direction. Each memory cell a1 is respectively connected to a bit line BL and a word line WL, and at least one of the word line WL and the bit line BL connected to different memory cells a1 is different.
在一种可实现方式中,如图6所示,存储单元a1包括串联的可变电阻R和选通器件T。该可变电阻R用作存储单元a1的存储介质,用于存储信息。并且,可变电阻R的制作材料包括相变材料。可变电阻R的一端与位线BL连接,可变电阻R的另一端与选通器件T的第一端口连接,字线WL与选通器件T的第二端口连接。字线WL和位线BL的电压差决定位线与字线之间回路的开启与关闭,如字线WL和位线BL的电压差大于特定阈值电压时两者之间的回路开启。当位线与字线之间回路的开启时,位线BL上施加的电信号才能传输至可变电阻R上,才能在该电信号的控制下实现对该可变电阻R的数据写入和读取。In one implementable manner, as shown in FIG. 6 , the storage unit a1 includes a variable resistor R and a gate device T connected in series. The variable resistor R is used as a storage medium of the storage unit a1 for storing information. Moreover, the material for making the variable resistor R includes a phase change material. One end of the variable resistor R is connected to the bit line BL, the other end of the variable resistor R is connected to the first port of the strobe device T, and the word line WL is connected to the second port of the strobe device T. The voltage difference between the word line WL and the bit line BL determines the opening and closing of the loop between the bit line and the word line. For example, the loop between the word line WL and the bit line BL is opened when the voltage difference between the word line WL and the bit line BL is greater than a certain threshold voltage. When the loop between the bit line and the word line is opened, the electrical signal applied on the bit line BL can be transmitted to the variable resistor R, and the data writing and writing to the variable resistor R can be realized under the control of the electrical signal. read.
应当理解的是,以上内容是对本申请实施例提供的存储器的数据写入方法的应用场景的示例性说明,并不构成对于该事件分析方法的应用场景的限定,本领域普通技术人员可知,随着业务需求的改变,其应用场景可以根据应用需求进行调整,本申请实施例对其不做一一列举。It should be understood that the above content is an exemplary description of the application scenario of the method for writing data to the memory provided by the embodiment of the present application, and does not constitute a limitation on the application scenario of the event analysis method. As business requirements change, its application scenarios can be adjusted according to application requirements, and the embodiments of this application do not list them one by one.
下面以图1所示的应用场景为例,对本申请实施例提供的存储器的数据写入方法的实现过程进行说明。如图7所示,该存储器的数据写入方法的实现过程可以包括以下步骤:The following uses the application scenario shown in FIG. 1 as an example to describe the implementation process of the method for writing data into the memory provided by the embodiment of the present application. As shown in Figure 7, the implementation process of the data writing method of the memory may include the following steps:
步骤701、存储器接收控制器指示向存储器写入指定长度的数据的写指令。Step 701, the memory receives a write instruction from the controller indicating to write data of a specified length into the memory.
根据前述内容,存储系统包括控制器和存储器,控制器用于向存储器发送写指令。例如,当存储器用作内存时,处理器用于向控制器指示需要将运算数据进行存储,控制器获取该运算数据后,可以在内存的存储空间中确定用于存储该运算数据的存储地址,然后根据该运算数据和存储地址向内存发送写指令和运算数据,以便于内存根据该写指令将运算数据存储在对应的存储地址上。According to the foregoing content, the storage system includes a controller and a memory, and the controller is configured to send a write instruction to the memory. For example, when the memory is used as a memory, the processor is used to indicate to the controller that the operation data needs to be stored. After the controller obtains the operation data, it can determine the storage address for storing the operation data in the storage space of the memory, and then Sending the write instruction and the operation data to the memory according to the operation data and the storage address, so that the memory stores the operation data at the corresponding storage address according to the write instruction.
由于存储器包括多个存储阵列,多个存储阵列之间的数据访问过程互不影响,向存储阵列写入数据通过控制存储阵列的位线和字线实现。并且,每条位线均对应一段地址范围,不同位线对应的地址范围不同,同一存储阵列连接的多条位线对应的地址组成存储阵列的地址范围内的一段地址。每条字线均对应一段地址范围,不同字线对应的地址范围不同,同一存储阵列连接的多条字线对应的地址组成存储阵列的地址范围内的一段地址。以及,每个存储阵列均对应一段地址范围,不同存储阵列对应的地址范围不同,同一存储其中多个存储阵列对应的地址组成存储器的地址范围内的一段地址。因此,指定长度可以通过以下任一种或多种反映:基于写指令写入数据需要控制的地址连续的位线的总数,基于写指令写入数据需要控制的地址连续的字线的总数,以及,基于写指令被写入数据的地址连续的存储阵列的总数。Since the memory includes multiple storage arrays, the data access process between the multiple storage arrays does not affect each other, and writing data to the storage arrays is realized by controlling the bit lines and word lines of the storage arrays. Moreover, each bit line corresponds to an address range, and different bit lines correspond to different address ranges, and the addresses corresponding to multiple bit lines connected to the same storage array constitute a segment of addresses within the address range of the storage array. Each word line corresponds to an address range, and different word lines correspond to different address ranges, and the addresses corresponding to multiple word lines connected to the same memory array constitute a segment of addresses within the address range of the memory array. And, each storage array corresponds to a range of addresses, and different storage arrays correspond to different address ranges, and addresses corresponding to multiple storage arrays in the same storage form a range of addresses within the address range of the memory. Therefore, the specified length can be reflected by any one or more of the following: the total number of address continuous bit lines that need to be controlled based on the write command to write data, the total number of address continuous word lines that need to be controlled based on the write command to write data, and , the total number of memory arrays whose addresses are contiguous to which data is written based on the write command.
在一种可实现方式中,地址连续的位线可以为在对存储器进行位线扫描时,会被依次施加电信号的多条位线。通常地,地址连续的多条位线在存储阵列上依次部署。并且,对于每两个相邻的位线,后一位线的首地址可以等于前一位线的最大地址+1。例如,如图6所示,存储阵列上的位线BL(1)、位线BL(2)和位线BL(3)为连续排列的位线,且在对存储器进行位线扫描时,会依次向位线BL(1)、位线BL(2)和位线BL(3)施加电信号,因此该位线BL(1)、位线BL(2)和位线BL(3)为地址连续的位线。In a practicable manner, the bit lines with consecutive addresses may be a plurality of bit lines to which electrical signals are sequentially applied when bit line scanning is performed on the memory. Usually, multiple bit lines with consecutive addresses are arranged sequentially on the memory array. Also, for every two adjacent bit lines, the first address of the latter bit line can be equal to the maximum address of the previous bit line+1. For example, as shown in Figure 6, bit lines BL(1), bit line BL(2) and bit line BL(3) on the memory array are bit lines arranged continuously, and when the memory is scanned for bit lines, the The electrical signal is applied to the bit line BL(1), bit line BL(2) and bit line BL(3) in sequence, so the bit line BL(1), bit line BL(2) and bit line BL(3) are address continuous bit lines.
在一种可实现方式中,地址连续的字线可以为在对存储器进行字线扫描时,会被依次施加电信号的多条字线。通常地,地址连续的多条字线在存储阵列上依次部署。并且,对于每两个相邻的字线,后一字线的首地址可以等于前一字线的最大地址+1。例如,如图6所示,存储阵列上的字线WL(1)、字线WL(2)和字线WL(3)为连续排列的字线,且在对存储器进行字线扫描时,会依次向字线WL(1)、字线WL(2)和字线WL(3)施加电信号,因此该字线WL(1)、字线WL(2)和字线WL(3)为地址连续的字线。In a practicable manner, the word lines with consecutive addresses may be a plurality of word lines to which electrical signals are sequentially applied when the memory is scanned for the word lines. Usually, multiple word lines with consecutive addresses are arranged sequentially on the memory array. And, for every two adjacent word lines, the first address of the next word line can be equal to the maximum address+1 of the previous word line. For example, as shown in FIG. 6, the word line WL(1), word line WL(2) and word line WL(3) on the memory array are word lines arranged continuously, and when the memory is scanned for the word lines, the Apply electrical signals to word line WL(1), word line WL(2) and word line WL(3) in sequence, so the word line WL(1), word line WL(2) and word line WL(3) are address continuous word lines.
在一种可实现方式中,地址连续的存储阵列可以为在需要向存储器中多个存储阵列连续写入数据时,会被依次写入数据的多个存储阵列。通常地,地址连续的多个存储阵列在存储器上依次部署。并且,对于每两个逻辑地址相邻的存储阵列,后一存储阵列的首地址可以等于前一存储阵列的最大地址+1。例如,如图5所示,存储器0221包括依次排布的多个存储阵列0221a,且向存储器0221中多个存储阵列0221a连续写入数据时,会依次向存储阵列0221a(1)和存储阵列0221a(2)写入数据,因此该存储阵列0221a(1)和存储阵列0221a(2)为地址连续的存储阵列。In a practicable manner, the storage arrays with consecutive addresses may be multiple storage arrays into which data is sequentially written when data needs to be continuously written into multiple storage arrays in the memory. Generally, multiple storage arrays with consecutive addresses are deployed sequentially on the memory. Moreover, for every two storage arrays with adjacent logical addresses, the first address of the latter storage array may be equal to the maximum address+1 of the previous storage array. For example, as shown in FIG. 5, the memory 0221 includes a plurality of storage arrays 0221a arranged in sequence, and when data is continuously written to the multiple storage arrays 0221a in the memory 0221, the storage array 0221a(1) and the storage array 0221a (2) Data is written, so the memory array 0221a(1) and the memory array 0221a(2) are memory arrays with consecutive addresses.
在本申请实施例中,指定长度的数据可以包括多个相同的数据。例如,当数据采用二进制数值表示时,该指定长度的数据可以为多个二进制数值1组成的数据,或者,该指定长度的数据可以为多个二进制数值0组成的数据。此时,通过在写指令中指定长度,能够通过发送一条写指令指示写入该指定长度的数据,相对于相关技术中指示待写入数据的长度相同且为固定值的写指令,无需发送多条写指令指示写入,减少了需要发送的写指令的条数。In this embodiment of the application, the data of the specified length may include multiple pieces of the same data. For example, when the data is represented by a binary value, the data of the specified length may be data composed of a plurality of binary values 1, or the data of the specified length may be data composed of a plurality of binary values 0. At this time, by specifying the length in the write command, it is possible to send a write command to indicate to write the data of the specified length. Compared with the write command indicating that the data to be written has the same length and is a fixed value in the related art, there is no need to send multiple write commands. The number of write instructions indicates writing, reducing the number of write instructions that need to be sent.
在一种可实现方式中,写指令还可以指示执行写指令指示的写入操作使用的电流信号的电流值小于参考值。其中,参考值为执行未指示电流值的写指令所指示的写入操作使用的电流信号的电流值。由于向某存储单元执行写入操作时,需要对该存储单元连接的位线施加电流脉冲信号,向该存储单元连接的字线施加选通使能电压信号,使得存储单元的存储介质的电学特性在信号的作用下发生变化,以便于通过发生变化的电学特性存储信息。因此,当写入指令未指示电流值时,同一存储阵列中所有存储单元连接的位线上施加的电流脉冲信号的电流值可以均相同,且该电流值为该参考值。当写指令指示执行写指令指示的写入操作使用的电流信号的电流值小于参考值时,相当于该写指令指示使用较小的电流或瞬态操作电流执行写入操作。在一种可实现方式中,使用较小的电流或瞬态操作电流执行写入操作,可以通过降低写入操作在同一时间操作的比特数实现。In a practicable manner, the write instruction may also indicate that the current value of the current signal used to perform the write operation indicated by the write instruction is smaller than the reference value. Wherein, the reference value is the current value of the current signal used to execute the write operation indicated by the write instruction not indicating the current value. When performing a write operation to a memory cell, it is necessary to apply a current pulse signal to the bit line connected to the memory cell, and to apply a gate enabling voltage signal to the word line connected to the memory cell, so that the electrical characteristics of the storage medium of the memory cell Changes under the action of a signal in order to store information through changed electrical properties. Therefore, when the write instruction does not indicate a current value, the current value of the current pulse signal applied to the bit lines connected to all memory cells in the same memory array may be the same, and the current value is the reference value. When the write instruction indicates that the current value of the current signal used for the write operation indicated by the write instruction is smaller than the reference value, it means that the write instruction indicates that a smaller current or a transient operating current is used to perform the write operation. In an implementable manner, using a smaller current or a transient operating current to perform the write operation can be achieved by reducing the number of bits operated by the write operation at the same time.
通过写指令指示执行写入操作使用的电流信号的电流值小于参考值,能够降低写入操作的功耗。并且,由于该写入操作的功耗较低,对于包括多个存储阵列的存储器,控制器能够根据存储器的功耗情况,向该存储器的多个存储阵列并发访问指令,以在该多个存储阵列之间进行灵活的带宽分配和功耗分配,从而满足更多应用需求。由于该写指令指示使用较小的电流或瞬态操作电流执行写入操作能够降低写入操作的功耗,该写指令也可称为低功耗(low power)写指令。The write instruction indicates that the current value of the current signal used to perform the write operation is smaller than the reference value, so that the power consumption of the write operation can be reduced. Moreover, since the power consumption of the write operation is relatively low, for a memory including multiple storage arrays, the controller can concurrently send access instructions to the multiple storage arrays of the memory according to the power consumption of the memory, so as to store data in the multiple storage arrays. Flexible bandwidth allocation and power consumption allocation between arrays to meet more application requirements. Since the write command indicates that using a smaller current or a transient operating current to perform the write operation can reduce the power consumption of the write operation, the write command may also be referred to as a low power write command.
在另一种可实现方式中,写指令还可以指示允许根据存储器的功耗分一个或多个时段写入指定长度的数据。其中,存储器的功耗包括存储器中多个存储阵列的功耗之和。当写指令指示允许根据存储器的功耗分多个时段写入指定长度的数据时,存储器可以根据存储器的整体功耗,选择在该多个时段中每个时段分别写入指定长度的数据中的部分数据,以达到降低存储器的整体功耗的目的。由于按照该写指令的指示写入数据也能够降低存储器的功耗,该写指令也可称为低功耗写指令。In another practicable manner, the write instruction may also indicate that data of a specified length is allowed to be written in one or more periods according to the power consumption of the memory. Wherein, the power consumption of the memory includes the sum of the power consumption of multiple storage arrays in the memory. When the write instruction indicates that data of a specified length is allowed to be written in multiple time periods according to the power consumption of the memory, the memory can select the data of the specified length to be written in each of the multiple time periods according to the overall power consumption of the memory. Part of the data, in order to achieve the purpose of reducing the overall power consumption of the memory. Since writing data according to the instruction of the write instruction can also reduce the power consumption of the memory, the write instruction can also be called a low-power write instruction.
在再一种可实现方式中,写指令还可以指示:对于写指令指示的任一存储地址,当该存储地址已存储的数据与写入指令指示写入该存储地址的数据不同时,基于写指令对该存储地址执行写入操作,当该存储地址已存储的数据与写入指令指示写入该存储地址的数据相同时,不对该存储地址执行写入操作。例如,假设某存储地址已存储的数据均为1,且写入指令指示当存储地址已存储的数据与写入指令指示写入存储地址的数据不同时,基于写指令对存储地址执行写入操作,当存储地址已存储的数据与写入指令指示写入存储地址的数据相同时,不对存储地址执行写入操作。则在执行该写入指令指示的写入操作时,当待写入该存储地址的比特位的数据为0时,需要将该比特位存储的数据刷新为0,当待写入该存储地址的比特位的数据为1时,不对该比特位执行任何操作。由于此时无需对比特位执行操作,能够实现对存储器的快写。In yet another practicable manner, the write instruction may also indicate: for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data written to the storage address indicated by the write instruction, based on the write The instruction performs a write operation on the storage address, and when the data stored in the storage address is the same as the data written in the storage address indicated by the write instruction, the write operation is not performed on the storage address. For example, assume that the stored data of a certain storage address are all 1, and the write instruction indicates that when the stored data of the storage address is different from the data written to the storage address indicated by the write instruction, the write operation is performed on the storage address based on the write instruction , when the stored data at the storage address is the same as the data written to the storage address indicated by the write instruction, no write operation is performed on the storage address. Then, when executing the write operation indicated by the write instruction, when the bit data to be written into the storage address is 0, the data stored in the bit needs to be refreshed to 0, and when the data to be written into the storage address When the data of a bit is 1, no operation is performed on the bit. Since there is no need to perform operations on bits at this time, fast writing to the memory can be realized.
当存储地址已存储的数据与写入指令指示写入该存储地址的数据相同时,通过不对该存储地址执行写入操作,能够有效减少该写指令指示的写入操作的操作时间,实现对存储器的快速写,能够使该写指令对应的指令间隔变短,从而能够利用节省出的时间写入其他数据,降低了存储器的写时延,并提高了存储器的写带宽。由于该写指令能够减少执行写入操作的操作时间,该写指令可称为快速写(fast write)指令。When the data stored at the storage address is the same as the data written to the storage address indicated by the write instruction, by not performing a write operation on the storage address, the operation time of the write operation indicated by the write instruction can be effectively reduced, and the memory The fast write can shorten the command interval corresponding to the write command, so that other data can be written in the saved time, the write delay of the memory is reduced, and the write bandwidth of the memory is improved. Since the write command can reduce the operation time for performing the write operation, the write command may be called a fast write command.
对应于该快速写指令,一种可能的应用场景可以为:在对存储器的连续地址执行写操作前,控制器指示存储器预先将该连续地址全部写成统一值,以便于存储器根据后续接收到的写指令执行写入操作时,只需要对该连续地址中已存储的数据与写入指令指示的数据不同的比特位进行操作。例如,在存储器的某个存储阵列空闲期间,控制器可以通过指示写指定长度的数据的写指令或者低功耗写指令,控制存储器将该存储阵列指定长度的连续地址的比特位均写成统一值,使得在控制器接收到紧急的数据写入需求时,能够采用快速写指令在该连续地址中执行写入操作。其中,该统一值可以根据存储器的性能进行设置,例如,当存储器的写0速度快,写1速度慢时,该统一值可以为1。Corresponding to the fast write instruction, a possible application scenario may be: before performing a write operation on consecutive addresses of the memory, the controller instructs the memory to write all the consecutive addresses into a unified value in advance, so that the memory can When the instruction executes the write operation, it only needs to operate on the bits that are different from the data stored in the continuous address and the data indicated by the write instruction. For example, when a certain storage array of the memory is idle, the controller can control the memory to write the bits of the consecutive addresses of the specified length of the storage array to a uniform value through a write command or a low-power write command indicating to write data of a specified length. , so that when the controller receives an urgent data write request, it can use a fast write command to perform a write operation in the continuous address. Wherein, the uniform value can be set according to the performance of the memory, for example, when the speed of writing 0 to the memory is fast and the speed of writing 1 is slow, the uniform value can be 1.
另外,写指令还可以直接指定写入的数据,如指定写二进制值1或0。通过写指令指示写指定长度的二进制数值1或指定长度的写二进制数值0,使得无需通过数据总线传输待写入数据,能够降低数据传输的功耗。此时,写指令也可称为写1指令或写0指令,或者,也可称写指定长度0的指令或写指定长度1的指令。类似的,上述低功耗写指令也可称为低功耗写1指令或低功耗写0指令,或者,也可称低功耗写指定长度0的指令或低功耗写指定长度1的指令。上述快写指令也可称为快写1指令或快写0指令,或者,也可称快写指定长度0的指令或快写指定长度1的指令。In addition, the write command can also directly specify the data to be written, such as specifying to write a binary value of 1 or 0. The write command indicates to write a binary value 1 of a specified length or a binary value 0 of a specified length, so that the data to be written does not need to be transmitted through the data bus, and the power consumption of data transmission can be reduced. At this time, the write command may also be called a write 1 command or a write 0 command, or may also be called a write command with a specified length of 0 or a command with a specified length of 1. Similarly, the above-mentioned low-power write instruction can also be called a low-power write 1 instruction or a low-power write 0 instruction, or it can also be called a low-power write instruction with a specified length of 0 or a low-power write instruction with a specified length of 1. instruction. The above-mentioned fast write command may also be called a fast write 1 command or a fast write 0 command, or it may also be called a fast write specified length 0 command or a fast write specified length 1 command.
步骤702、存储器基于写指令向存储器的存储介质写入指定长度的数据。Step 702, the memory writes data of a specified length to the storage medium of the memory based on the write instruction.
存储器接收到控制器发送的写指令后,即可根据该写指令执行写入操作,将待写入数据写到存储器的存储介质上。并且,当写入操作指示的内容不同时,执行写入操作的实现方式稍有不同,下面针对步骤701中写指令的多种实现方式,分多种情况对执行对应写入操作的实现方式进行说明。After the memory receives the write instruction sent by the controller, it can execute a write operation according to the write instruction, and write the data to be written to the storage medium of the memory. Moreover, when the content indicated by the write operation is different, the implementation of the write operation is slightly different. The implementation of the corresponding write operation is carried out in various situations for the various implementations of the write instruction in step 701. illustrate.
在第一种情况中,当写指令的指定长度基于写指令写入数据需要控制的地址连续的位线的总数反映时,存储器在执行该写指令指示的写入操作的过程中,可以根据该写指令依次按照存储阵列、字线和位线的层次找到该写指令指示的第一个存储地址,然后对该第一个存储地址执行写入操作,然后将位线的地址加一,找到写指令指示的第二个存储地址,然后对该第二个存储地址执行写入操作,依次类推按照位线、字线和存储阵列的层次进行遍历并执行写入操作,直至完成写指令指示的写入操作。In the first case, when the specified length of the write command is reflected based on the total number of consecutive address bit lines that need to be controlled by the write command to write data, the memory can perform the write operation indicated by the write command according to the The write command finds the first storage address indicated by the write command according to the level of the storage array, word line and bit line in turn, and then performs a write operation on the first storage address, and then adds one to the address of the bit line to find the write The second storage address indicated by the instruction, and then perform the write operation on the second storage address, and so on, traverse and execute the write operation according to the level of the bit line, word line and storage array, until the write operation indicated by the write instruction is completed Enter operation.
在第二种情况中,当写指令的指定长度基于写指令写入数据需要控制的地址连续的字线的总数反映时,存储器在执行该写指令指示的写入操作的过程中,可以根据该写指令依次按照存储阵列、字线和位线的层次找到该写指令指示的第一个存储地址,然后对该第一个存储地址执行写入操作,然后将字线的地址加一,找到写指令指示的第二个存储地址,然后对该第二个存储地址执行写入操作,依次类推按照字线、位线和存储阵列的层次进行遍历并执行写入操作,直至完成写指令指示的写入操作。In the second case, when the specified length of the write command is reflected based on the total number of word lines with consecutive addresses that need to be controlled by the write command to write data, the memory may, during the process of executing the write operation indicated by the write command, according to the The write command finds the first storage address indicated by the write command according to the level of the storage array, word line and bit line in turn, and then performs a write operation on the first storage address, and then adds one to the address of the word line to find the write address. The second storage address indicated by the instruction, and then perform the write operation on the second storage address, and so on, traverse and execute the write operation according to the level of the word line, bit line and storage array, until the write operation indicated by the write instruction is completed Enter operation.
在第三种情况中,当写指令的指定长度基于写指令写入数据需要控制的地址连续的存储阵列的总数反映时,存储器在执行该写指令指示的写入操作的过程中,可以根据该写指令依次按照存储阵列、位线和字线的层次找到该写指令指示的第一个存储地址,然后对该第一个存储地址执行写入操作,然后将存储阵列的地址加一,找到写指令指示的第二个存储地址,然后对该第二个存储地址执行写入操作,依次类推按照存储阵列、位线和字线的层次进行遍历并执行写入操作,直至完成写指令指示的写入操作。示例地,图5中的箭头b1为存储阵列0021a的存储地址增加的方向,图6中的箭头b2为对存储阵列0221a上位线BL进行扫描的方向,即位线BL的存储地址增加的方向,图6中的箭头b3为对存储阵列0221a上字线WL进行扫描的方向,即字线WL的存储地址增加的方向,则可以按照该顺序对存储阵列、位线和字线进行遍历。In the third case, when the specified length of the write command is reflected based on the total number of memory arrays with continuous addresses that need to be controlled by the write command, the memory may, during the process of executing the write operation indicated by the write command, according to the The write command finds the first storage address indicated by the write command according to the level of the storage array, bit line and word line in turn, and then performs a write operation on the first storage address, and then adds one to the address of the storage array to find the write The second storage address indicated by the instruction, and then perform the write operation on the second storage address, and so on, traverse and execute the write operation according to the level of the storage array, bit line and word line, until the write operation indicated by the write instruction is completed Enter operation. For example, arrow b1 in FIG. 5 is the direction in which the storage address of the memory array 0021a increases, and arrow b2 in FIG. The arrow b3 in 6 is the direction of scanning the word line WL on the memory array 0221a, that is, the direction in which the storage address of the word line WL increases, and the memory array, bit line and word line can be traversed in this order.
在第四种情况中,当写指令中指定长度的数据包括多个相同的数据时,存储器在执行该写指令指示的写入操作的过程中,可以根据该写指令将该写指令指示的该指定长度的存储地址的比特位直接刷新为该相同的数据。In the fourth case, when the data of the specified length in the write command includes a plurality of identical data, the memory may, according to the write command indicate the The bits of the storage address of the specified length are directly refreshed to the same data.
在第五种情况中,当写指令还指示执行写指令指示的写入操作使用的电流信号的电流值小于参考值时,存储器在执行该写指令指示的写入操作的过程中,可以向该写指令指示的存储单元连接的位线施加电流脉冲信号,且该电流脉冲信号的电流值小于参考值,并向该存储单元连接的字线施加选通使能电压信号,以完成该写指令指示的写入操作。In the fifth case, when the write instruction also indicates that the current value of the current signal used for the write operation indicated by the write instruction is smaller than the reference value, the memory may send A current pulse signal is applied to the bit line connected to the memory cell indicated by the write instruction, and the current value of the current pulse signal is less than a reference value, and a gate enabling voltage signal is applied to the word line connected to the memory cell to complete the write instruction instruction write operation.
在第六种情况中,当写指令还指示允许根据存储器的功耗分一个或多个时段写入指定长度的数据时,存储器在执行该写指令指示的写入操作的过程中,可以预测存储器的整体功耗,并在存储器的整体功耗的较低的一个或多个时段写入写指令指示的数据,从而达到降低存储器整体功耗的目的。In the sixth case, when the write instruction also indicates that data of a specified length is allowed to be written in one or more periods according to the power consumption of the memory, the memory can predict that the memory The overall power consumption of the memory is lower, and the data indicated by the write command is written in one or more periods of time when the overall power consumption of the memory is lower, so as to achieve the purpose of reducing the overall power consumption of the memory.
在第七种情况中,当写指令为上述快写指令时,存储器在执行该写指令指示的写入操作的过程中,对于写指令指示的任一存储地址,当该存储地址已存储的数据与写入指令指示写入该存储地址的数据不同时,存储器可以基于写指令对该存储地址执行写入操作,当该存储地址已存储的数据与写入指令指示写入该存储地址的数据相同时,存储器可以不对该存储地址执行写入操作。In the seventh case, when the write instruction is the above-mentioned fast write instruction, during the process of the memory executing the write operation indicated by the write instruction, for any storage address indicated by the write instruction, when the data stored at the storage address When the write instruction indicates that the data to be written to the storage address is different, the memory can perform a write operation on the storage address based on the write instruction, when the data stored at the storage address is the same as the data written to the storage address indicated by the write instruction At the same time, the memory may not perform a write operation on the storage address.
需要说明的是,存储器的实际应用过程中,写指令可以为以上多种实现方式中的部分或全部的结合,当写指令为以上多种实现方式的结合时,存储器在执行写入操作时,可以根据写指令实现方式的结合情况,综合使用上述情况中与写指令实现方式对应的情况执行写入操作,此处对其实现过程不再赘述。It should be noted that during the actual application of the memory, the write instruction may be a combination of some or all of the above multiple implementations. When the write instruction is a combination of the above multiple implementations, when the memory performs the write operation, According to the combination of implementation methods of the write instruction, the writing operation may be performed by comprehensively using the situations corresponding to the implementation methods of the write instruction in the above situations, and the implementation process thereof will not be repeated here.
步骤703、存储器向控制器反馈针对写指令的写响应。Step 703, the memory feeds back a write response to the write command to the controller.
存储器对写指令进行响应后,可以向控制器反馈针对写指令的写响应,以向控制器反馈是否完成写指令指示的写入操作。需要说明的是,存储器也可以不向控制器反馈写响应,此时控制器可以通过其他方式确定写指令的执行结果。例如,可以定义指令时延,当控制器发送写指令后的指定时间段内未收到存储器的反馈时,确定未完成写入操作。After the memory responds to the write command, it may feed back a write response to the write command to the controller, so as to feed back to the controller whether the write operation indicated by the write command is completed. It should be noted that the memory may not feed back the write response to the controller, and at this time, the controller may determine the execution result of the write instruction in other ways. For example, a command delay can be defined, and when the controller does not receive feedback from the memory within a specified period of time after sending the write command, it is determined that the write operation is not completed.
综上所述,在本申请实施例提供的存储器的数据写入方法中,存储器接收控制器指示向存储器写入指定长度的数据的写指令,存储器基于写指令向存储器的存储介质写入指定长度的数据。由于写指令能够指定待写入数据的长度,使得在需要写入指定长度的数据时,能够减少需要发送的写指令的条数,减小了写指令的开销。并且,由于需要发送的写指令的条数减少了,存储器需要等待的指令间隔随之减短,能够利用节省出的时间写入其他数据,从而降低了存储器的写时延,并有效提升存储器的写带宽。To sum up, in the data writing method of the memory provided by the embodiment of the present application, the memory receives a write instruction from the controller indicating to write data of a specified length to the memory, and the memory writes data of a specified length to the storage medium of the memory based on the write instruction. The data. Since the write command can specify the length of the data to be written, when the data of the specified length needs to be written, the number of write commands to be sent can be reduced, reducing the overhead of the write command. Moreover, since the number of write instructions that need to be sent is reduced, the instruction interval that the memory needs to wait for is shortened accordingly, and the saved time can be used to write other data, thereby reducing the write delay of the memory and effectively improving the performance of the memory. Write bandwidth.
需要说明的是,本申请实施例提供的存储器的数据写入方法的步骤先后顺序可以进行适当调整,步骤也可以根据情况进行相应增减。任何熟悉本技术领域的技术人员在本申请揭露的技术范围内,可轻易想到变化的方法,都应涵盖在本申请的保护范围之内,因此不再赘述。It should be noted that the sequence of steps in the method for writing data into the memory provided by the embodiment of the present application can be adjusted appropriately, and the steps can also be increased or decreased accordingly according to the situation. Any person skilled in the art within the technical scope disclosed in this application can easily think of changes, which should be covered within the scope of protection of this application, and thus will not be repeated here.
本申请实施例还提供了一种存储器的数据写入装置。如图8所示,该存储器的数据写入装置80包括:The embodiment of the present application also provides a device for writing data into a memory. As shown in Figure 8, the data writing device 80 of this memory comprises:
接收模块801,用于接收控制器指示向存储器写入指定长度的数据的写指令。The receiving module 801 is configured to receive a write instruction from the controller indicating to write data of a specified length into the memory.
访问模块802,用于基于写指令向存储器的存储介质写入指定长度的数据。The access module 802 is configured to write data of a specified length to the storage medium of the memory based on the write instruction.
可选地,存储器包括多个存储阵列,多个存储阵列之间的数据访问过程互不影响,向存储阵列写入数据通过对存储阵列连接的位线和字线进行控制实现,指定长度通过以下任一种或多种反映:基于写指令写入数据需要控制的地址连续的位线的总数,基于写指令写入数据需要控制的地址连续的字线的总数,以及,基于写指令被写入数据的地址连续的存储阵列的总数。Optionally, the memory includes multiple storage arrays, and the data access process between the multiple storage arrays does not affect each other. Writing data to the storage arrays is realized by controlling the bit lines and word lines connected to the storage arrays. The specified length is as follows Any one or more reflections: the total number of address continuous bit lines that need to be controlled based on the write command to write data, the total number of address continuous word lines that need to be controlled based on the write command to write data, and, based on the write command to be written The total number of memory arrays whose data addresses are contiguous.
可选地,写指令还指示执行写指令指示的写入操作使用的电流信号的电流值小于参考值,参考值为执行未指示电流值的写指令所指示的写入操作使用的电流信号的电流值。Optionally, the write instruction also indicates that the current value of the current signal used to execute the write operation indicated by the write instruction is less than a reference value, and the reference value is the current of the current signal used by the write operation indicated by the write instruction that does not indicate the current value. value.
可选地,写指令还指示允许根据存储器的功耗分一个或多个时段写入指定长度的数据。Optionally, the write instruction also indicates that data of a specified length is allowed to be written in one or more periods according to the power consumption of the memory.
可选地,写指令还指示:对于写指令指示的任一存储地址,当存储地址已存储的数据与写入指令指示写入存储地址的数据不同时,基于写指令对存储地址执行写入操作,当存储地址已存储的数据与写入指令指示写入存储地址的数据相同时,不对存储地址执行写入操作。Optionally, the write instruction also indicates: for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data written to the storage address indicated by the write instruction, perform a write operation on the storage address based on the write instruction , when the stored data at the storage address is the same as the data written to the storage address indicated by the write instruction, no write operation is performed on the storage address.
可选地,指定长度的数据为多个二进制数值1组成的数据,或者,指定长度的数据为多个二进制数值0组成的数据。Optionally, the data of the specified length is data composed of multiple binary values 1, or the data of the specified length is data composed of multiple binary values 0.
综上所述,在本申请实施例提供的存储器的数据写入装置中,接收模块接收控制器指示向存储器写入指定长度的数据的写指令,写入模块基于写指令向存储器的存储介质写入指定长度的数据。由于写指令能够指定待写入数据的长度,使得在需要写入指定长度的数据时,能够减少需要发送的写指令的条数,减小了写指令的开销。并且,由于需要发送的写指令的条数减少了,存储器需要等待的指令间隔随之减短,能够利用节省出的时间写入其他数据,从而降低了存储器的写时延,并有效提升存储器的写带宽。To sum up, in the data writing device of the memory provided by the embodiment of the present application, the receiving module receives a write instruction from the controller indicating to write data of a specified length to the memory, and the writing module writes to the storage medium of the memory based on the write instruction. Enter the data of the specified length. Since the write command can specify the length of the data to be written, when the data of the specified length needs to be written, the number of write commands to be sent can be reduced, reducing the overhead of the write command. Moreover, since the number of write instructions that need to be sent is reduced, the instruction interval that the memory needs to wait for is shortened accordingly, and the saved time can be used to write other data, thereby reducing the write delay of the memory and effectively improving the performance of the memory. Write bandwidth.
所属领域的技术人员可以清楚地了解到,为描述的方便和简洁,上述描述的装置和模块的具体工作过程,可以参考前述方法实施例中的对应内容,在此不再赘述。Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the above-described devices and modules can refer to the corresponding content in the foregoing method embodiments, which will not be repeated here.
本申请实施例提供了一种计算机设备。图1所示的存储系统可以部署在该计算设备中。该计算机设备包括存储器和处理器,存储器存储有程序指令,处理器运行程序指令以执行本申请提供的存储器的数据写入方法或执行本申请提供的存储器的数据写入方法的任一步骤。The embodiment of the present application provides a computer device. The storage system shown in FIG. 1 can be deployed in the computing device. The computer device includes a memory and a processor, the memory stores program instructions, and the processor executes the program instructions to execute the method for writing data into the memory provided by this application or to execute any step of the method for writing data to a memory provided by this application.
图9是本申请实施例提供的一种计算机设备90的结构示意图。如图9所示,该计算机设备90包括存储器901、处理器902、通信接口903以及总线904。其中,存储器901、处理器902、通信接口903通过总线904实现彼此之间的通信连接。并且,该计算机设备90可以包括多个处理器902,以便于通过不同的处理器实现上述不同功能模块的功能。FIG. 9 is a schematic structural diagram of a computer device 90 provided by an embodiment of the present application. As shown in FIG. 9 , the computer device 90 includes a memory 901 , a processor 902 , a communication interface 903 and a bus 904 . Wherein, the memory 901 , the processor 902 , and the communication interface 903 are connected to each other through a bus 904 . Moreover, the computer device 90 may include multiple processors 902, so that different processors may be used to realize the functions of the above-mentioned different functional modules.
存储器901可以是只读存储器(read only memory,ROM),静态存储设备,动态存储设备或者随机存取存储器(random access memory,RAM)。存储器901可以存储可执行代码序,当存储器901中存储的可执行代码被处理器902执行时,处理器902和通信接口903用于执行本申请实施例提供的存储器的数据写入方法。存储器901中还可以包括操作系统等其他运行进程所需的软件模块和数据等。The memory 901 may be a read only memory (read only memory, ROM), a static storage device, a dynamic storage device or a random access memory (random access memory, RAM). The memory 901 can store executable codes. When the executable codes stored in the memory 901 are executed by the processor 902, the processor 902 and the communication interface 903 are used to execute the method for writing data into the memory provided by the embodiment of the present application. The memory 901 may also include software modules and data required by other running processes such as an operating system.
处理器902可以采用通用的中央处理器(central processing unit,CPU),微处理器,应用专用集成电路(application specific integrated circuit,ASIC),图形处理器(graphics processing unit,GPU)或者一个或多个集成电路。The processor 902 may be a general-purpose central processing unit (central processing unit, CPU), a microprocessor, an application specific integrated circuit (application specific integrated circuit, ASIC), a graphics processing unit (graphics processing unit, GPU) or one or more integrated circuit.
处理器902还可以是一种集成电路芯片,具有信号的处理能力。在实现过程中,本申请的存储器的数据写入方法的部分或全部功能可以通过处理器902中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器902还可以是通用处理器、数字信号处理器(digital signal processing,DSP)、专用集成电路(ASIC)、现成可编程门阵列(fieldprogrammable gate array,FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本申请实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本申请实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成,或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器,闪存、只读存储器,可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器901,处理器902读取存储器901中的信息,结合其硬件完成本申请实施例的存储器的数据写入方法。The processor 902 may also be an integrated circuit chip, which has a signal processing capability. During implementation, part or all of the functions of the data writing method of the memory of the present application may be implemented by an integrated logic circuit of hardware in the processor 902 or instructions in the form of software. The aforementioned processor 902 may also be a general-purpose processor, a digital signal processor (digital signal processing, DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (fieldprogrammable gate array, FPGA) or other programmable logic devices, Discrete gate or transistor logic devices, discrete hardware components. Various methods, steps, and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. A general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the field such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, register. The storage medium is located in the memory 901, and the processor 902 reads the information in the memory 901, and combines its hardware to complete the data writing method of the memory in the embodiment of the present application.
通信接口903使用例如但不限于收发器一类的收发模块,来实现计算机设备90与其他设备或通信网络之间的通信。例如,通信接口903可以是以下器件的任一种或任一种组合:网络接口(如以太网接口)、无线网卡等具有网络接入功能的器件。The communication interface 903 uses a transceiver module such as but not limited to a transceiver to implement communication between the computer device 90 and other devices or communication networks. For example, the communication interface 903 may be any one or any combination of the following devices: a network interface (such as an Ethernet interface), a wireless network card and other devices with network access functions.
总线904可包括在计算机设备90各个部件(例如,存储器901、处理器902、通信接口903)之间传送信息的通路。Bus 904 may include pathways for transferring information between various components of computer device 90 (eg, memory 901 , processor 902 , communication interface 903 ).
需要说明的是,当该计算机设备为客户端时,该计算机设备还包括显示屏,该显示屏用于显示程序开发平台的图形用户界面。It should be noted that, when the computer device is the client, the computer device also includes a display screen, which is used to display the graphical user interface of the program development platform.
上述各个附图对应的流程的描述各有侧重,某个流程中没有详述的部分,可以参见其他流程的相关描述。The descriptions of the processes corresponding to the above-mentioned figures have their own emphasis. For the parts not described in detail in a certain process, you can refer to the relevant descriptions of other processes.
在上述实施例中,可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时,可以全部或部分地以计算机程序产品的形式实现。提供程序开发平台的计算机程序产品包括一个或多个计算机指令,在计算机设备上加载和执行这些计算机程序指令时,全部或部分地实现本申请实施例提供的存储器的数据写入方法的流程或功能。In the above embodiments, all or part of them may be implemented by software, hardware, firmware or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product that provides the program development platform includes one or more computer instructions, and when these computer program instructions are loaded and executed on the computer device, the process or function of the data writing method of the memory provided by the embodiment of the present application is fully or partially realized .
计算机设备可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。计算机指令可以存储在计算机可读存储介质中,或者从一个计算机可读存储介质向另一个计算机可读存储介质传输,例如,计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。计算机可读存储介质存储有提供程序开发平台的计算机程序指令。The computer equipment can be a general purpose computer, special purpose computer, a computer network, or other programmable apparatus. Computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, e.g. Coaxial cable, optical fiber, digital subscriber line or wireless (such as infrared, wireless, microwave, etc.) transmission to another website site, computer, server or data center.Computer-readable storage medium stores a computer program that provides a program development platform instruction.
本申请实施例还提供了一种计算机可读存储介质,该计算机可读存储介质为非易失性计算机可读存储介质,该计算机可读存储介质包括程序指令,当程序指令在计算机设备上运行时,使得计算机设备执行如本申请实施例提供的存储器的数据写入方法。The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium is a non-volatile computer-readable storage medium. The computer-readable storage medium includes program instructions. When the program instructions are run on the computer device When, the computer device is made to execute the method for writing data into the memory as provided in the embodiment of the present application.
本申请实施例还提供了一种包含指令的计算机程序产品,当计算机程序产品在计算机上运行时,使得计算机执行本申请实施例提供的存储器的数据写入方法。The embodiment of the present application also provides a computer program product including instructions, and when the computer program product is run on the computer, the computer is made to execute the method for writing data into the memory provided in the embodiment of the present application.
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成,也可以通过程序来指令相关的硬件完成,所述的程序可以存储于一种计算机可读存储介质中,上述提到的存储介质可以是只读存储器,磁盘或光盘等。Those of ordinary skill in the art can understand that all or part of the steps for implementing the above embodiments can be completed by hardware, and can also be completed by instructing related hardware through a program. The program can be stored in a computer-readable storage medium. The above-mentioned The storage medium mentioned may be a read-only memory, a magnetic disk or an optical disk, and the like.
需要说明的是,本申请所涉及的信息(包括但不限于用户设备信息、用户个人信息等)、数据(包括但不限于用于分析的数据、存储的数据、展示的数据等)以及信号,均为经用户授权或者经过各方充分授权的,且相关数据的收集、使用和处理需要遵守相关国家和地区的相关法律法规和标准。例如,本申请中涉及到的阻值信息都是在充分授权的情况下获取的。It should be noted that the information (including but not limited to user equipment information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application, All are authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with the relevant laws, regulations and standards of the relevant countries and regions. For example, the resistance value information involved in this application is obtained under full authorization.
在本申请实施例中,术语“第一”、“第二”和“第三”仅用于描述目的,而不能理解为指示或暗示相对重要性。术语“至少一个”是指一个或多个,术语“多个”指两个或两个以上,除非另有明确的限定。In the embodiments of the present application, the terms "first", "second" and "third" are used for description purposes only, and cannot be understood as indicating or implying relative importance. The term "at least one" means one or more, and the term "plurality" means two or more, unless otherwise clearly defined.
本申请中术语“和/或”,仅仅是一种描述关联对象的关联关系,表示可以存在三种关系,例如,A和/或B,可以表示:单独存在A,同时存在A和B,单独存在B这三种情况。另外,本文中字符“/”,一般表示前后关联对象是一种“或”的关系。The term "and/or" in this application is only an association relationship describing associated objects, which means that there may be three relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and A and B exist alone. There are three cases of B. In addition, the character "/" in this article generally indicates that the contextual objects are an "or" relationship.
以上所述仅为本申请的可选实施例,并不用以限制本申请,凡在本申请的构思和原则之内,所作的任何修改、等同替换、改进等,均应包含在本申请的保护范围之内。The above are only optional embodiments of the application, and are not intended to limit the application. Any modifications, equivalent replacements, improvements, etc. made within the concept and principles of the application shall be included in the protection of the application. within range.
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