CN116705114A - Memory data writing method and device - Google Patents

Abstract

The application discloses a method and device for writing data into a memory, belonging to the technical field of memory. The method includes: the memory receives a write instruction from the controller indicating to write data of a specified length into the memory; and the memory writes the data of the specified length to a storage medium of the memory based on the write instruction. Since the write command can specify the length of the data to be written, when the data of the specified length needs to be written, the number of write commands to be sent can be reduced, reducing the overhead of the write command.

Description

Memory data writing method and device

technical field

The present application relates to the technical field of storage, and in particular to a method and device for writing data into a storage.

Background technique

In the field of storage technology, when the controller writes data to the storage medium of the memory, the controller needs to send a write instruction and the data to be written to the memory, so as to instruct writing the data to be written into the storage medium of the memory.

Generally, the length of the data to be written that can be indicated by the write command sent by the controller to the same memory is the same and a fixed value.

However, when the same data (such as 0 or 1) needs to be written continuously, if the total length of the data is greater than the length of the data to be written that can be written by one write command, the controller needs to send multiple write commands and data, resulting in Writing data is expensive.

Contents of the invention

The present application provides a data writing method and device for a memory. The present application reduces the overhead of writing instructions. The technical scheme that this application provides is as follows:

In a first aspect, the present application provides a data writing method of a memory, the data writing method includes: the memory receives a write instruction from the controller indicating to write data of a specified length to the memory; the memory writes data to the storage medium of the memory based on the write instruction Write data of the specified length.

In the data writing method of the memory provided by the present application, the memory receives a write instruction from the controller indicating to write data of a specified length to the memory, and the memory writes data of the specified length to the storage medium of the memory based on the write instruction. Since the write command can specify the length of the data to be written, when the data of the specified length needs to be written, the number of write commands to be sent can be reduced, reducing the overhead of the write command. Moreover, since the number of write instructions that need to be sent is reduced, the instruction interval that the memory needs to wait for is shortened accordingly, and the saved time can be used to write other data, thereby reducing the write delay of the memory and effectively improving the performance of the memory. Write bandwidth.

In a practicable manner, since the memory includes multiple storage arrays, the data access process among the multiple storage arrays does not affect each other, and writing data to the storage arrays is realized by controlling bit lines and word lines of the storage arrays. Moreover, each bit line corresponds to an address range, and different bit lines correspond to different address ranges, and the addresses corresponding to multiple bit lines connected to the same storage array constitute a segment of addresses within the address range of the storage array. Each word line corresponds to an address range, and different word lines correspond to different address ranges, and the addresses corresponding to multiple word lines connected to the same memory array constitute a segment of addresses within the address range of the memory array. And, each storage array corresponds to a range of addresses, and different storage arrays correspond to different address ranges, and addresses corresponding to multiple storage arrays in the same storage form a range of addresses within the address range of the memory. Therefore, the specified length is reflected by any one or more of the following: the total number of bit lines whose addresses need to be controlled to write data based on the write command, the total number of word lines whose addresses need to be controlled to write data based on the write command, and, The total number of memory arrays whose addresses are contiguous to which data is written based on the write command.

In a practicable manner, the bit lines with consecutive addresses may be a plurality of bit lines to which electrical signals are sequentially applied when bit line scanning is performed on the memory. Usually, multiple bit lines with consecutive addresses are arranged sequentially on the memory array. Similarly, the word lines with consecutive addresses may be a plurality of word lines to which electrical signals are sequentially applied when the memory is scanned for the word lines. And multiple word lines with consecutive addresses are usually deployed in sequence on the memory array. The storage arrays with continuous addresses may be multiple storage arrays into which data is sequentially written when data needs to be continuously written into multiple storage arrays in the memory. And multiple storage arrays with consecutive addresses are usually deployed sequentially on the memory.

In a possible implementation scenario, the write instruction also indicates that the current value of the current signal used to execute the write operation indicated by the write instruction is less than a reference value, and the reference value is used for the write operation indicated by the write instruction that does not indicate the current value. The current value of the current signal.

The write instruction indicates that the current value of the current signal used to perform the write operation is smaller than the reference value, so that the power consumption of the write operation can be reduced. Moreover, since the power consumption of the write operation is relatively low, for a memory including multiple storage arrays, the controller can concurrently send access instructions to the multiple storage arrays of the memory according to the power consumption of the memory, so as to store data in the multiple storage arrays. Flexible bandwidth allocation and power consumption allocation between arrays to meet more application requirements.

In another possible implementation scenario, the write instruction further indicates that data of a specified length is allowed to be written in one or more periods according to the power consumption of the memory.

When the write instruction indicates that data of a specified length is allowed to be written in multiple time periods according to the power consumption of the memory, the memory can select the data of the specified length to be written in each of the multiple time periods according to the overall power consumption of the memory. Part of the data, in order to achieve the purpose of reducing the overall power consumption of the memory.

In yet another possible implementation scenario, the write instruction also indicates: for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data written to the storage address indicated by the write instruction, based on the write instruction, the A write operation is performed on the storage address, and when the data stored at the storage address is the same as the data written to the storage address indicated by the write instruction, no write operation is performed on the storage address.

When the data stored at the storage address is the same as the data written to the storage address indicated by the write instruction, by not performing a write operation on the storage address, the operation time of the write operation indicated by the write instruction can be effectively reduced, and the memory The fast write can shorten the command interval corresponding to the write command, so that other data can be written in the saved time, the write delay of the memory is reduced, and the write bandwidth of the memory is improved.

Further, the data of the specified length may include multiple pieces of the same data. For example, when the data is represented by a binary value, the data of the specified length is data composed of a plurality of binary values 1, or the data of the specified length is data composed of a plurality of binary values 0.

At this time, by specifying the length in the write command, it is possible to send a write command to indicate to write the data of the specified length. Compared with the write command indicating that the data to be written has the same length and is a fixed value in the related art, there is no need to send multiple write commands. The number of write instructions indicates writing, reducing the number of write instructions that need to be sent.

In a second aspect, the present application provides a data writing device for a memory, the data writing device includes: a receiving module, used to receive a write instruction from the controller indicating to write data of a specified length to the memory; an access module, used to Writing data of a specified length to the storage medium of the memory based on the write command.

Optionally, the memory includes multiple storage arrays, and the data access process between the multiple storage arrays does not affect each other. Writing data to the storage arrays is realized by controlling the bit lines and word lines connected to the storage arrays. The specified length is as follows Any one or more reflections: the total number of address continuous bit lines that need to be controlled based on the write command to write data, the total number of address continuous word lines that need to be controlled based on the write command to write data, and, based on the write command to be written The total number of memory arrays whose data addresses are contiguous.

Optionally, the write instruction also indicates that the current value of the current signal used to execute the write operation indicated by the write instruction is less than a reference value, and the reference value is the current of the current signal used by the write operation indicated by the write instruction that does not indicate the current value. value.

Optionally, the write instruction also indicates that data of a specified length is allowed to be written in one or more periods according to the power consumption of the memory.

Optionally, the write instruction also indicates: for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data written to the storage address indicated by the write instruction, perform a write operation on the storage address based on the write instruction , when the stored data at the storage address is the same as the data written to the storage address indicated by the write instruction, no write operation is performed on the storage address.

Optionally, the data of the specified length is data composed of multiple binary values 1, or the data of the specified length is data composed of multiple binary values 0.

In a third aspect, the present application provides a computer device, including a memory and a processor, the memory stores program instructions, and the processor executes the program instructions to perform the method provided in the first aspect of the present application and any possible implementation thereof .

In a fourth aspect, the present application provides a computer-readable storage medium. The computer-readable storage medium is a non-volatile computer-readable storage medium. The computer-readable storage medium includes program instructions. When the program instructions are stored on a computer device During operation, the computer device is made to execute the method provided in the first aspect of the present application and any possible implementation manner thereof.

In a fifth aspect, the present application provides a computer program product containing instructions, which, when the computer program product is run on a computer, cause the computer to execute the method provided in the first aspect of the present application and any possible implementation thereof.

Description of drawings

FIG. 1 is a schematic diagram of an application scenario involved in a data writing method of a memory provided by an embodiment of the present application;

FIG. 2 is a schematic diagram of a transmission write instruction and data to be written provided by an embodiment of the present application;

Fig. 3 is a schematic diagram of another transmission of write instructions and data to be written provided by the embodiment of the present application;

FIG. 4 is a schematic structural diagram of a memory provided by an embodiment of the present application;

Fig. 5 is a schematic structural diagram of a storage component provided by an embodiment of the present application;

FIG. 6 is a schematic diagram of a storage array provided by an embodiment of the present application;

FIG. 7 is a flow chart of a method for writing data into a memory according to an embodiment of the present application;

FIG. 8 is a schematic structural diagram of a device for writing data into a memory according to an embodiment of the present application;

FIG. 9 is a schematic structural diagram of a computer device provided by an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the implementation manners of the present application will be further described in detail below in conjunction with the accompanying drawings.

Currently, in the field of storage technology, when the controller writes data to the storage medium of the memory, the controller needs to send a write instruction and the data to be written to the memory to instruct writing the data to be written into the storage medium of the memory. Moreover, the length of the data to be written that can be indicated by the write command sent by the controller to the same memory is the same and a fixed value. Therefore, when the same data (such as 0 or 1) needs to be written continuously, if the total length of the data is greater than the length of the data to be written that can be written by one write command, the controller needs to send multiple write commands and data, resulting in Writing data is expensive. Moreover, since the improvement of the memory write bandwidth (especially the write bandwidth of continuous writing to the same storage array) is restricted by the instruction interval (time write to write, tW2W), when a large number of instructions need to be sent, the execution interval that needs to be waited for is longer, resulting in memory Write bandwidth will be affected. Wherein, the memory includes one or more storage arrays (banks), and the data access process among the multiple storage arrays does not affect each other.

An embodiment of the present application provides a method for writing data into a memory. The method includes: the memory receives a write instruction from the controller indicating to write data of a specified length into the memory, and the memory writes the data of the specified length to a storage medium of the memory based on the write instruction. Since the write command can specify the length of the data to be written, when the data of the specified length needs to be written, the number of write commands to be sent can be reduced, reducing the overhead of the write command. Moreover, since the number of write instructions that need to be sent is reduced, the instruction interval that the memory needs to wait for is shortened accordingly, and the saved time can be used to write other data, thereby reducing the write delay of the memory and effectively improving the performance of the memory. Write bandwidth.

FIG. 1 is a schematic structural diagram of an implementation environment involved in a method for writing data into a memory provided by an embodiment of the present application. As shown in FIG. 1 , the implementation environment includes: a processor 01 and a storage system 02 . Optionally, the storage system 02 may be a storage chip. Also, the storage system 02 includes a controller 021 and a memory 022 . A communication connection is established between the processor 01 and the controller 021 , and a communication connection is established between the controller 021 and the memory 022 . The processor 01 is used to indicate the write requirement to the controller 021 , that is, to notify the controller 021 of the logical address of the data to be written that needs to be written. The controller 021 is configured to determine a physical address for writing data to be written according to an instruction of the processor 01, and send a write instruction to the memory 022 according to the physical address and the data to be written. The memory 022 is used to write the data to be written into the corresponding physical address according to the write instruction.

Optionally, the processor 01 may be a hardware chip, and the hardware chip may be an application-specific integrated circuit (application-specific integrated circuit, ASIC), a programmable logic device (programmablelogic device, PLD) or a combination thereof. The aforementioned PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), a general array logic (generic array logic, GAL) or any combination thereof. Alternatively, the processor 01 may be a general processor, for example, a central processing unit (central processing unit, CPU), a network processor (network processor, NP), or a combination of a CPU and an NP.

The memory 022 can be a nonvolatile memory such as a phase change memory (phase change memory, PCM), a spin transfer torque memory (shared transistor technology random access memory, STT-RAM), or a variable resistance memory (resistive random-access memory, RRAM). Lost memory (non-volatile memory, NVM). The embodiment of the present application is described by taking the memory 022 as a phase change memory as an example. Phase change memory is a new type of non-volatile semiconductor memory based on chalcogenides. The memory 022 includes a plurality of storage units. The storage medium of each storage unit is realized by phase-change material, which stores 0/1 bit information by utilizing the difference in electrical characteristics between the crystalline state and the amorphous state of the phase-change material. Among them, the high-resistance amorphous state is defined as the write 0 state (ie, the RESET (0) state), and the low-resistance crystalline state is defined as the write 1 state (ie, the SET (1) state, also called the erase 1 state). The write 0 state is obtained by performing a write operation on the memory cell. The write operation is realized by applying a high-amplitude and narrow-width electrical pulse to the memory cell. Under the action of this electric pulse, the temperature of the phase change material is rapidly raised above the melting temperature and then quenched. Since the microscopic atoms of the phase change material do not have sufficient time to crystallize during this process, the phase change material remains at a high temperature. Resistant amorphous state. The erase 1 state is obtained by performing an erase operation on a memory cell. The erasing operation is realized by applying an electrical pulse with a lower amplitude than that of the write operation to the memory cell, but with a relatively longer duration. Under the action of this electric pulse, the temperature of the phase change material is raised above the crystallization temperature and below the melting temperature, during which the phase change material can be transformed into a low-resistance state through a thermally induced crystallization process. The read operation of the phase change memory 022 is realized by applying an electric pulse with a lower magnitude than that of the write operation and the erase operation to the memory cell. Under the action of this electric pulse, the resistance value information of the phase change material is sensed by the read circuit in the form of current or voltage, thereby realizing the read operation of the memory cell. Wherein, since the writing operation and the erasing operation both write data to the storage unit, the writing operation in the embodiment of the present application does not distinguish whether it is a writing operation or an erasing operation.

In the embodiment of the present application, the storage 022 can be used as a memory for temporarily storing data required for the operation of the processor 01 . Correspondingly, the controller 021 may be a memory controller. Moreover, an application scenario of the data writing method of the memory 022 provided in the embodiment of the present application may be: the processor 01 generates calculation data during operation, and the calculation data needs to be stored in the memory. In this application scenario, the cooperative process between the processor 01, the controller 021, and the memory includes: the processor 01 indicates to the controller 021 that the operation data needs to be stored, and the controller 021 acquires the operation data and stores them in the memory. Determine the storage address for storing the operation data in the space, and then send the write instruction and operation data to the memory according to the operation data and storage address, and the memory stores the operation data at the corresponding storage address according to the write instruction.

Wherein, the write command and the data to be written can be sent through different ports. For example, when it is necessary to send write instructions and operation data to the memory, as shown in Figure 2 and Figure 3, port 1 can be used to send write instructions to the memory, and port 2 can be used to send operation data to the memory. Also, the write command may include the write command itself for instructing the write operation and a storage address for storing the data to be written. In a practicable manner, the write instruction itself and the storage address can be sent to the memory through the same port. For example, as shown in Figure 2, port 1 can be used to send the write command itself and the storage address to the memory. Alternatively, the write command itself and the store address can be sent to memory through separate ports. For example, as shown in FIG. 3 , port 1 may be used to send the write command itself to the memory, and port 3 may be used to send the storage address to the memory.

In one implementable manner, as shown in FIG. 4 , the memory 022 includes: a storage component 0221 , a drive circuit 0222 , a control component 0223 and an input/output (input/output, I/O) port 0224 . The implementation process of the method for writing data to the memory 022 provided in the embodiment of the present application can be implemented through the cooperation of the control component 0223 , the driving circuit 0222 , the storage component 0221 and the I/O port 0224 . Wherein, the control component 0223 is configured to determine the control parameters required to execute the access operation indicated by the write instruction, and instruct the drive circuit 0222 to provide a drive signal to the storage component 0221 according to the control parameters. The storage component 0221 is used for writing data under the driving signal.

As shown in Figure 5, the storage component 0221 includes one or more storage arrays (bank) 0221a, and the data access process between the multiple storage arrays 0221a does not affect each other, that is, each storage array 0221a can accept reads and writes independently or in parallel instruction and complete the corresponding operation. Each memory array 0221a includes a plurality of memory cells a1. Each memory cell a1 is connected to a word line (word line, WL) and a bit line (bit line, BL), and at least one of the word line and the bit line connected to different memory cells a1 is different. The read and write operations on different memory cells a1 can be implemented by applying electrical signals to the word lines and bit lines connected to the corresponding memory cells a1. And when at least one of the word line and the bit line to which the electrical signal is applied during the read and write operations is different, the memory cells a1 affected by the read and write operations are different. For example, as shown in FIG. 6, a plurality of bit lines BL and a plurality of word lines WL are arranged in a criss-cross pattern on the memory array 0221a, and the plurality of word lines WL are arranged in sequence along the column direction, and each word line WL is arranged along the row direction. Extending, a plurality of bit lines BL are arranged in sequence along the row direction, and each bit line BL extends along the column direction. Each memory cell a1 is respectively connected to a bit line BL and a word line WL, and at least one of the word line WL and the bit line BL connected to different memory cells a1 is different.

In one implementable manner, as shown in FIG. 6 , the storage unit a1 includes a variable resistor R and a gate device T connected in series. The variable resistor R is used as a storage medium of the storage unit a1 for storing information. Moreover, the material for making the variable resistor R includes a phase change material. One end of the variable resistor R is connected to the bit line BL, the other end of the variable resistor R is connected to the first port of the strobe device T, and the word line WL is connected to the second port of the strobe device T. The voltage difference between the word line WL and the bit line BL determines the opening and closing of the loop between the bit line and the word line. For example, the loop between the word line WL and the bit line BL is opened when the voltage difference between the word line WL and the bit line BL is greater than a certain threshold voltage. When the loop between the bit line and the word line is opened, the electrical signal applied on the bit line BL can be transmitted to the variable resistor R, and the data writing and writing to the variable resistor R can be realized under the control of the electrical signal. read.

It should be understood that the above content is an exemplary description of the application scenario of the method for writing data to the memory provided by the embodiment of the present application, and does not constitute a limitation on the application scenario of the event analysis method. As business requirements change, its application scenarios can be adjusted according to application requirements, and the embodiments of this application do not list them one by one.

The following uses the application scenario shown in FIG. 1 as an example to describe the implementation process of the method for writing data into the memory provided by the embodiment of the present application. As shown in Figure 7, the implementation process of the data writing method of the memory may include the following steps:

Step 701, the memory receives a write instruction from the controller indicating to write data of a specified length into the memory.

According to the foregoing content, the storage system includes a controller and a memory, and the controller is configured to send a write instruction to the memory. For example, when the memory is used as a memory, the processor is used to indicate to the controller that the operation data needs to be stored. After the controller obtains the operation data, it can determine the storage address for storing the operation data in the storage space of the memory, and then Sending the write instruction and the operation data to the memory according to the operation data and the storage address, so that the memory stores the operation data at the corresponding storage address according to the write instruction.

Since the memory includes multiple storage arrays, the data access process between the multiple storage arrays does not affect each other, and writing data to the storage arrays is realized by controlling the bit lines and word lines of the storage arrays. Moreover, each bit line corresponds to an address range, and different bit lines correspond to different address ranges, and the addresses corresponding to multiple bit lines connected to the same storage array constitute a segment of addresses within the address range of the storage array. Each word line corresponds to an address range, and different word lines correspond to different address ranges, and the addresses corresponding to multiple word lines connected to the same memory array constitute a segment of addresses within the address range of the memory array. And, each storage array corresponds to a range of addresses, and different storage arrays correspond to different address ranges, and addresses corresponding to multiple storage arrays in the same storage form a range of addresses within the address range of the memory. Therefore, the specified length can be reflected by any one or more of the following: the total number of address continuous bit lines that need to be controlled based on the write command to write data, the total number of address continuous word lines that need to be controlled based on the write command to write data, and , the total number of memory arrays whose addresses are contiguous to which data is written based on the write command.

In a practicable manner, the bit lines with consecutive addresses may be a plurality of bit lines to which electrical signals are sequentially applied when bit line scanning is performed on the memory. Usually, multiple bit lines with consecutive addresses are arranged sequentially on the memory array. Also, for every two adjacent bit lines, the first address of the latter bit line can be equal to the maximum address of the previous bit line+1. For example, as shown in Figure 6, bit lines BL(1), bit line BL(2) and bit line BL(3) on the memory array are bit lines arranged continuously, and when the memory is scanned for bit lines, the The electrical signal is applied to the bit line BL(1), bit line BL(2) and bit line BL(3) in sequence, so the bit line BL(1), bit line BL(2) and bit line BL(3) are address continuous bit lines.

In a practicable manner, the word lines with consecutive addresses may be a plurality of word lines to which electrical signals are sequentially applied when the memory is scanned for the word lines. Usually, multiple word lines with consecutive addresses are arranged sequentially on the memory array. And, for every two adjacent word lines, the first address of the next word line can be equal to the maximum address+1 of the previous word line. For example, as shown in FIG. 6, the word line WL(1), word line WL(2) and word line WL(3) on the memory array are word lines arranged continuously, and when the memory is scanned for the word lines, the Apply electrical signals to word line WL(1), word line WL(2) and word line WL(3) in sequence, so the word line WL(1), word line WL(2) and word line WL(3) are address continuous word lines.

In a practicable manner, the storage arrays with consecutive addresses may be multiple storage arrays into which data is sequentially written when data needs to be continuously written into multiple storage arrays in the memory. Generally, multiple storage arrays with consecutive addresses are deployed sequentially on the memory. Moreover, for every two storage arrays with adjacent logical addresses, the first address of the latter storage array may be equal to the maximum address+1 of the previous storage array. For example, as shown in FIG. 5, the memory 0221 includes a plurality of storage arrays 0221a arranged in sequence, and when data is continuously written to the multiple storage arrays 0221a in the memory 0221, the storage array 0221a(1) and the storage array 0221a (2) Data is written, so the memory array 0221a(1) and the memory array 0221a(2) are memory arrays with consecutive addresses.

In this embodiment of the application, the data of the specified length may include multiple pieces of the same data. For example, when the data is represented by a binary value, the data of the specified length may be data composed of a plurality of binary values 1, or the data of the specified length may be data composed of a plurality of binary values 0. At this time, by specifying the length in the write command, it is possible to send a write command to indicate to write the data of the specified length. Compared with the write command indicating that the data to be written has the same length and is a fixed value in the related art, there is no need to send multiple write commands. The number of write instructions indicates writing, reducing the number of write instructions that need to be sent.

In a practicable manner, the write instruction may also indicate that the current value of the current signal used to perform the write operation indicated by the write instruction is smaller than the reference value. Wherein, the reference value is the current value of the current signal used to execute the write operation indicated by the write instruction not indicating the current value. When performing a write operation to a memory cell, it is necessary to apply a current pulse signal to the bit line connected to the memory cell, and to apply a gate enabling voltage signal to the word line connected to the memory cell, so that the electrical characteristics of the storage medium of the memory cell Changes under the action of a signal in order to store information through changed electrical properties. Therefore, when the write instruction does not indicate a current value, the current value of the current pulse signal applied to the bit lines connected to all memory cells in the same memory array may be the same, and the current value is the reference value. When the write instruction indicates that the current value of the current signal used for the write operation indicated by the write instruction is smaller than the reference value, it means that the write instruction indicates that a smaller current or a transient operating current is used to perform the write operation. In an implementable manner, using a smaller current or a transient operating current to perform the write operation can be achieved by reducing the number of bits operated by the write operation at the same time.

The write instruction indicates that the current value of the current signal used to perform the write operation is smaller than the reference value, so that the power consumption of the write operation can be reduced. Moreover, since the power consumption of the write operation is relatively low, for a memory including multiple storage arrays, the controller can concurrently send access instructions to the multiple storage arrays of the memory according to the power consumption of the memory, so as to store data in the multiple storage arrays. Flexible bandwidth allocation and power consumption allocation between arrays to meet more application requirements. Since the write command indicates that using a smaller current or a transient operating current to perform the write operation can reduce the power consumption of the write operation, the write command may also be referred to as a low power write command.

In another practicable manner, the write instruction may also indicate that data of a specified length is allowed to be written in one or more periods according to the power consumption of the memory. Wherein, the power consumption of the memory includes the sum of the power consumption of multiple storage arrays in the memory. When the write instruction indicates that data of a specified length is allowed to be written in multiple time periods according to the power consumption of the memory, the memory can select the data of the specified length to be written in each of the multiple time periods according to the overall power consumption of the memory. Part of the data, in order to achieve the purpose of reducing the overall power consumption of the memory. Since writing data according to the instruction of the write instruction can also reduce the power consumption of the memory, the write instruction can also be called a low-power write instruction.

In yet another practicable manner, the write instruction may also indicate: for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data written to the storage address indicated by the write instruction, based on the write The instruction performs a write operation on the storage address, and when the data stored in the storage address is the same as the data written in the storage address indicated by the write instruction, the write operation is not performed on the storage address. For example, assume that the stored data of a certain storage address are all 1, and the write instruction indicates that when the stored data of the storage address is different from the data written to the storage address indicated by the write instruction, the write operation is performed on the storage address based on the write instruction , when the stored data at the storage address is the same as the data written to the storage address indicated by the write instruction, no write operation is performed on the storage address. Then, when executing the write operation indicated by the write instruction, when the bit data to be written into the storage address is 0, the data stored in the bit needs to be refreshed to 0, and when the data to be written into the storage address When the data of a bit is 1, no operation is performed on the bit. Since there is no need to perform operations on bits at this time, fast writing to the memory can be realized.

When the data stored at the storage address is the same as the data written to the storage address indicated by the write instruction, by not performing a write operation on the storage address, the operation time of the write operation indicated by the write instruction can be effectively reduced, and the memory The fast write can shorten the command interval corresponding to the write command, so that other data can be written in the saved time, the write delay of the memory is reduced, and the write bandwidth of the memory is improved. Since the write command can reduce the operation time for performing the write operation, the write command may be called a fast write command.

Corresponding to the fast write instruction, a possible application scenario may be: before performing a write operation on consecutive addresses of the memory, the controller instructs the memory to write all the consecutive addresses into a unified value in advance, so that the memory can When the instruction executes the write operation, it only needs to operate on the bits that are different from the data stored in the continuous address and the data indicated by the write instruction. For example, when a certain storage array of the memory is idle, the controller can control the memory to write the bits of the consecutive addresses of the specified length of the storage array to a uniform value through a write command or a low-power write command indicating to write data of a specified length. , so that when the controller receives an urgent data write request, it can use a fast write command to perform a write operation in the continuous address. Wherein, the uniform value can be set according to the performance of the memory, for example, when the speed of writing 0 to the memory is fast and the speed of writing 1 is slow, the uniform value can be 1.

In addition, the write command can also directly specify the data to be written, such as specifying to write a binary value of 1 or 0. The write command indicates to write a binary value 1 of a specified length or a binary value 0 of a specified length, so that the data to be written does not need to be transmitted through the data bus, and the power consumption of data transmission can be reduced. At this time, the write command may also be called a write 1 command or a write 0 command, or may also be called a write command with a specified length of 0 or a command with a specified length of 1. Similarly, the above-mentioned low-power write instruction can also be called a low-power write 1 instruction or a low-power write 0 instruction, or it can also be called a low-power write instruction with a specified length of 0 or a low-power write instruction with a specified length of 1. instruction. The above-mentioned fast write command may also be called a fast write 1 command or a fast write 0 command, or it may also be called a fast write specified length 0 command or a fast write specified length 1 command.

Step 702, the memory writes data of a specified length to the storage medium of the memory based on the write instruction.

After the memory receives the write instruction sent by the controller, it can execute a write operation according to the write instruction, and write the data to be written to the storage medium of the memory. Moreover, when the content indicated by the write operation is different, the implementation of the write operation is slightly different. The implementation of the corresponding write operation is carried out in various situations for the various implementations of the write instruction in step 701. illustrate.

In the first case, when the specified length of the write command is reflected based on the total number of consecutive address bit lines that need to be controlled by the write command to write data, the memory can perform the write operation indicated by the write command according to the The write command finds the first storage address indicated by the write command according to the level of the storage array, word line and bit line in turn, and then performs a write operation on the first storage address, and then adds one to the address of the bit line to find the write The second storage address indicated by the instruction, and then perform the write operation on the second storage address, and so on, traverse and execute the write operation according to the level of the bit line, word line and storage array, until the write operation indicated by the write instruction is completed Enter operation.

In the second case, when the specified length of the write command is reflected based on the total number of word lines with consecutive addresses that need to be controlled by the write command to write data, the memory may, during the process of executing the write operation indicated by the write command, according to the The write command finds the first storage address indicated by the write command according to the level of the storage array, word line and bit line in turn, and then performs a write operation on the first storage address, and then adds one to the address of the word line to find the write address. The second storage address indicated by the instruction, and then perform the write operation on the second storage address, and so on, traverse and execute the write operation according to the level of the word line, bit line and storage array, until the write operation indicated by the write instruction is completed Enter operation.

In the third case, when the specified length of the write command is reflected based on the total number of memory arrays with continuous addresses that need to be controlled by the write command, the memory may, during the process of executing the write operation indicated by the write command, according to the The write command finds the first storage address indicated by the write command according to the level of the storage array, bit line and word line in turn, and then performs a write operation on the first storage address, and then adds one to the address of the storage array to find the write The second storage address indicated by the instruction, and then perform the write operation on the second storage address, and so on, traverse and execute the write operation according to the level of the storage array, bit line and word line, until the write operation indicated by the write instruction is completed Enter operation. For example, arrow b1 in FIG. 5 is the direction in which the storage address of the memory array 0021a increases, and arrow b2 in FIG. The arrow b3 in 6 is the direction of scanning the word line WL on the memory array 0221a, that is, the direction in which the storage address of the word line WL increases, and the memory array, bit line and word line can be traversed in this order.

In the fourth case, when the data of the specified length in the write command includes a plurality of identical data, the memory may, according to the write command indicate the The bits of the storage address of the specified length are directly refreshed to the same data.

In the fifth case, when the write instruction also indicates that the current value of the current signal used for the write operation indicated by the write instruction is smaller than the reference value, the memory may send A current pulse signal is applied to the bit line connected to the memory cell indicated by the write instruction, and the current value of the current pulse signal is less than a reference value, and a gate enabling voltage signal is applied to the word line connected to the memory cell to complete the write instruction instruction write operation.

In the sixth case, when the write instruction also indicates that data of a specified length is allowed to be written in one or more periods according to the power consumption of the memory, the memory can predict that the memory The overall power consumption of the memory is lower, and the data indicated by the write command is written in one or more periods of time when the overall power consumption of the memory is lower, so as to achieve the purpose of reducing the overall power consumption of the memory.

In the seventh case, when the write instruction is the above-mentioned fast write instruction, during the process of the memory executing the write operation indicated by the write instruction, for any storage address indicated by the write instruction, when the data stored at the storage address When the write instruction indicates that the data to be written to the storage address is different, the memory can perform a write operation on the storage address based on the write instruction, when the data stored at the storage address is the same as the data written to the storage address indicated by the write instruction At the same time, the memory may not perform a write operation on the storage address.

It should be noted that during the actual application of the memory, the write instruction may be a combination of some or all of the above multiple implementations. When the write instruction is a combination of the above multiple implementations, when the memory performs the write operation, According to the combination of implementation methods of the write instruction, the writing operation may be performed by comprehensively using the situations corresponding to the implementation methods of the write instruction in the above situations, and the implementation process thereof will not be repeated here.

Step 703, the memory feeds back a write response to the write command to the controller.

After the memory responds to the write command, it may feed back a write response to the write command to the controller, so as to feed back to the controller whether the write operation indicated by the write command is completed. It should be noted that the memory may not feed back the write response to the controller, and at this time, the controller may determine the execution result of the write instruction in other ways. For example, a command delay can be defined, and when the controller does not receive feedback from the memory within a specified period of time after sending the write command, it is determined that the write operation is not completed.

To sum up, in the data writing method of the memory provided by the embodiment of the present application, the memory receives a write instruction from the controller indicating to write data of a specified length to the memory, and the memory writes data of a specified length to the storage medium of the memory based on the write instruction. The data. Since the write command can specify the length of the data to be written, when the data of the specified length needs to be written, the number of write commands to be sent can be reduced, reducing the overhead of the write command. Moreover, since the number of write instructions that need to be sent is reduced, the instruction interval that the memory needs to wait for is shortened accordingly, and the saved time can be used to write other data, thereby reducing the write delay of the memory and effectively improving the performance of the memory. Write bandwidth.

It should be noted that the sequence of steps in the method for writing data into the memory provided by the embodiment of the present application can be adjusted appropriately, and the steps can also be increased or decreased accordingly according to the situation. Any person skilled in the art within the technical scope disclosed in this application can easily think of changes, which should be covered within the scope of protection of this application, and thus will not be repeated here.

The embodiment of the present application also provides a device for writing data into a memory. As shown in Figure 8, the data writing device 80 of this memory comprises:

The receiving module 801 is configured to receive a write instruction from the controller indicating to write data of a specified length into the memory.

The access module 802 is configured to write data of a specified length to the storage medium of the memory based on the write instruction.

Optionally, the memory includes multiple storage arrays, and the data access process between the multiple storage arrays does not affect each other. Writing data to the storage arrays is realized by controlling the bit lines and word lines connected to the storage arrays. The specified length is as follows Any one or more reflections: the total number of address continuous bit lines that need to be controlled based on the write command to write data, the total number of address continuous word lines that need to be controlled based on the write command to write data, and, based on the write command to be written The total number of memory arrays whose data addresses are contiguous.

Optionally, the write instruction also indicates that the current value of the current signal used to execute the write operation indicated by the write instruction is less than a reference value, and the reference value is the current of the current signal used by the write operation indicated by the write instruction that does not indicate the current value. value.

Optionally, the write instruction also indicates that data of a specified length is allowed to be written in one or more periods according to the power consumption of the memory.

Optionally, the write instruction also indicates: for any storage address indicated by the write instruction, when the data stored at the storage address is different from the data written to the storage address indicated by the write instruction, perform a write operation on the storage address based on the write instruction , when the stored data at the storage address is the same as the data written to the storage address indicated by the write instruction, no write operation is performed on the storage address.

Optionally, the data of the specified length is data composed of multiple binary values 1, or the data of the specified length is data composed of multiple binary values 0.

To sum up, in the data writing device of the memory provided by the embodiment of the present application, the receiving module receives a write instruction from the controller indicating to write data of a specified length to the memory, and the writing module writes to the storage medium of the memory based on the write instruction. Enter the data of the specified length. Since the write command can specify the length of the data to be written, when the data of the specified length needs to be written, the number of write commands to be sent can be reduced, reducing the overhead of the write command. Moreover, since the number of write instructions that need to be sent is reduced, the instruction interval that the memory needs to wait for is shortened accordingly, and the saved time can be used to write other data, thereby reducing the write delay of the memory and effectively improving the performance of the memory. Write bandwidth.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the above-described devices and modules can refer to the corresponding content in the foregoing method embodiments, which will not be repeated here.

The embodiment of the present application provides a computer device. The storage system shown in FIG. 1 can be deployed in the computing device. The computer device includes a memory and a processor, the memory stores program instructions, and the processor executes the program instructions to execute the method for writing data into the memory provided by this application or to execute any step of the method for writing data to a memory provided by this application.

FIG. 9 is a schematic structural diagram of a computer device 90 provided by an embodiment of the present application. As shown in FIG. 9 , the computer device 90 includes a memory 901 , a processor 902 , a communication interface 903 and a bus 904 . Wherein, the memory 901 , the processor 902 , and the communication interface 903 are connected to each other through a bus 904 . Moreover, the computer device 90 may include multiple processors 902, so that different processors may be used to realize the functions of the above-mentioned different functional modules.

The memory 901 may be a read only memory (read only memory, ROM), a static storage device, a dynamic storage device or a random access memory (random access memory, RAM). The memory 901 can store executable codes. When the executable codes stored in the memory 901 are executed by the processor 902, the processor 902 and the communication interface 903 are used to execute the method for writing data into the memory provided by the embodiment of the present application. The memory 901 may also include software modules and data required by other running processes such as an operating system.

The processor 902 may be a general-purpose central processing unit (central processing unit, CPU), a microprocessor, an application specific integrated circuit (application specific integrated circuit, ASIC), a graphics processing unit (graphics processing unit, GPU) or one or more integrated circuit.

The processor 902 may also be an integrated circuit chip, which has a signal processing capability. During implementation, part or all of the functions of the data writing method of the memory of the present application may be implemented by an integrated logic circuit of hardware in the processor 902 or instructions in the form of software. The aforementioned processor 902 may also be a general-purpose processor, a digital signal processor (digital signal processing, DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (fieldprogrammable gate array, FPGA) or other programmable logic devices, Discrete gate or transistor logic devices, discrete hardware components. Various methods, steps, and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. A general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the field such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, register. The storage medium is located in the memory 901, and the processor 902 reads the information in the memory 901, and combines its hardware to complete the data writing method of the memory in the embodiment of the present application.

The communication interface 903 uses a transceiver module such as but not limited to a transceiver to implement communication between the computer device 90 and other devices or communication networks. For example, the communication interface 903 may be any one or any combination of the following devices: a network interface (such as an Ethernet interface), a wireless network card and other devices with network access functions.

Bus 904 may include pathways for transferring information between various components of computer device 90 (eg, memory 901 , processor 902 , communication interface 903 ).

It should be noted that, when the computer device is the client, the computer device also includes a display screen, which is used to display the graphical user interface of the program development platform.

The descriptions of the processes corresponding to the above-mentioned figures have their own emphasis. For the parts not described in detail in a certain process, you can refer to the relevant descriptions of other processes.

In the above embodiments, all or part of them may be implemented by software, hardware, firmware or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product that provides the program development platform includes one or more computer instructions, and when these computer program instructions are loaded and executed on the computer device, the process or function of the data writing method of the memory provided by the embodiment of the present application is fully or partially realized .

The computer equipment can be a general purpose computer, special purpose computer, a computer network, or other programmable apparatus. Computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, e.g. Coaxial cable, optical fiber, digital subscriber line or wireless (such as infrared, wireless, microwave, etc.) transmission to another website site, computer, server or data center.Computer-readable storage medium stores a computer program that provides a program development platform instruction.

The embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium is a non-volatile computer-readable storage medium. The computer-readable storage medium includes program instructions. When the program instructions are run on the computer device When, the computer device is made to execute the method for writing data into the memory as provided in the embodiment of the present application.

The embodiment of the present application also provides a computer program product including instructions, and when the computer program product is run on the computer, the computer is made to execute the method for writing data into the memory provided in the embodiment of the present application.

Those of ordinary skill in the art can understand that all or part of the steps for implementing the above embodiments can be completed by hardware, and can also be completed by instructing related hardware through a program. The program can be stored in a computer-readable storage medium. The above-mentioned The storage medium mentioned may be a read-only memory, a magnetic disk or an optical disk, and the like.

It should be noted that the information (including but not limited to user equipment information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application, All are authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with the relevant laws, regulations and standards of the relevant countries and regions. For example, the resistance value information involved in this application is obtained under full authorization.

In the embodiments of the present application, the terms "first", "second" and "third" are used for description purposes only, and cannot be understood as indicating or implying relative importance. The term "at least one" means one or more, and the term "plurality" means two or more, unless otherwise clearly defined.

The term "and/or" in this application is only an association relationship describing associated objects, which means that there may be three relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and A and B exist alone. There are three cases of B. In addition, the character "/" in this article generally indicates that the contextual objects are an "or" relationship.

The above are only optional embodiments of the application, and are not intended to limit the application. Any modifications, equivalent replacements, improvements, etc. made within the concept and principles of the application shall be included in the protection of the application. within range.

Claims (15)

1. A data writing method of memory, is characterized in that, described method comprises: The memory receives a write instruction from the controller indicating to write data of a specified length to the memory; The memory writes the data of the specified length to the storage medium of the memory based on the write instruction. 2. The method according to claim 1, wherein the memory comprises a plurality of storage arrays, the data access process between the plurality of storage arrays does not affect each other, and writing data to the storage arrays is performed by The bit lines and word lines connected to the memory array are controlled and realized, and the specified length is reflected by any one or more of the following: based on the total number of address continuous bit lines that need to be controlled for writing data in the write command, based on the specified length The total number of word lines with continuous addresses that need to be controlled by the write command to write data, and the total number of memory arrays with continuous addresses to which data is written based on the write command. 3. The method according to claim 1 or 2, wherein the write instruction further indicates that the current value of the current signal used to execute the write operation indicated by the write instruction is smaller than a reference value, and the reference value is executed The current value of the current signal used for the write operation indicated by the write command that does not indicate the current value. 4. The method according to any one of claims 1 to 3, wherein the write instruction further indicates that the data of the specified length is allowed to be written in one or more periods according to the power consumption of the memory. 5. The method according to any one of claims 1 to 4, wherein the write instruction further indicates: for any storage address indicated by the write instruction, when the stored data at the storage address is the same as the When the write instruction indicates that the data written to the storage address is different, perform a write operation on the storage address based on the write instruction, and when the data stored at the storage address is different from the data written to the storage address indicated by the write instruction When the data of the storage address is the same, no write operation is performed on the storage address. 6. The method according to any one of claims 1 to 5, wherein the data of the specified length is composed of a plurality of binary values 1, or the data of the specified length is composed of a plurality of binary values 0 The data. 7. A data writing device for a memory, characterized in that the device comprises: A receiving module, configured to receive a write instruction from the controller indicating to write data of a specified length to the memory; An access module, configured to write data of the specified length to the storage medium of the memory based on the write instruction. 8. The device according to claim 7, wherein the memory comprises a plurality of storage arrays, the data access process between the plurality of storage arrays does not affect each other, and writing data to the storage arrays is performed by pairing The bit lines and word lines connected to the memory array are controlled and realized, and the specified length is reflected by any one or more of the following: based on the total number of address continuous bit lines that need to be controlled for writing data in the write command, based on the specified length The total number of word lines with continuous addresses that need to be controlled by the write command to write data, and the total number of memory arrays with continuous addresses to which data is written based on the write command. 9. The device according to claim 7 or 8, wherein the write instruction further indicates that the current value of the current signal used to execute the write operation indicated by the write instruction is smaller than a reference value, and the reference value is executed The current value of the current signal used for the write operation indicated by the write command that does not indicate the current value. 10. The device according to any one of claims 7 to 9, wherein the write instruction further indicates that the data of the specified length is allowed to be written in one or more periods according to the power consumption of the memory. 11. The device according to any one of claims 7 to 10, wherein the write instruction further indicates: for any storage address indicated by the write instruction, when the stored data at the storage address is the same as the When the write instruction indicates that the data written to the storage address is different, perform a write operation on the storage address based on the write instruction, and when the data stored at the storage address is different from the data written to the storage address indicated by the write instruction When the data of the storage address is the same, no write operation is performed on the storage address. 12. The device according to any one of claims 7 to 11, wherein the data of the specified length is composed of a plurality of binary values 1, or the data of the specified length is composed of a plurality of binary values 0 The data. 13. A computer device, characterized by comprising a memory and a processor, the memory stores program instructions, and the processor executes the program instructions to execute the method according to any one of claims 1 to 6. 14. A computer-readable storage medium, characterized by comprising program instructions, and when the program instructions are run on a computer device, the computer device is made to execute the method according to any one of claims 1 to 6. 15. A computer program product, characterized in that, when the computer program product is run on a computer, the computer is made to execute the method according to any one of claims 1 to 6.