CN116702665B - Large-scale integrated circuit design optimization method based on common sub-expression - Google Patents
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Abstract
The invention belongs to the technical field of circuit data processing, and particularly relates to a large-scale integrated circuit design optimization method based on a common sub-expression. The method specifically comprises the following steps: firstly, traversing and searching connection relations among devices in the combinational logic, determining the interrelationships between an output device and an input device, and constructing binary matrix vectors between the output and the input; each row in the binary matrix vector represents a binary expression equation, common sub-expressions needing to be processed are identified through matrix analysis, and one of the common sub-expressions is selected as a term needing to be eliminated; then eliminating the selected common sub-expression until no common sub-expression can be extracted; and then, creating a new module according to the extracted public sub-expression information, and establishing a connection relation between the new module and the input end and the output end. The invention solves the problems of resource optimization of the large-scale integrated circuit and lower performance and efficiency of the circuit in the prior art.
Description
Technical Field
The invention belongs to the technical field of circuit data processing, and particularly relates to a large-scale integrated circuit design optimization method based on a common sub-expression.
Background
The modern large-scale integrated circuit design resource optimization method is widely applied to the field of electronic engineering, and aims to optimize circuit design, reduce hardware resources required in a circuit, reduce power consumption and cost and improve performance and reliability of the circuit on the premise of ensuring circuit functions. In practical applications, the optimization of the resources of the large-scale integrated circuit can be achieved by various methods, for example: logic synthesis, place and route, timing optimization, power consumption optimization, application-specific integrated circuit design, and the like. Along with the continuous development of electronic engineering technology, the resource optimization technology of the large-scale integrated circuit is also continuously evolved and perfected, and makes an important contribution to the development of the field of electronic engineering.
The chinese patent document CN115577662a discloses a sequential device resource optimization method based on multiple fanout logic, and based on the module grouping of the multiple fanout logic, the design of a large-scale circuit is simplified by combining multiple output fanout structures, the lowest coupling degree between the modules in the combinational logic, that is, the minimum number of inputs or outputs, is traversed and searched, the optimal placement position of the sequential device is determined, and the number of the sequential devices with the same minimum coupling degree is created at the optimal placement position to reduce the number of the sequential devices.
However, with the continuous progress of the chip manufacturing process, the complexity of the integrated circuit design is also continuously increased, and meanwhile, different design targets are often mutually restricted, so that trade-off and decision among multiple targets are required. On the other hand, with the progress of the chip manufacturing process, the demand for the co-design of software and hardware is becoming stronger. Meanwhile, under the background that the current electronic product takes low power consumption as a design target, the target of power consumption optimization is realized on the premise of ensuring the circuit performance. In order to achieve the goal of optimizing the resources of the large-scale integrated circuit, on the basis of comprehensively considering various design methods, effective measures are required to reduce the number of logic gates in the circuit, reduce the power consumption and the cost, and improve the performance and the reliability of the circuit.
In summary, in the prior art, devices at the same level are regarded as a whole, the immediate devices are optimized, and a core problem of the optimized design of the large-scale integrated circuit resources is to comprehensively consider a plurality of factors to reduce the number of logic devices in a circuit and optimize the circuit design resources, and the complexity of the problem causes the current research difficulty, and continuous exploration and investigation are required to improve the efficiency and quality of the large-scale integrated circuit design.
Disclosure of Invention
The present invention is directed to overcoming at least one of the above-mentioned drawbacks of the prior art, and providing a method for optimizing a large-scale integrated circuit design based on a common sub-expression, so as to solve the deficiencies of the prior art in optimizing circuit design resources.
The detailed technical scheme of the invention is as follows:
the large-scale integrated circuit design optimization method based on the common sub-expression comprises the following steps: s1, obtaining a netlist to be analyzed, and if a combinational logic device exists in the netlist to be analyzed, performing the next step;
the combinational logic device refers to: the output of the combination logic device only depends on the current input and is irrelevant to the original state of the circuit, and the output can be changed correspondingly at any moment as long as the input is changed;
s2, obtaining groups of combinational logic devices with the same function type in the netlist to be analyzed;
if the grouping has only one combination logic device, the optimization is not needed, the direct ending is carried out, and the next grouping is optimized;
if a plurality of combinational logic devices with the same function type exist, searching the connected combinational logic devices to an input end and an output end respectively through a breadth-first traversal method according to the positions of the current combinational logic device group;
s3, acquiring an input end signal corresponding to the output end combination logic device in the packet and a connection relation between the output end combination logic device and the input end signal;
s4, calculating binary matrix vectors of the combined logic devices in the group, wherein each row in the binary matrix vectors represents a binary expression equation;
s5, calculating the occurrence times of the public sub-expressions in the binary expression equation, and finding out the public sub-expression with the largest occurrence times;
s6, traversing all binary expression equations, and if the common sub-expression with the largest occurrence frequency exists in the binary expression equation, replacing the common sub-expression with the largest occurrence frequency by a new variable in the binary expression equation; if not, continuing to traverse the next binary expression equation;
s7, circulating S5-S6 until only one variable exists in each binary expression equation, or all binary expression equations have no common sub-expression;
s8, setting a new combination logic part according to a new variable in the circuit, wherein the method specifically comprises the following steps:
s81, obtaining an input end signal corresponding to a new variable;
s82, taking an input end signal corresponding to a new variable as the input of the newly added combination logic element, and taking an output end combination logic element corresponding to the new variable as the output direction of the newly added combination logic element;
s9, updating the circuit. According to the newly added combination logic piece, the combination logic piece in the original circuit can be replaced, or the combination logic piece in the original circuit is deleted, the newly added combination logic piece is reconstructed, and a technician can adjust the updating mode according to actual needs.
Further, the corresponding relation between the output end and the input end combination logic device in the group is obtained through a breadth-first traversal method, and the method is specifically:
starting from the output end combination logic device, searching for a combination logic device which is adjacent to the output end combination logic device and is not accessed in the group; starting from the combination logic device, searching for a combination logic device which is adjacent to the combination logic device and is not accessed until the combination logic device connected with the input end signal of the traversed combination logic device is not in the group, and recording the corresponding relation between the output end combination logic device and the input end signal and the connection relation between the output end combination logic device and the input end signal;
the basic principle of the breadth-first traversal method is that a certain combination logic device or a group of combination logic devices in a circuit is started, the combination logic devices which are adjacent to the combination logic devices and are not accessed yet are searched, the number of the found combination logic devices is the number of accesses, and then the combination logic devices are respectively used as starting points for next traversal, and the processes are repeated; breadth-first traversal may be considered as a layer-by-layer traversal, with each time all combinational logic devices of a layer are traversed, the traversal proceeds to the next layer. The traversal mode can effectively search all the combinational logic devices connected with the target combinational logic device, and the searching efficiency can be improved.
Further, the variables refer to input signals having correspondence with the output combinational logic devices in the binary expression equation.
Compared with the prior art, the invention has the beneficial effects that:
the invention provides a large-scale integrated circuit design optimization method based on a common sub-expression, which is characterized in that a binary matrix vector between an output combination logic device and an input combination logic device is constructed by traversing the device connection relation in the combination logic circuit, the common sub-expression needing to be processed is identified through matrix analysis, then the common sub-expression with the most frequent occurrence frequency is eliminated in each binary expression equation, and the eliminated common sub-expression is constructed as a new module, so that the goal of large-scale integrated circuit design optimization based on the common sub-expression is realized.
Drawings
FIG. 1 is a flow chart of resource optimization in accordance with the present invention.
FIG. 2 is a schematic diagram of the netlist connection relationship described in embodiment 1 of the invention.
FIG. 3 is a schematic diagram of the connection relationship of devices in the optimized netlist according to embodiment 1 of the present invention.
Detailed Description
The disclosure is further described below with reference to the drawings and examples.
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the present disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments in accordance with the present disclosure. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
Embodiments of the present disclosure and features of embodiments may be combined with each other without conflict.
Example 1
The embodiment provides a large-scale integrated circuit design optimization method based on a common sub-expression, and the method provided by the invention can be used for solving the logic synthesis problem of a digital EDA tool and realizing the resource optimization of a combined logic device, thereby improving the performance and efficiency of a circuit:
0-5 in fig. 2 and 3 are signal terminals providing input signals for a group of combinational logic devices of the same functional type in the dashed box;
in fig. 2, the combinational logic device C, E, G and the combinational logic device H are output-side combinational logic devices, and are output signals of a group of combinational logic devices with the same function type in a dashed line box; the signal end and the output end of the group of combined logic devices with the same function type are connected through 4 combined logic devices A, B, D with the same function type and a combined logic device F;
in fig. 3, the combinational logic devices C, E, 6 (G) and the combinational logic device H are output-side combinational logic devices, and are output signals of a group of combinational logic devices with the same function type in a dashed line box; the signal end and the output end of the group of combined logic devices with the same function type are connected through 3 combined logic devices B, 6 (G) with the same function type and a combined logic device 7; wherein the output signal of the newly constructed combinational logic device 6 (G) is both the output signal of the group of combinational logic devices of the same functional type and the input signal of the intermediate combinational logic device B; the output signal of the combinational logic device 7 is utilized multiple times by the combinational logic device E and the combinational logic device H in the netlist.
The specific method is as shown in fig. 1:
s1, obtaining a netlist to be analyzed, and analyzing whether a combinational logic device exists in the netlist; if the combinational logic device exists in the netlist to be analyzed, the next step is performed.
With the continuous development of the resource optimization design technology of large-scale integrated circuits, a large number of combinational logic devices generally exist in the process of optimizing circuit design, so that optimization is required. The combinational logic devices A-H with the same function types in FIG. 1 refer to: the output of the combinational logic device is only dependent on the current input, is irrelevant to the original state of the circuit, and can be changed correspondingly at any moment as long as the input is changed.
S2, obtaining groups of combinational logic devices with the same function type in the netlist to be analyzed, such as a group of combinational logic devices with the same function type shown in a dotted line frame of FIG. 2;
FIG. 2 is a schematic diagram of a netlist connection comprising a plurality of combinational logic devices, wherein a group of combinational logic devices of the same functional type are shown in a dashed box, the combinational logic devices of the same functional type represent that the combinational logic devices have 2 inputs (fanin) and 1 output (fanout) and the output is the same as the logic relationship of the input signals. For example, the inputs of the combinational logic device a are from the signal terminal 0 and the signal terminal 1, and output to the combinational logic device B, wherein the connection between the combinational logic device a and the combinational logic device B represents the connection relationship therebetween. Likewise, the inputs of the combinational logic device D are from the signal terminal 1 and the signal terminal 2 and output to the combinational logic device E, wherein one wire can reach a plurality of combinational logic devices, that is, one wire can have a plurality of outputs;
if the grouping has only one combination logic device, the optimization is not needed, and the next grouping is optimized after the direct ending;
if a plurality of combinational logic devices with the same function type exist, searching the connected combinational logic devices to an input end and an output end respectively through a breadth-first traversal method according to the positions of the current combinational logic device group.
S3, obtaining the corresponding relation between the output end and the input end combination logic device in the group: acquiring an input end signal corresponding to an output end combination logic device in a group and a connection relation between the output end combination logic device and the input end signal;
starting from the output end combination logic device, searching a combination logic device which is adjacent to the output end combination logic device and is not accessed in the group by adopting a breadth-first traversal method; starting from the combination logic device, searching for a combination logic device which is adjacent to the combination logic device and is not accessed until the combination logic device connected with the input end signal of the traversed combination logic device is not in the group, and recording the corresponding relation between the output end combination logic device and the input end signal and the connection relation between the output end combination logic device and the input end signal;
for example, in fig. 2, starting from the output-end combinational logic device C, an breadth-first traversal method may be adopted to obtain that input-end signals corresponding to the output-end combinational logic device C are signal end 5, signal end 3, signal end 1 and signal end 0; similarly, the input end signals corresponding to the output end combinational logic device E are obtained as a signal end 4, a signal end 2 and a signal end 1; the input end signals corresponding to the output end combination logic device G are a signal end 3 and a signal end 1; the input signals corresponding to the output combinational logic device H are a signal terminal 4, a signal terminal 2 and a signal terminal 0.
S4, calculating binary matrix vectors of the combination logic devices in the group, wherein each row in the binary matrix vectors represents a binary expression equation for representing the influence relation between the output end device and the input end signal;
calculating a binary matrix vector of the whole netlist according to the corresponding relation between the output end combination logic device and the input end signals in the step S3;
element a in the matrix ij Indicating that the ith output terminal device is affected by the jth signal terminal, a ij =1 denotes the output device y j Receiving end x i Influence of a) ij =0 denotes the output device y j Free of signal terminal x i Is a function of (a) and (b). Each row in the binary matrix vector represents a binary expression equation to represent the influence relationship between the output device and the signal terminal.
For example, the first row of the binary matrix vector in equation (1) may be expressed as y C =x 0 +x 1 +x 3 +x 5 Indicating that the output end device C has a corresponding relation with the signal end 5, the signal end 3, the signal end 1 and the signal end 0;
the second row may be denoted as y E =x 1 +x 2 +x 4 Indicating that the output end device E has a corresponding relation with the signal end 1, the signal end 2 and the signal end 4;
the third row may be denoted as y G =x 1 +x 3 Indicating that the output end device G has a corresponding relation with the signal end 1 and the signal end 3;
the fourth row may be denoted as y H =x 0 +x 2 +x 4 Indicating that the output end device H has a corresponding relation with the signal end 0, the signal end 2 and the signal end 4;
（1）。
s5, calculating the occurrence times of the public sub-expressions in the binary expression equation, and finding out the public sub-expression with the largest occurrence times;
for example, the neutron expression x in equation (1) 1 +x 3 Respectively present at the output side of the combinational logic device y C And output side combinational logic device y G In, i.e. common sub-expression x 1 +x 3 Equation in all binary expressionsCo-occurrence 2 times, sub-expression x 2 +x 4 Respectively present at the output side of the combinational logic device y E And output side combinational logic device y H In, i.e. common sub-expression x 2 +x 4 2 times in total in all binary expression equations, and it can be seen that a common sub-expression x 1 +x 3 And x 2 +x 4 The number of occurrences is the greatest, so a new variable x is used 6 And x 7 Respectively used for replacing the common sub-expression x with the largest occurrence number 1 +x 3 And x 2 +x 4 。
S6, traversing all binary expression equations, establishing new variables, and if the common sub-expression x with the largest occurrence number exists in the binary expression equations 1 +x 3 And x 2 +x 4 Then a new variable x is generated in the corresponding binary expression equation 6 And x 7 Respectively replace x 1 +x 3 And x 2 +x 4 The method comprises the steps of carrying out a first treatment on the surface of the Otherwise, continuing to traverse the next binary expression equation;
for example, the first row y of the binary matrix vector in equation (1) C =x 0 +x 1 +x 3 +x 5 In which x is 6 Substitute x 1 +x 3 I.e. y C =x 0 +x 6 +x 5 The method comprises the steps of carrying out a first treatment on the surface of the Similarly, the second row y E =x 1 +x 2 +x 4 In which x is 7 Substitute x 2 +x 4 I.e. y E =x 1 +x 7 The method comprises the steps of carrying out a first treatment on the surface of the Third row y G =x 1 +x 3 In which x is 6 Substitute x 1 +x 3 I.e. y G =x 6 The method comprises the steps of carrying out a first treatment on the surface of the Fourth row y H =x 0 +x 2 +x 4 In which x is 7 Substitute x 2 +x 4 I.e. y H =x 0 +x 7 。
S7, judging whether all binary expression equations have a common sub-expression or not: looping S5-S6 until there is only one variable in each binary expression equation or, all binary expression equations have no common sub-expression; the iterative process of the specific binary expression equation is shown in the formula (1);
s8, setting a new combination logic part according to a new variable in the circuit, wherein the method specifically comprises the following steps:
s81, obtaining an input end signal corresponding to a new variable;
s82, taking an input end signal corresponding to a new variable as the input of the newly added combination logic element, and taking an output end combination logic element corresponding to the new variable as the output direction of the newly added combination logic element;
s9, updating a circuit: according to the newly added combination logic piece, the combination logic piece in the original circuit can be replaced, or the newly added combination logic piece is reconstructed, and a technician can adjust the updating mode according to actual needs;
the reconstruction of the newly added combinational logic is as follows: according to the obtained common sub-expression with the largest occurrence number, the corresponding input end signal is taken out to be constructed into a newly added combination logic element, such as the construction process of the newly added combination logic element 6 (G) in FIG. 3, on one hand, the common sub-expression x with the largest occurrence number is constructed 1 +x 3 Comprising a signal terminal x 1 Sum signal terminal x 3 As input signal of the newly added combinational logic element 6 (G), on the other hand, the output signal of the newly added combinational logic element 6 (G) is used as the common sub-expression x containing the largest occurrence number 1 +x 3 Binary expression equation y of (2) C =x 0 +x 1 +x 3 +x 5 And y G =x 1 +x 3 New input signal variable x of (2) 6 I.e. y C =x 0 +x 6 +x 5 、y G =x 6 ；
The same construction module 7 first uses the common sub-expression x with the largest appearance number 2 +x 4 Comprising a signal terminal x 2 Sum signal terminal x 4 As input signal to the newly added combinational logic element 7, and then as common sub-expression x containing the largest number of occurrences of the newly added combinational logic element 7 2 +x 4 Binary expression equation y of (2) E =x 1 +x 2 +x 4 And y H =x 0 +x 2 +x 4 New input signal variable x of (2) 7 I.e. y E =x 1 +x 7 、y H =x 0 +x 7 。
Finally, under the condition of not influencing the circuit function, the circuit originally using 8 combinational logic devices (combinational logic devices A-H) is simplified into a circuit which only needs 6 combinational logic devices (combinational logic device 6 (G), combinational logic device 7, combinational logic device B, combinational logic device C, combinational logic device E and combinational logic device H) by adopting a common sub-expression elimination algorithm, wherein the combinational logic device 6 (G) is used as an output end device and also used as an input end signal of the combinational logic device B, so that the number of the combinational logic devices is saved; the combination logic device 7 is used as a common input end signal of the combination logic device E and the combination logic device H, and by adopting the method provided by the invention, the device is constructed in advance, so that the use amount of the combination logic device is reduced, and the resource occupation of the device is reduced.
In specific application, for example, the problem of logic synthesis of digital EDA tools is solved, and a plurality of combined logic devices can reach hundreds, so that the method can greatly reduce the number of logic devices in a circuit so as to improve the efficiency and the quality of large-scale integrated circuit design.
It should be understood that the foregoing examples of the present invention are merely illustrative of the present invention and are not intended to limit the present invention to the specific embodiments thereof. Any modification, equivalent replacement, improvement, etc. that comes within the spirit and principle of the claims of the present invention should be included in the protection scope of the claims of the present invention.
Claims (3)
1. The method for optimizing the design of the large-scale integrated circuit based on the common sub-expression is characterized by comprising the following steps of;
s1, obtaining a netlist to be analyzed, and if a combinational logic device exists in the netlist to be analyzed, performing the next step;
the combinational logic device refers to: the output of the combination logic device only depends on the current input and is irrelevant to the original state of the circuit, and the output can be changed correspondingly at any moment as long as the input is changed;
s2, obtaining groups of combinational logic devices with the same function type in the netlist to be analyzed;
if the grouping has only one combination logic device, the optimization is not needed, and the next grouping is directly finished and optimized;
if a plurality of combinational logic devices with the same function type exist, searching the connected combinational logic devices to an input end and an output end respectively through a breadth-first traversal method according to the positions of the current combinational logic device group;
s3, acquiring an input end signal corresponding to the output end combination logic device in the packet and a connection relation between the output end combination logic device and the input end signal;
s4, calculating binary matrix vectors of the combined logic devices in the group, wherein each row in the binary matrix vectors represents a binary expression equation;
s5, calculating the occurrence times of the public sub-expressions in the binary expression equation, and finding out the public sub-expression with the largest occurrence times;
s6, traversing all binary expression equations, and if the common sub-expression with the largest occurrence frequency exists in the binary expression equation, replacing the common sub-expression with the largest occurrence frequency by a new variable in the binary expression equation; if not, continuing to traverse the next binary expression equation;
s7, circulating S5-S6 until only one variable exists in each binary expression equation, or all binary expression equations have no common sub-expression;
s8, setting a new combination logic part in the circuit according to a new variable;
s9, updating a circuit;
the setting of the new combination logic in the circuit according to the new variable specifically comprises:
s81, obtaining an input end signal corresponding to a new variable;
s82, taking an input end signal corresponding to a new variable as the input of the newly added combination logic element, and taking an output end combination logic element corresponding to the new variable as the output direction of the newly added combination logic element;
s83, the output of the newly added combination logic is taken as direct output or taken as input of the output combination logic.
2. The method of optimizing a design of a large scale integrated circuit based on a common sub-expression according to claim 1, wherein the plurality of combinational logic devices having the same functional type include the same number of input signals and the same number of output directives.
3. The method for optimizing the design of a large scale integrated circuit based on a common sub-expression according to claim 1, wherein the obtaining the input signals corresponding to the output combinational logic devices in the packet and the connection relationship between the input signals and the output signals specifically comprises:
starting from the output end combination logic device, searching for a combination logic device which is adjacent to the output end combination logic device and is not accessed in the group; and searching for a combination logic device which is adjacent to the combination logic device and is not accessed from the combination logic device until the combination logic device connected with the input end signal of the traversed combination logic device is not in the group, and recording the corresponding relation between the output end combination logic device and the input end signal and the connection relation between the output end combination logic device and the input end signal.
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