CN115913216A - Combined logic lookup table circuit - Google Patents
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- CN115913216A CN115913216A CN202211306393.XA CN202211306393A CN115913216A CN 115913216 A CN115913216 A CN 115913216A CN 202211306393 A CN202211306393 A CN 202211306393A CN 115913216 A CN115913216 A CN 115913216A
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Abstract
The invention discloses a combined logic lookup table circuit, comprising: a conversion array circuit for converting an M-bit lookup input signal to an M-bit hot code; the logic AND array is used for placing a two-input AND gate on any node of the M rows of signals and the N columns of signals; and the logical OR operation circuit is used for carrying out OR operation on any column output logic of the logical AND operation array. The invention realizes the searching function through the pure logic unit, the complexity of the manufacture, the programming and the device is lower than that of the searching table method in the prior art, simultaneously, the characteristics of simple storage and convenient operation are particularly obvious because the storage unit is saved, the cost is reduced, the searching speed is high, and the on-line monitoring requirement of the realization of future intelligent hardware is met.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a combined logic lookup table circuit.
Background
The method of the common lookup table in science and engineering operation is used for improving the operation precision and speed, for example, the platinum thermal resistors PT1000 and PT100 have high measurement precision, can be used for industrial temperature measurement, and can also be made into a standard reference instrument, the relation between the resistance value and the temperature can be calculated by a formula given by the international electrotechnical commission standard IEC751, but if a mode of directly calculating the value of the platinum thermal resistor by adopting the formula, the calculated amount is huge, and the industrial online temperature detection is difficult to realize. Therefore, a lookup table may be used to find the resistance value corresponding to each index by constructing a lookup table with multiple entries, each having a width of 20, and corresponding to the index value of PT 1000.
However, in the lookup table in the prior art, the mode of a storage unit, address gating and a read-write driving circuit is adopted, the time required for the lookup process is long, the types of devices are multiple, the structure is complex, and the industrial online temperature detection is not facilitated.
Therefore, the combined logic lookup table circuit is provided and is suitable for quick implementation of a programmable logic FPGA chip and integrated circuit intelligent hardware so as to solve the problems.
Disclosure of Invention
The combined logic lookup table circuit realizes the lookup function through the pure logic unit, saves the storage unit, has the characteristics of simple storage and convenient operation, not only reduces the cost, but also has high lookup speed, meets the online monitoring requirement of future intelligent hardware realization, and solves the problems provided in the background technology.
In order to achieve the purpose, the invention provides the following technical scheme:
the invention provides a combined logic lookup table circuit, which comprises: a conversion array circuit for converting an M-bit lookup input signal to an M-bit hot code;
the logic AND array is used for placing a two-input AND gate on any node of the M rows of signals and the N columns of signals;
and the logical OR operation circuit is used for performing OR operation on any column output logic of the logical AND operation array.
Preferably, if the input signal is S, the conversion array circuit is:
S＝[S[1] S[2]…S[m]] T 。
preferably, a binary value is set to s [1] s [2] … s [ m ], and the expression of the logic value to obtain the output thermal code is:
wherein i, j, M, p and M are natural numbers, and 0 is less than 2 m When the input signal value is i, the hot code value of only the ith row is 1, and the hot code values of the rest rows are 0.
Preferably, a two-input and gate is placed at any node (i, j) in the M row signals and the N column signals, one input end of the and gate is connected to the hot code output signal X [ i ] of the row, the signal X (i, j) at the other input end of the and gate is a logic value corresponding to the unit (i, j) value D (i, j) in the lookup table, and the logic value expression is as follows:
preferably, the two-input and gate output logic value x (i, j) of the node (i, j) is:
y(i，j)＝X[i]∧x(i，j)；
in the formula, "^" represents and operation.
Preferably, in the N columns of signals, all the two-input and gate output signals y (i, j) in the j-th column are logically or-operated, and the obtained logical or operation circuit is:
in the formula, "" V "" represents a logical OR operation, and Y [ j ] represents the value of the jth cell to be searched.
The invention has the beneficial effects that:
the combined logic lookup table circuit realizes the lookup function through the pure logic unit, the complexity of manufacturing, programming and devices is lower than that of a lookup table method in the prior art, and meanwhile, the combined logic lookup table circuit saves the storage unit, so that the characteristics of simple storage and convenient operation are particularly remarkable, the cost is reduced, the lookup speed is high, and the on-line monitoring requirement of future intelligent hardware realization is met.
Drawings
FIG. 1 is a schematic diagram of an AND gate array of a combinational logic lookup table circuit according to the present invention;
FIG. 2 is a schematic diagram of a combinational logic lookup table circuit according to the present invention;
FIG. 3 is a logic diagram of a combinational logic look-up table circuit according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The combined logic lookup table circuit provided by the present invention is described with reference to fig. 1 to 3, and includes:
the conversion array circuit is used for converting the M-bit search input signal into an M-bit hot code;
the logic AND array is used for placing a two-input AND gate on any node in the M rows of signals and the N columns of signals;
and the logic OR operation circuit is used for carrying out OR operation on any column output logic of the logic AND operation array.
The conversion array circuit is a conversion matrix E for realizing the hot code conversion process, and the expression of the conversion matrix E is as follows:
in the conversion matrix E, m and n are respectively the bit width of each piece of data and the number of the items of the lookup table, I is the serial number of the items to be looked up, the binary value form of the hot code is the unit matrix E, and the decimal value form is:
the logic and array functions by the following logical relationship:
for any node (i, j) in M row signals and N column signals, a two-input AND gate is arranged, one input end of the AND gate is connected with a hot code output signal X [ i ] of the row, the other input end signal X (i, j) of the AND gate is a logic value corresponding to the unit (i, j) value D (i, j) in the lookup table, and the logic value expression is as follows:
the two-input and gate output logic value x (i, j) of the node (i, j) is:
y(i，j)＝X[i]∧x(i，j)；
in the formula, "^" represents and operation;
as shown in fig. 2 and 3, it can be seen that all cells storing data 1 in the lookup table can be connected to the power supply VDD, and all cells storing data 0 in the lookup table can be connected to the ground GND.
The conversion matrix E, the logic and the array are all designed by adopting a hardware description language Verliog, the hardware description language Verliog describes the structure and the behavior of the digital system hardware in a text form, the conversion matrix E, the logic and the array are suitable for modeling the digital system with various abstract design levels from an algorithm level, a gate level to a switch level, and the complexity of a modeled digital system object is between a simple gate and a complete electronic digital system. The hardware description language Verliog defines not only syntax, but also clear simulation and emulation semantics for each syntax structure, so that a model written in this language can be verified using a Verilog emulator.
When the programmable logic FPGA chip selects Artix7 (XC 7a200 tfbg 484-3) and adopts Vivado tool for comprehensive analysis, the comprehensive performance parameters of the circuit are shown in Table 1. Vivado adopts ESL design for quickly integrating and verifying C language algorithm IP, can realize reused standard algorithm and RTL IP packaging technology, and system integration of standard IP packaging and various system building modules, so that the simulation speed of module and system verification is improved by 3 times, and the hardware co-simulation performance is improved by 100 times. When the programmable logic FPGA chip selects CycloneIV (EP 4CE 10F 17C 8) and adopts a Quartus tool to carry out comprehensive analysis, the performance parameters of the circuit after the comprehensive analysis are shown in the table 2. The Quartus tool enables the compiling performance to be improved by 15% on average through a module level design mode of a reinforced layer LogicLock, meanwhile, a new quick-adaptation compiling option is added, the setting of the best performance is reserved by a quick-adaptation compiling function, and the compiling time can be improved by 50%.
TABLE 1 Vivado Circuit Performance parameters after Synthesis
| Name (R) | Logic sheetYuan | Register with a plurality of registers | Operable frequency |
| PT1000 | 682 | 0 | 475MHz |
TABLE 2 post-circuit synthesis performance parameters in Quartus
As can be seen from tables 1 and 2, no matter whether the programmable logic FPGA chip employs Artix7 (XC 7a200 tfbg 484-3) or cycleiv (EP 4CE 10F 17C 8), the logic units required by the present invention are less than 700, considering that PT1000 requires 300 × 20=6000 (bits) memory units, and some column read/write circuits and operation processors.
Although the performance of the adopted FPGA devices is different, the operating frequency of the FPGA device is higher than 190MHz, the searching speed of the FPGA device is superior to that of the traditional software and hardware lookup table method, and the FPGA device saves a storage unit, so that the characteristics of simple storage and convenient operation are particularly obvious, the cost is reduced, and the on-line monitoring requirement of future intelligent hardware realization can be met.
The above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention, and they should be construed as being included in the following claims and description.
Claims (6)
1. A combinational logic lookup table circuit that sets a bit width of M entries of a data table to N, comprising:
a conversion array circuit for converting an M-bit lookup input signal to an M-bit hot code;
the logic AND array is used for placing a two-input AND gate on any node of the M rows of signals and the N columns of signals;
and the logical OR operation circuit is used for carrying out OR operation on any column output logic of the logical AND operation array.
2. The combinational logic look-up table circuit of claim 1, wherein if the input signal is S, the conversion array circuit is:
S＝[S[1] S[2]...S[m]] T 。
3. the combinational logic lookup table circuit of claim 2 wherein a binary value is set to s [1] s [ 2.. S [ m ], and the logic value expression for the output thermal code is obtained as:
wherein i, j, M, p and M are natural numbers, and 0 is less than 2 m When the input signal value is i, the hot code value of only the ith row is 1, and the hot code values of the rest rows are 0.
4. A combinational logic look-up table circuit according to claim 1, wherein a two-input and gate is disposed at any node (i, j) of the M row signal and the N column signal, one input end of the and gate is connected to the hot code output signal X [ i ] of the row, the other input end signal X (i, j) of the and gate is a logic value corresponding to the unit (i, j) value D (i, j) in the look-up table, and the logic value is expressed as:
5. the combinational logic look-up table circuit according to claim 4, wherein the two-input AND gate output logic value x (i, j) of the node (i, j) is:
y(i，j)＝X[i]∧x(i，j)；
in the formula, "^" represents and operation.
6. The combinational logic lookup table circuit according to claim 1, wherein, in the N columns of signals, all the two-input and gate output signals y (i, j) in the jth column are logically or-ed, and the obtained logical or operation circuit is:
in the formula, V represents a logic OR operation, and Y [ j ] represents the value of the j-th cell to be searched.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116702665A (en) * | 2023-08-04 | 2023-09-05 | 山东启芯软件科技有限公司 | Large-scale integrated circuit design optimization method based on common sub-expression |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116702665A (en) * | 2023-08-04 | 2023-09-05 | 山东启芯软件科技有限公司 | Large-scale integrated circuit design optimization method based on common sub-expression |
| CN116702665B (en) * | 2023-08-04 | 2023-10-27 | 山东启芯软件科技有限公司 | Large-scale integrated circuit design optimization method based on common sub-expression |
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