CN116701295A - In-memory computing circuit and control method - Google Patents
In-memory computing circuit and control method Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 18
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7821—Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
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- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
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- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
- G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The application discloses an in-memory computing circuit and a control method, and relates to the technical field of in-memory computing, wherein the in-memory computing circuit comprises: a memory array comprising a plurality of memory cells; a transfer gate array including a plurality of transfer gate units, the transfer gate units being electrically connected one-to-one with the memory units; a plurality of multipliers, each of which is electrically connected to a row of the transmission gate units, or each of which is electrically connected to a column of the transmission gate units; the transmission gate unit is used for controlling the storage unit to output storage data to the multiplier based on the screening signal. The digital domain memory circuit can solve the problems of large number of operation devices and large occupied circuit area in the existing digital domain memory circuit.
Description
Technical Field
The application belongs to the technical field of memory computing, and particularly relates to a memory computing circuit and a control method.
Background
In the existing in-memory computing unit, the memory is required to participate in computing operation, so that the memory array is correspondingly modified based on different computing modes, and can be divided into analog domain computing and digital domain computing based on different computing modes, wherein the analog domain computing utilizes current, charge accumulation and the like to perform computing, and is widely applied to low-precision computing application scenes, and the digital domain computing has high precision and strong robustness compared with the analog domain computing. However, in the existing digital domain calculation, the number of the computing devices is large, the occupied circuit area is large, the area of the in-memory computing circuit is large, and the power consumption is high.
Disclosure of Invention
The embodiment of the application provides an in-memory computing circuit and a control method, which can solve the problems of large number of computing devices, large occupied circuit area and high power consumption in the existing digital domain memory computing circuit.
In a first aspect of an embodiment of the present application, there is provided an in-memory computing circuit, the circuit including:
a memory array comprising a plurality of memory cells;
a transfer gate array including a plurality of transfer gate units, the transfer gate units being electrically connected one-to-one with the memory units;
a plurality of multipliers, each of which is electrically connected to a row of the transmission gate units, or each of which is electrically connected to a column of the transmission gate units;
the transmission gate unit is used for controlling the storage unit to output storage data to the multiplier based on the screening signal.
In some embodiments, the in-memory computing circuit further comprises:
an adder array electrically connected to a plurality of the multipliers.
In some embodiments, the in-memory computing circuit further comprises:
the screening control module is used for generating the screening signal;
in the case that the multiplier is electrically connected to one row of the transmission gate units, the screening signals include column screening signals for controlling on or off of the corresponding same column of the transmission gate units;
in the case that the multiplier is electrically connected to a column of the transmission gate units, the screening signal includes a row screening signal for controlling on or off of the corresponding same row of the transmission gate units.
In some embodiments of the present application, in some embodiments,
the transmission gate unit comprises a transistor, and a gate of the transistor is used for receiving the screening signal.
In some embodiments of the present application, in some embodiments,
the transistor comprises at least two transistors connected in parallel;
the screening signal is used for controlling the switching state of the transistors to be consistent.
In some embodiments of the present application, in some embodiments,
the screening control module comprises an inverter, wherein the screening signals comprise a first screening signal and a second screening signal, and the second screening signal is obtained through the inverter based on the first screening signal;
the transistors comprise an N-type transistor and a P-type transistor, and the first screening signal and the second screening signal are respectively used for controlling the transistors of different types.
In some embodiments of the present application, in some embodiments,
the screening control module comprises a plurality of output ports, wherein the output ports are used for outputting the screening signals;
each of the output ports is electrically connected to the same row or column of the transmission gate units.
In some embodiments of the present application, in some embodiments,
the memory cell comprises an SRAM memory cell;
the SRAM memory cell includes:
the first phase-change device comprises a first phase-change device,
the output end of the second inverter is electrically connected with the input end of the first inverter to form a first storage node, and the input end of the second inverter is connected with the output end of the first inverter to form a second storage node;
the transmission gate unit is electrically connected to one of the first storage node or the second storage node.
In some embodiments of the present application, in some embodiments,
the multiplier comprises an exclusive-or gate, a first input end of the exclusive-or gate is used for receiving the storage data, and a second input end of the exclusive-or gate is used for receiving an excitation signal.
In a second aspect of the embodiment of the present application, a method for controlling an in-memory computing circuit is provided, the method including:
generating a screening signal according to the calculation instruction;
controlling the conduction state of the transmission gate unit based on the screening signal;
based on the conducted transmission gate unit, controlling the corresponding storage unit to transmit storage data to the corresponding connected multiplier;
and multiplying the received stored data by using the multiplier.
In summary, an in-memory computing circuit provided by an embodiment of the present application includes: a memory array comprising a plurality of memory cells; a transfer gate array including a plurality of transfer gate units, the transfer gate units being electrically connected one-to-one with the memory units; a plurality of multipliers, each of which is electrically connected to a row of the transmission gate units, or each of which is electrically connected to a column of the transmission gate units; the transmission gate unit is used for controlling the storage unit to output storage data to the multiplier based on the screening signal. By electrically connecting one transmission gate unit to each storage unit, the transmission gate unit can control the storage data in the storage units electrically connected with the transmission gate units to be output to the multipliers of each row or each column based on the screening signals, so that each row or each column can select the storage data in the required storage unit by only configuring one multiplier to complete binary multiplication calculation, the number of the multipliers is reduced, electronic components of the in-memory computing circuit are reduced, the number of operating components is reduced, the area of the in-memory computing circuit is reduced, and the effect of reducing the operating power consumption of the circuit can be achieved.
Correspondingly, the control method of the in-memory computing circuit provided by the embodiment of the application also has the technical effects.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for the purpose of illustrating preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to designate like parts throughout the figures.
In the drawings:
FIG. 1 is a schematic block diagram of an in-memory computing circuit according to an embodiment of the present application;
FIG. 2 is a schematic block diagram of another in-memory computing circuit according to an embodiment of the present application;
FIG. 3 is a schematic block diagram of yet another in-memory computing circuit provided by an embodiment of the present application;
fig. 4 is a schematic block diagram of a screening control module according to an embodiment of the present application;
fig. 5 is a schematic flowchart of a control method of an in-memory computing circuit according to an embodiment of the present application.
Detailed Description
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments.
In the existing digital memory computing unit for performing multiply-accumulate operation, each storage unit needs to be provided with a multiplier, and the corresponding adder array needs to be provided with more input interfaces, so that the adder array needs to be provided with more digital logic units, and occupies a large amount of area and power consumption of the digital memory computing unit.
Therefore, there is a need to provide an in-memory computing circuit to solve at least the above-mentioned problems.
In a first aspect of the embodiment of the present application, an in-memory computing circuit is provided, and fig. 1 is a schematic block diagram of an in-memory computing circuit according to an embodiment of the present application. As shown in fig. 1, the above circuit includes:
a memory array including a plurality of memory cells 100; a transfer gate array including a plurality of transfer gate units 200, the transfer gate units 200 being electrically connected one-to-one with the memory units 100; a plurality of multipliers 300, each multiplier 300 being electrically connected to a row of transmission gate units 200, or each multiplier 300 being electrically connected to a column of transmission gate units 200; the transmission gate unit 200 is used to control the storage unit 100 to output the storage data to the multiplier 300 based on the screening signal S1.
Illustratively, as shown in fig. 1, the filtering signal S1 may be used to select the memory cell 100, may be an address signal, or the like, and is used to control the transmission gate unit 200 that receives the filtering signal to output the stored data to the multiplier 300, and the multiplier 300 is electrically connected to the transmission gate unit 200 of the same row or column. The transfer gate unit 200 is electrically connected one-to-one with the memory units 100, so that the transfer gate unit 200 can control the stored data in the corresponding memory unit 100 to be output to the multiplier 300 in case of receiving the screening signal S1.
It should be noted that, each multiplier 300 is electrically connected to all the transmission gate units 200 in the same row or the same column, and according to the filtering signal S1, the transmission gate unit 200 in each row or each column that receives the filtering signal S1 can control the storage data in the connected storage unit 100 to be output to the multiplier 300 connected to the corresponding row or column, so that only one multiplier 300 is required to be configured for each storage unit 100 in each row or each column to select the storage data in the required storage unit 100 to complete the binary multiplication calculation.
It can be explained that, in order to implement binary multiplication operation of storage data, each storage unit in the storage array is usually connected with a multiplier, and the storage unit outputs the storage data to the multiplier by an address line addressing mode, and in the storage computing circuit provided by the application, by electrically connecting each storage unit 100 with a transmission gate unit 200, the transmission gate unit 200 can control the storage data in the storage unit 100 electrically connected with the transmission gate unit 200 to be output to the multiplier 300 of each row or each column based on the screening signal S1, so that each row or each column can select the storage data in the required storage unit 100 only by configuring one multiplier 300 to complete the binary multiplication operation, the number of multipliers 300 is reduced, and electronic components of the storage computing circuit are reduced, and power consumption generated by the multiplier 300 is saved.
According to some embodiments, the in-memory computing circuit further comprises: adder array 400, adder array 400 is electrically connected to plurality of multipliers 300.
As shown in fig. 2, fig. 2 is a schematic block diagram of another in-memory computing circuit according to an embodiment of the present application, and an adder array 400 is electrically connected to the multipliers 300 and is configured to receive output results of the multipliers 300 to perform an accumulation operation, so that the multiply-accumulate operation on the memory array can be completed by setting one adder array 400.
It will be appreciated that the adder array 400 may be combined differently by full-adder, half-adder based on different numbers of multipliers 300. As shown in fig. 3, fig. 3 is a schematic block diagram of another in-memory computing circuit provided by the embodiment of the present application, in which an Adder array 400 includes a Full-Adder (Full Adder) and two Half-adders (Half Adder), and is constructed in a CMOS (Complementary Metal Oxide Semiconductor; complementary metal oxide) structure, wherein an added port a and an added port B, cin of the Full Adder are respectively connected to output terminals of the exclusive-or gates of different rows, a Cout high-order carry port and a Sum port are respectively connected to added ports a and B of the Half Adder 1 and 2, an added port B of the Half Adder 1 is connected to an output terminal of the exclusive-or gates, a Cout high-order carry terminal of the Half Adder 1 is connected to an added port B of the Half Adder 2, a Cout high-order terminal of the Half Adder 2, a Sum terminal of the Half Adder 1 and a Sum terminal of the Half Adder 1 are used for outputting an accumulated computing result, and the output terminal of the Adder 300 of each row is connected to output terminals of the multiplier 300, and can receive 4 single-bit computing results <0> to <0 >. The structure of the adder array 400 is merely for convenience of description and is not particularly limited.
It should be noted that, the multipliers 300 are connected to all the transmission gate units 200 in the same row or the same column, based on the filtering signal S1, the selected transmission gate unit 200 may output data to the multiplier 300 in the row or the column, the multipliers 300 are connected to one adder array 400, and the adder array 400 may output the operation results of the multipliers 300 to complete the multiply-accumulate operation. By arranging the adder array 400, the multiply-accumulate operation of the storage array can be completed, and the number of electronic components of the summation operation is reduced, so that the area and the power consumption of the in-memory calculation unit are saved.
According to some embodiments, the in-memory computing circuit further comprises: the screening control module 500, the screening control module 500 is configured to generate a screening signal S1, where the screening signal S1 includes a column screening signal for controlling on or off of a corresponding same column transmission gate unit 200 in a case where the multiplier 300 is electrically connected to a row transmission gate unit 200, and the screening signal S1 includes a row screening signal for controlling on or off of a corresponding same row transmission gate unit 200 in a case where the multiplier 300 is electrically connected to a column transmission gate unit 200.
The in-memory computing circuit further includes a filtering control module 500 for generating a filtering signal S1, where each multiplier 300 and each transmission gate unit 200 of each row, the filtering signal S1 includes a column filtering signal, and the column filtering signal is used to control on or off of all transmission gate units 200 of a corresponding same column, so as to control whether the control unit of the corresponding column outputs stored data, and the stored data of each row in the same column may be output to the multiplier 300 connected to each row through the transmission gate unit 200. In the case of each multiplier 300 and each column of the transmission gate units 200, the selection signal includes a row selection signal for controlling on or off of all the transmission gate units 200 of the corresponding same row, so that whether the control units of the corresponding row output the stored data can be controlled, and the stored data of each column in the same row can be output to each column of the connected multipliers 300 through the transmission gate units 200. The filtering control module 500 generates a column filtering signal or a row filtering signal, so that the output of stored data can be controlled based on the selection requirements of different memory units 100, and the application range of the in-memory computing circuit provided by the embodiment of the application is improved.
According to some embodiments, the transmission gate unit 200 includes a transistor having a gate for receiving the screening signal S1.
Illustratively, the pass gate unit 200 includes a transistor whose gate may be based on the received screening signal S1 to control the transistor to be turned on or off. It is to be readily understood that the transistor includes a voltage driving type, such as a field effect transistor, or a current driving type, such as a bipolar transistor, by providing the transistor as a transmission unit, the transistor can be driven to be turned on or off based on a change in the voltage or current of the selection signal S1, so that whether or not the stored data in the memory cell 100 to which the transistor is connected is outputted can be controlled.
According to some embodiments, the transistors comprise at least two transistors connected in parallel, and the screening signal S1 is used to control the switching states of the transistors to be identical.
For example, the transistors may include at least two transistors connected in parallel, the transistors connected in parallel maintaining a consistent switching state based on the screening signal S1.
It can be understood that at least two parallel transistors are adopted to control whether the memory unit 100 outputs or not, and the current can be split under the high current scene, so that the transistors are prevented from being broken down, the normal output of the stored data is ensured, and the reliability of the in-memory computing circuit provided by the application is improved.
According to some embodiments, the screening control module 500 includes an inverter, the screening signal S1 includes a first screening signal and a second screening signal, the second screening signal is obtained through the inverter based on the first screening signal, the transistor includes an N-type transistor and a P-type transistor, and the first screening signal and the second screening signal are used to control different types of transistors, respectively.
For example, the screening control module 500 may generate the first and second screening signals having opposite potentials by setting an inverter. As shown in fig. 3, the pass gate unit 200 includes an N-type transistor and a P-type transistor connected in parallel, and gates of the N-type transistor and the P-type transistor are used to receive the first screening signal and the second screening signal.
It may be noted that the first screening signal and the second screening signal are opposite in potential, thereby controlling the transistors of different types to be turned on or off simultaneously. The parallel N-type transistor and P-type transistor are used as the transmission gate unit 200, and are respectively turned on or off based on the first screening signal and the second screening signal, so that the N-type transistor and the P-type transistor are connected in parallel, and a complete voltage swing is provided under the condition that both the N-type transistor and the P-type transistor are turned on, so that the stored data can output a stable potential output under the condition of 1 or 0, and the accuracy of identifying the stored data is improved.
According to some embodiments, the filtering control module 500 includes a plurality of output ports for outputting the filtering signal S1, and each output port is electrically connected to the same row or column of the transmission gate units 200.
As shown in fig. 3 and 4, fig. 4 is a schematic block diagram of a screening control module according to an embodiment of the present application, where the screening control module 500 includes a shift register and a nor gate 520, the shift register is formed by three cascaded flip-flops 510, the flip-flops may be DQ flip-flops 510, input terminals D and Q of the three cascaded flip-flops 510 are connected, input terminals of the three input nor gates are respectively connected to the output terminal Q of the DQ flip-flops 510, output terminals of the nor gate are respectively connected to the input terminal D of the DQ flip-flops 510 based on a timing signal trend, the three cascaded flip-flops 510 are simultaneously controlled by the same clock signal Clk, one output terminal and three input terminals of the nor gate 520 are respectively connected to an inverter, where one output terminal and three input terminals of the nor gate 520 are denoted by D <0> to D <3>, gates of all transistors in each column are connected to one of D <0> to D <3>, and the screening control module 500 may control a change in potential from D <0> to D <3> based on the clock signal. For example, the logical operation may be implemented as follows:
as shown in fig. 3, the flip-flop 510 may be an edge flip-flop 510, the output gate unit may be turned on when receiving a high signal, the screening control module 500 may be 1000 from D <0> to D <3> in an initial state, and at this time, all the transmission gate units 200 connected to the same column of D <0> are in an on state, and the stored data in the corresponding memory cells 100 connected to the transmission gate units 200 may be transferred to the multiplier 300, and the multiplier 300 is connected to all the transmission gate units 200 of the column of D <0 >. In case that the flip-flop 510 receives the next clock rising edge signal, D <0> to D <3> become 0100, that is, all the transfer gate units 200 connected to the same column of D <1> are in the on state, the stored data in the corresponding memory cells 100 connected to the transfer gate units 200 can be transferred to the multiplier 300, and the multiplier 300 is connected to all the transfer gate units 200 of the column D <1 >. Thus, 4-column bitwise multiplication can be completed in one clock cycle calculation, and the obtained 4-column multiplication result can also be input to the adder array 400, with the accumulation result being output from OUT <2> to OUT <0> of the adder array 400. Depending on the manner of logical operation, multiply-accumulate operations of stored data may be performed in multiple rows or columns within one clock cycle.
In some cases, one output and three inputs of nor gate 520 may also be connected to inverter 530 to generate opposite-potential signals, denoted by DB <0> through DB <3>, respectively, with gates of all two transistors in parallel in the same column of transmission gates connected to a pair of D <0> through D <3> and DB <0> through DB <3>, respectively. The D and DB output signals have opposite potentials, and at this time, the transistors may be P-type transistors or N-type transistors, respectively, so that the transistors may be controlled to be turned on or off simultaneously based on signals of opposite potentials to determine whether or not the stored data in the memory cell 100 connected to the transfer gate unit 200 is output.
It may be noted that, the filtering control module 500 sets a plurality of output ports, each output port is connected to all the transmission gate units 200 in the same row or the same column, and the output ports output the filtering signal S1, so that all the transmission gate units 200 in the same row or the same column can control whether the stored data is output based on the outputted filtering signals S1 of different output ports. The screening control module 500 with multiple output ports can only adopt one screening control module 500 to control whether the storage data of the storage units 100 in multiple rows or multiple columns are output, so that the number of components of a calculation circuit in the storage is reduced, the power consumption is saved, and meanwhile, the storage units 100 in the rows or columns are screened based on one screening control module 500, so that the storage units 100 in the same row or column can receive the same screening signal S1, and the consistency and the reliability of the storage data selection are ensured.
According to some embodiments, the memory cell 100 comprises an SRAM memory cell 100; the SRAM memory cell 100 includes: the first inverter, the second inverter, the output of the second inverter is connected to the input of the first inverter to form a first storage node, the input of the second inverter is connected to the output of the first inverter to form a second storage node, and the transmission gate unit 200 is connected to one of the first storage node or the second storage node.
As shown in fig. 3, the Memory unit 100 includes an SRAM (Static Random-Access Memory) Memory unit 100, and it is easy to understand that the SRAM Memory unit 100 mainly includes a 4T or 6T structure, and the 6T structure may be configured by a dual inverter interlocking structure, so that dual storage nodes commonly store data to ensure stability of the stored data. The storage node Q near the BL bit line stores normal weight data, the storage node QB near the BLB bit line stores reverse weight data, where, for example, Q0<3> represents the storage node of column 0 and row 3, QB2<1> represents the storage node of column 2 and row 1, and the WL word line is used to control the SRAM memory cell to write data.
It may be noted that the transmission gate unit 200 is electrically connected to one of the first storage node or the second storage node of the SRAM, and is used for controlling one of the positive weight data and the positive weight data to be output to the multiplier 300 connected to the row or the column where the transmission gate unit 200 is located. The SRAM memory unit 100 can acquire normal phase weight stored data or reverse phase weight data, and based on the interlocking structure of the SRAM memory unit 100, the reliability and stability of the stored data are improved, and the accuracy of the operation result of the in-memory computing circuit is further ensured.
According to some embodiments, multiplier 300 includes an exclusive-or gate having a first input for receiving the stored data and a second input for receiving the stimulus signal.
Illustratively, as shown IN FIG. 3, multiplier 300 includes an exclusive OR gate having a first input coupled to transmission gate unit 200 for receiving the stored data and a second input for receiving an enable signal IN, e.g., IN <2> represents the enable signal of row 2. And outputting a two-stage multiplication operation result according to the truth table of the exclusive OR gate. With the exclusive or gate as the multiplier 300, data having the same weight can be output. It should be noted that the multiplier 300 may select different logic gates according to different requirements, which is not limited in particular.
In a second aspect, the present application provides a method for controlling an in-memory computing circuit, referring to fig. 5, fig. 5 is a schematic flowchart of a method for controlling an in-memory computing circuit provided by the present application, specifically including S110-S40,
s110, generating a screening signal according to the calculation instruction.
Illustratively, as shown in FIG. 1, a screening signal S1 may be generated based on a computational instruction issued by a processor, the screening signal may be generated by a counter, and the screening signal may include an addressing signal for determining a transmission gate unit to be selected.
S120, controlling the conduction state of the transmission gate unit based on the screening signal.
For example, as shown in fig. 1, each transmission gate unit 200 may receive the screening signal S1 and may control its turn-on state based on the screening signal S1.
S130, based on the conducted transmission gate unit, the corresponding storage unit is controlled to transmit storage data to the corresponding connected multiplier.
Illustratively, as shown in fig. 1, the transmission gate units 200 are electrically connected one-to-one with the memory cells 100 in the memory array, and each row of the transmission cells is connected to one multiplier 300, that is, each multiplier 300 is correspondingly connected to all the transmission cells in each row. The on state of the transfer gate unit 200 may be controlled based on the selection signal S1, and in case the transfer gate unit 200 is turned on, stored data in the memory cells 100, which are electrically connected one-to-one with the transfer gate unit 200, may be controlled to be transferred to the corresponding multipliers 300 through the transfer gate unit 200. In some cases, each column of transmission units may be connected to one multiplier 300, i.e., each multiplier 300 is correspondingly connected to all transmission units in each column.
S140, multiplying the received storage data by a multiplier.
Illustratively, as shown in fig. 1, the multiplier 300 may perform binary multiplication based on the received storage data, for example, the multiplier 300 may receive the excitation signal from the outside and perform multiplication with the storage data, and based on different requirements, the multiplier 300 may select different logic gates, for example, the multiplier 300 may select an exclusive or gate, so that multiplication results with the same weight may be output.
In some cases, the outputs of the multipliers 300 may also be coupled to an adder array 400, and a different number of input ports of the adder array 400 may be selected based on the number of coupled multipliers 300. Adder array 400 may perform an addition operation based on the multiplication results of the outputs of the plurality of multipliers 300.
According to the control method of the in-memory computing circuit provided by the embodiment of the application, the on state of the transmission gate unit 200 is controlled by the screening signal S1, then the stored data in the storage unit 100 which is electrically connected with the transmission gate unit 200 in the on state one by one can be output to the multiplier 300, the multiplier 300 is electrically connected with all the transmission gate units 200 in the same row or the same column, and the multiplier 300 can perform binary multiplication operation based on the received stored data. By arranging one multiplier 300 in the same row or the same column, when the transmission gate unit 200 is turned on based on the screening signal S1, the data stored in the connected storage unit 100 can be transmitted to the input end of the multiplier 300 connected to the transmission gate unit 200 to complete the binary multiplication operation, thereby reducing the number of multipliers 300, further reducing the number of components, and saving the area and power consumption of the in-memory computing circuit.
While preferred embodiments of the present description have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present specification without departing from the spirit or scope of the specification. Thus, if such modifications and variations of the present specification fall within the scope of the claims and the equivalents thereof, the present specification is also intended to include such modifications and variations.
Claims (10)
1. An in-memory computing circuit, comprising:
a memory array comprising a plurality of memory cells;
a transfer gate array including a plurality of transfer gate units, the transfer gate units being electrically connected one-to-one with the memory units;
a plurality of multipliers, each of which is electrically connected to a row of the transmission gate units, or each of which is electrically connected to a column of the transmission gate units;
the transmission gate unit is used for controlling the storage unit to output storage data to the multiplier based on the screening signal.
2. The in-memory computing circuit of claim 1, further comprising:
an adder array electrically connected to a plurality of the multipliers.
3. The in-memory computing circuit of claim 1, further comprising:
the screening control module is used for generating the screening signal;
in the case that the multiplier is electrically connected to one row of the transmission gate units, the screening signals include column screening signals for controlling on or off of the corresponding same column of the transmission gate units;
in the case that the multiplier is electrically connected to a column of the transmission gate units, the screening signal includes a row screening signal for controlling on or off of the corresponding same row of the transmission gate units.
4. The in-memory computing circuit of claim 3, wherein,
the transmission gate unit comprises a transistor, and a gate of the transistor is used for receiving the screening signal.
5. The in-memory computing circuit of claim 4, wherein,
the transistor comprises at least two transistors connected in parallel;
the screening signal is used for controlling the switching state of the transistors to be consistent.
6. The in-memory computing circuit of claim 5, wherein,
the screening control module comprises an inverter, wherein the screening signals comprise a first screening signal and a second screening signal, and the second screening signal is obtained through the inverter based on the first screening signal;
the transistors comprise an N-type transistor and a P-type transistor, and the first screening signal and the second screening signal are respectively used for controlling the transistors of different types.
7. The in-memory computing circuit of claim 3, wherein,
the screening control module comprises a plurality of output ports, wherein the output ports are used for outputting the screening signals;
each of the output ports is electrically connected to the same row or column of the transmission gate units.
8. The in-memory computing circuit of any one of claims 1-7, wherein,
the memory cell comprises an SRAM memory cell;
the SRAM memory cell includes:
the first phase-change device comprises a first phase-change device,
the output end of the second inverter is electrically connected with the input end of the first inverter to form a first storage node, and the input end of the second inverter is connected with the output end of the first inverter to form a second storage node;
the transmission gate unit is electrically connected to one of the first storage node or the second storage node.
9. The in-memory computing circuit of any one of claims 1-7, wherein,
the multiplier comprises an exclusive-or gate, a first input end of the exclusive-or gate is used for receiving the storage data, and a second input end of the exclusive-or gate is used for receiving an excitation signal.
10. A control method of an in-memory computing circuit, characterized by being applied to the in-memory computing circuit according to any one of claims 1 to 9, the control method comprising:
generating a screening signal according to the calculation instruction;
controlling the conduction state of the transmission gate unit based on the screening signal;
based on the conducted transmission gate unit, controlling the corresponding storage unit to transmit storage data to the corresponding connected multiplier;
and multiplying the received stored data by using the multiplier.
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