CN105405387A

CN105405387A - Shifting register unit, driving method thereof, gate drive circuit and display device

Info

Publication number: CN105405387A
Application number: CN201610006857.3A
Authority: CN
Inventors: 宋洋; 于海峰
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Priority date: 2016-01-05
Filing date: 2016-01-05
Publication date: 2016-03-16
Anticipated expiration: 2036-01-05
Also published as: CN105405387B

Abstract

The invention provides a shifting register unit, a driving method thereof, a gate drive circuit and a display device. The shifting register unit comprises a storage capacitor, an output control unit and a discharge unit for controlling and releasing residual charge in the storage capacitor in a discharge period of each display cycle; an output cut-off phase comprises the discharge period. According to the shifting register unit, the driving method thereof, the gate drive circuit and the display device, the discharge unit is adopted to eliminate the influence of the residual charge in the storage capacitor to a gate drive signal in the discharge period of each display cycle, and accurate output of the gate drive signal is ensured, so that a circuit structure of the shifting register unit can be optimized, and the integrated design of a display panel can be optimized.

Description

Shift register cell and driving method, gate driver circuit and display device

Technical field

The present invention relates to display technique field, particularly relate to a kind of shift register cell and driving method, gate driver circuit and display device.

Background technology

The driver of display device mainly comprises gate driver circuit and data drive circuit, and gate driver circuit forms primarily of multi-stage shift register unit, all and between grid line there is corresponding relation in shift register cell, by the gate drive signal that shift register cell exports, line by line scan and drive pixel TFT (ThinFilmTransistor, thin film transistor (TFT)).But existing shift register cell is after the effective gate drive signal of output, effectively cannot discharge electric charge residual in memory capacitance, residual charge in memory capacitance can not be got rid of and, on the impact of gate drive signal, the accurate output of gate drive signal can not be ensured.

Summary of the invention

Fundamental purpose of the present invention is to provide a kind of shift register cell and driving method, gate driver circuit and display device, solve existing shift register cell and effectively cannot discharge electric charge residual in memory capacitance, residual charge in memory capacitance can not be got rid of and, on the impact of gate drive signal, the problem of the accurate output of gate drive signal can not be ensured.

In order to achieve the above object, the invention provides a kind of shift register cell, comprise gate drive signal output terminal, described shift register cell also comprises:

Memory capacitance, first end is connected with pull-up node, and the second end is connected with described gate drive signal output terminal;

Output control unit, the current potential of described pull-up node is drawn high in the charging stage of each display cycle by charging to described memory capacitance for controlling, maintain the current potential of described pull-up node in the output stage of each display cycle and control described gate drive signal output terminal and export the first signal, control to drag down the current potential of described pull-up node at the output turn off phase of each display cycle and control described gate drive signal output terminal and export secondary signal; And,

Discharge cell, for electric charge residual in the discharge time in each display cycle memory capacitance described in section Co ntrolled release;

Described output turn off phase comprises section described discharge time.

During enforcement, described discharge cell comprises: arresting element, control end access discharge control signal, and first end is connected with described gate drive signal output terminal, and the second end is connected with discharge end;

In section discharge time of each display cycle, described in described discharge control signal controlled discharge element conductive, gate drive signal output terminal is connected with described discharge end;

In section described discharge time, described discharge end is in low level state.

During enforcement, described arresting element comprises discharge transistor;

The grid of described discharge transistor is connected with the first clock signal input terminal, and the first pole of described discharge transistor is connected with described gate drive signal output terminal, and the second pole of described discharge transistor is connected with described first clock signal input terminal;

Described discharge transistor is p-type transistor.

During enforcement, described arresting element comprises discharge transistor;

The grid of described discharge transistor is connected with the first clock signal input terminal, and the first pole of described discharge transistor is connected with described gate drive signal output terminal, and the second pole of described discharge transistor is connected with low level input end;

Described discharge transistor is p-type transistor.

During enforcement, described arresting element comprises discharge transistor;

The grid of described discharge transistor is connected with second clock signal input part, and the first pole of described discharge transistor is connected with low level input end, and the second pole of described discharge transistor is connected with described gate drive signal output terminal;

Described discharge transistor is n-type transistor, the first clock signal and second clock signal inversion.

During enforcement, shift register cell of the present invention also comprises the input end of access input signal and the reset terminal of access reset signal;

Described output control unit comprises:

Load module, is connected with described input end and described pull-up node respectively, charges under the control of described input signal for the charging stage in each display cycle to described memory capacitance;

First output module, is connected with described pull-up node and described gate drive signal output terminal respectively, and under the control of described pull-up node, described in the output stage control of each display cycle, gate drive signal output terminal exports the first signal;

Reseting module, be connected with described reset terminal, described pull-up node and described gate drive signal output terminal respectively, under the control of described reset signal, described pull-up node is resetted for the output turn off phase in each display cycle, and control described gate drive signal output terminal output secondary signal;

Pull-down node control module, be connected with pull-down node and described pull-up node respectively, be low level for controlling the current potential of described pull-down node when the current potential of described pull-up node is high level, and be high level at the current potential that described output turn off phase controls described pull-down node;

Pull-up node control module, is connected with described pull-up node and described pull-down node respectively, is low level for controlling the current potential of described pull-up node when the current potential of described pull-down node is high level; And,

Second output module, is connected with described pull-down node and described gate drive signal output terminal respectively, at described output turn off phase, under the control of described pull-down node, controls described gate drive signal output terminal and exports secondary signal.

During enforcement, described load module comprises input transistors;

The grid of described input transistors is all connected with described input end with the first pole of described input transistors, and the second pole of described input transistors is connected with described pull-up node.

During enforcement, described first output module comprises the first output transistor;

The grid of described first output transistor is connected with described pull-up node, and the first pole of described first output transistor is connected with described first clock signal input terminal, and the second pole of described first output transistor is connected with described gate drive signal output terminal.

During enforcement, described reseting module, comprises the first reset transistor and the second reset transistor;

The grid of described first reset transistor is connected with described reset terminal, and the first pole of described first reset transistor is connected with described pull-up node, the second pole access low level of described first reset transistor;

The grid of described second reset transistor is connected with described reset terminal, and the first pole of described second reset transistor is connected with described gate drive signal output terminal, the second pole access secondary signal of described second reset transistor.

During enforcement, described pull-down node control module comprises the first pull-down node and controls transistor, the second pull-down node control transistor and the 3rd pull-down node control transistor;

The grid that described first pull-down node controls transistor is connected with described pull-up node, and the first pole that described first pull-down node controls transistor is connected with described pull-down node, and described first pull-down node controls the second pole access low level of transistor;

High level is all accessed in first pole of grid and described second pull-down node control transistor that described second pull-down node controls transistor, and the second pole that described second pull-down node controls transistor is connected with described pull-down node;

The grid that described 3rd pull-down node controls transistor is connected with described reset terminal, and described 3rd pull-down node controls the first pole access high level of transistor, and the second pole that described 3rd pull-down node controls transistor is connected with described pull-down node.

During enforcement, described pull-up node control module comprises pull-up node control transistor;

The grid of described pull-up node control transistor is connected with described pull-down node, and the first pole of described pull-up node control transistor is connected with described pull-up node, the second pole access low level of described pull-up node control transistor.

During enforcement, described second output module comprises the second output transistor;

The grid of described second output transistor is connected with described pull-down node, and the first pole of described second output transistor is connected with described gate drive signal output terminal, the second pole access secondary signal of described second output transistor.

During enforcement, described first signal is high level signal, and described secondary signal is low level signal; Or,

Described first signal is low level signal, and described secondary signal is high level signal.

Present invention also offers a kind of driving method of shift register cell, be applied to above-mentioned shift register cell, it is characterized in that, described driving method comprises:

In the charging stage of each display cycle, output control unit is by drawing high the current potential of described pull-up node to described memory capacitance charging;

In the output stage of each display cycle, output control unit maintains the current potential of described pull-up node and controls described gate drive signal output terminal and export the first signal;

At the output turn off phase of each display cycle, output control unit control drags down the current potential of described pull-up node and controls described gate drive signal output terminal output secondary signal;

In section discharge time that the output turn off phase of each display cycle comprises, electric charge residual in memory capacitance described in discharge cell Co ntrolled release.

During enforcement, when described discharge cell comprises arresting element, described section discharge time comprised at the output turn off phase of each display cycle, charge step residual in memory capacitance described in discharge cell Co ntrolled release comprises: section discharge time comprised at the output turn off phase of each display cycle, discharge control signal controlled discharge element conductive, thus control described gate drive signal output terminal and be connected with the discharge end being in low level state.

Present invention also offers a kind of driving method of shift register cell, be applied to above-mentioned shift register cell, described driving method comprises:

In section discharge time that the output turn off phase of each display cycle comprises, when the first clock signal input terminal input low level, discharge transistor conducting, thus control described gate drive signal output terminal and the first clock signal input terminal conducting.

In section discharge time that the output turn off phase of each display cycle comprises, when the first clock signal input terminal input low level, discharge transistor conducting, thus control described gate drive signal output terminal and the conducting of low level input end.

In section discharge time that the output turn off phase of each display cycle comprises, when second clock signal input part input high level, discharge transistor conducting, thus control described gate drive signal output terminal and the conducting of low level input end.

Present invention also offers a kind of gate driver circuit, comprise multistage above-mentioned shift register cell;

Except first order shift register cell, the input end of shift register cell described in every one-level is connected with the gate drive signal output terminal of upper level shift register cell;

Except afterbody shift register cell, the reset terminal of shift register cell described in every one-level is connected with the gate drive signal output terminal of next stage shift register cell.

Present invention also offers a kind of display device, comprise above-mentioned gate driver circuit.

Compared with prior art, shift register cell of the present invention and driving method, gate driver circuit and display device, discharge cell is adopted to get rid of in memory capacitance residual charge to the impact of gate drive signal in section discharge time of each display cycle, ensure the accurate output of gate drive signal, thus the circuit structure of shift register cell can be optimized, optimize display panel global design.

Accompanying drawing explanation

Figure 1A is the structural drawing of the shift register cell described in the embodiment of the present invention;

Figure 1B is that the shift register cell shown in Figure 1A of the present invention is high level signal at the first signal, working timing figure when secondary signal is low level signal;

Fig. 1 C is that the shift register cell shown in Figure 1A of the present invention is low level signal at the first signal, working timing figure when secondary signal is high level signal;

Fig. 2 is the structural drawing that discharge cell that the shift register cell described in the embodiment of the present invention comprises comprises arresting element;

Fig. 3 A is the structural drawing of the shift register cell described in another embodiment of the present invention;

Fig. 3 B is the structural drawing of the shift register cell described in further embodiment of this invention;

Fig. 3 C is the structural drawing of the shift register cell described in yet another embodiment of the invention;

Fig. 4 is the structure structural drawing of the shift register cell described in another embodiment of the present invention;

Fig. 5 is the circuit diagram of the first specific embodiment of shift register cell of the present invention;

Fig. 6 is the working timing figure of the first specific embodiment of shift register cell of the present invention;

Fig. 7 is the circuit diagram of the second specific embodiment of shift register cell of the present invention;

Fig. 8 is the circuit diagram of the 3rd specific embodiment of shift register cell of the present invention;

Fig. 9 is the working timing figure of the 3rd specific embodiment of shift register cell of the present invention;

Figure 10 is the circuit diagram of the 4th specific embodiment of shift register cell of the present invention;

Figure 11 is the working timing figure of the 4th specific embodiment of shift register cell of the present invention.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.

As shown in Figure 1A, the shift register cell described in the embodiment of the present invention, comprise gate drive signal output terminal OUTPUT, described shift register cell also comprises:

Memory capacitance C1, first end is connected with pull-up node PU, and the second end is connected with described gate drive signal output terminal OUTPUT;

Output control unit 11, the current potential of described pull-up node PU is drawn high at the charging stage T1 of each display cycle by charging to described memory capacitance C1 for controlling, maintain the current potential of described pull-up node PU at the output stage T2 of each display cycle and control described gate drive signal output terminal OUTPUT and export the first signal, control to drag down the current potential of described pull-up node PU at the output turn off phase T3 of each display cycle and control described gate drive signal output terminal OUTPUT and export secondary signal; And,

Discharge cell 12, for electric charge residual in the discharge time in each display cycle memory capacitance C1 described in section Co ntrolled release;

Described output turn off phase T3 comprises section described discharge time.

Figure 1B is the working timing figure of the present invention's shift register cell as shown in Figure 1A, and in fig. ib, the charging stage is denoted as T1, and the output stage is denoted as T2, exports turn off phase and is denoted as T3.

Described discharge time, section was contained in described output turn off phase T3, namely can complete the release of electric charge residual in memory capacitance C1 in all or part of time exporting turn off phase T4.

Shift register cell described in the embodiment of the present invention adopts discharge cell 12 to get rid of in memory capacitance residual charge to the impact of gate drive signal in section discharge time of each display cycle, ensure the accurate output of gate drive signal, thus the circuit structure of shift register cell can be optimized, optimize display panel global design.

Working timing figure shown in Figure 1B is with the first signal for high level signal, and secondary signal is low level signal is that example is drawn, but the type selecting of the first signal and secondary signal is not limited to this.

Also namely when practical operation, according to the requirement of different gate drive signals, described first signal can be low level signal, described secondary signal can be high level signal, like this, as shown in Figure 1 C, OUTPUT export gate drive signal and the gate drive signal shown in Figure 1B anti-phase.

When practical operation, according to a kind of embodiment, described discharge cell 12 can be connected with the first end of described memory capacitance C1 (i.e. described memory capacitance C1 be connected with pull-up node PU terminal), namely by the first end release electric charge of described memory capacitance C1;

According to another kind of embodiment, described discharge cell 12 also can connect with second end of described memory capacitance C1 (i.e. described memory capacitance C1 be connected with gate drive signal output terminal OUTPUT terminal), namely by the second end release electric charge of described memory capacitance C1; (embodiment shown in Fig. 1 is discharge cell 12 and is connected with second end of memory capacitance C1)

According to another embodiment, described discharge cell 12 also can be connected with the first end of described memory capacitance C1 and second end of described memory capacitance C1 simultaneously, discharges electric charge by the first end of described memory capacitance C1 and the second end simultaneously.

Concrete, as shown in Figure 2, described discharge cell 12 can comprise: arresting element 121, control end access discharge control signal Ctrl, and first end is connected with described gate drive signal output terminal OUTPUT, and the second end is connected with discharge end DT;

In section discharge time of each display cycle, described discharge control signal Ctrl controls gate drive signal output terminal OUTPUT described in conducting and is connected with described discharge end DT;

In section described discharge time, described discharge end DT is in low level state, and in such memory capacitance C1, residual charge can be discharged to discharge end DT by the arresting element 121 of conducting, to ensure the accurate output of gate drive signal.

Concrete, as shown in Figure 3A, described arresting element 121 can comprise: discharge transistor M12;

The grid of described discharge transistor M12 is connected with the first clock signal input terminal CLK, first pole of described discharge transistor M12 is connected with described gate drive signal output terminal OUTPUT, and second pole of described discharge transistor M12 is connected with described first clock signal input terminal CLK;

Described discharge transistor M12 is p-type transistor;

In embodiment as shown in Figure 3A, arresting element 121 comprises discharge transistor M12, the control end of arresting element 121 is the grid of discharge transistor M12, the first end of arresting element 121 is first pole of discharge transistor M12, second end of arresting element 121 is second pole of discharge transistor M12, and discharge end is the first clock signal input terminal CLK;

When the first clock signal inputted by CLK is low level, electric charge residual in memory capacitance C1 is discharged to the first clock signal input terminal CLK of now input low level by the discharge transistor M12 of conducting, residual charge in memory capacitance C1 can be got rid of by discharge transistor M12 in section discharge time of each display cycle like this and, on the impact of gate drive signal, ensure the accurate output of gate drive signal.

Concrete, as shown in Figure 3 B, described arresting element 121 can comprise discharge transistor M12;

The grid of described discharge transistor M12 is connected with the first clock signal input terminal CLK, and first pole of described discharge transistor M12 is connected with described gate drive signal output terminal OUTPUT, and second pole of described discharge transistor M12 is connected with low level input end;

Described discharge transistor M12 is p-type transistor; By described low level input end input low level VSS;

In embodiment as shown in Figure 3 B, arresting element 121 comprises discharge transistor M12, the control end of arresting element 121 is the grid of discharge transistor M12, the first end of arresting element 121 is first pole of discharge transistor M12, second end of arresting element 121 is second pole of discharge transistor M12, and discharge end is low level input end;

When the first clock signal inputted by CLK is low level, electric charge residual in memory capacitance C1 is discharged to low level input end by the discharge transistor M12 of conducting, residual charge in memory capacitance C1 can be got rid of by discharge transistor M12 in section discharge time of each display cycle like this and, on the impact of gate drive signal, ensure the accurate output of gate drive signal.

Concrete, as shown in Figure 3 C, described discharge cell 12 can comprise discharge transistor M12;

The grid of described discharge transistor M12 is connected with second clock signal input part CLKB, and first pole of described discharge transistor M12 is connected with low level input end, and second pole of described discharge transistor M12 is connected with described gate drive signal output terminal OUTPUT;

Described discharge transistor M12 is n-type transistor, the first clock signal inputted by the first clock signal input terminal CLK and the second clock signal inversion inputted by second clock signal input part CLKB;

In embodiment as shown in Figure 3 C, arresting element 121 comprises discharge transistor M12, the control end of arresting element 121 is the grid of discharge transistor M12, the first end of arresting element 121 is second pole of discharge transistor M12, second end of arresting element 121 is first pole of discharge transistor M12, and discharge end is low level input end;

When the second clock signal inputted by CLKB is high level, electric charge residual in memory capacitance C1 is discharged to low level input end by the discharge transistor M12 of conducting, residual charge in memory capacitance C1 can be got rid of by discharge transistor M12 in section discharge time of each display cycle like this and, on the impact of gate drive signal, ensure the accurate output of gate drive signal.

As shown in Figure 4, the shift register cell described in the embodiment of the present invention also comprises the input end INPUT of access input signal and the reset terminal RESET of access reset signal;

As shown in Figure 4, described output control unit comprises:

Load module 111, is connected with described input end INPUT and described pull-up node PU respectively, charges for the charging stage in each display cycle under the control of described input signal to described memory capacitance C1;

First output module 112, be connected with described pull-up node PU and described gate drive signal output terminal OUTPUT respectively, for under the control of described pull-up node PU, described in the output stage control of each display cycle, gate drive signal output terminal OUTPUT exports high level;

Reseting module 113, be connected with described reset terminal RESET, described pull-up node PU and described gate drive signal output terminal OUTPUT respectively, under the control of described reset signal, described pull-up node PU and described gate drive signal output terminal OUTPUT resetted for the output turn off phase in each display cycle;

Pull-down node control module 114, be connected with pull-down node PD and described pull-up node PU respectively, be low level for controlling the current potential of described pull-down node PD when the current potential of described pull-up node PU is high level, and be high level at the current potential that the output turn off phase of each display cycle controls described pull-down node PD;

Pull-up node control module 115, is connected with described pull-up node PU and described pull-down node PD respectively, is low level for controlling the current potential of described pull-up node PU when the current potential of described pull-down node PD is high level; And,

Second output module 116, be connected with described pull-down node PD and described gate drive signal output terminal OUTPUT respectively, for the output turn off phase in each display cycle, under the control of described pull-down node PD, control described gate drive signal output terminal OUTPUT output low level.

The present invention's shift register cell as shown in Figure 4 operationally, described output control unit controls to charge to memory capacitance C1 in the charging stage of each display cycle by adopting load module 111, export turn off phase by adopting reseting module 113 at each to control to reset to pull-up node PU and gate drive signal output terminal OUTPUT, by adopting pull-down node control module 114, pull-up node control module 115 controls the current potential of pull-down node PD respectively, the current potential of pull-up node PU, thus the first output module 112 exports high level at the output stage control gate drive signal output terminal OUTPUT of each display cycle, second output module 116 is in the output turn off phase control gate drive singal output terminal OUTPUT output low level of each display cycle, thus correctly can export gate drive signal by control gate drive singal output terminal OUTPUT.

Concrete, described load module can comprise input transistors;

The grid of described load module is all connected with described input end with the first pole of described load module, and the second pole of described load module is connected with described pull-up node.

Concrete, described first output module can comprise the first output transistor;

Concrete, described reseting module can comprise the first reset transistor and the second reset transistor;

The grid of described first reset transistor is connected with described reset terminal, and the first pole of described first reset transistor is connected with described pull-up node, the second pole access low level of described first reset transistor; And,

Second reset transistor, the grid of described second reset transistor is connected with described reset terminal, and the first pole of described second reset transistor is connected with described gate drive signal output terminal, the second pole access low level of described second reset transistor.

Concrete, described pull-down node control module can comprise the first pull-down node and control transistor, the second pull-down node control transistor and the 3rd pull-down node control transistor;

High level is all accessed in first pole of grid and described second pull-down node control transistor that described second pull-down node controls transistor, and the second pole that described second pull-down node controls transistor is connected with described pull-down node; And,

Concrete, described pull-up node control module can comprise pull-up node control transistor;

Concrete, described second output module can comprise the second output transistor;

Second output transistor gates is connected with described pull-down node, and the second output transistor first pole is connected with described gate drive signal output terminal, the second output transistor second pole access low level.

The transistor adopted in all embodiments of the present invention can be all thin film transistor (TFT) or field effect transistor or the identical device of other characteristics.In embodiments of the present invention, for distinguishing transistor the two poles of the earth except grid, wherein will be called source electrode in a pole, another pole is called drain electrode.In addition, distinguish transistor can be divided into n-type transistor or p-type transistor according to the characteristic of transistor.

Below by four specific embodiments, shift register cell of the present invention is described.

As shown in Figure 5, the first specific embodiment of shift register cell of the present invention comprises input end INPUT, reset terminal RESET, gate drive signal output terminal OUTPUT, memory capacitance C1, output control unit and discharge cell;

Described output control unit comprises load module, the first output module, reseting module, pull-down node control module, pull-up node control module and the second output module, wherein,

Described load module comprises input transistors M1; The grid of described input transistors M1 is all connected with described input end INPUT with the drain electrode of described input transistors M1, and the source electrode of described input transistors M1 is connected with described pull-up node PU.

Described first output module can comprise the first output transistor M2; The grid of described first output transistor M2 is connected with described pull-up node PU, the drain electrode of described first output transistor M2 is connected with described first clock signal input terminal CLK, and the source electrode of described first output transistor M2 is connected with described gate drive signal output terminal OUTPUT.

Described reseting module can comprise the first reset transistor M3 and the second reset transistor M4;

The grid of described first reset transistor M3 is connected with described reset terminal RESET, and the drain electrode of described first reset transistor M3 is connected with described pull-up node PU, the source electrode access low level VSS of described first reset transistor M3;

The grid of described second reset transistor M4 is connected with described reset terminal RESET, and the drain electrode of described second reset transistor M4 is connected with described gate drive signal output terminal OUTPUT, the source electrode access low level VSS of described second reset transistor M4;

Described pull-down node control module comprises the first pull-down node and controls transistor M5, the second pull-down node control transistor M6 and the 3rd pull-down node control transistor M7;

The grid that described first pull-down node controls transistor M5 is connected with described pull-up node PU, and the drain electrode that described first pull-down node controls transistor M5 is connected with described pull-down node PD, and described first pull-down node controls the source electrode access low level VSS of transistor M5;

The drain electrode of grid and described second pull-down node control transistor M6 that described second pull-down node controls transistor M6 all accesses high level VDD, and the source electrode that described second pull-down node controls transistor M6 is connected with described pull-down node PD;

The grid that described 3rd pull-down node controls transistor M7 is connected with described reset terminal RESET, described 3rd pull-down node controls the drain electrode access high level VDD of transistor M7, and the source electrode that described 3rd pull-down node controls transistor M7 is connected with described pull-down node PD;

Described pull-up node control module 115 comprises pull-up node control transistor M8;

The grid of described pull-up node control transistor M8 is connected with described pull-down node PD, and the drain electrode of described pull-up node control transistor M8 is connected with described pull-up node PU, the source electrode access low level VSS of described pull-up node control transistor M8;

Described second output module 116 comprises the second output transistor M9;

The grid of described second output transistor M9 is connected with described pull-down node PD, and the drain electrode of described second output transistor M9 is connected with described gate drive signal output terminal OUTPUT, the source electrode access low level VSS of described second output transistor M9;

Described discharge cell comprises discharge transistor M10;

The grid of described discharge transistor M10 is all connected with described first clock signal input terminal CLK with the source electrode of described discharge transistor M10, and the drain electrode of described discharge transistor M10 is connected with described gate drive signal output terminal OUTPUT;

In the first specific embodiment of shift register cell as shown in Figure 5, discharge transistor M10 is p-type transistor, and remaining transistor is all n-type transistor.

As shown in Figure 6, the first specific embodiment of the present invention's shift register cell as shown in Figure 5 operationally,

At the charging stage T1 of each display cycle, the first clock signal inputted by CLK is low level, the input signal inputted by INPUT is high level, the reset signal inputted by RESET is low level, M1 conducting, by input signal, C1 charging is drawn high to the current potential of PU, M2 conducting, now OUTPUT output low level; Current potential due to PU is high level, therefore M5 conducting, and the current potential of PD is low level;

At the output stage T2 of each display cycle, the first clock signal inputted by CLK is high level, and the input signal inputted by INPUT is low level, the reset signal inputted by RESET is low level, the current potential of PU is drawn high by C1 bootstrapping, and M3 continues conducting, and OUTPUT exports high level; Potential duration due to PU is high level, and therefore M5 continues conducting, and the potential duration of PD is low level;

At section T31 reset time that the output turn off phase T3 of each display cycle comprises, the first clock signal inputted by CLK is low level, the input signal inputted by INPUT is low level, the reset signal inputted by RESET is high level, now M3 conducting, the current potential of PU is dragged down into low level, and now M6 conducting, with by the current potential pull-up of PD for high level, thus control M8 and M9 all conductings, thus control OUTPUT output low level, now M10 also conducting, thus the electric charge remained in C1 can be discharged, the impact that in C1, residual charge exports gate drive signal can be got rid of, ensure that the accurate output of gate drive signal,

At the output cut-off retention time section T32 that the output turn off phase T3 of each display cycle comprises, the input signal inputted by INPUT is low level, and the reset signal inputted by RESET is low level, M6 constant conduction, with the potential duration of control PD for high level; The first clock signal inputted by CLK is alternately high level and low level;

When described first clock signal is low level, M10 conducting, thus the electric charge remained in C1 is released into CLK by M10, the impact that in C1, residual charge exports gate drive signal can be got rid of, ensure that the accurate output of gate drive signal;

In the first specific embodiment of shift register cell of the present invention, discharge time section comprise reset time section and export cut-off retention time section in the first clock signal be low level part-time section.

As shown in Figure 7, the second specific embodiment of shift register cell of the present invention comprises input end INPUT, reset terminal RESET, gate drive signal output terminal OUTPUT, memory capacitance C1, output control unit and discharge cell;

Described second output module 116 comprises the second output transistor M9;

Described discharge cell comprises discharge transistor M10;

The grid of described discharge transistor M10 is connected with the first clock signal input terminal CLK, and the source electrode of described discharge transistor M10 is connected with described gate drive signal output terminal OUTPUT, and the drain electrode of described discharge transistor M10 is connected with low level input end;

By described low level input end input low level VSS;

In the second specific embodiment of shift register cell as shown in Figure 7, discharge transistor M10 is p-type transistor, and remaining transistor is all n-type transistor.

As shown in Figure 6, the second specific embodiment of the present invention's shift register cell as shown in Figure 7 operationally,

At section T31 reset time that the output turn off phase T3 of each display cycle comprises, the first clock signal inputted by CLK is low level, the input signal inputted by INPUT is low level, the reset signal inputted by RESET is high level, now M3 conducting, the current potential of PU is dragged down into low level, and now M6 conducting, with by the current potential pull-up of PD for high level, thus control M8 and M9 all conductings, thus control OUTPUT output low level, now M10 also conducting, thus can by the electric charge remained in C1 by being released into low level input end, the impact that in C1, residual charge exports gate drive signal can be got rid of, ensure that the accurate output of gate drive signal,

When described second clock signal is high level, M10 conducting, thus the electric charge remained in C1 is discharged to low level input end by M10, the impact that in C1, residual charge exports gate drive signal can be got rid of, ensure that the accurate output of gate drive signal;

In the second specific embodiment of the present invention's shift register cell as shown in Figure 7, discharge time section comprise reset time section and export cut-off retention time section in the first clock signal be low level part-time section.

As shown in Figure 8, the 3rd specific embodiment of shift register cell of the present invention comprises input end INPUT, reset terminal RESET, gate drive signal output terminal OUTPUT, memory capacitance C1, output control unit and discharge cell;

Described second output module 116 comprises the second output transistor M9;

Described discharge cell comprises discharge transistor M10;

The grid of described discharge transistor M10 is connected with second clock signal input part CLKB, and the drain electrode of described discharge transistor M10 is connected with low level input end, and the source electrode of described discharge transistor M10 is connected with described gate drive signal output terminal OUTPUT;

The first clock signal inputted by the first clock signal input terminal CLK and the second clock signal inversion inputted by second clock signal input part CLKB;

In the 3rd specific embodiment of shift register cell as shown in Figure 8, all transistors are all n-type transistor.

As shown in Figure 9, the 3rd specific embodiment of the present invention's shift register cell as shown in Figure 8 operationally,

At the charging stage T1 of each display cycle, the first clock signal inputted by CLK is low level, the second clock signal inputted by CLKB is high level, M10 conducting, the input signal inputted by INPUT is high level, and the reset signal inputted by RESET is low level, M1 conducting, by input signal, C1 charging is drawn high to the current potential of PU, M2 conducting, now OUTPUT output low level; Current potential due to PU is high level, therefore M5 conducting, and the current potential of PD is low level;

At the output stage T2 of each display cycle, the first clock signal inputted by CLK is high level, the second clock signal inputted by CLKB is low level, the input signal inputted by INPUT is low level, the reset signal inputted by RESET is low level, the current potential of PU is drawn high by C1 bootstrapping, and M3 continues conducting, and OUTPUT exports high level; Potential duration due to PU is high level, and therefore M5 continues conducting, and the potential duration of PD is low level;

At section T31 reset time that the output turn off phase T3 of each display cycle comprises, the first clock signal inputted by CLK is low level, the second clock signal inputted by CLKB is high level, the input signal inputted by INPUT is low level, the reset signal inputted by RESET is high level, now M3 conducting, the current potential of PU is dragged down into low level, and now M6 conducting, with by the current potential pull-up of PD for high level, thus control M8 and M9 all conductings, thus control OUTPUT output low level, now M10 also conducting, thus the electric charge remained in C1 can be released into low level input end by M10, the impact that in C1, residual charge exports gate drive signal can be got rid of, ensure that the accurate output of gate drive signal,

When described first clock signal is low level, M10 conducting, thus the electric charge remained in C1 is released into low level input end by M10, the impact that in C1, residual charge exports gate drive signal can be got rid of, ensure that the accurate output of gate drive signal;

In the 3rd specific embodiment of shift register cell of the present invention, discharge time section comprise reset time section and the second clock signal exported in cut-off retention time section be the part-time section of high level.

In the first specific embodiment of shift register cell of the present invention, the second specific embodiment and the 3rd specific embodiment, all for high level signal with the first signal, secondary signal is low level signal is that example illustrates, in 4th specific embodiment of the shift register cell of the present invention recorded below, first signal is low level signal, and secondary signal is high level signal.

As shown in Figure 10, the 4th specific embodiment of shift register cell of the present invention comprises input end INPUT, reset terminal RESET, gate drive signal output terminal OUTPUT, memory capacitance C1, output control unit and discharge cell;

Described second output module 116 comprises the second output transistor M9;

The grid of described second output transistor M9 is connected with described pull-down node PD, and the drain electrode of described second output transistor M9 is connected with described gate drive signal output terminal OUTPUT, the source electrode access high level VDD of described second output transistor M9;

Described discharge cell comprises discharge transistor M10;

In the 4th specific embodiment of shift register cell as shown in Figure 10, discharge transistor M10 is p-type transistor, and remaining transistor is all n-type transistor.

As shown in figure 11, the 4th specific embodiment of the present invention's shift register cell as shown in Figure 10 operationally,

At the charging stage T1 of each display cycle, the first clock signal inputted by CLK is high level, the input signal inputted by INPUT is high level, the reset signal inputted by RESET is low level, M1 conducting, by input signal, C1 charging is drawn high to the current potential of PU, M2 conducting, now OUTPUT exports high level; Current potential due to PU is high level, therefore M5 conducting, and the current potential of PD is low level;

At the output stage T2 of each display cycle, the first clock signal inputted by CLK is low level, and the input signal inputted by INPUT is low level, the reset signal inputted by RESET is low level, the current potential of PU is drawn high by C1 bootstrapping, and M3 continues conducting, OUTPUT output low level; Potential duration due to PU is high level, and therefore M5 continues conducting, and the potential duration of PD is low level;

At section T31 reset time that the output turn off phase T3 of each display cycle comprises, the first clock signal inputted by CLK is high level, the input signal inputted by INPUT is low level, the reset signal inputted by RESET is high level, now M3 and M4 all conductings, the current potential of PU is dragged down into low level, and now M6 conducting, with by the current potential pull-up of PD for high level, thus control M8 and M9 all conductings, thus control OUTPUT exports high level, now M10 also conducting, thus the electric charge remained in C1 can be discharged, the impact that in C1, residual charge exports gate drive signal can be got rid of, ensure that the accurate output of gate drive signal,

At the output cut-off retention time section T32 that the output turn off phase T3 of each display cycle comprises, the input signal inputted by INPUT is low level, and the reset signal inputted by RESET is low level, M6 constant conduction, with the potential duration of control PD for high level; The first clock signal inputted by CLK is alternately low level and high level;

In the 4th specific embodiment of shift register cell of the present invention, discharge time section comprise reset time section and export cut-off retention time section in the first clock signal be low level part-time section.

The driving method of the shift register cell described in the embodiment of the present invention, is applied to above-mentioned shift register cell, and each display cycle comprises charging stage, output stage successively and exports turn off phase; Described output turn off phase comprises section discharge time;

Described driving method comprises:

In section discharge time of each display cycle, electric charge residual in memory capacitance described in discharge cell Co ntrolled release.

The driving method of the shift register cell described in the embodiment of the present invention to get rid of in memory capacitance residual charge to the impact of gate drive signal in section discharge time of each display cycle by discharge cell, ensure the accurate output of gate drive signal, thus the circuit structure of shift register cell can be optimized, optimize display panel global design.

Concrete, when described discharge cell comprises arresting element, described section discharge time comprised at the output turn off phase of each display cycle, charge step residual in memory capacitance described in discharge cell Co ntrolled release comprises: section discharge time comprised at the output turn off phase of each display cycle, discharge control signal controlled discharge element conductive, thus control described gate drive signal output terminal and be connected with the discharge end being in low level state, discharge end can be released into by the arresting element of conducting with electric charge residual in control store electric capacity.

The driving method of another embodiment of the present invention shift register cell, is applied to shift register as shown in Figure 3A, and described driving method comprises:

In section discharge time that the output turn off phase of each display cycle comprises, when the first clock signal input terminal input low level, discharge transistor conducting, thus control described gate drive signal output terminal and the first clock signal input terminal conducting;

Section discharge time that driving method described in this embodiment of the invention comprises at the output turn off phase of each display cycle, when the first clock signal is low level, electric charge residual in control store electric capacity is released into the first clock signal input terminal by the discharge transistor of conducting, to get rid of the impact that in memory capacitance, residual charge exports gate drive signal, ensure that the accurate output of gate drive signal.

The driving method of the shift register cell described in further embodiment of this invention, is applied to shift register as shown in Figure 3 B, and described driving method comprises:

In section discharge time that the output turn off phase of each display cycle comprises, when the first clock signal input terminal input low level, discharge transistor conducting, thus control described gate drive signal output terminal and the conducting of low level input end;

Section discharge time that driving method described in this embodiment of the invention comprises at the output turn off phase of each display cycle, when the first clock signal is low level, electric charge residual in control store electric capacity is released into low level input end by the discharge transistor of conducting, to get rid of the impact that in memory capacitance, residual charge exports gate drive signal, ensure that the accurate output of gate drive signal.

The driving method of the shift register cell of the present invention again described in a specific embodiment, is applied to shift register as shown in Figure 3 C, and described driving method comprises:

In section discharge time that the output turn off phase of each display cycle comprises, when second clock signal input part input high level, discharge transistor conducting, thus control described gate drive signal output terminal and the conducting of low level input end;

Section discharge time that driving method described in this embodiment of the invention comprises at the output turn off phase of each display cycle, when second clock signal is high level, electric charge residual in control store electric capacity is released into low level input end by the discharge transistor of conducting, to get rid of the impact that in memory capacitance, residual charge exports gate drive signal, ensure that the accurate output of gate drive signal.

Gate driver circuit described in the embodiment of the present invention comprises multistage above-mentioned shift register cell;

Display device described in the embodiment of the present invention comprises above-mentioned gate driver circuit.

The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims

1. a shift register cell, is characterized in that, comprises gate drive signal output terminal, and described shift register cell also comprises:

Described output turn off phase comprises section described discharge time.

2. shift register cell as claimed in claim 1, it is characterized in that, described discharge cell comprises: arresting element, control end access discharge control signal, and first end is connected with described gate drive signal output terminal, and the second end is connected with discharge end;

3. shift register cell as claimed in claim 2, it is characterized in that, described arresting element comprises discharge transistor;

Described discharge transistor is p-type transistor.

4. shift register cell as claimed in claim 2, it is characterized in that, described arresting element comprises discharge transistor;

Described discharge transistor is p-type transistor.

5. shift register cell as claimed in claim 2, it is characterized in that, described arresting element comprises discharge transistor;

6. shift register cell as claimed in claim 1, is characterized in that, also comprises the input end of access input signal and the reset terminal of access reset signal;

Described output control unit comprises:

7. shift register cell as claimed in claim 6, it is characterized in that, described load module comprises input transistors;

8. shift register cell as claimed in claim 6, it is characterized in that, described first output module comprises the first output transistor;

9. shift register cell as claimed in claim 6, is characterized in that, described reseting module, comprises the first reset transistor and the second reset transistor;

10. shift register cell as claimed in claim 6, is characterized in that, described pull-down node control module comprises the first pull-down node and controls transistor, the second pull-down node control transistor and the 3rd pull-down node control transistor;

11. shift register cells as claimed in claim 6, it is characterized in that, described pull-up node control module comprises pull-up node control transistor;

12. shift register cells as claimed in claim 6, it is characterized in that, described second output module comprises the second output transistor;

13. shift register cells as described in claim arbitrary in claim 1 to 12, described first signal is high level signal, and described secondary signal is low level signal; Or,

The driving method of 14. 1 kinds of shift register cells, be applied to the shift register cell as described in claim arbitrary in claim 1 to 13, it is characterized in that, described driving method comprises:

The driving method of 15. shift registers as claimed in claim 14, it is characterized in that, when described discharge cell comprises arresting element, described section discharge time comprised at the output turn off phase of each display cycle, charge step residual in memory capacitance described in discharge cell Co ntrolled release comprises: section discharge time comprised at the output turn off phase of each display cycle, discharge control signal controlled discharge element conductive, thus control described gate drive signal output terminal and be connected with the discharge end being in low level state.

The driving method of 16. 1 kinds of shift register cells, be applied to the shift register cell as described in claim 3,6,7,8,9,10,11,12 or 13, it is characterized in that, described driving method comprises:

The driving method of 17. 1 kinds of shift register cells, be applied to the shift register cell as described in claim 4,6,7,8,9,10,11,12 or 13, it is characterized in that, described driving method comprises:

The driving method of 18. 1 kinds of shift register cells, be applied to the shift register cell as described in claim arbitrary in claim 5 to 13, it is characterized in that, described driving method comprises:

19. 1 kinds of gate driver circuits, is characterized in that, comprise multistage shift register cell as described in claim arbitrary in claim 1 to 13;

20. 1 kinds of display device, is characterized in that, comprise gate driver circuit as claimed in claim 19.