CN116701069A

CN116701069A - Data path testing method, device, apparatus, storage medium and program product

Info

Publication number: CN116701069A
Application number: CN202210176980.5A
Authority: CN
Inventors: 强鹏
Original assignee: Tencent Technology Shenzhen Co Ltd
Current assignee: Tencent Technology Shenzhen Co Ltd
Priority date: 2022-02-25
Filing date: 2022-02-25
Publication date: 2023-09-05

Abstract

The application provides a data path testing method, a device, an electronic device, a computer readable storage medium and a computer program product of a memory; relates to artificial intelligence and chip technology, and the method comprises the following steps: sequentially transmitting a plurality of random numbers to a memory according to a writing sequence through a test host; performing chained processing on a plurality of random numbers according to a writing sequence through a circuit of a test host to obtain a first chained processing result; reading a second chained processing result from the memory; the second chained processing result is obtained by chained processing the received random numbers according to the receiving sequence through a circuit of the memory, and the bit number of the second chained processing result corresponds to the bit number of the last random number received by the memory; and comparing the first chain type processing result with the second chain type processing result through the test host, and determining that the data path test of the memory passes when the comparison results are consistent. The application can improve the data path test efficiency of the memory.

Description

Data path testing method, device, apparatus, storage medium and program product

Technical Field

The present application relates to artificial intelligence and chip technology, and more particularly, to a method, an apparatus, an electronic device, a computer readable storage medium, and a computer program product for testing a data path of a memory.

Background

Artificial intelligence (AI, artificial Intelligence) is the theory, method and technique and application system that uses a digital computer or a machine controlled by a digital computer to simulate, extend and extend human intelligence, sense the environment, acquire knowledge and use the knowledge to obtain optimal results.

High bandwidth memory is a standardized stack storage technique that provides a high bandwidth channel for data within the stack and between storage and logic elements. The high bandwidth memory package stacks the memory dies, so that a higher read-write speed can be realized, and a read-write data path of the high bandwidth memory is usually required to be tested, so as to ensure the correctness of data in the process of reading and writing data at high speed.

In the related art, once verification is performed after each data reading and writing, namely, the verification is equivalent to the need of verifying the whole data, and the verification needs to be performed for many times, so that the test efficiency is lower, and the hardware processing resources are wasted.

Disclosure of Invention

The embodiment of the application provides a data path testing method and device of a memory, electronic equipment, a computer readable storage medium and a computer program product, which can improve the data path testing efficiency of the memory.

The technical scheme of the embodiment of the application is realized as follows:

the embodiment of the application provides a data path testing method of a memory, which comprises the following steps:

sequentially transmitting a plurality of random numbers to the memory according to the writing sequence through the test host;

performing chained processing on the random numbers according to the writing sequence through a circuit of the test host to obtain a first chained processing result;

wherein the bit number of the first chained processing result corresponds to the bit number of the last random number written in;

reading a second chained processing result from the memory;

the second chained processing result is obtained by chained processing the received random numbers according to the receiving sequence through a circuit of the memory, the bit number of the second chained processing result corresponds to the bit number of the last random number received by the memory, and the circuit logic of the circuit of the memory is the same as the circuit logic of the circuit of the test host;

And comparing the first chain type processing result with the second chain type processing result through the test host, and determining that the data path test of the memory passes when the comparison results are consistent.

The embodiment of the application provides a data path testing device of a memory, which comprises:

the sending module is used for sequentially sending the random numbers to the memory according to the writing sequence through the test host;

the chain module is used for carrying out chain processing on the random numbers according to the writing sequence through a circuit of the test host to obtain a first chain processing result; wherein the bit number of the first chained processing result corresponds to the bit number of the last random number written in;

a receiving module for reading a second chain processing result from the memory; the second chained processing result is obtained by chained processing the received random numbers according to the receiving sequence through a circuit of the memory, the bit number of the second chained processing result corresponds to the bit number of the last random number received by the memory, and the circuit logic of the circuit of the memory is the same as the circuit logic of the circuit of the test host;

And the comparison module is used for comparing the first chain type processing result with the second chain type processing result through the test host, and determining that the data path test of the memory passes when the comparison results are consistent.

In the above solution, the test host includes a random number generator, and before the test host sequentially sends the plurality of random numbers to the memory according to the writing sequence, the sending module is further configured to: for each of a plurality of time nodes, performing the following: generating at least one random number at the time node by a random number generator of the test host; the random numbers generated by the time nodes are mutually independent, and the writing sequence is the time sequence writing sequence of the time node for generating each random number.

In the above solution, the sending module is further configured to: before sequentially transmitting a plurality of random numbers to the memory in a writing order by a test host, performing the following processing for each of a plurality of time nodes: when the time node is the earliest time node in the plurality of time nodes, acquiring a random number of circuit configuration aiming at the test host; when the time node is not the earliest time node in the plurality of time nodes, performing digital signal processing on input data through a circuit of the test host to obtain a random number corresponding to the time node; the write sequence is a time sequence write sequence of a time node for generating each random number, and the input data of the circuit of the test host is the random number output by the last adjacent time node of the time node.

In the above scheme, the number of the circuits of the test host is a plurality; the sending module is further configured to: acquiring a random number unit configured for each circuit of the test host, and forming a plurality of random number units into the random number; each of the circuits through the test host performs the following processing: receiving a random number unit output by a previous adjacent time node, and performing digital signal processing on the received random number unit to obtain a random number unit corresponding to the time node; forming a random number unit output by each circuit of the test host at the time node into the random number; the circuits of the test host correspond to the random number units one by one.

In the above solution, the sending module is further configured to: performing, by the test host, the following processing in the write order for each of the random numbers: dividing the random number based on configuration digits to obtain a plurality of random number units; wherein the random number unit comprises at least one rising edge data bit, at least one falling edge data bit, a rising edge data mask bit, a falling edge data mask bit, a rising edge data bus flip bit, and a falling edge data bus flip bit; and transmitting the random number units to the memory in parallel.

In the above aspect, the chain module is further configured to: performing the following processing for each of the plurality of random numbers in the writing order: carrying out digital signal processing on the chain processing result of the last adjacent random number and the random number through a circuit of the test host to obtain a chain processing result corresponding to the random number; and determining a chain processing result corresponding to the random number as the first chain processing result when the random number is the last random number based on the writing order among the plurality of random numbers.

In the above scheme, the number of the circuits of the test host is a plurality; the chain module is further configured to: each of the circuits through the test host performs the following processing: receiving a chain processing result of a last adjacent random number unit, and carrying out digital signal processing on the received chain processing result of the last adjacent random number unit and a random number unit corresponding to the circuit in the random numbers to obtain a chain processing result corresponding to the random number unit; and forming a chain type processing result corresponding to the random number by using the chain type processing result corresponding to the random number unit output by each circuit of the test host.

In the above solution, each of the circuits includes N cascaded circuit units, and the chain module is further configured to: determining the input of an nth circuit unit based on the chain processing result of the last adjacent random number unit and the random number unit corresponding to the circuit in the random number; performing shift processing on the input of an nth circuit unit through an nth circuit unit in N cascaded circuit units to obtain an output bit code corresponding to the nth circuit unit; determining an input of an n+1-th circuit unit based on an output bit code corresponding to the n-th circuit unit; the method comprises the steps of continuing to carry out shift processing on the input of an n+1th circuit unit through the n+1th circuit unit to obtain output bit codes corresponding to the n+1th circuit unit; wherein, N is an integer greater than or equal to 2, N is an integer variable whose value increases from 1, and the value range of N is 1-N < N; and performing descending order sorting processing on the output bit codes of each circuit unit based on the n value of the corresponding circuit unit, and forming a plurality of output bit codes into a chain processing result corresponding to the random number unit according to the descending order sorting result.

In the above aspect, the chain module is further configured to: when the n+1-th circuit unit is directly connected with the n-th circuit unit, the output bit code of the n-th circuit unit and the input bit code corresponding to the n+1-th circuit unit in the random number unit are used as the input of the n+1-th circuit unit; when the n+1 circuit unit is connected with the N circuit unit through an exclusive or gate, performing exclusive or processing on the first bit code output by the N circuit unit at the last adjacent time node and the output bit code of the N circuit unit to obtain an exclusive or output bit code, and determining the exclusive or output bit code and the input bit code corresponding to the n+1 circuit unit in the random number unit as the input of the n+1 circuit unit.

In the above scheme, the nth circuit unit includes a first and gate, a second and gate, an exclusive or gate, and a flip-flop; the chain module is further configured to: when the value of n is 1, performing AND gate processing on the last bit code of the random number unit and the first code value through the first AND gate to obtain a first AND gate result; performing AND gate processing on the second code value and the first code of the random number unit output by the circuit at the last adjacent time node through the second AND gate to obtain a second AND gate result; performing exclusive-or processing on the first AND gate result and the second AND gate result through the exclusive-or gate to obtain an exclusive-or result, and transmitting the exclusive-or result to the trigger; when the flip-flop receives a clock signal, the exclusive-or result is determined as an output bit code of the nth circuit.

In the above scheme, the nth circuit unit includes a first and gate, a second and gate, an exclusive or gate, and a flip-flop; the chain module is further configured to: when the value range of N is 2-N < N, performing AND gate processing on the N-n+1 bit code of the random number unit and the first code value through the first AND gate to obtain a first AND gate result; when the N-1 circuit unit is connected with the N circuit unit through the exclusive-OR gate, performing exclusive-OR processing on the first bit code output by the N circuit unit at the last adjacent time node and the output bit code of the N-1 circuit unit to obtain an exclusive-OR output bit code, and performing AND gate processing on a second code value and the exclusive-OR output bit code through the second AND gate to obtain a second AND gate result; when the n-1 circuit unit is directly connected with the n circuit unit, performing AND gate processing on a second coding value and the output bit code of the n-1 circuit unit through the second AND gate to obtain a second AND gate result;

the method comprises the steps of carrying out a first treatment on the surface of the Performing exclusive-or processing on the first AND gate result and the second AND gate result through the exclusive-or gate to obtain an exclusive-or result, and transmitting the exclusive-or result to the trigger; when the flip-flop receives a clock signal, the exclusive-or result is determined as an output bit code of the nth circuit.

An embodiment of the present application provides an electronic device, including:

a memory for storing executable instructions;

and the processor is used for realizing the data path testing method of the memory when executing the executable instructions stored in the memory.

The embodiment of the application provides a computer readable storage medium which stores executable instructions for realizing the data path testing method of the memory provided by the embodiment of the application when being executed by a processor.

The embodiment of the application has the following beneficial effects:

according to the data path testing method of the memory, the test host can send the plurality of random numbers to the memory, receive the second chained processing result of the last random number returned by the memory, compare the chained processing result of the last random number returned by the memory with the first chained processing result obtained by the test host in chained processing the plurality of random numbers, so that the whole process comprises multiple data sending and single data receiving, and finally, only the second chained processing result of the last random number obtained based on single receiving is needed to be compared, the comparison times are reduced, the data quantity needed to be compared in the comparison is saved, and the data path testing efficiency of the memory is improved.

Drawings

FIG. 1 is a schematic diagram of a related art memory data path test system;

FIG. 2 is a timing diagram of a related art method for testing a data path of a memory;

FIG. 3 is a schematic diagram of a data path testing system of a memory according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

FIGS. 5A-5C are flow diagrams of a method for testing a data path of a memory according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a data path testing system of a memory according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a data path structure of a method for testing a data path of a memory according to an embodiment of the present application;

FIG. 8 is a schematic circuit diagram of a method for testing a data path of a memory according to an embodiment of the present application;

fig. 9 is a timing diagram of a data path testing method of a memory according to an embodiment of the application.

Detailed Description

The present application will be further described in detail with reference to the accompanying drawings, for the purpose of making the objects, technical solutions and advantages of the present application more apparent, and the described embodiments should not be construed as limiting the present application, and all other embodiments obtained by those skilled in the art without making any inventive effort are within the scope of the present application.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

In the following description, the terms "first\second\third" are merely used to distinguish similar objects and do not represent a particular ordering for the objects, it being understood that the "first\second\third" may interchange a particular order or sequencing of writing, if permitted, to enable embodiments of the application described herein to be implemented in other than that illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the application only and is not intended to be limiting of the application.

Before describing embodiments of the present application in further detail, the terms and terminology involved in the embodiments of the present application will be described, and the terms and terminology involved in the embodiments of the present application will be used in the following explanation.

1) Multiple-input shift register circuit (MISR, multiple-input Shift Register): in a digital circuit, a multiple input shift register circuit is a flip-flop based device that operates on several identical time pulses, into which data is input in parallel or in series, and then each time pulse is shifted one bit to the left or right in turn, and output is made at the output.

2) High-Bandwidth Memory (HBM): the high-bandwidth memory (English: high Bandwidth Memory, abbreviated HBM) is a high-performance dynamic random access memory based on three-dimensional stack technology initiated by an ultrafine semiconductor, and is suitable for application occasions with high memory bandwidth requirements, such as a graphic processor, network switching and forwarding equipment (such as a router and a switch).

In the related art, according to the related protocol of the HBM, the data read-write speed of the HBM memory can reach the baud rate of up to 3.6 gigahertz. Because HBM memory transfers data on both the rising and falling edges of the clock, the HBM memory actually communicates at a clock frequency of up to 1.8 gigahertz. At such higher operating frequencies, data transmission is prone to data read/write errors in the fast operating mode if disturbed by noise on the data communications link or crosstalk occurs between the data lines. Therefore, when the HBM memory is just shipped from the factory, and when environmental factors such as temperature and voltage of the HBM memory change, the read-write data path of the HBM memory needs to be checked once, so that the correctness of the data of the HBM memory in the process of reading and writing the data at high speed is ensured.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a data path testing system of a memory in the related art, which is used for generating data by an HBM host for performing a data path test on the HBM memory, and writing the data into the HBM memory through a data transmitting unit of the HBM host, for example, the HBM memory is an HBM dynamic random access memory, the HBM dynamic random access memory receives the written data in a double-edge manner and stores the received data into a register unit in the HBM memory, the HBM host restarts a read operation, reads the double-edge data in the register unit of the HBM memory into the HBM host, and performs a data comparison with the originally transmitted data. If the comparison shows that the error occurs, the data read-write error occurs on the line, and the bit with the data transmission error can be determined according to the error occurrence result, so that the fault of the data read-write channel is determined.

In the related art, the HBM host needs to generate 6 data, which is 128 bits, the method comprises the following steps of: data 4 "110010011001100111001110001110011100111001110011100011100111001110001110011100011100111001110011100011100111001110011010111001110011010111", data 5 "111100001110000111100011001110011100111001110011100111001110011100111001110011100111001110011100111001110011100111001110011100111001110011100111001110011100111001heat", data 6 "data of data 6" 000011110000111001110011100111001110011100111001110011100115 110011100115 "are 0, 1 interval, in the related art, data 1-data 6 are required to be circularly transmitted once, so that the following three faults can be found: data failure on a single bit; rising edge data transitions from 0 to 1; falling edge data transitions from 1 to 0 fail.

The applicant has found the following disadvantages in the related art when practicing embodiments of the present application: firstly, the data 1-data 6 are too simple, and the data dispersion is not high enough, so that only limited faults on a data line can be found after testing, and faults affecting the data bit due to certain random jump of adjacent data bits in the communication process can not be found; secondly, as the data 1-6 are designed manually, the randomness is lacking, the coverage rate of fault test is not high enough for a data path of high-speed reading and writing, and missed detection faults can occur in actual measurement; in the third, related art, a comparison mechanism of writing and reading is adopted, referring to fig. 2, fig. 2 is a timing diagram of a data path testing method of a memory in related art, data to be written in each time need to be read immediately and then compared, the data path needs to be frequently read and compared, the reading operation is complicated, and the real-time performance of comparison is high.

The embodiments of the present application provide a method, an apparatus, an electronic device, a computer readable storage medium, and a computer program product for testing a data path of a memory, which can improve the efficiency of testing the data path of the memory, and hereinafter illustrate an exemplary application of the electronic device provided by the embodiments of the present application, where the electronic device provided by the embodiments of the present application may be implemented as a notebook computer, a tablet computer, a desktop computer, a set-top box, a mobile device (for example, a mobile phone, a portable music player, a personal digital assistant, a dedicated messaging device, and a portable game device) and other various types of user terminals, and may also be implemented as a server. In the following, an exemplary application when the device is implemented as a server will be described.

Referring to fig. 3, fig. 3 is a schematic diagram of an architecture of a data path testing system of a memory according to an embodiment of the present application, in order to support a chip testing application, a terminal is connected to a server 200 through a network 300, where the network 300 may be a wide area network or a local area network, or a combination of the two.

In some embodiments, the method for testing a data path of a memory provided by the embodiments of the present application may be implemented by a terminal and a server in cooperation, where the method for testing a data path of a memory provided by the embodiments of the present application may be applied to a test APP, and in response to receiving a data path test request for a memory 500 by a terminal 400, the method sends a test request to a server 200, and the server 200 sends a plurality of random numbers to the memory 500 in turn according to a writing sequence; performing chained processing on a plurality of random numbers according to the writing sequence through a shift register circuit of the server 200 to obtain a first chained processing result of the last random number correspondingly written; wherein the last random number is the last random number sent to the memory 500 from among the plurality of random numbers; reading a second chained processing result from the memory; the second chained processing result is obtained by chained processing the received random numbers according to the receiving sequence through a shift register circuit of the memory, and corresponds to the chained processing result of the last received random number; the first chain type processing result and the second chain type processing result are compared through the server 200, when the comparison results are consistent, the data path test of the memory 500 is determined to pass, the server 200 feeds back the test result of the data path test to the terminal 400, and the test result is displayed on the terminal 400.

In some embodiments, the data path testing method of the memory provided by the embodiments of the present application may be implemented by a terminal or a server, and when implemented by the terminal alone, in response to the terminal 400 receiving a data path testing request for the memory 500, the terminal 400 sequentially sends a plurality of random numbers to the memory 500 in a writing order; performing chained processing on a plurality of random numbers according to the writing sequence through a shift register circuit of the terminal 400 to obtain a first chained processing result of the last random number correspondingly written; wherein the last random number is the last random number sent to the memory 500 from among the plurality of random numbers; reading a second chained processing result from the memory; the second chained processing result is obtained by chained processing the received random numbers according to the receiving sequence through a shift register circuit of the memory, and corresponds to the chained processing result of the last received random number; and comparing the first chain type processing result with the second chain type processing result through the terminal 400, when the comparison results are consistent, determining that the data path test of the memory 500 is passed, feeding back the test result passed by the data path test to the terminal 400 by the terminal 400, and displaying the test result on the terminal 400.

In some embodiments, the terminal or the server may implement the data path testing method of the memory provided by the embodiment of the present application by running a computer program. For example, the computer program may be a native program or a software module in an operating system; may be a Native Application (APP), i.e. a program that needs to be installed in an operating system to run, such as a test APP; the method can also be an applet, namely a program which can be run only by being downloaded into a browser environment; but also an applet that can be embedded in any app. In general, the computer programs described above may be any form of application, module or plug-in.

In some embodiments, the server 200 may be an independent physical server, a server cluster or a distributed system formed by a plurality of physical servers, or a cloud server that provides cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDNs, and basic cloud computing services such as big data and artificial intelligence platforms. The terminal 400 may be, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, a smart speaker, a smart watch, etc. The terminal and the server may be directly or indirectly connected through wired or wireless communication, which is not limited in the embodiment of the present application.

Referring to fig. 4, fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application, and a server 200 shown in fig. 4 includes: at least one processor 210, a memory 250, at least one network interface 220, and a user interface 230. The various components in terminal 200 are coupled together by bus system 240. It is understood that the bus system 240 is used to enable connected communications between these components. The bus system 240 includes a power bus, a control bus, and a status signal bus in addition to the data bus. But for clarity of illustration the various buses are labeled as bus system 240 in fig. 4.

The processor 210 may be an integrated circuit chip with signal processing capabilities such as a general purpose processor, such as a microprocessor or any conventional processor, or the like, a digital signal processor (DSP, digital Signal Processor), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or the like.

The memory 250 may be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid state memory, hard drives, optical drives, and the like. Memory 250 optionally includes one or more storage devices physically remote from processor 210, where memory is that in server 200, rather than that being tested.

Memory 250 includes volatile memory or nonvolatile memory, and may also include both volatile and nonvolatile memory. The non-volatile memory may be read only memory (ROM, read Only Me mory) and the volatile memory may be random access memory (RAM, random Access Memor y). The memory 250 described in embodiments of the present application is intended to comprise any suitable type of memory.

In some embodiments, memory 250 is capable of storing data to support various operations, examples of which include programs, modules and data structures, or subsets or supersets thereof, as exemplified below.

An operating system 251 including system programs for handling various basic system services and performing hardware-related tasks, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and handling hardware-based tasks;

network communication module 252 for reaching other computing devices via one or more (wired or wireless) network interfaces 220, exemplary network interfaces 220 include: bluetooth, wireless compatibility authentication (WiFi), and universal serial bus (USB, universal Serial Bus), etc.

In some embodiments, the data path testing device of the memory provided in the embodiments of the present application may be implemented in software, and fig. 4 shows the data path testing device 255 of the memory stored in the memory 250, which may be software in the form of a program and a plug-in, and includes the following software modules: the sending module 2551, the chained module 2552, the receiving module 2553, and the comparing module 2554 are logically, and thus may be arbitrarily combined or further split according to the implemented functions. The functions of the respective modules will be described hereinafter.

In other embodiments, the data path testing apparatus of the memory provided in the embodiments of the present application may be implemented in hardware, and by way of example, the data path testing apparatus of the memory provided in the embodiments of the present application may be a processor in the form of a hardware decoding processor that is programmed to perform the data path testing method of the memory provided in the embodiments of the present application, for example, the processor in the form of a hardware decoding processor may employ one or more application specific integrated circuits (ASIC, application Specific Integrated Circui t), DSP, programmable logic device (PLD, programmable Logic Device), complex programmable logic device (CPLD, complex Programmable Logic Device), field programmable gate array (FPGA, field-Programmable Gate Array), or other electronic components.

The artificial intelligence technology is a comprehensive subject, and relates to the technology with wide fields, namely the technology with a hardware level and the technology with a software level. Artificial intelligence infrastructure technologies generally include technologies such as sensors, dedicated artificial intelligence chips, cloud computing, distributed storage, big data processing technologies, operation/interaction systems, mechatronics, and the like. The artificial intelligence software technology mainly comprises a computer vision technology, a voice processing technology, a natural language processing technology, machine learning/deep learning and other directions.

The data path testing method of the memory provided by the embodiment of the application will be described below in connection with exemplary application and implementation of the server or the terminal provided by the embodiment of the application.

Referring to fig. 5A, fig. 5A is a flowchart of a data path testing method of a memory according to an embodiment of the present application, and will be described with reference to steps 101 to 105 shown in fig. 5A.

In step 101, a plurality of random numbers are sequentially sent to a memory in a write order by a test host.

As an example, the test host may be a terminal or a server.

In some embodiments, the test host includes a random number generator that performs the following processing for each of a plurality of time nodes before sequentially sending the plurality of random numbers to the memory in a write order by the test host in step 101: generating at least one random number at a time node by a random number generator of the test host; the random numbers generated by the time nodes are mutually independent, and the writing sequence is the time sequence writing sequence of the time node for generating each random number. By independently generating random numbers at different time nodes, the fault detection coverage rate of the data path can be effectively improved.

As an example, the random number generator may generate a random number at each time node and write the random number to the memory in real time after the random number is generated, so that the time node at which the random number is generated corresponds to the time node at which the random number is written, the number of time nodes and the specific corresponding time are preconfigured, the random number generators are independent from each other among the random numbers generated at each time node, the generated random number is sent to the memory after the random number is generated at each time node, for example, the random number generator generates a random number 1 at the first time node, then the random number generator generates a random number 2 at the second time node, then the random number generator generates a random number 3 at the third time node, and finally the random number generator generates a random number 4 at the fourth time node.

In some embodiments, the random number generator may also generate a random number for each time node, e.g., the random number generator may simultaneously generate 10 random numbers, where each random number corresponds to one time node where the random number would be sent to the memory.

In some embodiments, the test host includes circuitry, which may be a shift register circuit, that performs the following for each of a plurality of time nodes before sequentially sending the plurality of random numbers to the memory in a write order by the test host in step 101: when the time node is the earliest time node in the plurality of time nodes, acquiring a random number configured by a shift register circuit aiming at the test host; when the time node is not the earliest time node in the plurality of time nodes, digital signal processing is carried out on the input data through a shift register circuit of the test host to obtain a random number corresponding to the time node; the writing sequence is the time sequence writing sequence of the time node for generating each random number, and the input data of the shift register circuit of the test host is the random number output by the last adjacent time node of the time node. The random number generated by the shift register circuit jumps in each clock beat according to the shift register circuit, so that the generated random number has large discrete type, and is favorable for testing random faults.

As an example, the random number corresponding to the earliest time node is a preconfigured random number, for example, 20 bits of data "01010101010101010101", and the random number is taken as an input of the shift register circuit, so that the random number of the subsequent time node is obtained, for example, the random number of the first time node is 20 bits of data "01010101010110110101", the random number of the second time node is 20 bits of data "11100101010101010111" output by the shift register circuit after "01010101010101" is input to the shift register circuit, wherein the first time node is the last adjacent time node of the second time node, the 20 bits of data "01010101010101" is the random number output by the last adjacent time node, and thus, the random number of the third time node is 20 bits of data "01011010101010101110" output by the shift register circuit after "11100101010101010111" is input to the shift register circuit.

In some embodiments, the number of circuits of the test host is multiple, and the circuits may be shift register circuits; the above-mentioned acquisition of the random number for the shift register circuit configuration of the test host can be achieved by the following technical scheme: acquiring a random number unit configured for each shift register circuit of a test host, and forming a plurality of random number units into a random number; the above-mentioned shift register circuit through test host computer carries out digital signal processing to the input data, obtains the random number of corresponding time node, can realize through following technical scheme: the following is performed by each shift register circuit of the test host: receiving a random number unit output by a previous adjacent time node, and performing digital signal processing on the received random number unit to obtain a random number unit corresponding to the time node; forming random numbers by random number units output by each shift register circuit of the test host at the time node; the circuits of the test host correspond to the random number units one by one.

As an example, referring to fig. 7, fig. 7 is a schematic diagram of a data path structure of a data path testing method of a memory according to an embodiment of the present application, dividing a 320-bit data path DWORD into 4 sub-data paths, for example, DWORD0, DWORD1, DWORD2, and DWORD3, and dividing each sub-data path into 4 data path units in total according to an input width of a shift register circuit. For each data path unit, there is a corresponding shift register circuit to obtain a corresponding random number unit, so that the test host includes a plurality of shift register circuits, the random number unit of each shift register circuit corresponding to the test host can be obtained, and the random number units are formed into random numbers, for example, for the random number of the first time node, the random number unit configured for each shift register circuit of the test host is obtained, and the random number units are formed into random numbers, for example, the random number unit output by the last adjacent time node is received, and digital signal processing is performed on the received random number units to obtain a random number unit corresponding to the time node, wherein the random number of the first time node is 20 bits of data "01010101010101010101010110101", and the random number units of the first time node are "0101", "0101" and "0101", the random number of the second time node is "1110", "0101" and "0101" respectively input to the corresponding five shift register circuits in one-to-one correspondence, each shift register circuit outputs "1110", "0101" and "0111" respectively, wherein the first time node is the last adjacent time node of the second time node, the 4-bit data "1" is a random number unit output by a certain shift register circuit at the last adjacent time node, the random number units output by each shift register circuit of the test host at the time node constitute random numbers, that is, "1110", "0101" and "0111" respectively output by each shift register circuit constitute "11100101010101010111", the plurality of random number units have the same configuration bit, for example, the number of bits of the random number unit is 4 bits, and the product of the number of bits and the number of shift register circuits is the number of bits of the random number.

In some embodiments, referring to fig. 5B, fig. 5B is a flowchart of a method for testing a data path of a memory according to an embodiment of the present application, in step 101, a plurality of random numbers are sequentially sent to the memory by a test host according to a writing sequence, and steps 1011 to 1012 in fig. 5B may be performed by the test host according to the writing sequence for each random number.

In step 1011, the random number is subjected to a division process based on the number of configuration bits, resulting in a plurality of random number units having the same number of configuration bits.

As an example, the random number cell includes at least one rising edge data bit, at least one falling edge data bit, a rising edge data mask bit, a falling edge data mask bit, a rising edge data bus flip bit, and a falling edge data bus flip bit. The plurality of random number units have the same configuration bit number, for example, the configuration bit number of the random number unit is 4 bits, the product of the configuration bit number and the number of shift register circuits is the bit number of the random number, each random number unit includes at least one rising edge Data bit, at least one falling edge Data bit, a rising edge Data Mask bit, a falling edge Data Mask bit, a rising edge Data bus flip bit, and a falling edge Data bus flip bit, and in each Data path unit, when the configuration bit number of the random number unit is 20 bits, the 19 th bit to the 0 th bit are respectively the falling edge Data bus flip bit (DBI, data Bus Inverter), the rising edge Data bus flip bit, the falling edge Data bit (DQ, data Q ue) of each bit in the 8 bits Data, and the rising edge Data Mask bit (DM, mask) and the falling edge Data Mask bit.

In step 1012, a plurality of random number units are sent in parallel to a memory.

As an example, there is a similar data path structure as well, i.e. a data path DWORD of 320 bits is divided into 4 sub data paths, e.g. DWORD0, DWOR D1, DWORD2 and DWORD3, each sub data path is divided into 4 data path units in total according to the input width of the shift register circuit, thus each data path unit comprises 20 bits, i.e. each random number unit has 20 bits, and a plurality of random number units are transmitted in parallel to the memory through different data path units.

In step 102, a shift register circuit of a test host performs chained processing on a plurality of random numbers according to a writing sequence to obtain a first chained processing result.

As an example, the number of bits of the first chain processing result corresponds to the number of bits of the last random number written, the number of bits of the first chain processing result is related only to the number of bits of the last random number written, and the number of bits of the first chain processing result is the same as the number of bits of the last random number written for a shift register circuit with the same number of input and output bits.

In some embodiments, referring to fig. 5C, fig. 5C is a flowchart illustrating a method for testing a data path of a memory according to an embodiment of the present application, in step 102, a shift register circuit of a test host performs a chain process on a plurality of random numbers according to a writing sequence to obtain a first chain process result, and steps 1021 to 1022 may be performed on each random number in the plurality of random numbers according to the writing sequence.

In step 1021, the shift register circuit of the test host performs digital signal processing on the chain processing result of the last adjacent random number and the random number to obtain a chain processing result of the corresponding random number.

In step 1022, when the random number is the last random number based on the writing order among the plurality of random numbers, the chain processing result of the corresponding random number is determined as the first chain processing result.

The method can effectively shorten the number of data bits to be compared by a chained processing mode, if the chained processing is not performed, 3 320-bit random numbers are input, 3 320-bit data are required to be read out and compared, if the chained processing is performed, after the first 320-bit random number a is input, a 320-bit chained processing result a1 is output, the chained processing result a1 and the second 320-bit random number b (which can be the same as or different from the chained processing result a 1) are continuously input, a 320-bit chained processing result b1 and a third 320-bit random number c are continuously input, and a 320-bit chained processing result c1 is output.

In some embodiments, the number of shift register circuits of the test host is multiple; in step 1021, the shift register circuit of the test host performs digital signal processing on the chain processing result of the last adjacent random number and the random number to obtain the chain processing result of the corresponding random number, which can be realized by the following technical scheme: the following is performed by each shift register circuit of the test host: receiving a chain processing result of a last adjacent random number unit, and carrying out digital signal processing on the received chain processing result of the last adjacent random number unit and a random number unit of a random number corresponding shift register circuit to obtain a chain processing result of a corresponding random number unit; and forming a chain type processing result of the corresponding random number unit output by each shift register circuit of the test host into a chain type processing result of the corresponding random number. The parallel processing of a plurality of shift register units and the random number unit corresponding to each shift register unit can improve the processing efficiency of digital signal processing, thereby improving the testing efficiency of a data path.

As an example, the number of shift register circuits of the test host is plural, each shift register circuit has a respective number of configuration bits, and the number of configuration bits may be the same or different, for example, the number of configuration bits of the shift register circuit 1 is a first bit to a fourth bit, and description is made taking as an example a random number written by a second one of the random numbers, the first written random number is 20 bits of data "01010101010101010101", and the random number unit of the first written random number is "0101" (0101 is referred to as a random number unit a, corresponding to shift register circuit 1), "0101" (corresponding to shift register circuit 2), "0101" (corresponding to shift register circuit 3), "0101" (corresponding to shift register circuit 4), and "0101".

(corresponding to shift register circuit 5), the second random number may be a random number b (random number unit is still divided into 4-bit arrangement bits) which is independent of the first random number b, or the shift register circuit may output a random number unit a1 based on the output of the first random number, for example, "1110" (random number unit a1, corresponding shift register circuit 1), "0101" and "0111", which are output after "0101", "0101" and "0101" are input to the corresponding five shift register circuits one by one, respectively, when the shift register circuit 1 performs processing, the last adjacent random number unit is a random number unit corresponding to the shift register circuit 1 in the last written random number, for example, the random number unit a is a random number unit adjacent to the last random number unit of the random number unit a1, or the random number unit a is a random number unit adjacent to the last random number unit b, the chain processing result of the last adjacent random number unit (random number unit a) is the random number unit a1, when the second written random number is the output of the shift register circuit based on the first written random number, the random number unit a1 and the random number unit a1 are subjected to digital signal processing to obtain the chain processing result corresponding to the random number unit corresponding to the shift register circuit 1 in the second written random number, when the second written random number can be the random number b independent of the first written random number, and carrying out digital signal processing on the random number unit a1 and the random number unit b1 (corresponding to the shift register circuit 1) of the random number b to obtain a chain processing result corresponding to the random number unit of the corresponding shift register circuit 1 in the second written random number, forming the random number by the random number unit output by each shift register circuit of the test host, and forming the chain processing result corresponding to the random number by the chain processing result of the corresponding random number unit output by each shift register circuit.

In some embodiments, each shift register circuit includes N cascaded shift register circuit units, and the above-mentioned performing digital signal processing on the received chain processing result of the last adjacent random number unit and the random number unit of the shift register circuit corresponding to the random number to obtain the chain processing result of the corresponding random number unit may be implemented by the following technical scheme: determining the input of the nth shift register circuit unit based on the chain processing result of the last adjacent random number unit and the random number unit corresponding to the shift register circuit in the random numbers; the input of the N-th shift register circuit unit is shifted through the N-th shift register circuit unit in the N cascaded shift register circuit units, so that output bit codes corresponding to the N-th shift register circuit unit are obtained; determining an input of an n+1 shift register circuit unit based on the output bit encoding corresponding to the n shift register circuit unit; the input of the n+1th shift register circuit unit is continuously shifted through the n+1th shift register circuit unit, and output bit codes corresponding to the n+1th shift register circuit unit are obtained; wherein, N is an integer greater than or equal to 2, N is an integer variable whose value increases from 1, and the value range of N is 1-N < N; the output bit codes of each shift register circuit unit are subjected to descending order sorting processing based on the n value of the corresponding shift register circuit unit, and a plurality of output bit codes are formed into a chain processing result of the corresponding random number unit according to the descending order sorting result. The shift register circuit obtained by cascading the shift register circuit units can realize multi-input and multi-output circuit configuration, thereby improving the processing efficiency of digital signal processing.

As an example, each shift register circuit includes 4 shift register circuit units in cascade, and the shift processing is performed on the input of the 1 st shift register circuit unit through the 1 st shift register circuit unit in the 4 shift register circuit units in cascade, so as to obtain the output bit code of the corresponding 1 st shift register circuit unit; determining an input of a 2 nd shift register circuit unit based on the output bit encoding corresponding to the 1 st shift register circuit unit; the shift processing is continuously carried out on the input of the 2 nd shift register circuit unit through the 2 nd shift register circuit unit, and the output bit code corresponding to the 2 nd shift register circuit unit is obtained; the output bit codes of each shift register circuit unit are subjected to descending order sorting processing based on the serial number (i.e., the numerical value of n) of the corresponding shift register circuit unit, and the plurality of output bit codes are formed into a chain processing result of the corresponding random number unit according to the descending order sorting result, i.e., the output bit code of the shift register circuit unit having the larger serial number is arranged at a earlier position, for example, the output bit code of the corresponding 1 st shift register is 0, the output bit code of the corresponding 2 nd shift register is 1, the output bit code of the corresponding 3 rd shift register is 1, and the output bit code of the corresponding 4 th shift register is 1, and the chain processing result of the corresponding random number unit is "1110".

In some embodiments, the determining the input of the n+1th shift register circuit unit based on the output bit encoding corresponding to the n shift register circuit unit may be implemented by the following technical scheme: when the n+1 shift register circuit unit is directly connected with the n shift register circuit unit, the output bit code of the n shift register circuit unit and the input bit code of the corresponding n+1 shift register circuit unit in the random number unit are used as the input of the n+1 shift register circuit unit; when the n+1 shift register circuit unit is connected with the N shift register circuit unit through an exclusive OR gate, exclusive OR processing is carried out on the first bit code output by the N shift register circuit unit in the shift register circuit and the output bit code of the N shift register circuit unit in the last adjacent time node, so as to obtain exclusive OR output bit code, and the exclusive OR output bit code and the input bit code corresponding to the n+1 shift register circuit unit in the random number unit are determined as the input of the n+1 shift register circuit unit. By means of the connection mode of direct connection and exclusive-OR gate connection, each random number can contribute to the final first chained processing result, and therefore the testing reliability of a data path can be improved.

As an example, referring to fig. 8, fig. 8 is a circuit schematic diagram of a data path testing method of a memory according to an embodiment of the present application, fig. 8 shows a shift register circuit with input and output being 4 bits, a 3 rd shift register circuit unit is directly connected with a 2 nd shift register circuit unit, and an output bit code Out2 of the 2 nd shift register circuit unit and an input bit code In1 of a random number corresponding to the 2 nd shift register circuit unit are used as inputs of the 3 rd shift register circuit unit; when the 2 nd shift register circuit unit and the 1 st shift register circuit unit are connected through an exclusive OR gate, the first bit code of the random number unit output by the 4 th shift register circuit unit In the last adjacent time node (corresponding to Out0 In the random number correspondingly processed by the last adjacent time node) and the output bit code Out3 of the 1 st shift register circuit unit are subjected to exclusive OR processing, so as to obtain an exclusive OR output bit code, and the exclusive OR output bit code and the input bit code In2 corresponding to the 2 nd shift register circuit unit In the random number unit are determined as the input of the 2 nd shift register circuit unit.

In some embodiments, the nth shift register circuit unit includes a first and gate, a second and gate, an exclusive or gate, and a flip-flop; the shift processing of the input of the N-th shift register circuit unit by the N-th shift register circuit unit in the N-th cascade shift register circuit units can be realized by the following technical scheme: when n takes a value of 1, the following processing is performed: performing AND gate processing on the last bit code and the first code value of the random number unit through a first AND gate to obtain a first AND gate result; performing AND gate processing on the second code value and the first code of the random number unit output by the shift register circuit of the last adjacent time node by a second AND gate to obtain a second AND gate result; performing exclusive-or processing on the first AND gate result and the second AND gate result through an exclusive-or gate to obtain an exclusive-or result, and transmitting the exclusive-or result to a trigger; when the flip-flop receives the clock signal, the exclusive-or result is determined as the output bit code of the n-th shift register circuit. Output feedback can be realized through the gate circuit structure and the trigger structure, so that the effectiveness and accuracy of the test result are improved.

As an example, referring to fig. 8, a shift register circuit with 4 bits input is shown, where M1 and M0 are each connected to 1, which indicates that the input data is used to perform an exclusive-or operation, and the specific calculation procedure is as follows: for a random number 1 with 4 bits and a random number 2 with 4 bits which are sequentially input, wherein the random number 2 is obtained based on the random number 1, in3 of the random number 2 and M1 are subjected to AND gate processing to obtain a first AND gate result (In 3 of the random number 2), M0 and a first code (Out 0 of the random number 1) of a random number unit output by a shift register circuit of a last adjacent time node are subjected to AND gate processing to obtain a second AND gate result (Out 0 of the random number 1); performing exclusive-or processing on the first AND gate result and the second AND gate result through an exclusive-or gate to obtain an exclusive-or result, and transmitting the exclusive-or result to a D trigger; when the D flip-flop receives the clock signal, the exclusive or result is determined as the output bit code of the 1 st shift register circuit (Out 3 of random number 2), and the output bit code of the 1 st shift register circuit (Out 3 of random number 2) is transmitted to the 2 nd shift register circuit unit through the flip-flop.

In some embodiments, the nth shift register circuit unit includes a first and gate, a second and gate, an exclusive or gate, and a flip-flop; the shift processing of the input of the N-th shift register circuit unit by the N-th shift register circuit unit in the N-th cascade shift register circuit units can be realized by the following technical scheme: when the value range of N is 2.ltoreq.n < N, the following processing is executed: performing AND gate processing on the N-n+1 bit code of the random number unit and the first code value through a first AND gate to obtain a first AND gate result; when the N-1 circuit unit is connected with the N circuit unit through an exclusive or gate, performing exclusive or processing on the first bit code output by the N circuit unit at the last adjacent time node and the output bit code of the N-1 circuit unit to obtain an exclusive or output bit code, and performing AND gate processing on the second code value and the exclusive or output bit code through a second AND gate to obtain a second AND gate result; when the n-1 circuit unit is directly connected with the n circuit unit, performing AND gate processing on the second coding value and the output bit code of the n-1 circuit unit through a second AND gate to obtain a second AND gate result; performing exclusive-or processing on the first AND gate result and the second AND gate result through an exclusive-or gate to obtain an exclusive-or result, and transmitting the exclusive-or result to a trigger; when the flip-flop receives the clock signal, the exclusive-or result is determined as the output bit code of the n-th shift register circuit. Output feedback can be realized through the gate circuit structure and the trigger structure, so that the effectiveness and accuracy of the test result are improved.

With the above example in mind, referring to fig. 8, a shift register circuit with an input of 4 bits is shown, where M1 and M0 are each connected to 1, which represents exclusive or operation using input data, and the specific calculation process is described as follows: for a random number 1 with 4 bits and a random number 2 with 4 bits which are sequentially input, wherein the random number 2 is obtained based on the random number 1, and gate processing is carried out on In2 and M1 of the random number 2, so as to obtain a first AND gate result (In 2 of the random number 2); performing AND gate processing on the output bit codes of the M0 and 1 shift register circuit units to obtain a second AND gate result, performing exclusive OR processing on the first AND gate result and the second AND gate result through an exclusive OR gate to obtain an exclusive OR result, and transmitting the exclusive OR result to a trigger; when the D flip-flop receives the clock signal, the exclusive or result is determined as the output bit code of the 2 nd shift register circuit (Out 2 of random number 2), and the output bit code of the 2 nd shift register circuit (Out 2 of random number 2) is transmitted to the 3 rd shift register circuit unit through the flip-flop.

In step 103, the received plurality of random numbers are chained according to the receiving order by the shift register circuit of the memory, and a second chained result is obtained.

In some embodiments, in step 103, the received plurality of random numbers are chained according to the receiving order by using the shift register circuit of the memory, and the second chained processing result corresponding to the last received random number may be implemented by the following technical scheme: the following processing is performed for each of the plurality of random numbers in the reception order: carrying out digital signal processing on the chain processing result of the last adjacent random number and the random number through a shift register circuit of the memory to obtain a chain processing result of the corresponding random number; when the random number is the last random number based on the receiving order among the plurality of random numbers, the chain processing result corresponding to the random number is determined as the second chain processing result corresponding to the last random number received.

In some embodiments, the number of shift register circuits of the memory is multiple; the shift register circuit through the memory performs digital signal processing on the chain processing result of the last adjacent random number and the random number to obtain the chain processing result of the corresponding random number, and the method can be realized by the following technical scheme: the following processing is performed by each shift register circuit of the memory: receiving a chain processing result of a last adjacent random number unit, and carrying out digital signal processing on the received chain processing result of the last adjacent random number unit and a random number unit of a random number corresponding shift register circuit to obtain a chain processing result of a corresponding random number unit; and forming a chain processing result of the corresponding random number unit output by each shift register circuit of the memory into a chain processing result of the corresponding random number.

In some embodiments, each shift register circuit includes N cascaded shift register circuit units, and the above-mentioned performing digital signal processing on the received chain processing result of the last adjacent random number unit and the random number unit of the shift register circuit corresponding to the random number to obtain the chain processing result of the corresponding random number unit may be implemented by the following technical scheme: the input of the N-th shift register circuit unit is shifted through the N-th shift register circuit unit in the N cascaded shift register circuit units, so that output bit codes corresponding to the N-th shift register circuit unit are obtained; determining an input of an n+1 shift register circuit unit based on the output bit encoding corresponding to the n shift register circuit unit; the input of the n+1th shift register circuit unit is continuously shifted through the n+1th shift register circuit unit, and output bit codes corresponding to the n+1th shift register circuit unit are obtained; wherein, N is an integer greater than or equal to 2, N is an integer variable whose value increases from 1, and the value range of N is 1-N < N; the output bit codes of each shift register circuit unit are subjected to descending order sorting processing based on the n value of the corresponding shift register circuit unit, and a plurality of output bit codes are formed into a chain processing result of the corresponding random number unit according to the descending order sorting result.

In some embodiments, the determining the input of the n+1th shift register circuit unit based on the output bit encoding corresponding to the n shift register circuit unit may be implemented by the following technical scheme: when the n+1 shift register circuit unit is directly connected with the n shift register circuit unit, the output bit code of the n shift register circuit unit is used as the input of the n+1 shift register circuit unit; when the n+1 shift register circuit unit is connected with the N shift register circuit unit through an exclusive OR gate, the first bit code of the random number unit output by the N shift register circuit of the last adjacent time node and the output bit code of the N shift register circuit unit are subjected to exclusive OR processing to obtain exclusive OR output bit codes, and the exclusive OR output bit codes are determined as the input of the n+1 shift register circuit unit.

In some embodiments, the nth shift register circuit unit includes a first and gate, a second and gate, an exclusive or gate, and a flip-flop; the shift processing of the input of the N-th shift register circuit unit by the N-th shift register circuit unit in the N-th cascade shift register circuit units can be realized by the following technical scheme: when n takes a value of 1, the following processing is performed: performing AND gate processing on the last bit code and the first code value of the random number unit through a first AND gate to obtain a first AND gate result; performing AND gate processing on the second code value and the first code of the random number unit output by the n shift register circuit of the last adjacent time node by a second AND gate to obtain a second AND gate result; performing exclusive-or processing on the first AND gate result and the second AND gate result through an exclusive-or gate to obtain an exclusive-or result, and transmitting the exclusive-or result to a trigger; when the flip-flop receives the clock signal, the exclusive-or result is determined as the output bit code of the n-th shift register circuit.

In some embodiments, the nth shift register circuit unit includes a first and gate, a second and gate, an exclusive or gate, and a flip-flop; the shift processing of the input of the N-th shift register circuit unit by the N-th shift register circuit unit in the N-th cascade shift register circuit units can be realized by the following technical scheme: when the value range of N is 2.ltoreq.n < N, the following processing is executed: performing AND gate processing on the N-n+1 bit code of the random number unit and the first code value through a first AND gate to obtain a first AND gate result; when the N-1 circuit unit is connected with the N circuit unit through an exclusive or gate, performing exclusive or processing on the first bit code output by the N circuit unit at the last adjacent time node and the output bit code of the N-1 circuit unit to obtain an exclusive or output bit code, and performing AND gate processing on the second code value and the exclusive or output bit code through a second AND gate to obtain a second AND gate result; when the n-1 circuit unit is directly connected with the n circuit unit, performing AND gate processing on the second coding value and the output bit code of the n-1 circuit unit through a second AND gate to obtain a second AND gate result; performing exclusive-or processing on the first AND gate result and the second AND gate result through an exclusive-or gate to obtain an exclusive-or result, and transmitting the exclusive-or result to a trigger; when the flip-flop receives the clock signal, the exclusive-or result is determined as the output bit code of the n-th shift register circuit.

As an example, the shift register circuit built in the memory is identical to the shift register circuit built in the test host in structure or the digital signal processing logic is identical, so the chain processing logic in step 103 is identical, and specific implementation details can refer to the chain processing scheme in step 102.

In step 104, the second chain processing result is read from the memory.

As an example, the number of bits of the second chain processing result corresponds to the number of bits of the last random number received by the memory, the number of bits of the second chain processing result is related only to the number of bits of the last random number received by the memory, and the number of bits of the second chain processing result is the same as the number of bits of the last random number received by the memory for the shift register circuit with the same input/output bit number.

In step 105, the test host compares the first chained processing result with the second chained processing result, and determines that the data path of the memory passes the test when the comparison result is consistent.

As an example, the following processing is performed by the shift register circuit of the test main sentence: after the first 320 bits of random number a is input, the 320 bits of chain processing result a1 is output, the chain processing result a1 and the second 320 bits of random number b (which may be the same or different from the chain processing result a 1) are continuously input, the 320 bits of chain processing result b1 is output, the chain processing result b1 and the third 320 bits of random number c are continuously input, the 320 bits of chain processing result c1 is output, because the third 320 bits of random number c is the last random number written in, the chain processing result c1 is the first chain processing result, the sequence of the random numbers written in the memory is a, b and c, the received random numbers a, b and c are subjected to chain processing according to the receiving sequence by a shift register circuit in the memory, so that the chain processing result c2 is the second chain processing result, and thus only the 320 bits of chain processing result c1 and the 320 bits of chain processing result c2 need to be compared, or when the comparison is performed, for example, the data paths can be divided into 8 data paths, and compared into 8 data paths, namely, the data paths can be compared by using each data path 20, and the data paths can be compared in parallel.

In the following, an exemplary application of the embodiment of the present application in a practical application scenario will be described.

The data path testing method of the memory provided by the embodiment of the application can be applied to testing APP, the terminal responds to receiving the data path testing request aiming at the memory, the testing request is sent to the server, and the server sequentially sends a plurality of random numbers to the memory according to the writing sequence; performing chained processing on a plurality of random numbers according to the writing sequence through a shift register circuit of a server to obtain a first chained processing result of the last random number correspondingly written; wherein the last random number is the last random number sent to the memory 500 from among the plurality of random numbers; performing chain processing on the received random numbers according to the receiving sequence through a shift register circuit of the memory, and correspondingly receiving a second chain processing result of the last received random number, wherein the server receives the second chain processing result from the memory; and comparing the first chain type processing result with the second chain type processing result through the server, when the comparison result is consistent, determining that the data path test of the memory passes, feeding back the test result of the data path test to the terminal through the server, and displaying the test result on the terminal.

The embodiment of the application provides a self-loop test mode of a read-write data path of an HBM memory, which is realized based on a MISR circuit and can be used for the self-loop test of the read-write data path of the HBM memory, thereby ensuring the correctness of the read-write data path of the HBM memory. Meanwhile, the MISR circuit can work at the actual working frequency of the HBM memory, so that the test mode can also provide relevant tests of read-write data paths of the HBM memory at the actual working frequency, and the accuracy of the fast working of the HBM memory is ensured.

The data path testing method of the memory provided by the embodiment of the application can be realized by adopting the shift register circuit, can be used for performing self-loop test on the read-write data path of the HBM memory, and ensures the correctness and stability of the read-write data path of the HBM memory.

Referring to fig. 6, fig. 6 is a schematic structural diagram of a data path testing system of a memory according to an embodiment of the present application, in which the following circuit structure is used to complete a self-loop test of a data path. The shift register circuit in the HBM host generates random numbers, the generated random numbers are sequentially written into the HBM memory through the data sending unit of the HBM host, for example, the HBM memory is an HBM dynamic random access memory, the HBM memory receives written data in a double-edge mode, the shift register circuit in the HBM memory carries out chained processing on the received random numbers, a second chained processing result corresponding to the last random number is stored in a register unit in the HBM memory, the generated last random number is transmitted forwards in the shift register circuit in the HBM host, a first chained processing result corresponding to the written last random number is obtained, the HBM host starts a read operation again, the second chained processing result corresponding to the last random number in the register unit of the H BM memory is read into the HBM host, and data comparison is carried out with the first chained processing result corresponding to the written last random number. If the comparison shows that the error occurs, the data read-write error occurs on the line, and the bit with the data transmission error can be determined according to the error occurrence result, so that the fault of the data read-write channel is determined.

In the embodiment of the present application, the data path of the HBM memory is divided, referring to fig. 7, into 4 sub-data paths, for example, DWORD0, DWORD1, DWORD2, and DWORD3, and each sub-data path is divided into 4 data path units in total according to the input width of the shift register circuit for comparison. Within each data path cell, bit 0 is a rising edge data mask bit, bit 1 is a falling edge data mask bit, bits 2 through 17 correspond to a data queue (the data queue includes 8 bits of data, each bit of data including a rising edge and a falling edge, thus requiring 16 bits), bit 18 is a rising edge data bus inversion bit, and bit 19 is a falling edge data bus inversion bit.

In the embodiment of the present application, the input width of the shift register circuit provided by the present application is 20, the shift register circuit is generally composed of dynamic or static master-slave flip-flops, the feedback loop is composed of an exclusive-or gate, the characteristic of the feedback loop is generally characterized by a characteristic polynomial, and the characteristic polynomial of the maximum length or near maximum length register of the feedback function is calculated by using a two-input exclusive-or gate. The output bits participating in feedback are called taps, the taps are sequentially exclusive-ored with the output bits, a shift register circuit with the maximum length generates a sequence, and in the shift register circuit, the setting of the taps can be represented by a polynomial of a modulus 2 in a finite field operand. All coefficients in the polynomial must be either "1" or "0", this polynomial is called a characteristic polynomial, the constant "1" in the polynomial does not represent a tap, it refers to one bit input, and the exponent in the polynomial represents the tap bit from left to right. The characteristic polynomial of the shift register circuit with 20 bits input adopted in the embodiment of the application is f (x) =x ²⁰ +x ¹⁷ +1, x in the characteristic polynomial, which is used to characterize the structure of the 20-bit shift register circuit, represents a circuit element in the shift register circuit, as explained in detail below: highest of feature polynomialsThe power of 20, the characteristic shift register circuit is composed of 20 cascaded circuit units, the 17-power of x term exists in the characteristic polynomial, the difference value between 20 and 17 is 3, therefore, an exclusive-or structure exists between the 3 rd circuit unit and the next circuit unit of the characteristic cascade, namely, the output of the 3 rd circuit unit and the output of the last circuit unit of the last time node are subjected to exclusive-or operation, and the exclusive-or operation result is input into the next circuit unit.

Based on the 20-bit shift register circuit, a 20-bit random number of each data path unit can be used as an input, other random numbers can be generated by processing based on the shift register circuit, the processing effect that two outputs are in a shift relation can be realized through the shift register circuit, and the realization codes of the 20-bit shift register circuit are as follows:

/>

the shift register circuit will be described below by taking 4 bits as an example, and the characteristic polynomial of the shift register circuit input with 4 bits is f (x) =x ⁴ +x ³ +1, where x represents a circuit unit of a shift register circuit, the characteristic polynomial here is used to characterize the structure of a 4-bit shift register circuit, and is explained in detail as follows: the highest power of the characteristic polynomial is 4, the characteristic shift register circuit consists of 4 cascaded circuit units, the characteristic polynomial has the 3-power of x term, the difference value between 4 and 3 is 1, therefore, an exclusive-OR structure exists between the 1 st circuit unit and the next circuit unit of the characteristic cascade, namely, the output of the 1 st circuit unit and the output of the last circuit unit of the last time node are subjected to exclusive-OR operation, the exclusive-OR operation result is input into the next circuit unit, referring to fig. 8, the shift register circuit with 4 bits is shown, M1 and M0 are connected with 1 in the figure, the exclusive-OR operation is performed by using input data, and the method is particularlyThe calculation process is described as follows: for a random number 1 with 4 bits and a random number 2 with 4 bits which are sequentially input, wherein the random number 2 is obtained based on the random number 1, in3 of the random number 2 and M1 are subjected to AND gate processing to obtain a first AND gate result (In 3 of the random number 2), and M0 and Out0 of the random number unit output by an nth shift register circuit of a last adjacent time node are subjected to AND gate processing to obtain a second AND gate result (Out 0 of the random number 1); performing exclusive-or processing on the first AND gate result and the second AND gate result through an exclusive-or gate to obtain an exclusive-or result, and transmitting the exclusive-or result to a D trigger; when the D flip-flop receives the clock signal, the exclusive or result is determined as the output bit code of the 1 st shift register circuit (Out 3 of random number 2), and the output bit code of the 1 st shift register circuit (Out 3 of random number 2) is transmitted to the 2 nd shift register circuit unit through the flip-flop. Performing exclusive OR processing on the output bit code (Out 0 of the random number 1) of the 4 th shift register circuit and the output bit code (Out 3 of the random number 2) of the 1 st shift register circuit unit at the last adjacent time node to obtain exclusive OR output bit codes, and performing AND gate processing on In2 and M1 of the random number 2 to obtain a first AND gate result (In 2 of the random number 2); performing AND gate processing on the M0 and the exclusive-or output bit codes to obtain a second AND gate result, performing exclusive-or processing on the first AND gate result and the second AND gate result through an exclusive-or gate to obtain an exclusive-or result, and transmitting the exclusive-or result to a trigger; when the D flip-flop receives the clock signal, the exclusive or result is determined as the output bit code of the 2 nd shift register circuit (Out 2 of random number 2), and the output bit code of the 2 nd shift register circuit (Out 2 of random number 2) is transmitted to the 3 rd shift register circuit unit through the flip-flop.

In addition to the MISR circuit scheme, a linear feedback shift register (LFSR, linear F eedback Shift Register) circuit may be used to make a similar self-loop test. In the scheme of the LFSR circuit, the first code is 0, the second code is 1, and the rest data comparison and circuit structure are similar.

The data of the HBM memory realized based on the MISR circuit provided by the embodiment of the applicationThe path test method has the following advantages: the MISR circuit is adopted to realize that the initial input random number of data is 0xaa aaa, then the MISR circuit automatically calculates the random number of the next time node based on the initial input random number and sends the HBM memory, and the random numbers generated by the MISR circuit at the first 10 time nodes are as follows: "10101010101010101010", "01010101010101010101", "00111010101010101011", "11100101010101010111", "01011010101010101110", "10110101010101011100", "01101010101010111001", "01000101010101110011", "00011010101011100111", and "10100101010111001111". It can be seen that after the MISR circuit is used, the random number hops at each time node according to the MISR circuit, and the random number has a large discrete shape, so that the random fault can be conveniently tested; the random number generated by MISR circuit is changed continuously with the increase of simulation period, and the user can determine the period number of test according to the test requirement, and the random number is 2 ²⁰ The jump can occur continuously in the cycle number of the data read-write channel, if the application occasion with high accuracy requirement on the data read-write channel, the simulation test length is recommended to last more than 1024; referring to fig. 9, fig. 9 is a timing diagram of a data path testing method of a memory according to an embodiment of the present application, in which data is read once after data is written many times for comparison, the data paths do not need to be frequently read and data comparison is performed, and since the HBM memory is in the MISR mode, the same MISR circuit is also used to perform chain processing on the data in the HBM memory and store the processed data in an internal register unit of the HBM memory, therefore, after 320 bits of writing, data comparison of all written data can be completed only by reading 320 bits of chain processing results at last, and the operation times of the read data and the data comparison times are reduced.

Continuing with the description below of an exemplary architecture of the memory data path testing device 255 implemented as a software module provided by embodiments of the present application, in some embodiments, as shown in fig. 4, the software modules stored in the memory data path testing device 255 of the memory 250 may include: a transmitting module 2551, configured to sequentially transmit, by the test host, the plurality of random numbers to the memory in a writing order; the chained module 2552 is configured to perform chained processing on the plurality of random numbers according to the writing sequence through a circuit of the test host, so as to obtain a first chained processing result; wherein, the bit number of the first chained processing result corresponds to the bit number of the last random number written in; a receiving module 2553, configured to read the second chain processing result from the memory; the second chained processing result is obtained by chained processing the received random numbers according to the receiving sequence through a circuit of the memory, the bit number of the second chained processing result corresponds to the bit number of the last random number received by the memory, and the circuit logic of the circuit of the memory is the same as the circuit logic of the circuit of the test host; the comparison module 2554 is configured to compare the first chain processing result with the second chain processing result through the test host, and determine that the data path of the memory passes the test when the comparison result is consistent.

In some embodiments, the test host includes a random number generator, and the transmitting module 2551 is further configured to, before sequentially transmitting the plurality of random numbers to the memory in the write order by the test host: the following is performed for each of a plurality of time nodes: generating at least one random number at a time node by a random number generator of the test host; the random numbers generated by the time nodes are mutually independent, and the writing sequence is the time sequence writing sequence of the time node for generating each random number.

In some embodiments, the sending module 2551 is further configured to: before sequentially transmitting a plurality of random numbers to a memory in a write order by a test host, the following processing is performed for each of a plurality of time nodes: when the time node is the earliest time node in the plurality of time nodes, acquiring a random number of circuit configuration aiming at the test host; when the time node is not the earliest time node in the plurality of time nodes, digital signal processing is carried out on the input data through a circuit of the test host to obtain a random number corresponding to the time node; the writing sequence is the time sequence writing sequence of the time node for generating each random number, and the input data of the circuit of the test host is the random number output by the last adjacent time node of the time node.

In some embodiments, the number of circuits of the test host is multiple; the sending module 2551 is further configured to: acquiring a random number unit configured for each circuit of a test host, and forming a plurality of random number units into a random number; the following is performed by each circuit of the test host: receiving a random number unit output by a previous adjacent time node, and performing digital signal processing on the received random number unit to obtain a random number unit corresponding to the time node; forming a random number by a random number unit output by each circuit of the test host at a time node; the circuits of the test host correspond to the random number units one by one.

In some embodiments, the sending module 2551 is further configured to: the following processing is performed in the write order for each random number by the test host: dividing the random number based on configuration bits to obtain a plurality of random number units; wherein the random number unit comprises at least one rising edge data bit, at least one falling edge data bit, a rising edge data mask bit, a falling edge data mask bit, a rising edge data bus flip bit, and a falling edge data bus flip bit; a plurality of random number units are sent in parallel to the memory.

In some embodiments, chain module 2552 is further configured to: the following processing is performed for each of the plurality of random numbers in the writing order: carrying out digital signal processing on the chain processing result of the last adjacent random number and the random number through a circuit of the test host to obtain a chain processing result of the corresponding random number; when the random number is the last random number based on the writing order among the plurality of random numbers, the chain processing result of the corresponding random number is determined as the first chain processing result.

In some embodiments, the number of circuits of the test host is multiple; chain module 2552, also for: the following is performed by each circuit of the test host: receiving a chain processing result of a last adjacent random number unit, and carrying out digital signal processing on the received chain processing result of the last adjacent random number unit and a random number unit of a corresponding circuit in the random number to obtain a chain processing result of the corresponding random number unit; and forming a chain type processing result of the corresponding random number unit output by each circuit of the test host into a chain type processing result of the corresponding random number.

In some embodiments, each circuit includes N cascaded circuit cells, chain module 2552, further configured to: determining the input of an nth circuit unit based on the chain processing result of the last adjacent random number unit and the random number unit of the corresponding circuit in the random number; shifting the input of the nth circuit unit through the nth circuit unit in the N cascaded circuit units to obtain an output bit code corresponding to the nth circuit unit; determining an input of an n+1-th circuit unit based on the output bit code corresponding to the n-th circuit unit; the n+1 circuit unit is used for continuously carrying out shift processing on the input of the n+1 circuit unit, so that the output bit code corresponding to the n+1 circuit unit is obtained; wherein, N is an integer greater than or equal to 2, N is an integer variable whose value increases from 1, and the value range of N is 1-N < N; the output bit codes of each circuit unit are subjected to descending order sorting processing based on the n value of the corresponding circuit unit, and a plurality of output bit codes are formed into a chain processing result of the corresponding random number unit according to the descending order sorting result.

In some embodiments, chain module 2552 is further configured to: when the n+1 circuit unit is directly connected with the n circuit unit, the output bit code of the n circuit unit and the input bit code of the random number unit corresponding to the n+1 circuit unit are used as the input of the n+1 circuit unit; when the n+1 circuit unit is connected with the N circuit unit through an exclusive OR gate, the first bit code output by the N circuit unit at the last adjacent time node and the output bit code of the N circuit unit are subjected to exclusive OR processing to obtain an exclusive OR output bit code, and the exclusive OR output bit code and the input bit code of the corresponding n+1 circuit unit in the random number unit are determined as the input of the n+1 circuit unit.

In some embodiments, the nth circuit unit includes a first and gate, a second and gate, an exclusive or gate, and a flip-flop; chain module 2552, also for: when the value of n is 1, performing AND gate processing on the last bit code of the random number unit and the first code value through a first AND gate to obtain a first AND gate result; performing AND gate processing on the second code value and the first code of the random number unit output by the node circuit at the last adjacent time through a second AND gate to obtain a second AND gate result; performing exclusive-or processing on the first AND gate result and the second AND gate result through an exclusive-or gate to obtain an exclusive-or result, and transmitting the exclusive-or result to a trigger; when the flip-flop receives the clock signal, the exclusive-or result is determined as the output bit code of the nth circuit.

In some embodiments, the nth circuit unit includes a first and gate, a second and gate, an exclusive or gate, and a flip-flop; chain module 2552, also for: when the value range of N is 2-N < N, performing AND gate processing on the N-n+1 bit code of the random number unit and the first code value through a first AND gate to obtain a first AND gate result; performing AND gate processing on the second coding value and the output bit code of the n-1 th circuit unit through a second AND gate to obtain a second AND gate result; performing exclusive-or processing on the first AND gate result and the second AND gate result through an exclusive-or gate to obtain an exclusive-or result, and transmitting the exclusive-or result to a trigger; when the flip-flop receives the clock signal, the exclusive-or result is determined as the output bit code of the nth circuit.

Embodiments of the present application provide a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions, so that the computer device executes the data path testing method of the memory according to the embodiment of the application.

Embodiments of the present application provide a computer readable storage medium storing executable instructions, wherein the executable instructions are stored, which when executed by a processor, will be executed by the processor to perform a data path testing method of a memory provided by embodiments of the present application, for example, a data path testing method of a memory as shown in fig. 5A-5C.

In some embodiments, the computer readable storage medium may be FRAM, ROM, PROM, EP ROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; but may be a variety of devices including one or any combination of the above memories.

In some embodiments, the executable instructions may be in the form of programs, software modules, scripts, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and they may be deployed in any form, including as stand-alone programs or as modules, components, subroutines, or other units suitable for use in a computing environment.

As an example, the executable instructions may, but need not, correspond to files in a file system, may be stored as part of a file that holds other programs or data, such as in one or more scripts in a hypertext markup language (html, hyper Text Markup Language) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub-programs, or portions of code).

As an example, executable instructions may be deployed to be executed on one computing device or on multiple computing devices located at one site or, alternatively, distributed across multiple sites and interconnected by a communication network.

In summary, according to the data path testing method for the memory provided by the embodiment of the application, the test host can send the plurality of random numbers to the memory, receive the second chained processing result corresponding to the last random number returned by the memory, and compare the chained processing result corresponding to the last random number returned by the memory with the first chained processing result obtained by the test host chained processing the plurality of random numbers, so that the whole process comprises multiple data sending and single data receiving, and finally, only the comparison is needed based on the second chained processing result corresponding to the last random number obtained by single receiving, thereby reducing the comparison times and saving the data quantity required to be compared, and further improving the data path testing efficiency of the memory. .

The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and scope of the present application are included in the protection scope of the present application.

Claims

1. A method for testing a data path of a memory, the method comprising:

reading a second chained processing result from the memory;

2. The method of claim 1, wherein before the plurality of random numbers are sequentially sent to the memory by the test host in the write order, the method further comprises:

For each of a plurality of time nodes, performing the following:

when the time node is the earliest time node in the plurality of time nodes, acquiring a random number of circuit configuration aiming at the test host;

when the time node is not the earliest time node in the plurality of time nodes, performing digital signal processing on input data through a circuit of the test host to obtain a random number corresponding to the time node;

the write sequence is a time sequence write sequence of a time node for generating each random number, and the input data of the circuit of the test host is the random number output by the last adjacent time node of the time node.

3. The method of claim 2, wherein the number of circuits of the test host is a plurality;

the obtaining a random number for a circuit configuration of the test host includes:

acquiring a random number unit configured for each circuit of the test host, and forming a plurality of random number units into the random number;

the digital signal processing is carried out on the input data by the circuit of the test host to obtain the random number corresponding to the time node, and the method comprises the following steps:

Each of the circuits through the test host performs the following processing:

receiving a random number unit output by a previous adjacent time node, and performing digital signal processing on the received random number unit to obtain a random number unit corresponding to the time node;

forming a random number unit output by each circuit of the test host at the time node into the random number;

the circuits of the test host correspond to the random number units one by one.

4. The method of claim 1, wherein sequentially sending, by the test host, the plurality of random numbers to the memory in the write order, comprises:

performing, by the test host, the following processing in the write order for each of the random numbers:

dividing the random number based on configuration digits to obtain a plurality of random number units;

wherein the random number unit comprises at least one rising edge data bit, at least one falling edge data bit, a rising edge data mask bit, a falling edge data mask bit, a rising edge data bus flip bit, and a falling edge data bus flip bit;

and transmitting the random number units to the memory in parallel.

5. The method of claim 1, wherein the chaining the plurality of random numbers by the circuitry of the test host in the write order results in a first chaining result, comprising:

performing the following processing for each of the plurality of random numbers in the writing order:

carrying out digital signal processing on the chain processing result of the last adjacent random number and the random number through a circuit of the test host to obtain a chain processing result corresponding to the random number;

and determining a chain processing result corresponding to the random number as the first chain processing result when the random number is the last random number based on the writing order among the plurality of random numbers.

6. The method of claim 5, wherein the number of circuits of the test host is a plurality;

the circuit passing through the test host performs digital signal processing on the chain processing result of the last adjacent random number and the random number to obtain the chain processing result corresponding to the random number, and the method comprises the following steps:

each of the circuits through the test host performs the following processing:

Receiving a chain processing result of a last adjacent random number unit, and carrying out digital signal processing on the received chain processing result of the last adjacent random number unit and a random number unit corresponding to the circuit in the random numbers to obtain a chain processing result corresponding to the random number unit;

and forming a chain type processing result corresponding to the random number by using the chain type processing result corresponding to the random number unit output by each circuit of the test host.

7. The method of claim 6, wherein each of the circuits comprises N cascaded circuit cells;

the step of performing digital signal processing on the received chain processing result of the last adjacent random number unit and the random number unit corresponding to the circuit in the random number to obtain the chain processing result corresponding to the random number unit comprises the following steps:

determining the input of an nth circuit unit based on the chain processing result of the last adjacent random number unit and the random number unit corresponding to the circuit in the random number;

performing shift processing on the input of an nth circuit unit through an nth circuit unit in N cascaded circuit units to obtain an output bit code corresponding to the nth circuit unit;

Determining an input of an n+1-th circuit unit based on an output bit code corresponding to the n-th circuit unit;

the method comprises the steps of continuing to carry out shift processing on the input of an n+1th circuit unit through the n+1th circuit unit to obtain output bit codes corresponding to the n+1th circuit unit;

wherein, N is an integer greater than or equal to 2, N is an integer variable whose value is increased from 1, and the value range of N is 1-N < N;

and performing descending order sorting processing on the output bit codes of each circuit unit based on the n value of the corresponding circuit unit, and forming a plurality of output bit codes into a chain processing result corresponding to the random number unit according to the descending order sorting result.

8. The method of claim 7, wherein determining the input of the n+1 th circuit unit based on the output bit encoding corresponding to the n th circuit unit comprises:

when the n+1-th circuit unit is directly connected with the n-th circuit unit, the output bit code of the n-th circuit unit and the input bit code corresponding to the n+1-th circuit unit in the random number unit are used as the input of the n+1-th circuit unit;

When the n+1 circuit unit is connected with the N circuit unit through an exclusive or gate, performing exclusive or processing on the first bit code output by the N circuit unit at the last adjacent time node and the output bit code of the N circuit unit to obtain an exclusive or output bit code, and determining the exclusive or output bit code and the input bit code corresponding to the n+1 circuit unit in the random number unit as the input of the n+1 circuit unit.

9. The method of claim 7, wherein the nth circuit unit comprises a first and gate, a second and gate, an exclusive or gate, and a flip-flop;

when N takes the value of 1, the shifting processing is performed on the input of the nth circuit unit through the nth circuit unit in the N cascaded circuit units, and the shifting processing comprises the following steps:

performing AND gate processing on the last bit code of the random number unit and the first code value through the first AND gate to obtain a first AND gate result;

performing AND gate processing on the second code value and the first code of the random number unit output by the circuit at the last adjacent time node through the second AND gate to obtain a second AND gate result;

Performing exclusive-or processing on the first AND gate result and the second AND gate result through the exclusive-or gate to obtain an exclusive-or result, and transmitting the exclusive-or result to the trigger;

when the flip-flop receives a clock signal, the exclusive-or result is determined as an output bit code of the nth circuit.

10. The method of claim 7, wherein the nth circuit unit comprises a first and gate, a second and gate, an exclusive or gate, and a flip-flop;

when the value range of N is 2 less than or equal to N and less than N, the shifting processing is performed on the input of the nth circuit unit through the nth circuit unit in the N cascaded circuit units, and the shifting processing comprises the following steps:

performing AND gate processing on the N-n+1 bit code of the random number unit and the first code value through the first AND gate to obtain a first AND gate result;

when the N-1 circuit unit is connected with the N circuit unit through the exclusive-OR gate, performing exclusive-OR processing on the first bit code output by the N circuit unit at the last adjacent time node and the output bit code of the N-1 circuit unit to obtain an exclusive-OR output bit code, and performing AND gate processing on a second code value and the exclusive-OR output bit code through the second AND gate to obtain a second AND gate result;

When the n-1 circuit unit is directly connected with the n circuit unit, performing AND gate processing on a second coding value and the output bit code of the n-1 circuit unit through the second AND gate to obtain a second AND gate result;

11. The method of claim 1, wherein the test host includes a random number generator, the method further comprising, prior to sequentially sending the plurality of random numbers to the memory by the test host in a write order:

for each of a plurality of time nodes, performing the following:

generating at least one random number at the time node by a random number generator of the test host;

the random numbers generated by the time nodes are mutually independent, and the writing sequence is the time sequence writing sequence of the time node for generating each random number.

12. A data path testing apparatus for a memory, the apparatus comprising:

13. An electronic device, the electronic device comprising:

a memory for storing executable instructions;

a processor for implementing the data path testing method of a memory according to any one of claims 1 to 11 when executing executable instructions stored in said memory.

14. A computer readable storage medium storing executable instructions which when executed by a processor implement the method of datapath testing of a memory of any one of claims 1 to 11.

15. A computer program product comprising a computer program or instructions which, when executed by a processor, implements the data path testing method of the memory of any of claims 1 to 11.