CN116684684A

CN116684684A - SRIO serial video stream analysis method based on FPGA

Info

Publication number: CN116684684A
Application number: CN202310529254.1A
Authority: CN
Inventors: 于子涵; 李凯峰; 黄静颖; 黄成章
Original assignee: CETC 11 Research Institute
Current assignee: CETC 11 Research Institute
Priority date: 2023-05-11
Filing date: 2023-05-11
Publication date: 2023-09-01

Abstract

The application provides an SRIO serial video stream analysis method based on an FPGA, which comprises the following steps: confirming a zone bit of video stream image data acquired through an SRIO serial port; performing filling processing on each line of image data in the video image data; caching current image data, and synchronously performing clock domain transformation; and reading the cached image data according to a preset format, generating an effective enabling signal of the image data, and transmitting the effective enabling signal aligned with the analyzed image data to form data stream. The application realizes the SRIO serial image video stream analysis based on the FPGA, can be used for efficiently and quickly recovering the images in the video stream, and reduces the pressure of the subsequent FPGA image processing; and the data can be streamed, so that the real-time performance of the whole FPGA system operation is improved.

Description

SRIO serial video stream analysis method based on FPGA

Technical Field

The application relates to the technical field of image data processing, in particular to an SRIO serial video stream analysis method based on an FPGA.

Background

The computer software technology at the present stage provides a good development platform for the video image processing technology, and the powerful processing capacity of the computer processor is well applied to various video image processing algorithms. The field programmable gate array (FieldProgrammableGateArray, FPGA) device with high integration, high performance and low power consumption provides wide development prospect for video image system designers, and the unique performance advantage of the FPGA occupies a very important position in an embedded video image processing system.

In practical application, in order to meet the requirement of data processing instantaneity, data needs to be streamed when designing an FPGA program. By designing the data stream, the real-time processing of a large amount of data is realized by utilizing the strong parallel operation capability of the FPGA. If the data cannot be pipelined, the real-time nature of the overall FPGA design is compromised.

Disclosure of Invention

The application aims to solve the technical problem of how to efficiently and rapidly recover images in a video stream, stream data and promote the real-time performance of the whole FPGA system operation; in view of the above, the application provides an SRIO serial video stream analysis method based on FPGA.

The technical scheme adopted by the application is that the SRIO serial video stream analysis method based on the FPGA comprises the following steps:

step S1, confirming a zone bit of video stream image data acquired through an SRIO serial port;

step S2, carrying out filling processing on each line of image data in the video image data;

step S3, caching current image data and synchronously performing clock domain transformation;

and S4, reading the cached image data according to a preset format, generating an effective enabling signal of the image data, and transmitting the effective enabling signal aligned with the analyzed image data to form data stream.

In one embodiment, the performing flag bit validation on the video stream image data acquired via the SRIO serial port includes:

and confirming the start of each frame of image data in the video stream image and the start of each row of data in one frame of image data.

In one embodiment, the step of reading the buffered image data according to a preset format includes:

and synchronously carrying out secondary flag bit confirmation processing on the current image data.

In one embodiment, the caching the current image data includes: the current image data is buffered in the FIFO and counted.

In one embodiment, the preset format includes: the number of frames of the current image data, the size of each frame of the image data, and the number of lines are preconfigured.

In one embodiment, in step S4, the buffered image data is read according to a preset format by using a state machine, and a valid enable signal of the image data is generated.

In one embodiment, the state of the state machine includes: and (3) starting, reading, judging the line, delaying the line, judging the frame, delaying the frame, and if the current image data meets the jump condition of the state, performing the operation corresponding to the next state.

By adopting the technical scheme, the application realizes the SRIO serial image video stream analysis based on the FPGA, can be used for efficiently and quickly recovering the images in the video stream, and reduces the pressure of the subsequent FPGA image processing; and the data can be streamed, so that the real-time performance of the whole FPGA system operation is improved.

Drawings

Fig. 1 is a flow chart of an SRIO serial video stream parsing method based on an FPGA according to an embodiment of the present application;

FIG. 2 is a schematic diagram of an overall system architecture according to an embodiment of the present application;

FIG. 3 is a logic diagram of a state transition and image delay read function performed by internal counting of a state machine according to an embodiment of the present application;

fig. 4 is a schematic diagram of an image video stream parsing flow according to an embodiment of the application.

Detailed Description

In order to further describe the technical means and effects adopted by the present application for achieving the intended purpose, the following detailed description of the present application is given with reference to the accompanying drawings and preferred embodiments.

In the drawings, the thickness, size and shape of the object have been slightly exaggerated for convenience of explanation. The figures are merely examples and are not drawn to scale.

It will be further understood that the terms "comprises," "comprising," "includes," "including," "having," "containing," and/or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of the following" appears after a list of features that are listed, the entire listed feature is modified instead of modifying a separate element in the list. Furthermore, when describing embodiments of the present application, the use of "may" means "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

As used herein, the terms "substantially," "about," and the like are used as terms of a table approximation, not as terms of a table level, and are intended to illustrate inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.

In a first embodiment of the present application, as shown in fig. 1, an SRIO serial port video stream parsing method based on FPGA includes the following steps:

In one embodiment, the step of reading the buffered image data according to the preset format may specifically include: and synchronously carrying out secondary flag bit confirmation processing on the current image data.

In one embodiment, caching current image data includes: the current image data is buffered in FIFO (first in first out buffer) and counted.

In one embodiment, in step S4, the buffered image data is read according to a preset format by using a state machine, and a valid enable signal for the image data is generated.

The second embodiment of the present application, corresponding to the first embodiment, is an application example based on the first embodiment.

In this embodiment, the overall hardware platform includes two FPGAs, i.e., a front-end interface board and a signal processing board, and the overall system architecture is shown in fig. 2.

Specifically, the front-end interface board is mainly used for receiving an infrared image (it can be understood that the infrared image can be any possible image data generated in any other field) acquired by the infrared imaging device, and packaging the infrared image into a data packet according to a fixed format. Based on the requirements of the experiment, the image format is set to 1024x1280 format, each column contains 1280 pixel value data, and the image contains 1024 columns of images in total. When the front-end interface board is packaged, a flag bit is added at the beginning of each column, namely, a start flag exists in every 1280 data, and each frame of image also has a start flag. In this way, the front-end interface board card does not need to consider whether the data packet accords with the row-column structure of the image when transmitting data, only needs to pay attention to whether the generation of the flag bit is in compliance, and finally transmits the packed image data to the signal processing board card through the serial communication protocol. And using two boards to simulate a real camera to shoot a video transmission scene. Because the data exists in the form of data stream in the transmission, the two boards need to realize high-speed communication to ensure the real-time performance of the system, so the SRIO serial communication protocol is adopted to transmit the data.

The image data received by the signal processing board card is transmitted in the form of data packets, and in order to facilitate the subsequent image processing work, the image data packets need to be analyzed, and the data packets are restored to the form of data streams. And receiving an image data packet through the SRIO interface, and carrying out image analysis by using the frame header mark bit as a key word.

For example, the size of one image may be 1280x1024, when the image module is constructed, the finite state machine method is adopted to build the data packet analysis logic, the packet header and frame header analysis conditions are set, and the state jump of the finite state machine is utilized to complete the switching of the working mode and analyze the image data.

Meanwhile, because the data packets transmitted from the front end have the phenomenon that the interval time of each data is unequal, in order to ensure the normal operation of the operation logic of the image data and the stability of the frame frequency of the whole system by the follow-up algorithm data, a first-level FIFO method is adopted in the logic construction, and a fixed time interval is set for the data, so that the original image data packets are restored into stable image data streams. In the writing of the related FIFO, the control of FIFO read-write is also realized through a finite state machine, and the state jump and image delay reading functions are completed through the internal counting of the state machine, and the specific realization method is shown in figure 3, wherein Idle is the initial state; vs_num is a frame count state for counting one frame of image data; hs_num is a rank count state; hs_delay is a row-column delay state; vs_delay is the frame delay state. When fifo read/write operation is entered, the state starts from Idle, and when the skip flag is valid, the state is changed to the frame count state, and the image frame header is detected, and the data write fifo operation is started. When the image rank flag bit is detected, skipping to a rank counting state, after a row of data is completely written into fifo, entering a rank delay state, after fixed delay is completed, judging whether a frame of image is completed, and after the completion of writing of a frame of image, entering a frame delay state, and performing fixed time delay operation between two frames of images, wherein the rank counting state and the rank delay state are required to be continuously repeated.

The specific implementation steps are as follows, and reference is made to fig. 4:

1. judging a zone bit of a video stream received by SRIO, and delaying;

2. after judging, storing the data meeting the conditions into the FIFO through a state machine and counting;

3. running state machines in parallel, and if the jump condition of the slave state is met, performing operation corresponding to the next state;

4. based on the operation of the state machine, a valid enable signal of the data is generated, specifically, the frame valid signal is pulled high at the beginning of the frame count state, and the frame valid signal is pulled low at the time of entering the frame delay state, and the frame valid signal means that the frame image is valid at the time of pulling high. The column valid signal is pulled high at the beginning of the column count state, and pulled low at the time of entering the column delay state, which means that the column image data is valid. The effective signal of the image data is transmitted together with the image data, so that the image data and a judging mark for the effectiveness of the data are provided for subsequent image processing and other operations.

The foregoing is merely illustrative of specific embodiments and exemplary applications of the present application, but the scope of the application is not limited thereto, and any person skilled in the art will understand that modifications and substitutions made within the scope of the present application are included in the scope of the present application, and the scope of the present application shall be defined by the claims.

Compared with the prior art, the embodiment has at least the following advantages:

1) The embodiment realizes the SRIO serial image video stream analysis based on the FPGA, can be used for efficiently and quickly recovering the images in the video stream, and reduces the pressure of the subsequent FPGA image processing;

2) The embodiment can enable data to be streamed, and improves the real-time performance of the whole FPGA system operation.

While the application has been described in connection with specific embodiments thereof, it is to be understood that these drawings are included in the spirit and scope of the application, it is not to be limited thereto.

Claims

1. An SRIO serial port video stream analysis method based on FPGA is characterized by comprising the following steps:

2. The FPGA-based SRIO serial video stream parsing method of claim 1, wherein the performing flag bit validation on the video stream image data acquired via the SRIO serial port comprises:

3. The method for analyzing the SRIO serial video stream based on the FPGA according to claim 1, wherein the step of reading the buffered image data according to the preset format includes:

4. The FPGA-based SRIO serial video stream parsing method of claim 1, wherein the buffering the current image data comprises: the current image data is buffered in the FIFO and counted.

5. The method for analyzing an SRIO serial video stream based on an FPGA according to claim 1, wherein the preset format includes: the number of frames of the current image data, the size of each frame of the image data, and the number of lines are preconfigured.

6. The method for analyzing the SRIO serial video stream based on the FPGA of claim 1, wherein in the step S4, the buffered image data is read according to a preset format by using a state machine to generate an enabling signal for effectively enabling the image data.

7. The FPGA-based SRIO serial video stream parsing method of claim 6, wherein the state of the state machine comprises: and (3) starting, reading, judging the line, delaying the line, judging the frame, delaying the frame, and if the current image data meets the jump condition of the state, performing the operation corresponding to the next state.