CN116682806A

CN116682806A - Semiconductor device and test method thereof

Info

Publication number: CN116682806A
Application number: CN202310247159.2A
Authority: CN
Inventors: 赖昱安; 游本杰; 陈建宏; 谢正祥
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-05-11
Filing date: 2023-03-15
Publication date: 2023-09-01

Abstract

An embodiment of the present invention provides a semiconductor device including a transistor including: a plurality of layers, wherein each of the plurality of layers has at least one group III-V compound material; a gate electrode operatively connected to at least one of the plurality of layers; a source electrode disposed on a first side of the gate electrode; a drain electrode disposed on a second side of the gate electrode; a field plate disposed between the gate electrode and the drain electrode; and a plurality of wires disposed over the gate electrode, the source electrode and the drain electrode. The semiconductor device further includes a plurality of test structures, wherein each test structure including the first metal pattern and the second metal pattern simulates at least one of a gate electrode, a source electrode, a drain electrode, at least one of a field plate, or at least one of a plurality of conductive lines. The embodiment of the invention also provides a method for testing the semiconductor device.

Description

Semiconductor device and test method thereof

Technical Field

Embodiments of the present invention relate generally to the field of semiconductors, and more particularly, to semiconductor devices and methods of testing the same.

Background

Silicon-based electronic devices, such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), have achieved considerable success over the past few decades and represent the current standard for power applications ranging from tens of watts to hundreds or even kilowatts, such as AC/DC power, DC/DC power, and motor control. The on-resistance R of the silicon-based electronic device _DS(ON) Key parameters such as voltage rating, switching speed, packaging and other attributes are continually improved. However, the speed of improvement of these silicon-based electronic devices has tended to be smooth, as their performance is now approaching theoretical limits determined by the underlying physics of these materials and processes.

Disclosure of Invention

One aspect of the present invention provides a semiconductor device including: a transistor, comprising: a plurality of layers, wherein each of the plurality of layers has at least one group III-V compound material; a gate electrode operatively connected to at least one of the plurality of layers; a source electrode disposed on a first side of the gate electrode; a drain electrode disposed on a second side of the gate electrode; a field plate disposed between the gate electrode and the drain electrode; and a plurality of wires disposed over the gate electrode, the source electrode, and the drain electrode; and a plurality of test structures, wherein each test structure including a first metal pattern and a second metal pattern simulates at least one of the gate electrode, the source electrode, the drain electrode, the field plate, and at least one of the plurality of conductive lines.

Another aspect of the present invention provides a semiconductor device including: a first semiconductor die, comprising: a plurality of first transistors, wherein each of the plurality of first transistors has at least one group III-V compound material; a second semiconductor die comprising: a plurality of second transistors, wherein each of the plurality of second transistors has at least one group III-V compound material; and a test structure disposed beside the first semiconductor die and the second semiconductor die; wherein the test structure includes a first metal pattern and a second metal pattern and is configured to simulate one or more components in each of the first semiconductor die and the second semiconductor die to determine whether a defect is present in at least one of the first semiconductor die and the second semiconductor die.

Yet another aspect of the present invention provides a method for testing a semiconductor device, comprising: forming a transistor comprising a plurality of layers, wherein each of the plurality of layers has at least one group III-V compound material; forming a test structure comprising a first metal pattern and a second metal pattern, wherein the test structure is configured to simulate one or more components of the transistor; detecting whether abnormal behavior exists in a current-voltage curve related to the test structure; and in response to detecting the presence of the abnormal behavior, determining that the transistor is defective.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates a block diagram of a GaN-based integrated circuit, in accordance with various embodiments.

Fig. 2 illustrates an example arrangement of a GaN-based device and a plurality of test structures of the GaN-based integrated circuit of fig. 1, in accordance with various embodiments.

Fig. 3 illustrates a cross-sectional view of a GaN-based device, in accordance with various embodiments.

Fig. 4, 5, 6, 7, 8, and 9 illustrate various arrangements of test structures simulating GaN-based devices, respectively, according to various embodiments.

Fig. 10 illustrates a block diagram of a test system for identifying defects of a GaN-based device, in accordance with various embodiments.

Fig. 11 illustrates a circuit diagram of a high voltage charge pump in accordance with various embodiments.

Fig. 12 illustrates a circuit diagram of a high voltage clock generator operatively connected to the charge pump of fig. 11, in accordance with various embodiments.

Fig. 13 illustrates a cross-sectional view of a diode-connected transistor implemented by the charge pump of fig. 11, in accordance with various embodiments.

Fig. 14 illustrates an example flowchart of a method for identifying defects of a GaN-based device, in accordance with various embodiments.

Fig. 15 illustrates an example flow chart of a method for fabricating a GaN-based device and one or more corresponding test structures thereof, in accordance with various embodiments.

Detailed Description

The invention provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. Such as in the following description, forming the first component over or on the second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms such as "below …," "below …," "lower," "above …," "upper" and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Group III-V (or III-V) semiconductor compound materials are generally considered as one of the alternative materials to silicon because they have excellent material properties compared to silicon. For example, gallium nitride (GaN) based materials have been widely studied in various electronic and/or optoelectronic applications. GaN-based materials are commonly referred to as gallium nitride (GaN) and alloys thereof, such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). In particular, gaN-based materials are wide bandgap semiconductors that are capable of maintaining their electrical properties at higher temperatures than other semiconductors (such as silicon or gallium arsenide). GaN-based materials also have a higher carrier saturation velocity compared to silicon. Furthermore, gaN-based materials have wurtzite crystal structure, are hard materials, have high thermal conductivity, and have a much higher melting point than other conventional semiconductors (e.g., silicon, germanium, and gallium arsenide). Thus, gaN-based materials can be used for high voltage and high power applications.

Despite the great commercial importance of GaN-based optoelectronic and electronic devices, the quality and reliability of these devices is often affected by relatively high defect levels in one or more semiconductor layers formed therein. For example, such defects may result from: (1) Lattice mismatch of GaN-based semiconductor layers with non-GaN substrates (such as silicon, sapphire, or silicon carbide); (2) a coalescence front of the epitaxial overgrowth layer; (3) thermal expansion mismatch; (4) impurities; (5) tilting the boundary. The presence of defects has a detrimental effect on the epitaxial growth layer. Such effects include compromising the performance of the electronic/optoelectronic device.

Although some techniques have been proposed to identify some defects in GaN-based devices (e.g., gaN-based high voltage devices), these techniques still do not effectively identify a significant number of defects. For example, gaN-based high voltage devices typically form lateral devices to enlarge their drift region (and thus their breakdown voltage). Therefore, the dimensions of the various components of the GaN-based high voltage device (e.g., the pitch/spacing between the device components) are typically formed to be larger than Si-based high voltage devices. Thus, when defects are small enough and exist between these relatively widely spaced device components, no defects can be detected using any prior art technique. Thus, existing high voltage GaN-based devices or techniques for detecting defects in such devices are not entirely satisfactory in many respects.

The present disclosure provides various embodiments of GaN-based integrated circuits including GaN-based devices and one or more test structures. Each test structure can simulate a GaN-based device, so that defects of the GaN-based device can be effectively and accurately detected. According to one aspect of the present disclosure, some of the test structures may be formed as alternating structures, respectively. For example, the test structure may have a first pattern and a second pattern with respective portions disposed laterally adjacent (e.g., a pitch that is significantly smaller than a pitch of the GaN-based device to be inspected). According to another aspect of the present disclosure, some of the test structures may be formed as metal-insulator-metal (MIM) structures, respectively. For example, the test structure may have a first pattern and a second pattern, respective portions of which overlap each other in a vertical direction. In any of the alternating arrangements or MIM structures, the first pattern and the second pattern may simulate similar or different device features of the GaN-based device by being fabricated simultaneously with those simulated device features. Thus, when a device component of a GaN-based device develops defects during fabrication, such defects are likely to also be present in the simultaneously formed test structures. The prior art (e.g., measuring various electrical characteristics of GaN-based devices) may not be able to effectively detect defects because defects (on smaller dimensions) may exist in the spacing between relatively widely spaced device components. In contrast, the pattern of the disclosed test structure, having flexibly configured dimensions and contours, can quickly detect such defects. Further, since the pattern of the test structure may be formed simultaneously with any device component, the location and/or type of defect may be accurately determined by the test structure.

Fig. 1 illustrates an example block diagram of a GaN-based integrated circuit 100, in accordance with various embodiments. It should be understood that the block diagram of fig. 1 is simplified for illustration purposes. Thus, gaN-based integrated circuit 100 may include any of a variety of other (e.g., functional) blocks while remaining within the scope of the present disclosure.

As will be discussed below, the GaN-based integrated circuit 100 includes a plurality of (e.g., electronic) components formed based on GaN-based materials, such as gallium nitride (GaN) and alloys thereof, such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). Examples of such components include, but are not limited to, transistors, resistors, capacitors, diodes, and the like. Such GaN-based materials may be epitaxially grown on non-GaN-based materials, such as silicon, sapphire, and/or silicon carbide, used as substrates for GaN-based integrated circuit 100. GaN-based integrated circuit 100 may be implemented as a single system-on-a-chip (SoC) architecture or as a multi-SoC architecture. Thus, the GaN-based integrated circuit 100 may be formed on a single substrate or on multiple substrates.

As shown, gaN-based integrated circuit 100 includes at least one GaN-based device (or circuit) 102 and at least one test structure 104. The GaN-based device 102 and the test structure 104 may be surrounded by a ring structure (e.g., implemented as an isolation structure) 106. In some embodiments, gaN-based device 102 may include a GaN-based high voltage device having a plurality of active components (discussed further in fig. 3 below) formed from the GaN-based materials listed above. For example, gaN-based device 102 may remain operational over a voltage range of more than 40 volts (e.g., a voltage of approximately 600 volts), but GaN-based device 102 may operate over any of a variety of other voltage ranges while remaining within the scope of the present disclosure. The test structure 104 may include a first conductive (e.g., metal) pattern and a second conductive (e.g., metal) pattern that respectively simulate one or more conductive (e.g., metal) components contained in the GaN-based device 102 (as will be further discussed in fig. 4-9 below).

In the example block diagram of fig. 1, gaN-based device 102 and test structure 104 are disposed in close proximity to each other, e.g., gaN-based device 102 and test structure 104 are formed in different regions of the same semiconductor die, respectively. However, it should be understood that the space of GaN-based device 102 and test structure 104 may be configured differently while remaining within the scope of the present disclosure. For example, the test structure 104 may not be present on a semiconductor die (e.g., a single or singulated die). Although GaN-based devices 102 are formed on a particular die over a wafer, corresponding test structures 104 may be formed along one or more scribe lines over the wafer. Scribe lines (sometimes referred to as kerfs or frames) are areas in a wafer that are used to divide or otherwise separate individual dies at the end of a wafer process. Thus, in addition to simulating the conductive features of the illustrated GaN-based device 102 (formed on the first die), the test structure 104 may be configured to simulate the conductive features of another GaN-based device (formed on the second die). In such an embodiment, the test structure 104 may not be present on a single die. Furthermore, while only one test structure 104 corresponding to a respective GaN-based device is shown in fig. 1, it should be understood that GaN-based integrated circuit 100 may include any number of test structures corresponding to a GaN-based device to detect defects thereof while remaining within the scope of the present disclosure.

In some embodiments, the first and second conductive patterns of the test structure 104 may be formed simultaneously with the conductive features of the GaN-based device 102. In addition, the first and second conductive patterns may be formed on or in GaN-based materials that are also formed simultaneously with active components of GaN-based materials in GaN-based device 102. By examining the electrical characteristics of the test structure 104 (e.g., whether an open circuit or a short circuit exists between the first and second patterns), the test structure 104 may determine whether a defect exists between the first and second conductive patterns, which may effectively and accurately help determine whether a defect exists in or between the respective conductive features of the GaN-based device 102. Still further, the first and second conductive patterns of the test structure 104 may be formed to have a pitch that is much smaller than the pitch of the conductive features in the GaN-based device 102. Thus, the test structure 104 may advantageously enhance its sensitivity in detecting defects formed in itself (which may also be present in the GaN-based device 102).

In some embodiments, the first and second conductive patterns of the test structure 104 may be formed as alternating structures or metal-insulator-metal (MIM) structures. When formed in an alternating arrangement, the first and second conductive patterns may have a base and a plurality of protrusions extending away from the base, respectively. The respective protruding portions of the first conductive patterns and the second conductive patterns are alternately arranged with each other. In other words, each protrusion of the first conductive pattern is laterally disposed between adjacent protrusions of the second conductive pattern while having a configurable spacing. The spacing may be in the range of from about 0.25 micrometers (μm) to about 6 μm, although other ranges may be used. In general, the pitch may be configured according to the size of defects that may be induced. When formed in the MIM structure, the first conductive pattern and the second conductive pattern may have at least a first portion and at least a second portion, respectively, vertically overlapping each other.

In some embodiments, the first and second conductive patterns of the test structure 104 may simulate at least seven combinations of conductive features of the GaN-based device 102, as listed in the following table. In short, the conductive member may include a gate electrode (G), a Field Plate (FP), an Ohmic contact (Ohmic), a p-doped GaN region (p-GaN), and a conductive line (M1) of a metal layer. Further, the first and second conductive patterns of the test structure 104 may be formed as an alternating arrangement structure or MIM structure. When formed as an alternating arrangement of structures, the spacing between respective portions of the first and second conductive patterns may be configured to be from about 0.25 microns to about 6 microns, and the ratio of the area occupied by the test structures 104 to the area of the GaN-based device 102 may be configured to be from about 1% to about 10%; when formed as a MIM structure, the ratio of the area occupied by the test structure 104 to the area of the GaN-based device 102 may be configured to be about 1% to about 10%. Details of this combination of simulated conductive features will be discussed below based on the example GaN device shown in fig. 3.

Simulated conductive component	Pitch/area ratio
		G/FP (alternate arrangement)	0.25～6μm/1～10％
FP/FP (alternate arrangement)	0.25～6μm/1～10％
		Occic/FP (alternate arrangement)	0.25～6μm/1～10％
Ohmic/p-GaN (alternating arrangement)	0.25～6μm/1～10％
		M1/FP(MIM)	1～10％
FP/FP(MIM)	1～10％
		Ohmic/FP(MIM)	1～10％

List one

Fig. 2 illustrates an example arrangement of a plurality of test structures 104A, 104B, 104C, 104D, 104E, 104F, 104G, 104H, 104I, 104J, 104K, 104L, 104M, 104N, 104O, and 104P arranged alongside GaN-based device 102, in accordance with various embodiments. As shown, the test structures 104A-104P may be arranged as a ring around the GaN-based device 102. Although sixteen test structures are formed around GaN-based device 102, it should be understood that any number of test structures may be formed. Further, the test structures formed around GaN-based device 102 may be arranged in any of a variety of other configurations while remaining within the scope of the present disclosure. According to various embodiments, each of the test structures 104A-104P may include a first conductive pattern and a second conductive pattern that respectively simulate conductive features of the GaN-based device 102 listed in the above table. For example, some of the test structures 104A-104P (e.g., 104A and 104B) may simulate similar conductive features (e.g., G/FP) of the GaN-based device 102, but with different pitches, respectively.

Fig. 3 illustrates an example GaN-based device 300 that may be implemented as GaN-based device 102 of GaN-based integrated circuit 100, in accordance with various embodiments. The GaN-based device 300 includes at least one of GaN-based materials (e.g., gaN, alGaN, inGaN, alInGaN, etc.) as its active element (e.g., active channel of a transistor). Further, gaN-based device 300 can be formed on a substrate that is not GaN-based (e.g., silicon). Thus, gaN-based device 300 has one or more GaN-based materials epitaxially grown on a non-GaN-based substrate, possibly with different defects found above that are present in the GaN-based material layer or at the interface of different GaN-based layers.

In some embodiments, gaN-based device 300 may be implemented as a power transistor that may operate at a high voltage level. For example, device 300 may be a High Electron Mobility Transistor (HEMT) with high current density, high breakdown voltage (HEMT's ability to withstand high gate and/or drain electrode voltages without being damaged and/or exhibiting irregular current behavior), and low on-resistance, which allows device 300 to maintain operation over a voltage range of about 40 volts to about 650 volts. Thus, device 300 may sometimes be referred to as a "power HEMT 300". A two-dimensional electron gas (2 DEG) to be discussed below is typically used as a charge carrier in such HEMT.

As shown in the cross-sectional view of fig. 3, the power HEMT 300 includes a substrate 310, a first group III-V compound (e.g., including one or more GaN-based materials) layer 312 formed on the substrate 310, and a second group III-V compound (e.g., including one or more GaN-based materials) layer 314 formed on the first layer 312.

It should be understood that the power HEMT 300 of fig. 3 is an illustrative example, and thus, the power HEMT 300 may include any of a variety of other layers while remaining within the scope of the present disclosure. For example, the power HEMT 300 may further include a buffer layer and a transition layer between the substrate 310 and the first layer 312. The buffer layer may define a high resistivity layer for increasing the breakdown voltage (e.g., up to about 650 volts) of the power HEMT 300. In some embodiments, the buffer layer includes one or more GaN-based materials (e.g., gaN, alGaN, inGaN, inAlGaN, etc.). The transition layer may promote a gradual change in lattice structure and coefficient of thermal expansion between the substrate 310 and the overlying layer (e.g., first layer 312). In some embodiments, the transition layer comprises graded aluminum-gallium nitride (Al _x Ga _(1-x) N), x is the aluminum content ratio in the aluminum gallium component, 0<x<1) A layer. In some embodiments, the graded aluminum gallium nitride layer includes a plurality of layers from a bottom layer adjacent to the substrate 310 to a top layer adjacent to the first layer 312, each layer having a reduced ratio x.

The substrate 310 is a semiconductor substrate. In some embodiments, the semiconductor substrate 310 is made of the following materials: such as silicon; compound semiconductors such as silicon carbide, indium arsenide, indium phosphide, and the like; or an alloy semiconductor such as silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. The substrate 310 may also include various doped regions, dielectric features, or multilevel interconnects in a semiconductor substrate.

The first group III-V compound layer 312 and the second group III-V compound layer 314 are compounds made of groups III-V of the periodic table of elements. However, the first group III-V compound layer 312 and the second group III-V compound layer 314 are different from each other in composition. In some embodiments, the first group III-V compound layer 312 includes a gallium nitride (GaN) layer (also referred to as GaN layer 312). The GaN layer 312 may be epitaxially grown by a variety of processes, including but not limited to metal organic chemical vapor deposition (MOCVD, also known as Metal Organic Vapor Phase Epitaxy (MOVPE)), using suitable nitrogen-and gallium-containing precursors. For example, an exemplary gallium-containing precursor is Trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemical precursor. Exemplary nitrogen precursors include, but are not limited to, phenylhydrazine, dimethylhydrazine, t-butylamine, ammonia, or other suitable chemical precursors.

In some embodiments, the second group III-V compound layer 314 includes an aluminum gallium nitride (AlGaN) layer (also referred to as AlGaN layer 314). AlGaN layer 314 may be epitaxially grown by MOCVD using appropriate aluminum, nitrogen, and gallium precursors. The aluminum precursor includes Trimethylaluminum (TMA), triethylaluminum (TEA), or a suitable chemical precursor. Exemplary gallium-containing precursors are Trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemical precursors. Exemplary nitrogen precursors include, but are not limited to, phenylhydrazine, dimethylhydrazine, t-butylamine, ammonia, or other suitable chemical precursors. AlGaN layer 314 may also be referred to as a barrier layer. The GaN layer 312 and the AlGaN layer 314 are in direct contact with each other. The transition layer that typically exists between the substrate 310 and the GaN layer 312 is not shown.

The different materials formed on the semiconductor substrate 310 result in layers having different bandgaps. The bandgap discontinuity between GaN layer 312 and AlGaN layer 314, as well as the piezoelectric effect, creates a very thin layer 316 in GaN layer 312 with high mobility conductive electrons. The thin layer 316 forms a conductive two-dimensional electron gas (2 DEG) region near the junction of the two layers. Thin layer 316 (also referred to as 2DEG region 316) allows charge to flow through the device. The barrier layer, such as AlGaN layer 314, may be doped or undoped. Most nitride devices are typically on or depletion mode devices because the 2DEG region exists below the gate electrode at zero gate electrode bias.

The power HEMT 300 also includes a doped GaN region 320 over the AlGaN layer 314. In some embodiments, a mask layer, such as a photoresist layer, is formed over the blanket doped GaN layer. The blanket doped GaN layer may be a doped group III-V compound layer, such as a p-type doped GaN layer (also referred to as a doped GaN layer). Doped GaN layers can be epitaxially grown by MOCVD using appropriate aluminum, nitrogen, and gallium precursors. The aluminum precursor includes Trimethylaluminum (TMA), triethylaluminum (TEA), or a suitable chemical precursor. Exemplary gallium-containing precursors are Trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemical precursors. Exemplary nitrogen precursors include, but are not limited to, phenylhydrazine, dimethylhydrazine, t-butylamine, ammonia, or other suitable chemical precursors. Next, the mask layer is patterned by a photolithography process to form a plurality of features and a plurality of openings defined by the features on the doped GaN layer. The pattern of the mask layer is formed according to a predetermined integrated circuit pattern. The photolithographic process may include photoresist coating, exposure, post exposure bake and development. Then, an etching process is performed to define the doped GaN region 320.

After forming doped GaN region 320, a dielectric layer 322 is formed over doped GaN region 320 and AlGaN layer 314. Dielectric layer 322 may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, low-k dielectric material, or a combination thereof. The dielectric layer 322 may be formed by a deposition process, such as an ALD process, a CVD process, or a PVD process. The thickness of dielectric layer 322 is in the range of about 300 angstroms to about 3000 angstroms.

Next, the dielectric layer 322 is patterned to define a plurality of ohmic contact regions in the dielectric layer 322. For example, the ohmic contact regions may expose first and second portions of the AlGaN layer 314 to form a source electrode 330 and a drain electrode 332, respectively. In some embodiments, dielectric layer 322 is selectively etched and cleaned to define ohmic contact regions. Exemplary etching processes include sputter etching, reactive gas etching, chemical etching, and ion milling.

After the ohmic contact regions are defined, an ohmic metal layer is formed on the (patterned) dielectric layer 322 to fill the ohmic contact regions. An ohmic metal layer is deposited on the dielectric layer 322. The deposition process may be sputter deposition, evaporation or Chemical Vapor Deposition (CVD). Exemplary ohmic metals include, but are not limited to Ta, taN, pd, W, WSi, ti, al, tiN, alCu, alSiCu, and Cu. The ohmic metal layer has a thickness of about 2000 angstroms to about 5000 angstroms. A post-deposition anneal of the ohmic metal layer is then performed to initiate any desired reaction between the ohmic metal and the adjacent AlGaN layer 314. In some embodiments, the ohmic metal layer is formed by Rapid Thermal Annealing (RTA) at an annealing temperature ranging from about 800 ℃ to about 900 ℃.

Next, portions of the ohmic metal layer are removed to form the source electrode 330 and the drain electrode 332. The removal process includes performing one or more etching processes. The source electrode 330 and the drain electrode 332 are each connected to the AlGaN layer 314 through ohmic contacts. In some embodiments, the source electrode 330 and the drain electrode 332 are directly connected to the AlGaN layer 314. Accordingly, the source electrode 330 and the drain electrode 332 are sometimes referred to as "ohmic contact 330" and "ohmic contact 332", respectively.

Next, a first field plate 340 is formed on the dielectric layer 322. The process of forming the first field plate 340 includes forming a field plate metal layer and a patterned field plate metal layer on the dielectric layer 322. The field plate metal layer may be formed by a deposition process, such as an ALD process, a CVD process, or a PVD process. The patterning process includes performing one or more etching processes. The field plate 340 may be made of TiN, ti, al, alCu, cu or other suitable metal. The thickness of field plate 340 is in the range of about 100 angstroms to about 1200 angstroms. A field plate 340 is disposed adjacent to the doped GaN region 320 and extends toward the ohmic contact 332. The field plate 340 does not cover the doped GaN region 320. The field plate 340 may be electrically connected to one of the ohmic contacts, such as ohmic contact 330.

Next, another dielectric layer 350 is formed over the dielectric layer 322. The dielectric layer 350 also covers the field plate 340 and the ohmic contacts 330-332. Dielectric layer 350 may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, low-k dielectric material, or a combination thereof. Dielectric layer 350 may be formed by a deposition process, such as an ALD process, a CVD process, or a PVD process. The thickness of dielectric layer 350 is in the range of about 500 angstroms to about 5000 angstroms.

After forming dielectric layer 350, openings are formed through dielectric layers 322 and 350 to expose at least a portion of doped GaN region 320. The process of forming the openings includes forming a mask layer (e.g., a photoresist layer formed over the dielectric layer 350) and patterning the mask layer by a photolithographic process to form a plurality of features and at least one opening defined by the features on the dielectric layer 350. The pattern of the mask layer is formed according to a predetermined integrated circuit pattern, wherein the position of the opening of the mask layer is substantially the same as the position of the opening of the integrated circuit pattern. The photolithographic process may include photoresist coating, exposure, post exposure bake and development. Then, an etching process is performed to form an opening exposing the doped GaN region 320.

After forming the opening exposing the doped GaN region 320, a gate electrode (e.g., formed as a gate electrode metal stack) 334 is formed in the opening and connected to the doped GaN region 320. A gate electrode 334 is formed on the doped GaN region 320 between the source and drain electrodes (e.g., ohmic contact 330-ohmic contact 332). In some embodiments, gate electrode 334 includes a layer of conductive material, such as a metal layer that serves as a gate electrode configured for voltage biasing and electrical connection to the channel. The metal layer of gate electrode 334 includes Ti, mo, pt, cr, W, ni, al, alCu, alSiCu, cu or other suitable material. In some other embodiments, the gate electrode 334 may have a different composition. For example, gate electrode 334 includes one or more junction isolation features between the metal layer and doped GaN region 320. The junction isolation component, which may be configured as a diode, includes an n-doped semiconductor layer and an aluminum nitride (AlN) layer.

Next, another dielectric layer 360 is formed over the workpiece, e.g., covering dielectric layer 350 and gate electrode 334. Dielectric layer 360 may be configured as an etch stop layer. Dielectric layer 360 may be made of oxide, siN, or other suitable material. Dielectric layer 360 is deposited using a suitable vapor deposition process (e.g., CVD) or another method. Example silicon nitride (SiN) includes amorphous SiN, silicon nitride mono, and silicon nitride mono. In some embodiments, dielectric layer 360 is deposited to a thickness in the range of about 100 angstroms to about 1000 angstroms.

In some embodiments, a second field plate 370 is formed on the dielectric layer 360. The process of forming the second field plate 370 includes forming a field plate metal layer and a patterned field plate metal layer on the dielectric layer 362. The field plate metal layer may be formed by a deposition process, such as an ALD process, a CVD process, or a PVD process. The patterning process includes performing one or more etching processes. The field plate 370 may be made of TiN, ti, al, alCu, cu or other suitable metal. The thickness of field plate 370 is in the range of about 100 angstroms to about 1200 angstroms. A field plate 370 is disposed over portions of the gate electrode 334 and extends toward the ohmic contact 332. The field plate 370 may also be electrically connected to one of the ohmic contacts, such as ohmic contact 330.

The introduction of field plates 340/370 may accommodate the current collapse effect and may redistribute the electric field between gate electrode 334 and drain electrode 332. By forming field plates 340/370 between gate electrode 334 and drain electrode 332, the field strength maximum region is depleted toward drain electrode 332, reducing the peak of the electric field between gate electrode 334 and drain electrode 332, which can greatly improve (increase) the breakdown voltage of GaN-based device 300.

The power HEMT 300 may also include a plurality of metallization layers disposed over the aforementioned device components. For example, in fig. 3, the power HEMT 300 includes an interlayer dielectric (ILD) layer 380 deposited on the workpiece. ILD layer 380 may cover source electrode 330, drain electrode 332, gate electrode 334, and field plates 340 and 370.ILD layer 380 is made of a dielectric material. In some embodiments, ILD layer 380 is made of a low dielectric constant material, such as oxide, fluorinated quartz glass (FSG), siLK ^TM SiN or other suitable dielectric material. In some embodiments, an annealing process may be performed to improve the electrical insulation properties of ILD layer 380. In addition, ILD layer 380 may be doped, for example, with a carbon doped oxide or a boron/phosphorous doped oxide, to improve step coverage and annealing characteristics of ILD layer 390. The surface of ILD layer 380 is planarized. The process of planarizing ILD layer 380 includes performing a CMP process.

Above ILD layer 380, power HEMT 300 may further comprise a plurality of metallization layers (e.g., ml), each comprising a plurality of wires, e.g., 382, embedded in an inter-metal dielectric (IMD) layer 384. The wire 382 is made of Ti, mo, pt, cr, W, ni, al, alCu, alSiCu, cu or other suitable material. IMD layer 384 may be formed of a similar material as ILD layer 380. IMD layer 384 is used to isolate and support capacitor components, such as parallel conductive metal lines.

Referring again to the table shown above, the first and second conductive patterns of the disclosed test structure (104 of fig. 1-2) may simulate one or more conductive features of a corresponding GaN-based device (102 of fig. 1-2). Each combination of the conductive components simulated in the table will be described below by using the power HEMT 300 as a representative example of a simulated GaN-based device. It should be understood that the power HEMT 300 is provided as an illustrative example, and thus, the conductive components of the GaN-based devices simulated by the disclosed test structures may be otherwise configured while remaining within the scope of the present disclosure.

For example, the first and second conductive patterns may be formed simultaneously with the gate electrode (G) 334 and the first Field Plate (FP) 340, respectively, to infer whether a defect may exist somewhere between the gate electrode 334 and the first field plate 340. For example, the defect may be located in, on, or electrically connected to a portion of any one of the dielectric layer 322, the AlGaN layer 314, and the GaN layer 312 laterally between the gate electrode 334 and the first field plate 340. Such first and second conductive patterns may be formed in an alternately arranged structure. That is, the first conductive pattern formed simultaneously with the gate electrode 334 may have a plurality of protruding portions alternately arranged with the plurality of protruding portions of the second conductive pattern formed simultaneously with the first field plate 340. The lateral spacing between the different protrusions may be configured in the range of about 0.25 microns to about 6 microns. Thus, if a defect exists between the first and second conductive patterns, the defect can be detected if the defect size is not less than 0.25 μm. Further, the first and second conductive patterns (i.e., test structures 104) may occupy a relatively small area compared to the area occupied by the simulated GaN-based device 102, e.g., a ratio of from about 1% to about 10% in some embodiments.

In another example, the first and second conductive patterns may be formed simultaneously with the first Field Plate (FP) 340 and the second Field Plate (FP) 370, respectively, to infer whether a defect may exist somewhere between the first Field Plate (FP) 340 and the second Field Plate (FP) 370. For example, defects may be in, on, or connected to portions of dielectric layer 350/360 between first field plate 340 and second field plate 370. Such first and second conductive patterns may be formed in an alternately arranged structure. That is, the first conductive pattern formed simultaneously with the first field plate 340 may have a plurality of protruding portions alternately arranged with the plurality of protruding portions of the second conductive pattern formed simultaneously with the second field plate 370. The lateral spacing between the different protrusions may be configured in the range of about 0.25 microns to about 6 microns. Thus, if a defect exists between the first and second conductive patterns, the defect can be detected if the defect size is not less than 0.25 μm. Further, the first and second conductive patterns (i.e., test structures 104) may occupy a relatively small area compared to the area occupied by the simulated GaN-based device 102, e.g., a ratio of from about 1% to about 10% in some embodiments.

In yet another example, the first and second conductive patterns may be formed simultaneously with the Ohmic contacts (Ohmic) 330/332 and the first Field Plate (FP) 340, respectively, to infer whether a defect may exist somewhere between one of the Ohmic contacts 330 and 332 and the first field plate 340. For example, the defect may be located in, on, or connected to a portion of any one of the dielectric layer 322, the AlGaN layer 314, or the GaN layer 312 laterally interposed between the first field plate 340 and the ohmic contact 332. Such first and second conductive patterns may be formed in an alternately arranged structure. That is, the first conductive pattern formed simultaneously with the ohmic contact 332 may have a plurality of protruding portions alternately arranged with the plurality of protruding portions of the second conductive pattern formed simultaneously with the first field plate 340. The lateral spacing between the different protrusions may be configured in the range of about 0.25 microns to about 6 microns. Thus, if a defect exists between the first and second conductive patterns, the defect can be detected if the defect size is not less than 0.25 μm. Further, the first and second conductive patterns (i.e., test structures 104) may occupy a relatively small area compared to the area occupied by the simulated GaN-based device 102, e.g., a ratio of from about 1% to about 10% in some embodiments.

In yet another example, the first and second conductive patterns may be formed simultaneously with the Ohmic contacts (Ohmic) 330/332 and the GaN region (p-GaN) 320, respectively, to infer whether a defect may exist somewhere between one of the Ohmic contacts 330 and 332 and the doped GaN region 320. For example, the defect may be located in, on, or connected to a portion of any of the dielectric layer 322, alGaN layer 314, or GaN layer 312 laterally between the doped GaN region 320 and ohmic contact 330. Such first and second conductive patterns may be formed in an alternately arranged structure. That is, the first conductive pattern formed simultaneously with the ohmic contact 330 may have a plurality of protruding portions alternately arranged with the plurality of protruding portions of the second conductive pattern formed simultaneously with the doped GaN region 320. The lateral spacing between the different protrusions may be configured in the range of about 0.25 microns to about 6 microns. Thus, if a defect exists between the first and second conductive patterns, the defect can be detected if the defect size is not less than 0.25 μm. Further, the first and second conductive patterns (i.e., test structures 104) may occupy a relatively small area compared to the area occupied by the simulated GaN-based device 102, e.g., a ratio of from about 1% to about 10% in some embodiments.

In yet another example, the first and second conductive patterns may be formed simultaneously with the conductive lines (Ml) 382 and the Field Plates (FP) 340/370, respectively, to infer whether a defect may exist somewhere between one of the conductive lines 382 and the Field Plate (FP) 340/370. For example, defects may be in the portion of ILD layer 380 that is vertically between one of wires 382 and field plate 370. Such first and second conductive patterns may be formed in the MIM structure. That is, the first conductive pattern formed simultaneously with the conductive line 382 may have at least a portion vertically overlapping at least a portion of the second conductive pattern formed simultaneously with the field plate 370. Further, the first conductive pattern and the second conductive pattern (i.e., the test structure 104) may occupy a relatively small area compared to the area occupied by the simulated GaN-based device 102, e.g., a ratio of from about 1% to about 10% in some embodiments.

In yet another example, the first and second conductive patterns may be formed simultaneously with the first Field Plate (FP) 340 and the second Field Plate (FP) 370, respectively, to infer whether a defect may exist somewhere between the field plates 340 and 370, e.g., in the portion of the dielectric layer 350/360 vertically between the field plates 340 and 370. Such first and second conductive patterns may be formed in the MIM structure. That is, the first conductive pattern formed simultaneously with the first field plate 340 may have at least a portion vertically overlapped with at least a portion of the second conductive pattern formed simultaneously with the second field plate 370. Further, the first and second conductive patterns (i.e., test structures 104) may occupy a relatively small area compared to the area occupied by the simulated GaN-based device 102, e.g., a ratio of from about 1% to about 10% in some embodiments.

In yet another example, the first and second conductive patterns may be formed simultaneously with the ohmic contacts 330/332 and the Field Plate (FP) 370, respectively, to infer whether a defect may exist somewhere between one of the ohmic contacts 330/332 and the Field Plate (FP) 370. For example, defects may be in the portion of dielectric layer 350/360 laterally between field plate 370 and ohmic contact 332. Such first and second conductive patterns may be formed in the MIM structure. That is, the first conductive pattern formed simultaneously with the ohmic contacts 330/332 may have at least a portion vertically overlapping at least a portion of the second conductive pattern formed simultaneously with the field plate 370. Further, the first and second conductive patterns (i.e., test structures 104) may occupy a relatively small area compared to the area occupied by the simulated GaN-based device 102, e.g., a ratio of from about 1% to about 10% in some embodiments.

Although the first and second conductive patterns of the disclosed test structure (e.g., 104 of fig. 1) are formed simultaneously with the conductive features of the corresponding GaN-based device, it should be understood that the dimensions and contours of the first and second conductive patterns may be more flexibly configured. This is because the first and second conductive patterns are typically not configured as part of the active device of the entire GaN-based integrated circuit (e.g., 100 of fig. 1). Instead, the first and second conductive patterns are configured to mimic conductive features of an active device in a GaN-based integrated circuit (e.g., 102 of fig. 1) to infer whether the defect is located within, on, or connected to any layer of the active GaN-based device.

Fig. 4, 5, 6, 7, 8, and 9 illustrate various example arrangements 400, 500, 600, 700, 800, and 900, respectively, of first and second conductive patterns of the disclosed test structures according to various embodiments of the present disclosure. For example, the arrangements 400 to 600 of fig. 4 to 6 show the first and second conductive patterns formed in an alternating arrangement; and the arrangements 700 to 900 of figures 7-9 show the first and second conductive patterns formed as MIM structures.

In the arrangement 400 of fig. 4, the first conductive pattern includes a base 410 and a plurality of protrusions 412 extending away from the base 410, and the second conductive pattern includes a base 420 and a plurality of protrusions 422 extending away from the base 420. The furthest end of the protrusion 412 from the base 410 is spaced from the base 420 by a space "S0". Similarly, the furthest end of the projection 422 from the base 420 is spaced from the base 410 by a spacing "S0". Specifically, the protrusions 412 alternate with the protrusions 422. For example, one of the projections 412 (e.g., laterally) is interposed between a corresponding pair of projections 422 at a spacing "S1". In some embodiments, the spacing S0/S1 may be configured in a range of about 0.25 microns to about 6 microns. The arrangement 400 may further comprise connection pads (or test terminals) 430 and 440 connected to the first and second conductive patterns, respectively. The connection pads 430-440 may be electrically connected to corresponding probes of the test system to detect the presence of defects on the first conductive pattern and/or the second conductive pattern, as will be discussed in more detail below.

In the arrangement 500 of fig. 5, the first conductive pattern includes a base 510 and a plurality of protrusions 512 extending away from the base 510, and the second conductive pattern includes a base 520 and a plurality of protrusions 522 extending away from the base 520. The furthest end of the protrusion 512 from the base 510 is spaced from the base 520 by a space "S0". Similarly, the furthest end of the protrusion 522 from the base 520 is spaced from the base 510 by a spacing "S0". Specifically, the protrusions 512 alternate with the protrusions 522. For example, one of the projections 512 (e.g., laterally) is interposed between a corresponding pair of projections 522 at a spacing "S1". In some embodiments, the spacing S0/S1 may be configured in a range of about 0.25 microns to about 6 microns. The arrangement 500 may further comprise connection pads (or test terminals) 530 and 540 connected to the first and second conductive patterns, respectively. The connection pads 530-540 may be electrically connected to corresponding probes of the test system to detect the presence of defects on the first conductive pattern and/or the second conductive pattern, as will be discussed in further detail below.

In the arrangement 600 of fig. 6, the first conductive pattern includes a base 610 and a plurality of rounded portions 612A, 612B, and 612C connected to the base 610, and the second conductive pattern includes a base 620 and a plurality of rounded portions 622A, 622B, and 622C connected to the base 620. The circular portions 612A to 612C and 622A to 622C may form a plurality of concentric circles. Specifically, rounded portions 612A-612C alternate with rounded portions 622A-622C. For example, one of the rounded portions 612A-612C is interposed (e.g., laterally) between a pair of rounded portions of the corresponding rounded portion 622A-622C at a spacing "S1". In some embodiments, the spacing S1 may be configured in a range of about 0.25 microns to about 6 microns. The arrangement 600 may further comprise connection pads (or test terminals) 630 and 640 connected to the first and second conductive patterns, respectively. The connection pads 630-640 may be electrically connected to corresponding probes of the test system to detect the presence of defects on the first conductive pattern and/or the second conductive pattern, as will be discussed in further detail below.

In the arrangement 700 of fig. 7, the first conductive pattern comprises a base 710 and the second conductive pattern comprises a base 720, wherein the base 710 and the base 720 have at least some portions that overlap each other in the vertical direction. The base 710 and the base 720 may have similar dimensions (e.g., areas), and both may be formed as rectangles or squares. The base 710 and the base 720 may be laterally offset from each other to allow the connection pads 730 and the connection pads 740 to be connected thereto, respectively. In some embodiments, each of connection pads 730-740 may be implemented as a via structure. The connection pads 730-740 may be electrically connected to corresponding probes of the test system to detect the presence of defects on the first conductive pattern and/or the second conductive pattern, as will be discussed in more detail below.

In the arrangement 800 of fig. 8, the first conductive pattern comprises a base 810 and the second conductive pattern comprises a base 820, wherein the base 810 and the base 820 each have at least some portions overlapping each other in the vertical direction. The base 810 and the base 820 may each have different dimensions (e.g., areas), with the smaller base being surrounded by the larger base (when viewed from the top). Both the base 810 and the base 820 may be formed in a rectangular shape or a square shape. Arrangement 800 also includes connection pads 830 and 840 to connect to base 810 and base 820, respectively. In some embodiments, each of the connection pads 830-840 may be implemented as a via structure. The connection pads 830-840 may be electrically connected to corresponding probes of the test system to detect the presence of defects on the first conductive pattern and/or the second conductive pattern, as will be discussed in more detail below.

In the arrangement 900 of fig. 9, the first conductive pattern comprises a base 910 and the second conductive pattern comprises a base 920, wherein the base 910 and the base 920 each have at least some portions overlapping each other in the vertical direction. The base 910 and the base 920 may each have different dimensions (e.g., areas), with the smaller base being surrounded by the larger base (when viewed from the top). Both the base 910 and the base 920 may be formed in a circular shape. Arrangement 900 also includes connection pads 930 and 940 to connect to base 910 and base 920, respectively. In some embodiments, connection pads 930-940 may each be implemented as a via structure. Connection pads 930-940 may be electrically connected to corresponding probes of the test system to detect the presence of defects on the first conductive pattern and/or the second conductive pattern, as will be discussed in more detail below.

Fig. 10 illustrates a simplified block diagram of a test system 1000 that may detect various defects of a GaN-based device, in accordance with various embodiments. Such GaN-based devices to be tested may be fabricated simultaneously with one or more test structures. Thus, test system 1000 can detect the presence of defects in the test structure to infer whether defects are also present in the simulated GaN-based device. In one aspect, the test structure and GaN-based device may be formed as an integrated circuit on a single die. In another aspect, the test structure and the GaN-based device may not be formed on the same single die, wherein the test structure may be later removed from the integrated circuit with the GaN-based device (e.g., after the GaN-based device passes defect testing).

As shown, the test system 1000 includes at least a controller 1010 and a signal generator 1020 operably connected to each other. Although shown as a separate block, the signal generator 1020 may be integrated into the controller 1010 while remaining within the scope of the present disclosure. In various embodiments, controller 1010 may determine a number of test signals for GaN-based device 1050 to be tested placed on support 1060. For example, the test signal may include a positive voltage and a ground voltage applied to the first and second conductive patterns, respectively, that simulate the test structure of GaN-based device 1050. The voltage may be configured to be greater than 100 volts (e.g., about 650 volts) by the disclosed charge pump, as will be discussed below with respect to fig. 11-12. In configuring the test signals, signal generator 1020 may apply these test signals to GaN-based device 1050 to identify defects.

Test system 1000 may also include a probe card 1030 configured to support a plurality of probes 1040. In operation, probe card 1030 is moved until some of probes 1040 contact corresponding test structures of GaN-based device 1050. The movement is indicated by the vertical arrow in fig. 10. The wafer may be moved in the X and Y directions using an alignment device such as a microscope or a visual display device with magnification to place probes 1040 on, for example, one or more connection pads (test terminals) of the test structure described above. After probe 1040 is placed in electrical contact with the test terminal, a test signal as described above may be applied to the test structure (which may or may not be part of the final GaN-based device 1050) to identify the defect. Although not shown, the test system 1000 may include multiple (e.g., voltage and/or current) monitors to monitor the response of the test structure after those test signals are applied. The monitor may be in electrical contact with the test structure through the same or different terminals as the test terminals to which the test signals are applied.

Fig. 11 shows an example circuit diagram of a high voltage charge pump 1100 that may output voltages above 100 volts, and fig. 12 shows an example circuit diagram of a high voltage clock generator 1200, which high voltage clock generator 1200 may provide a clock signal (and its corresponding inverted clock signal) with a high voltage to the charge pump 1100, in accordance with various embodiments of the present invention.

Referring first to fig. 11, charge pump 1100 includes a plurality (e.g., 5) of GaN-based transistors 1102A, 1102B, 1102C, 1102D, and 1102E, a plurality (e.g., 4) of capacitors 1104A, 1104B, 1104C, and 1104D, and a load capacitor 1106. The charge pump 1100 may receive an input voltage Vi and pump or otherwise increase the voltage level of Vi as an output voltage Vo. Specifically, each of the GaN-based transistors 1102A-1102E may have its gate electrode and source electrode connected to each other (thereby functioning as a diode), and its drain electrode connected to a corresponding one of the capacitors 1104A-1104A1104D and the GaN-based transistor 1102A-1102E of the next stage. The other end of each capacitor 1104A-1104D is configured to receive a high voltage clock signal. In addition, adjacent capacitors (e.g., 1104A and 1104B) are configured to receive opposite high voltage clock signals, e.g., HV-CLK and HV-CLKB, respectively.

Thus, in the first clock cycle when HV-CLK is low and HV-CLKB is high, capacitor 1104A is connected to input voltage Vi (e.g., 100 volts) through diode-connected transistor 1102A, charging capacitor 1104A to the same voltage. Or, node X ₁ Charged to about 100 volts. In the second (next) clock cycle, in which HV-CLK is high and HV-CLKB is low, the circuit is reconfigured so that capacitor 1104A is connected in series with HV-CLK being high and capacitor 1104B of the next stage through diode-connected transistor 1102B. This causes node X to ₁ And node X ₂ Voltage at double-sum of original power supply (100 volts) and capacitor voltage (100 volts). Based on this principle, in the charge pump 1100 packageIn the case of five phases, the output voltage Vo may be increased to approximately 500 volts.

Referring next to fig. 12, a clock generator 1200 includes a pair of high voltage transistors (e.g., high voltage HEMTs) 1202 and 1204 connected between a supply voltage having a high voltage level (HVDD, e.g., about 100 volts) and ground (VSS). Further, the transistors 1202 and 1204 are connected to HVDD through resistors 1212 and 1214, respectively. The transistor 1202 is configured to be gated by a clock signal (CLK), while the transistor 1204 is configured to be gated by an inverse of the clock signal (CLKB). Thus, the transistors 1202 and 1204 can be alternately turned on/off. Thus, HV-CLK and HV-CLKB may be output at the drain electrodes of transistors 1202 and 1204, respectively.

Fig. 13 illustrates a cross-sectional view of a diode-connected transistor 1300 (e.g., 1102A-1102E) implemented in a charge pump 1100 (fig. 11). The diode-connected transistor 1300 includes a substrate 1310, a channel layer 1320 over the substrate 1310, and an active layer 1330 over the channel layer 1320. The channel layer 1320 and the active layer 1330 may be substantially similar to the GaN layer 312 and the AlGaN layer 314 (fig. 3), and thus a description will not be repeated. With such a GaN-based material, diode-connected transistor 1300 can operate at higher frequencies (when compared to Si-based transistors) because of its significantly lower parasitic capacitance. The diode-connected transistor 1300 also includes a source electrode 1340 and a drain electrode 1350 over the channel layer 1320, and a gate electrode 1360 over the active layer 1330. In some other embodiments, a source electrode 1340 and a drain electrode 1350 are formed over the active layer 1330. The source electrode 1340 and the gate electrode 1360 are shorted together, so that the source electrode 1340 and the gate electrode 1360 collectively function as a first terminal (e.g., anode) of the diode-connected transistor 1300 and the drain electrode 1350 functions as a second terminal (e.g., cathode) of the diode-connected transistor 1300.

Referring now to fig. 14, depicted is a flow diagram of an example method 1400 of identifying various defects of a GaN-based device through the disclosed test structures, in accordance with various embodiments. As disclosed herein, the test structure includes a first conductive pattern and a second conductive pattern that may respectively simulate conductive features of a GaN-based device. Defects in the GaN-based device may be identified by the test system inspecting one or more characteristics of the test structure. Thus, the following discussion of fig. 14 will incorporate some of the figures described above (e.g., power supply HMET300 of fig. 3, arrangements 400-900 of first and second conductive patterns shown in fig. 4-9, test system 1000 of fig. 10, charge pump 1100 of fig. 11, etc.). The illustrated embodiment of method 1400 is merely an example. Accordingly, it should be understood that any of a variety of operations may be omitted, reordered, and/or added while remaining within the scope of the present disclosure.

Method 1400 begins with operation 1402, i.e., forming one or more test structures that simulate a GaN-based device. Using the arrangement 400 of fig. 4 as an example, the first and second conductive patterns of the test structure may be formed with protruding portions 412 and 422 laterally staggered with respect to each other, wherein the first and second conductive patterns of the test structure simulate conductive components of a GaN-based device (e.g., simulate gate electrodes and field plates of a GaN-based device, different field plates of a GaN-based device, ohmic contacts and field plates of a GaN-based device, or ohmic contacts and doped GaN regions of a GaN-based device). Using the arrangement 700 of fig. 7 as another example, the first and second conductive patterns of the test structure may be formed with their corresponding portions 710 and 720 vertically overlapping each other, wherein the first and second conductive patterns of the test structure simulate conductive components of a GaN-based device (e.g., simulate gate electrodes and field plates of a GaN-based device, different field plates of a GaN-based device, ohmic contacts and field plates of a GaN-based device or ohmic contacts and doped GaN regions of a GaN-based device).

Next, the method 1400 proceeds to operation 1404 where a test signal is applied to the test structure. Continuing with the example of arrangement 400 (while also referring to test system 1000 of fig. 10), one probe 1040 may apply a positive voltage to the first conductive pattern (i.e., base 410 and protrusion 412) through connection pad 430, and another probe 1040 may apply a ground voltage to the second conductive pattern (i.e., base 420 and protrusion 422) through connection pad 440. The test system 1000 may monitor characteristics (e.g., IV curves) exhibited by the first and second conductive patterns. Continuing with the example of arrangement 700 (also referring to test system 1000 of fig. 10 and charge pump 1100 of fig. 11), one probe 1040 may apply a positive high voltage (e.g., about 500 volts) to a first conductive pattern (i.e., base 710) through connection pad 730, and another probe 1040 may apply a ground voltage to a second conductive pattern (i.e., base 720) through connection pad 740. The test system 1000 may monitor characteristics (e.g., IV curves) exhibited by the first and second conductive patterns.

Next, the method 1400 proceeds to operation 1406 to determine if any abnormal characteristics (or behaviors) are detected. If not, the method 1400 may proceed to operation 1408 to determine that the GaN-based device has passed the defect test. On the other hand, the method 1400 may proceed to operation 1410 and operation 1412 to further identify defects.

For example, when monitoring characteristics of the first and second conductive patterns configured in arrangement 400, test system 1000 may expect to detect an open circuit (or infinite resistance value) between the first and second conductive patterns because they are electrically isolated from each other. In some scenarios, the test system 1000 does detect an infinite resistance value between the first and second conductive patterns, so the test system 1000 may determine that the GaN-based device has passed the defect test (operation 1408). In other scenarios, the test system 1000 may detect a finite resistance value from which the test system 1000 may determine that an abnormal characteristic is detected. The test system 1000 may determine that such a connection path between the first and second conductive patterns is caused by a defect formed between the adjacent protruding portions 412 and 422 (operation 1410). Next, based on which conductive features of the GaN-based device are simulated by the first and second conductive patterns, the test system 1000 may identify defects that may exist between the simulated conductive features (operation 1412).

In another example, when monitoring the characteristics (behavior) of the first and second conductive patterns configured in arrangement 700, test system 1000 may expect to detect a sufficiently high breakdown voltage between the first and second conductive patterns, e.g., simulating a gate electrode and a field plate, respectively, of a GaN-based device. In some scenarios, the test system 1000 does detect such a high breakdown voltage between the first and second conductive patterns, so the test system 1000 may determine that the GaN-based device has passed the defect test (operation 1408). In other scenarios, the test system 1000 may detect a significantly lower breakdown voltage from which the test system 1000 may determine that an abnormal characteristic is detected. The test system 1000 may determine that this decrease in breakdown voltage is caused by a defect formed between the bases 710 and 720 (operation 1410). With the aid of the disclosed charge pump 1100, a high voltage (e.g., greater than 500 volts) may be applied to one of the first and second conductive patterns. Therefore, even if the defect is not in contact with either of the first and second conductive patterns, the reduced breakdown voltage can be detected. Next, based on which conductive features of the GaN-based device are simulated by the first and second conductive patterns, the test system 1000 may identify defects that may exist between the simulated conductive features (operation 1412).

Fig. 15 illustrates a flow diagram of an example method 1500 for fabricating one or more test structures concurrently with corresponding GaN-based devices, in accordance with various embodiments. For example, at least some operations (or steps) of method 1500 may be performed to fabricate, or otherwise form one or more test structures and GaN-based devices. It should be noted that the method 1500 is merely an example and is not intended to limit the present disclosure. Accordingly, it should be appreciated that additional operations may be provided before, during, and after the method 1500 of fig. 15, and that some other operations may only be briefly described herein. In some embodiments, the operation of method 1500 may be discussed in connection with some of the above figures (e.g., gaN-based integrated circuit 100 of fig. 1-2, power HMET 300 of fig. 3, arrangement 400-arrangement 900 of first and second conductive patterns shown in fig. 4-9, etc.).

The method 1500 begins with operation 1502 in which a first region and a second region are defined over a substrate. For example, a substrate (e.g., 310) may be provided. On the substrate 310, a first region and a second region may be defined to form a GaN-based device and its associated test structure, respectively. Taking fig. 1 as an example, gaN-based device 102 may be disposed on a first region of substrate 310 and test structure 104 may be disposed on a second region of substrate 310 surrounding the first region. In another example of fig. 2, gaN-based device 102 may be disposed on a first region of substrate 310 and test structure 104A-test structure 104P may be disposed on a second region of substrate 310 surrounding the first region.

Next, the method 1500 continues with operation 1504 where a plurality of layers are formed over both the first and second regions of the substrate, each layer having at least one of the GaN-based materials listed above. Using the power HEMT 300 (fig. 3) as a representative example, a GaN layer 312 and an AlGaN layer 314 are deposited sequentially on a substrate 310, covering the first and second regions. As described above, other one or more GaN-based layers may be formed over substrate 310. For example, a buffer layer defining a high resistivity layer for increasing breakdown voltage and a transition layer contributing to a gradual change in lattice structure and thermal expansion coefficient between the substrate 310 and the upper cladding layer may be formed between the GaN layer 312 and the substrate 310. In some embodiments, the buffer layer comprises one or more GaN-based materials (e.g., gaN, alGaN, inGaN, inAlGaN, etc.), and the transition layer comprises graded aluminum gallium nitride (Al _x Ga _(1-x) N)。

Next, the method 1500 continues to operation 1506, forming a plurality of conductive features for the GaN-based device over the first region, and forming a first conductive pattern and a second conductive pattern for the test structure over the second region. In some embodiments, the conductive features of the GaN-based device and the conductive patterns of the test structure may be formed simultaneously, but in respective first and second regions over the substrate. In this way, the conductive pattern of the test structure may simulate the conductive features of a GaN-based device. Further, although the conductive member may be formed to have a size and a profile that adapt the GaN-based device to a desired function, the conductive pattern of the test structure may be intentionally formed to have a different size and profile to enhance the sensitivity of the test structure in detecting defects.

For example, the first and second conductive patterns of the test structure may simulate the gate electrode (e.g., 334 of fig. 3) and the field plate (e.g., 340 of fig. 3), respectively, of their corresponding GaN-based devices. Although the gate electrode 334 and the field plate 340 may be laterally spaced apart from each other, the first and second conductive patterns may be formed in an alternating arrangement with their respective protruding portions laterally staggered from each other (e.g., the arrangement 400 of fig. 4).

For another example, the first and second conductive patterns of the test structure may simulate the wires (e.g., 382 of fig. 3) and the field plates (e.g., 370 of fig. 3), respectively, of their corresponding GaN-based devices. Although the conductive lines 382 and the field plates 370 may not vertically overlap each other or limited portions thereof overlap each other, the first and second conductive patterns may be formed in a MIM structure, most of which overlap each other (e.g., the arrangement 700 of fig. 7).

In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes the transistor including: a plurality of layers, wherein each of the plurality of layers has at least one group III-V compound material; a gate electrode operatively connected to at least one of the plurality of layers; a source electrode disposed on a first side of the gate electrode; a drain electrode disposed on a second side of the gate electrode; the field plate is arranged between the gate electrode and the drain electrode; and a plurality of wires disposed over the gate electrode, the source electrode and the drain electrode. The semiconductor device further includes a plurality of test structures, wherein each test structure includes a first metal pattern and a second metal pattern and simulates at least one of a gate electrode, a source electrode, a drain electrode, a field plate, and at least one of a plurality of conductive lines.

In some embodiments, the plurality of test structures are each disposed immediately adjacent to the transistor.

In some embodiments, the first metal pattern includes a first base and a plurality of first protrusions extending away from the first base, and the second metal pattern includes a second base and a plurality of second protrusions extending away from the second base.

In some embodiments, each of the plurality of first protrusions is disposed laterally between adjacent ones of the plurality of second protrusions at a pitch.

In some embodiments, the pitch is in the range of 0.25 micrometers (μm) to 6 micrometers.

In some embodiments, the first metal pattern comprises a first plate and the second metal pattern comprises a second plate, wherein at least a first portion of the first plate and at least a second portion of the second plate vertically overlap each other.

In some embodiments, the transistor occupies a first area on a substrate, and each of the plurality of test structures occupies a second area on the substrate, and a ratio of the second area to the first area is equal to or less than 10%.

In some embodiments, each of the test structures is configured to detect whether a defect is present in the transistor based on whether the corresponding first metal pattern and the corresponding second metal pattern form a short circuit.

In some embodiments, the semiconductor device further comprises: a charge pump connected to one of the corresponding first metal pattern and the corresponding second metal pattern of at least a first test structure of the test structures; wherein the charge pump is formed of at least one group III-V compound material and is configured to provide a voltage equal to or greater than 650 volts (V) to the connected first metal pattern or the connected second metal pattern.

In some embodiments, the first test structure is configured to detect whether a defect is present in the transistor based on whether an abnormal current-voltage curve associated with the first test structure is present.

In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a first semiconductor die including a plurality of first transistors, wherein each of the plurality of first transistors has at least one group III-V compound material. The semiconductor device includes a second semiconductor die including a plurality of second transistors, wherein each of the plurality of second transistors has at least one group III-V compound material. The semiconductor device includes a test structure disposed adjacent to the first semiconductor die and the second semiconductor die. The test structure includes a first metal pattern and a second metal pattern and is configured to simulate one or more components in each of the first semiconductor die and the second semiconductor die to determine whether a defect is present in at least one of the first semiconductor die or the second semiconductor die.

In some embodiments, each of the plurality of first protrusions is disposed laterally at a pitch between adjacent second protrusions of the plurality of second protrusions.

In some embodiments, the first metal pattern comprises a first plate and the second metal pattern comprises a second plate, and at least a first portion of the first plate and at least a second portion of the second plate vertically overlap each other.

In some embodiments, the first metal pattern and the second metal pattern simulate respectively: a gate electrode of the first semiconductor die or a gate electrode of the second semiconductor die; or a field plate of the first semiconductor die or a field plate of the second semiconductor die.

In some embodiments, the first metal pattern and the second metal pattern simulate respectively: a gate electrode of the first semiconductor die or a gate electrode of the second semiconductor die, a field plate of the first semiconductor die or a field plate of the second semiconductor die; a source/drain electrode of the first semiconductor die or a source/drain electrode of the second semiconductor die, a field plate of the first semiconductor die or a field plate of the second semiconductor die; a gate electrode of the first semiconductor die or a gate electrode of the second semiconductor die or a source/drain electrode of the first semiconductor die or a source/drain electrode of the second semiconductor die; or a wire and a field plate of the first semiconductor die or the second semiconductor die.

In yet another aspect of the present disclosure, a method for testing a semiconductor device is disclosed. The method includes forming a transistor including a plurality of layers, wherein each of the plurality of layers has at least one group III-V compound material. The method includes forming a test structure including a first metal pattern and a second metal pattern, wherein the test structure is configured to simulate one or more components of a transistor. The method includes detecting whether there is abnormal behavior in a current-voltage curve associated with the test structure. The method includes determining that the transistor has a defect in response to detecting the presence of the abnormal behavior.

In some embodiments, the first metal pattern includes a first base and a plurality of first protrusions extending away from the first base, and the second metal pattern includes a second base and a plurality of second protrusions extending away from the second base, each of the plurality of first protrusions being laterally disposed between adjacent ones of the plurality of second protrusions at a pitch in a range of 0.25 micrometers (μm) to 0.6 micrometers.

In some embodiments, the first metal pattern comprises a first plate and the second metal pattern comprises a second plate, and at least a first portion of the first plate and at least a second portion of the second plate are vertically overlapping one another.

As used herein, the terms "about" and "approximately" generally mean plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising:

a transistor, comprising:

a plurality of layers, wherein each of the plurality of layers has at least one group III-V compound material;

a gate electrode operatively connected to at least one of the plurality of layers;

a source electrode disposed on a first side of the gate electrode;

a drain electrode disposed on a second side of the gate electrode;

A field plate disposed between the gate electrode and the drain electrode; and

a plurality of wires disposed over the gate electrode, the source electrode, and the drain electrode; and

a plurality of test structures, wherein each test structure including a first metal pattern and a second metal pattern simulates at least one of the gate electrode, the source electrode, the drain electrode, the field plate, and at least one of the plurality of conductive lines.

2. The semiconductor device of claim 1, wherein the plurality of test structures are each disposed immediately adjacent to the transistor.

3. The semiconductor device of claim 1, wherein the first metal pattern comprises a first base and a plurality of first protrusions extending away from the first base, and the second metal pattern comprises a second base and a plurality of second protrusions extending away from the second base.

4. The semiconductor device according to claim 3, wherein each of the plurality of first protrusions is disposed laterally between adjacent ones of the plurality of second protrusions at a pitch.

5. The semiconductor device of claim 4, wherein the pitch is in a range of 0.25 micrometers (μm) to 6 μm.

6. A semiconductor device, comprising:

a first semiconductor die, comprising:

a plurality of first transistors, wherein each of the plurality of first transistors has at least one group III-V compound material;

a second semiconductor die comprising:

a plurality of second transistors, wherein each of the plurality of second transistors has at least one group III-V compound material; and

a test structure disposed beside the first semiconductor die and the second semiconductor die;

wherein the test structure includes a first metal pattern and a second metal pattern and is configured to simulate one or more components in each of the first semiconductor die and the second semiconductor die to determine whether a defect is present in at least one of the first semiconductor die and the second semiconductor die.

7. The semiconductor device of claim 6, wherein the first metal pattern comprises a first base and a plurality of first protrusions extending away from the first base, and the second metal pattern comprises a second base and a plurality of second protrusions extending away from the second base.

8. A method for testing a semiconductor device, comprising:

Forming a transistor comprising a plurality of layers, wherein each of the plurality of layers has at least one group III-V compound material;

forming a test structure comprising a first metal pattern and a second metal pattern, wherein the test structure is configured to simulate one or more components of the transistor;

detecting whether abnormal behavior exists in a current-voltage curve related to the test structure; and

in response to detecting the presence of the abnormal behavior, determining that the transistor is defective.

9. The method of claim 8, wherein the first metal pattern comprises a first base and a plurality of first protrusions extending away from the first base, and the second metal pattern comprises a second base and a plurality of second protrusions extending away from the second base, each of the plurality of first protrusions being laterally disposed between adjacent ones of the plurality of second protrusions at a pitch in a range of 0.25 micrometers (μιη) to 0.6 micrometers.

10. The method of claim 8, wherein the first metal pattern comprises a first plate and the second metal pattern comprises a second plate, and at least a first portion of the first plate and at least a second portion of the second plate are vertically overlapping one another.