CN116679186A - Multi-chip calibration system and method - Google Patents

Multi-chip calibration system and method Download PDF

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Publication number
CN116679186A
CN116679186A CN202310471926.8A CN202310471926A CN116679186A CN 116679186 A CN116679186 A CN 116679186A CN 202310471926 A CN202310471926 A CN 202310471926A CN 116679186 A CN116679186 A CN 116679186A
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calibration
chip
port
signal
send
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CN116679186B (en
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薄会健
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Shenzhen Gaobo Technology Co ltd
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Shenzhen Gaobo Technology Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The application discloses a multi-chip calibration system and a multi-chip calibration method, wherein the multi-chip calibration system comprises an electronic device and a calibration device, the electronic device is connected with a plurality of ALPGs, each ALPG in the plurality of ALPGs is connected with at least one group of chips, each group of chips comprises a first chip, a second chip, a third chip and a fourth chip, the calibration device is connected with the first chip, the second chip, the third chip and the fourth chip, and the calibration device comprises a first calibration device and a second calibration device.

Description

Multi-chip calibration system and method
Technical Field
The present application relates to the field of chip testing technologies, and in particular, to a system and a method for calibrating multiple chips.
Background
Automated test equipment (Automatic Test Equipment, ATE) is a system for automated testing of integrated circuits by means of computers and specialized equipment. In the field of semiconductor chip testing, because the number of pins of a tested chip is large, a plurality of chips in the testing equipment are matched cooperatively to finish the testing.
In the prior art, a single chip scheme is generally adopted for testing, so that the cost is high and the power consumption is high, and therefore, a system for synchronizing a plurality of chips is needed to complete the testing of the tested chip.
Disclosure of Invention
The invention mainly aims to provide a multi-chip calibration system and a multi-chip calibration method, and aims to solve the technical problems that in the prior art, a single chip scheme is adopted for testing, the cost is high, the power consumption is high, and a system for synchronizing a plurality of chips is needed to complete the test of a tested chip.
To achieve the above object, a first aspect of the present invention provides a multi-chip calibration system including an electronic device connected to a plurality of ALPGs, each of the plurality of ALPGs being connected to at least one set of chips, each set of chips including a first chip, a second chip, a third chip, and a fourth chip, and a calibration device connected to the first chip, the second chip, the third chip, and the fourth chip, the calibration device including a first calibration device and a second calibration device, wherein: the electronic device is configured to send a first control signal to a first ALPG, where the first control signal is used for the first ALPG to send a first calibration signal to the third chip, the first calibration signal is used for the third chip to send the first calibration signal to the first calibration device through a first IO port, the first ALPG is any one of the plurality of ALPGs, and the first IO port is any one of a plurality of IO ports of the third chip; the first calibration device is configured to send the first calibration signal to the second chip through a second IO port, where the second IO port is any one of a plurality of IO ports of the second chip; the electronic device is further configured to determine a first transmission time according to a time when the first IO port transmits the first calibration signal and a time when the second IO port receives the first calibration signal; the electronic device is further configured to send a second control signal to a first ALPG, where the second control signal is used for sending a second calibration signal to the third chip by the first ALPG, the second calibration signal is used for sending the second calibration signal to the first calibration device by the third chip through a third IO port, and the third IO port is an IO port adjacent to the first IO port among a plurality of IO ports of the third chip; the first calibration device is further configured to send the second calibration signal to the first chip through a fourth IO port, where the fourth IO port is any one of a plurality of IO ports of the first chip; the electronic device is further configured to determine a second transmission time according to a time when the third IO port transmits the first calibration signal and a time when the fourth IO port receives the first calibration signal; the electronic device is further configured to determine a first delay of the first chip and the second chip according to the first transmission time and the second transmission time; the electronic device is further configured to send a third control signal to the first ALPG, where the third control signal is used for the first ALPG to send a third calibration signal to the second chip, and the third calibration signal is used for the second chip to send the third calibration signal to the second calibration device through the second IO port; the second calibration device is further configured to send the third calibration signal to the first chip through the fourth IO port; the electronic device is further configured to determine a third transmission time according to a time when the second IO port sends the third calibration signal and a time when the fourth IO port receives the third calibration signal; the electronic device is further configured to send a fourth control signal to the first ALPG, where the fourth control signal is used for sending a fourth calibration signal to the second chip by the first ALPG, and the fourth calibration signal is used for sending the fourth calibration signal to the second calibration device by the second chip through a fifth IO port, where the fifth IO port is an IO port adjacent to the second IO port among the plurality of IO ports of the second chip; the second calibration device is further configured to send the fourth calibration signal to the third chip through the first IO port; the electronic device is further configured to determine a fourth transmission time according to a time when the fifth IO port transmits the fourth calibration signal and a time when the first IO port receives the fourth calibration signal; the electronic device is further configured to determine a second delay of the first chip and the third chip according to the third transmission time and the fourth transmission time; the electronic device is further configured to send a fifth control signal to the first ALPG, where the fifth control signal is used for the first ALPG to send a fifth calibration signal to the third chip, and the fifth calibration signal is used for the third chip to send the fifth calibration signal to the second calibration device through the first IO port; the second calibration device is further configured to send the fifth calibration signal to the second chip through the second IO port; the electronic device is further configured to determine a fifth transmission time according to a time when the first IO port transmits the fifth calibration signal and a time when the second IO port receives the fifth calibration signal; the electronic device is further configured to send a sixth control signal to the first ALPG, where the sixth control signal is used for the first ALPG to send a sixth calibration signal to the third chip, and the sixth calibration signal is used for the third chip to send the sixth calibration signal to the second calibration device through the third IO port; the second calibration device is further configured to send the sixth calibration signal to the fourth chip through a sixth IO port, where the sixth IO port is any one of a plurality of IO ports of the fourth chip; the electronic device is further configured to determine a sixth transmission time according to a time when the third IO port transmits the sixth calibration signal and a time when the sixth IO port receives the sixth calibration signal; the electronic device is further configured to determine a third delay of the second chip and the fourth chip according to the fifth transmission time and the sixth transmission time; the electronic device is further configured to determine a first calibration delay based on the first delay, the second delay, and the third delay; the electronic device is further configured to calibrate the first chip, the second chip, the third chip, and the fourth chip according to the first calibration delay.
A second aspect of an embodiment of the present application provides a multi-chip calibration method, the method being applied to a multi-chip calibration system including an electronic device and a calibration device, the electronic device being connected to a plurality of ALPGs, each ALPG of the plurality of ALPGs being connected to at least one set of chips, each set of chips including a first chip, a second chip, a third chip, and a fourth chip, the calibration device being connected to the first chip, the second chip, the third chip, and the fourth chip, the calibration device including a first calibration device and a second calibration device, wherein: the electronic device sends a first control signal to a first ALPG, wherein the first control signal is used for sending a first calibration signal to the third chip by the first ALPG, the first calibration signal is used for sending the first calibration signal to the first calibration device by the third chip through a first IO port, the first ALPG is any one of the ALPGs, and the first IO port is any one of the IO ports of the third chip; the first calibration device sends the first calibration signal to the second chip through a second IO port, wherein the second IO port is any one of a plurality of IO ports of the second chip; the electronic equipment determines a first transmission time according to the time when the first IO port transmits the first calibration signal and the time when the second IO port receives the first calibration signal; the electronic device sends a second control signal to a first ALPG, the second control signal is used for sending a second calibration signal to the third chip by the first ALPG, the second calibration signal is used for sending the second calibration signal to the first calibration device by the third chip through a third IO port, and the third IO port is an IO port adjacent to the first IO port in a plurality of IO ports of the third chip; the first calibration device sends the second calibration signal to the first chip through a fourth IO port, wherein the fourth IO port is any IO port in a plurality of IO ports of the first chip; the electronic equipment determines a second transmission time according to the time when the third IO port transmits the first calibration signal and the time when the fourth IO port receives the first calibration signal; the electronic device determines a first delay of the first chip and the second chip according to the first transmission time and the second transmission time; the electronic device sends a third control signal to the first ALPG, wherein the third control signal is used for sending a third calibration signal to the second chip by the first ALPG, and the third calibration signal is used for sending the third calibration signal to the second calibration device by the second chip through the second IO port; the second calibration device sends the third calibration signal to the first chip through the fourth IO port; the electronic equipment determines a third transmission time according to the time when the second IO port transmits the third calibration signal and the time when the fourth IO port receives the third calibration signal; the electronic device sends a fourth control signal to the first ALPG, wherein the fourth control signal is used for sending a fourth calibration signal to the second chip by the first ALPG, the fourth calibration signal is used for sending the fourth calibration signal to the second calibration device by the second chip through a fifth IO port, and the fifth IO port is an IO port adjacent to the second IO port in a plurality of IO ports of the second chip; the second calibration device sends the fourth calibration signal to the third chip through the first IO port; the electronic equipment determines a fourth transmission time according to the time when the fifth IO port transmits the fourth calibration signal and the time when the first IO port receives the fourth calibration signal; the electronic device determines second delays of the first chip and the third chip according to the third transmission time and the fourth transmission time; the electronic device sends a fifth control signal to the first ALPG, wherein the fifth control signal is used for sending a fifth calibration signal to the third chip by the first ALPG, and the fifth calibration signal is used for sending the fifth calibration signal to the second calibration device by the third chip through the first IO port; the second calibration device sends the fifth calibration signal to the second chip through the second IO port; the electronic equipment determines a fifth transmission time according to the time when the first IO port transmits the fifth calibration signal and the time when the second IO port receives the fifth calibration signal; the electronic device sends a sixth control signal to the first ALPG, wherein the sixth control signal is used for sending a sixth calibration signal to the third chip by the first ALPG, and the sixth calibration signal is used for sending the sixth calibration signal to the second calibration device by the third chip through the third IO port; the second calibration device sends the sixth calibration signal to the fourth chip through a sixth IO port, wherein the sixth IO port is any IO port in a plurality of IO ports of the fourth chip; the electronic equipment determines a sixth transmission time according to the time when the third IO port transmits the sixth calibration signal and the time when the sixth IO port receives the sixth calibration signal; the electronic equipment determines third delays of the second chip and the fourth chip according to the fifth transmission time and the sixth transmission time; the electronic device determining a first calibration delay from the first delay, the second delay, and the third delay; the electronic device calibrates the first chip, the second chip, the third chip, and the fourth chip according to the first calibration delay.
As can be seen from the above, the present application provides a multi-chip calibration system, including an electronic device and a calibration device, where the electronic device is connected to a plurality of ALPGs, each ALPG in the plurality of ALPGs is connected to at least one group of chips, each group of chips includes a first chip, a second chip, a third chip and a fourth chip, and the calibration device is connected to the first chip, the second chip, the third chip and the fourth chip, and includes a first calibration device and a second calibration device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an embodiment of a multi-chip calibration system according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an embodiment of another multi-chip calibration system according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an embodiment of a third multi-chip calibration system according to an embodiment of the present application;
FIG. 4 is a schematic diagram of an embodiment of a fourth multi-chip calibration system according to an embodiment of the present application;
FIG. 5 is a schematic diagram of an embodiment of a single chip calibration system according to an embodiment of the present application;
FIG. 6 is a schematic diagram of an embodiment of a chip pin according to an embodiment of the present application;
FIG. 7 is a schematic diagram of another embodiment of a chip pin according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of another embodiment of a single-chip calibration system according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in this specification and the appended claims, the term "if" may be interpreted in context as "when …" or "upon" or "in response to a determination" or "in response to detection. Similarly, the phrase "if a condition or event described is determined" or "if a condition or event described is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a condition or event described" or "in response to detection of a condition or event described".
The following description of the embodiments of the present invention will be made more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown, it being evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways other than those described herein, and persons skilled in the art will readily appreciate that the present invention is not limited to the specific embodiments disclosed below.
To solve the problems of the prior art, an embodiment of the present invention provides a multi-chip calibration system, as shown in fig. 1, including an electronic device and a calibration device, the electronic device being connected to a plurality of algorithm pattern generators (Algorithmic Pattern Generator, ALPGs), each ALPG of the plurality of ALPGs being connected to at least one set of chips, each set of chips including a first chip, a second chip, a third chip and a fourth chip, the calibration device being connected to the first chip, the second chip, the third chip and the fourth chip, the calibration device including a first calibration device and a second calibration device, wherein: the electronic device is configured to send a first control signal to a first ALPG, where the first control signal is used for the first ALPG to send a first calibration signal to the third chip, the first calibration signal is used for the third chip to send the first calibration signal to the first calibration device through a first IO port, the first ALPG is any one of the plurality of ALPGs, and the first IO port is any one of a plurality of IO ports of the third chip; the first calibration device is configured to send the first calibration signal to the second chip through a second IO port, where the second IO port is any one of a plurality of IO ports of the second chip; the electronic device is further configured to determine a first transmission time according to a time when the first IO port transmits the first calibration signal and a time when the second IO port receives the first calibration signal; the electronic device is further configured to send a second control signal to a first ALPG, where the second control signal is used for sending a second calibration signal to the third chip by the first ALPG, the second calibration signal is used for sending the second calibration signal to the first calibration device by the third chip through a third IO port, and the third IO port is an IO port adjacent to the first IO port among a plurality of IO ports of the third chip; the first calibration device is further configured to send the second calibration signal to the first chip through a fourth IO port, where the fourth IO port is any one of a plurality of IO ports of the first chip; the electronic device is further configured to determine a second transmission time according to a time when the third IO port transmits the first calibration signal and a time when the fourth IO port receives the first calibration signal; the electronic device is further configured to determine a first delay of the first chip and the second chip according to the first transmission time and the second transmission time; the electronic device is further configured to send a third control signal to the first ALPG, where the third control signal is used for the first ALPG to send a third calibration signal to the second chip, and the third calibration signal is used for the second chip to send the third calibration signal to the second calibration device through the second IO port; the second calibration device is further configured to send the third calibration signal to the first chip through the fourth IO port; the electronic device is further configured to determine a third transmission time according to a time when the second IO port sends the third calibration signal and a time when the fourth IO port receives the third calibration signal; the electronic device is further configured to send a fourth control signal to the first ALPG, where the fourth control signal is used for sending a fourth calibration signal to the second chip by the first ALPG, and the fourth calibration signal is used for sending the fourth calibration signal to the second calibration device by the second chip through a fifth IO port, where the fifth IO port is an IO port adjacent to the second IO port among the plurality of IO ports of the second chip; the second calibration device is further configured to send the fourth calibration signal to the third chip through the first IO port; the electronic device is further configured to determine a fourth transmission time according to a time when the fifth IO port transmits the fourth calibration signal and a time when the first IO port receives the fourth calibration signal; the electronic device is further configured to determine a second delay of the first chip and the third chip according to the third transmission time and the fourth transmission time; the electronic device is further configured to send a fifth control signal to the first ALPG, where the fifth control signal is used for the first ALPG to send a fifth calibration signal to the third chip, and the fifth calibration signal is used for the third chip to send the fifth calibration signal to the second calibration device through the first IO port; the second calibration device is further configured to send the fifth calibration signal to the second chip through the second IO port; the electronic device is further configured to determine a fifth transmission time according to a time when the first IO port transmits the fifth calibration signal and a time when the second IO port receives the fifth calibration signal; the electronic device is further configured to send a sixth control signal to the first ALPG, where the sixth control signal is used for the first ALPG to send a sixth calibration signal to the third chip, and the sixth calibration signal is used for the third chip to send the sixth calibration signal to the second calibration device through the third IO port; the second calibration device is further configured to send the sixth calibration signal to the fourth chip through a sixth IO port, where the sixth IO port is any one of a plurality of IO ports of the fourth chip; the electronic device is further configured to determine a sixth transmission time according to a time when the third IO port transmits the sixth calibration signal and a time when the sixth IO port receives the sixth calibration signal; the electronic device is further configured to determine a third delay of the second chip and the fourth chip according to the fifth transmission time and the sixth transmission time; the electronic device is further configured to determine a first calibration delay based on the first delay, the second delay, and the third delay; the electronic device is further configured to calibrate the first chip, the second chip, the third chip, and the fourth chip according to the first calibration delay.
The first calibration delay is the largest delay among the first delay, the second delay, and the third delay.
It should be further noted that, in order to avoid errors caused by different pins as much as possible, when the first chip, the second chip, the third chip and the fourth chip receive the calibration signals, the pins at the same position of each chip are selected to receive the calibration signals, for example, when the second chip receives the first calibration signals and the first chip receives the second calibration signals, the IO ports at the same position of the second chip and the first chip are selected to receive the calibration signals.
For example, as shown in fig. 2, the ALPG sends a first calibration signal to the chip C, the calibration signal is sent to TYPE-a through the pin C38 of the chip C, the TYPE-a sends the first calibration signal to the chip B through the pin B39 of the chip B, and the transmission time of the first calibration signal sent by the C38 and the first calibration signal received by the B39 can be obtained; ALPG sends a second calibration signal to chip C, the calibration signal sends the second calibration signal to TYPE-A through pin C39 of chip C, TYPE-A sends the second calibration signal to chip A through pin A39 of chip A, and the transmission time of C39 for sending the second calibration signal and A39 for receiving the first calibration signal can be obtained; because C38 and C39 are two similar pins on the same chip, the default delay is the same, and the delay between A39 and B39, namely the first delay of the chip and the chip B, is obtained; in order to improve the detection accuracy, avoid too many interfaces of the same pin, a second calibration board, namely TYPE-B in FIG. 2, is introduced, according to the above principle, the second delay of the chip A and the chip C is obtained through the signal delay between the A39 and the C38, the third delay of the chip B and the chip D is obtained through the signal delay between the B39 and the D38, the delay relation among the chip A, the chip B, the chip C and the chip D is obtained, the maximum delay is determined, and the calibration of the chip under ALPG is completed according to the maximum delay.
In some embodiments, the electronic device connection connects a plurality of control boards, each control board connecting at least one set of ALPGs, each set of ALPGs including a second ALPG, a third ALPG, and a fourth ALPG, wherein: the electronic device is further configured to send a seventh calibration signal to a fourth ALPG, where the seventh calibration signal is used for the fourth ALPG to send the seventh calibration signal to the first calibration device through a fifth chip, where the fifth chip is any chip in each group of chips; the first calibration device is further configured to send the seventh calibration signal to the second ALPG through the fifth chip; the electronic device is further configured to determine a seventh transmission time according to a time when the fourth ALPG transmits the seventh calibration signal and a time when the second ALPG receives the seventh calibration signal; the electronic device is further configured to send an eighth calibration signal to a fourth ALPG, where the eighth calibration signal is used for the fourth ALPG to send the eighth calibration signal to the first calibration device through the fifth chip; the first calibration device is further configured to send the eighth calibration signal to the third ALPG through the fifth chip; the electronic device is further configured to determine an eighth transmission time according to a time when the fourth ALPG transmits the eighth calibration signal and a time when the third ALPG receives the eighth calibration signal; the electronic device is further configured to determine a fourth delay of the second and third ALPGs according to the seventh and eighth transmission times; the electronic device is further configured to send a ninth calibration signal to a second ALPG, where the ninth calibration signal is used for the second ALPG to send the ninth calibration signal to the first calibration device through the fifth chip; the first calibration device is further configured to send the ninth calibration signal to the third ALPG through the fifth chip; the electronic device is further configured to determine a ninth transmission time according to a time when the second ALPG transmits the ninth calibration signal and a time when the third ALPG receives the ninth calibration signal; the electronic device is further configured to send a tenth calibration signal to a second ALPG, where the tenth calibration signal is used for the second ALPG to send the tenth calibration signal to the first calibration device through a fifth chip; the first calibration device is further configured to send the tenth calibration signal to the fourth ALPG through the fifth chip; the electronic device is further configured to determine a tenth transmission time according to a time when the tenth calibration signal is transmitted by the second ALPG and a time when the tenth calibration signal is received by the fourth ALPG; the electronic device is further configured to determine a fifth delay of the third and fourth ALPGs according to the ninth and tenth transmission times; the electronic device is further configured to determine a second calibration delay according to the fourth delay and the fifth delay; the electronic device is further configured to calibrate the second, third, and fourth ALPGs according to the second calibration delay.
For example, as shown in fig. 3, the transmission time of the alpg_2 transmitting the calibration signal to TYPE-a through the chip D and the TYPE-a transmitting the calibration signal to the alpg_0 through the chip D may be obtained as well as the transmission time of the alpg_0 receiving the calibration signal; ALPG_2 transmits a calibration signal to TYPE-A through chip D, TYPE-A transmits a calibration signal to ALPG_1 through chip D, so that the transmission time of the calibration signal transmitted by ALPG_2 and the transmission time of the calibration signal received by ALPG_1 can be obtained, the relationship between ALPG_0 and ALPG_1 can be further obtained, and similarly, the relationship between ALPG_1 and ALPG_2 can be obtained, and finally the relationship between ALPG_0, ALPG_1 and ALPG_2 can be obtained.
In some embodiments, the electronic device is connected to a plurality of synchronization boards, each synchronization board is connected to at least one set of control boards, each set of control boards including a first control board, a second control board, a third control board, and a fourth control board, wherein: the electronic device is further configured to send a first synchronization signal to the first control board, where the first synchronization signal is used for the first control board to send the first synchronization signal to the first calibration device; the first calibration device is further configured to send the first synchronization signal to the third control board; the electronic device is further configured to determine a first synchronization time of the first control board and the third control board according to a time when the first control board transmits the first synchronization signal and a time when the third control board receives the first synchronization signal; the electronic device is further configured to send a second synchronization signal to the second control board, where the second synchronization signal is used for the second control board to send the second synchronization signal to the first calibration device; the first calibration device is further configured to send the second synchronization signal to the fourth control board; the electronic device is further configured to determine a second synchronization time of the second control board and the fourth control board according to a time when the fourth control board transmits the second synchronization signal and a time when the fourth control board receives the second synchronization signal; the electronic device is further configured to send a third synchronization signal to the first control board, where the third synchronization signal is used for the first control board to send the third synchronization signal to the second calibration device; the second calibration device is further configured to send the third synchronization signal to the second control board; the electronic device is further configured to determine a third synchronization time of the first control board and the second control board according to a time when the first control board transmits the third synchronization signal and a time when the second control board receives the third synchronization signal; the electronic device is further configured to determine a synchronization delay according to the first synchronization time, the second synchronization time, and the third synchronization time; the electronic device is further configured to calibrate the first control board, the second control board, the third control board, and the fourth control board according to the synchronization delay.
For example, as shown in FIG. 4, when the control board is connected with TYPE-A, the synchronization time of A0 and A2, the synchronization time of A1 and A3 is obtained; when the control board is connected with TYPE-B, the synchronous time of A0 and A1 is obtained, so that the synchronous time of A0, A1, A2 and A3 is obtained, the largest synchronous time is determined to be synchronous delay, and the first control board, the second control board, the third control board and the fourth control board are calibrated according to the synchronous delay, and A4, A5, A6 and A7 are the same.
In some embodiments, the chip includes a plurality of IO ports, a plurality of groups of IO ports are included in the plurality of IO ports, an nth group of IO ports among the plurality of groups of IO ports includes an nth-1 th IO port, an nth IO port, an 2n+1th IO port, and an 2n+2nd IO port, n is a positive integer, and the 2n-1 th IO port, the 2n+1th IO port, and the 2n+2nd IO port are adjacent to each other, wherein: the electronic device is configured to send a first control instruction to the first ALPG, where the first control instruction is used for the first ALPG to send a first calibration instruction to the chip, and the first calibration instruction is used for the chip to send the first calibration instruction to the first calibration device through a 2n-1 th IO port; the first calibration device is configured to send the first calibration instruction to the chip through the 2nth IO port; the electronic device is further configured to send a second control instruction to the ALPG, where the second control instruction is used for the ALPG to send a second calibration instruction to the chip, and the second calibration instruction is used for the chip to send the second calibration instruction to the first calibration device through 2n+2nd IO ports; the first calibration device is further configured to send the second calibration instruction to the chip through the 2n+1st IO port; the electronic device is further configured to determine a first calibration time of the 2n-1 th IO port and the 2n+2 th IO port when delays of the 2n-1 th IO port and the 2n+1 th IO port are the same; the electronic device is further configured to send a third control instruction to the ALPG, where the third control instruction is used for the ALPG to send a third calibration instruction to the chip, where the third calibration instruction is used for the chip to send the third calibration instruction to the first calibration device through 2n+3rd IO ports, where the 2n+3rd IO ports are adjacent to the 2n+2nd IO ports; the first calibration device is further configured to send the third calibration instruction to the chip through the 2nth IO port; the electronic device is further configured to send a fourth control instruction to the ALPG, where the fourth control instruction is used for the ALPG to send a fourth calibration instruction to the chip, and the fourth calibration instruction is used for the chip to send the fourth calibration instruction to the first calibration device through 2n+2nd IO ports; the first calibration device is further configured to send the fourth calibration instruction to the chip through the 2n+1st IO port; the electronic device is further configured to determine a second calibration time of the 2n+2nd IO port and the 2n+1th IO port when the 2n+2nd IO port and the 2n+3rd IO port have the same delay; the electronic device is further configured to send a fifth control instruction to the ALPG, where the fifth control instruction is used for the ALPG to send a fifth calibration instruction to the chip, and the fifth calibration instruction is used for the chip to send the fifth calibration instruction to the second calibration device through the 2 n-th IO port; the second calibration device is configured to send the fifth calibration instruction to the chip through the 2n+1st IO port; the electronic device is further configured to send a sixth control instruction to the ALPG, where the sixth control instruction is used for the ALPG to send a sixth calibration instruction to the chip, and the sixth calibration instruction is used for the chip to send the sixth calibration instruction to the second calibration device through 2n+3rd IO ports; the second calibration device is further configured to send the sixth calibration instruction to the chip through the 2n+2nd IO port; the electronic device is further configured to determine a third calibration time of the 2n+1th IO port and the 2n+3rd IO port when the 2n+2nd IO port and the 2n+2nd IO port have the same delay; the electronic device is further configured to send a seventh control instruction to the ALPG, where the seventh control instruction is used for the ALPG to send a seventh calibration instruction to the chip, and the seventh calibration instruction is used for the chip to send the seventh calibration instruction to the first calibration device through 2n+1th IO ports; the second calibration device is further configured to send the seventh calibration instruction to the chip through the 2nth IO port; the electronic device is further configured to send an eighth control instruction to the ALPG, where the eighth control instruction is used for the ALPG to send an eighth calibration instruction to the chip, and the eighth calibration instruction is used for the chip to send the eighth calibration instruction to the second calibration device through 2n+2nd IO ports; the second calibration device is further configured to send the eighth calibration instruction to the chip through the 2n-1 st IO port; the electronic device is further configured to determine a fourth calibration time of the 2n_1st IO port and the 2n_2nd IO port when the 2n+1st IO port and the 2n+2nd IO port have the same delay; the electronic equipment is further used for determining a fifth calibration time according to the first calibration time and the third calibration time; the electronic device is further configured to determine a sixth calibration time according to the second calibration time and the fourth calibration time; the electronic device is further configured to determine a third calibration delay according to the fifth calibration time and the sixth calibration time; the electronic device is further configured to calibrate the chip according to the third calibration delay.
According to the application, the characteristic that the internal delays of two adjacent IO port chips are similar is utilized, namely, when the chips are connected with first calibration equipment, the internal delays of the chips of the 2n-th IO port and the 2n+1st IO port are the same, the internal delays of the chips of the 2n+2nd IO port and the 2n+3rd IO port are the same, when the chips are connected with second calibration equipment, the internal delays of the chips of the 2n+1st IO port and the 2n+2nd IO port are the same, and in the same calibration equipment, all IO ports transmit and receive calibration instructions through the control chip, delay time of different IO ports is recorded, the maximum delay is determined as the reference delay of the chip, and other IO ports are controlled to calibrate according to the maximum delay, so that the delay time of all IO ports is ensured to be in a controllable range, and the accuracy of chip calibration is improved.
In some embodiments, as shown in fig. 5, 6 and 7, the chip (ASIC) includes 40 IO ports (0-39), and when the chip is connected to the first calibration device (TYPE a) through the connector, the first calibration command is used for the chip to send the first calibration command to the first calibration device through the 0 th IO port; the first calibration device sends a first calibration instruction to the chip through the 1 st IO port; the second calibration instruction is used for the chip to send the second calibration instruction to the first calibration equipment through the 3 rd IO port; the first calibration device sends a second calibration instruction to the chip through a 2 nd IO port; under the condition that the delay of the 1 st IO port and the 2 nd IO port is the same, the electronic equipment determines the first calibration time delta of the 0 th IO port and the 3 rd IO port 0-3 Similarly, delta can be obtained 2-5 、…、Δ 36-39 。
When the chip is connected with second calibration equipment (TYPE B) through the connector, the fifth calibration instruction is used for sending the fifth calibration instruction to the second calibration equipment through the 1 st IO port; the second calibration device sends a fifth calibration instruction to the chip through the 2 nd IO port; the sixth calibration instruction is used for the chip to send the sixth calibration instruction to the second calibration device through the 4 th IO port; the second calibration device sends a sixth calibration instruction to the chip through the 3 rd IO port; under the condition that the delay of the 2 nd IO port and the 3 rd IO port is the same, the electronic equipment determines the third calibration time delta of the 1 st IO port and the 4 th IO port 1-4 、…、Δ 35-38 。
When the chip is connected with the first calibration equipment (TYPE A) through the connectorWhen the third calibration instruction is used for sending the third calibration instruction to the first calibration device through the 4 th IO port, and the 4 th IO port is adjacent to the 3 rd IO port; the first calibration device sends a third calibration instruction to the chip through the 1 st IO port; the fourth calibration instruction is used for the chip to send the fourth calibration instruction to the first calibration equipment through the 3 rd IO port; the first calibration device sends a fourth calibration instruction to the chip through the 2 nd IO port; the electronic equipment determines a second calibration time delta of the 1 st IO port and the 2 nd IO port under the condition that the delay of the 3 rd IO port and the 4 th IO port is the same 1-2 。
When the chip is connected with second calibration equipment (TYPE B) through the connector, the seventh calibration instruction is used for sending the seventh calibration instruction to the first calibration equipment through the 2 nd IO port, and the second calibration equipment sends the seventh calibration instruction to the chip through the 1 st IO port; the eighth calibration instruction is used for the chip to send the eighth calibration instruction to the second calibration device through the 3 rd IO port; the second calibration device sends an eighth calibration instruction to the chip through the 0 th IO port; under the condition that the delay of the 2 nd IO port and the 3 rd IO port is the same, the electronic equipment determines the fourth calibration time delta of the 0 th IO port and the 1 st IO port 0-1 。
From FIG. 6, x can be obtained 0 、x 3 …、x 39 And x 1 、x 4 …、x 37 Further, by FIG. 7, x can be obtained 0 、x 1 And x 2 And further obtaining a delay relation of 40 pins, obtaining the maximum delay, and synchronously calibrating all pins of the chip according to the maximum delay.
In some embodiments, the multi-chip calibration system further comprises an oscilloscope, wherein: the electronic device is further configured to send a test instruction to the first ALPG, where the test instruction is used for the first ALPG to send a test signal to the chip, and the test signal is used for the chip to send the test signal to the oscilloscope through a test IO port, where the test IO port is any one of a plurality of IO ports of the chip; the oscilloscope is used for receiving the test signal; the electronic equipment is also used for determining path delay according to the time of the test IO port for sending the test signal and the time of the oscilloscope for receiving the test signal; the electronic device is further configured to determine the third calibration delay based on the fifth calibration time, the sixth calibration time, and the path delay.
In some embodiments, as shown in fig. 8, the single chip calibration system further comprises an oscilloscope, wherein: the electronic equipment is also used for sending a ninth control signal to the ALPG, the ninth control signal is used for sending a test signal to the chip by the ALPG, the test signal is used for sending the test signal to the oscilloscope through the test IO port, and the test IO port is any IO port in a plurality of IO ports of the chip; the oscilloscope is used for receiving the test signal; the electronic equipment is also used for determining path delay according to the time of sending the test signal by the test IO port and the time of receiving the test signal by the oscilloscope; the electronic device is further configured to determine a third calibration delay based on the fifth calibration time, the sixth calibration time, and the path delay.
The first calibration time, the second calibration time, the third calibration time, and the fourth calibration time all include test delays, and in order to reduce the influence of the path delays, the path delays in the first calibration time, the second calibration time, the third calibration time, and the fourth calibration time need to be subtracted, and then the determination of the third calibration delay is performed.
Specifically, the chip ASIC simultaneously transmits square waves, the phase difference Δps is tested two by two with a high-speed oscilloscope, all IOs are simultaneously transmitted, and the oscilloscope decision level is consistent with the DUT decision level: test 0/1, yielding Δ0-1=x0-X1; test 1/2, resulting in Δ1-2=x1-X2; and so on, the rank sum delta value of all pins 0-39 is obtained.
In some embodiments, the multi-chip calibration system further comprises a connector connected to the chip and the calibration device, wherein: the first calibration instruction is used for the chip to send the first calibration instruction to the first calibration device through the 2n_1st IO port, and includes: the first calibration instruction is used for the chip to send the first calibration instruction to the first calibration equipment through the connector through the 2n-1 IO port.
In some embodiments, the length of the chip to the connector is equal to the length of the connector to the first calibration device.
In some embodiments, the multi-chip calibration system further comprises a connector connected to the chip and the calibration device, wherein; the fifth calibration instruction is configured to send, by the chip, the fifth calibration instruction to the second calibration device through the nth IO port, and includes: the fifth calibration instruction is used for the chip to send the fifth calibration instruction to the second calibration device through the connector through the 2 n-th IO port.
In some embodiments, the length of the chip to the connector is equal to the length of the connector to the second calibration device.
From the above, the present application provides a multi-chip calibration system, which includes an electronic device and a calibration device, where the electronic device is connected to a plurality of ALPGs, each ALPG in the plurality of ALPGs is connected to at least one group of chips, each group of chips includes a first chip, a second chip, a third chip and a fourth chip, and the calibration device is connected to the first chip, the second chip, the third chip and the fourth chip, and includes a first calibration device and a second calibration device.
Consistent with the foregoing, an embodiment of the present application provides a multi-chip calibration method, which is applied to a multi-chip calibration system including an electronic device and a calibration device, the electronic device being connected to a plurality of ALPGs, each ALPG of the plurality of ALPGs being connected to at least one group of chips, each group of chips including a first chip, a second chip, a third chip, and a fourth chip, the calibration device being connected to the first chip, the second chip, the third chip, and the fourth chip, the calibration device including a first calibration device and a second calibration device, including the steps of:
Step S10, the electronic device sends a first control signal to a first ALPG, where the first control signal is used for the first ALPG to send a first calibration signal to the third chip, the first calibration signal is used for the third chip to send the first calibration signal to the first calibration device through a first IO port, the first ALPG is any one of the plurality of ALPGs, and the first IO port is any one of a plurality of IO ports of the third chip;
step S20, the first calibration device sends the first calibration signal to the second chip through a second IO port, where the second IO port is any one of a plurality of IO ports of the second chip;
step S30, the electronic device determines a first transmission time according to the time when the first IO port transmits the first calibration signal and the time when the second IO port receives the first calibration signal;
step S40, the electronic device sends a second control signal to the first ALPG, where the second control signal is used for the first ALPG to send a second calibration signal to the third chip, the second calibration signal is used for the third chip to send the second calibration signal to the first calibration device through a third IO port, and the third IO port is an IO port adjacent to the first IO port among a plurality of IO ports of the third chip;
Step S50, the first calibration device sends the second calibration signal to the first chip through a fourth IO port, wherein the fourth IO port is any IO port in a plurality of IO ports of the first chip;
step S60, the electronic device determines a second transmission time according to the time when the third IO port sends the first calibration signal and the time when the fourth IO port receives the first calibration signal;
step S70, the electronic equipment determines a first delay of the first chip and the second chip according to the first transmission time and the second transmission time;
step S80, the electronic device sends a third control signal to the first ALPG, where the third control signal is used for the first ALPG to send a third calibration signal to the second chip, and the third calibration signal is used for the second chip to send the third calibration signal to the second calibration device through the second IO port;
step S90, the second calibration device sends the third calibration signal to the first chip through the fourth IO port;
step S100, the electronic device determines a third transmission time according to the time when the second IO port sends the third calibration signal and the time when the fourth IO port receives the third calibration signal;
Step S110, the electronic device sends a fourth control signal to the first ALPG, where the fourth control signal is used for the first ALPG to send a fourth calibration signal to the second chip, and the fourth calibration signal is used for the second chip to send the fourth calibration signal to the second calibration device through a fifth IO port, where the fifth IO port is an IO port adjacent to the second IO port among the multiple IO ports of the second chip;
step S120, the second calibration device sends the fourth calibration signal to the third chip through the first IO port;
step S130, the electronic device determines a fourth transmission time according to the time when the fifth IO port sends the fourth calibration signal and the time when the first IO port receives the fourth calibration signal;
step S140, the electronic device determines a second delay of the first chip and the third chip according to the third transmission time and the fourth transmission time;
step S150, the electronic device sends a fifth control signal to the first ALPG, where the fifth control signal is used for the first ALPG to send a fifth calibration signal to the third chip, and the fifth calibration signal is used for the third chip to send the fifth calibration signal to the second calibration device through the first IO port;
Step S160, the second calibration device sends the fifth calibration signal to the second chip through the second IO port;
step S170, the electronic device determines a fifth transmission time according to the time when the first IO port sends the fifth calibration signal and the time when the second IO port receives the fifth calibration signal;
step S180, the electronic device sends a sixth control signal to the first ALPG, where the sixth control signal is used for the first ALPG to send a sixth calibration signal to the third chip, and the sixth calibration signal is used for the third chip to send the sixth calibration signal to the second calibration device through the third IO port;
step S190, the second calibration device sends the sixth calibration signal to the fourth chip through a sixth IO port, where the sixth IO port is any one of a plurality of IO ports of the fourth chip;
step S200, the electronic device determines a sixth transmission time according to the time when the third IO port sends the sixth calibration signal and the time when the sixth IO port receives the sixth calibration signal;
step S210, the electronic device determines a third delay of the second chip and the fourth chip according to the fifth transmission time and the sixth transmission time;
Step S220, the electronic device determining a first calibration delay according to the first delay, the second delay and the third delay;
in step S230, the electronic device calibrates the first chip, the second chip, the third chip, and the fourth chip according to the first calibration delay.
Although the application is described herein in connection with the embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
It will be apparent to those skilled in the art that embodiments of the present application may be provided as a method, apparatus (device), or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. A computer program may be stored/distributed on a suitable medium supplied together with or as part of other hardware, but may also take other forms, such as via the Internet or other wired or wireless telecommunication systems.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (devices) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable information prompting device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable information prompting device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable information reminder device to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable information-bearing device to cause a series of operational steps to be performed on the computer or other programmable device to produce a computer implemented process such that the instructions which execute on the computer or other programmable device provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Although the application has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely exemplary illustrations of the present application as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (10)

1. A multi-chip calibration system comprising an electronic device coupled to a plurality of ALPGs, each ALPG of the plurality of ALPGs coupled to at least one set of chips, each set of chips comprising a first chip, a second chip, a third chip, and a fourth chip, and a calibration device coupled to the first chip, the second chip, the third chip, and the fourth chip, the calibration device comprising a first calibration device and a second calibration device, wherein:
the electronic device is configured to send a first control signal to a first ALPG, where the first control signal is used for the first ALPG to send a first calibration signal to the third chip, the first calibration signal is used for the third chip to send the first calibration signal to the first calibration device through a first IO port, the first ALPG is any one of the plurality of ALPGs, and the first IO port is any one of a plurality of IO ports of the third chip;
the first calibration device is configured to send the first calibration signal to the second chip through a second IO port, where the second IO port is any one of a plurality of IO ports of the second chip;
the electronic device is further configured to determine a first transmission time according to a time when the first IO port transmits the first calibration signal and a time when the second IO port receives the first calibration signal;
The electronic device is further configured to send a second control signal to a first ALPG, where the second control signal is used for sending a second calibration signal to the third chip by the first ALPG, the second calibration signal is used for sending the second calibration signal to the first calibration device by the third chip through a third IO port, and the third IO port is an IO port adjacent to the first IO port among a plurality of IO ports of the third chip;
the first calibration device is further configured to send the second calibration signal to the first chip through a fourth IO port, where the fourth IO port is any one of a plurality of IO ports of the first chip;
the electronic device is further configured to determine a second transmission time according to a time when the third IO port transmits the first calibration signal and a time when the fourth IO port receives the first calibration signal;
the electronic device is further configured to determine a first delay of the first chip and the second chip according to the first transmission time and the second transmission time;
the electronic device is further configured to send a third control signal to the first ALPG, where the third control signal is used for the first ALPG to send a third calibration signal to the second chip, and the third calibration signal is used for the second chip to send the third calibration signal to the second calibration device through the second IO port;
The second calibration device is further configured to send the third calibration signal to the first chip through the fourth IO port;
the electronic device is further configured to determine a third transmission time according to a time when the second IO port sends the third calibration signal and a time when the fourth IO port receives the third calibration signal;
the electronic device is further configured to send a fourth control signal to the first ALPG, where the fourth control signal is used for sending a fourth calibration signal to the second chip by the first ALPG, and the fourth calibration signal is used for sending the fourth calibration signal to the second calibration device by the second chip through a fifth IO port, where the fifth IO port is an IO port adjacent to the second IO port among the plurality of IO ports of the second chip;
the second calibration device is further configured to send the fourth calibration signal to the third chip through the first IO port;
the electronic device is further configured to determine a fourth transmission time according to a time when the fifth IO port transmits the fourth calibration signal and a time when the first IO port receives the fourth calibration signal;
the electronic device is further configured to determine a second delay of the first chip and the third chip according to the third transmission time and the fourth transmission time;
The electronic device is further configured to send a fifth control signal to the first ALPG, where the fifth control signal is used for the first ALPG to send a fifth calibration signal to the third chip, and the fifth calibration signal is used for the third chip to send the fifth calibration signal to the second calibration device through the first IO port;
the second calibration device is further configured to send the fifth calibration signal to the second chip through the second IO port;
the electronic device is further configured to determine a fifth transmission time according to a time when the first IO port transmits the fifth calibration signal and a time when the second IO port receives the fifth calibration signal;
the electronic device is further configured to send a sixth control signal to the first ALPG, where the sixth control signal is used for the first ALPG to send a sixth calibration signal to the third chip, and the sixth calibration signal is used for the third chip to send the sixth calibration signal to the second calibration device through the third IO port;
the second calibration device is further configured to send the sixth calibration signal to the fourth chip through a sixth IO port, where the sixth IO port is any one of a plurality of IO ports of the fourth chip;
The electronic device is further configured to determine a sixth transmission time according to a time when the third IO port transmits the sixth calibration signal and a time when the sixth IO port receives the sixth calibration signal;
the electronic device is further configured to determine a third delay of the second chip and the fourth chip according to the fifth transmission time and the sixth transmission time;
the electronic device is further configured to determine a first calibration delay based on the first delay, the second delay, and the third delay;
the electronic device is further configured to calibrate the first chip, the second chip, the third chip, and the fourth chip according to the first calibration delay.
2. The multi-chip calibration system of claim 1, wherein the electronics connection connects a plurality of control boards, each control board connecting at least one set of ALPGs, each set of ALPGs including a second ALPG, a third ALPG, and a fourth ALPG, wherein:
the electronic device is further configured to send a seventh calibration signal to a fourth ALPG, where the seventh calibration signal is used for the fourth ALPG to send the seventh calibration signal to the first calibration device through a fifth chip, where the fifth chip is any chip in each group of chips;
The first calibration device is further configured to send the seventh calibration signal to the second ALPG through the fifth chip;
the electronic device is further configured to determine a seventh transmission time according to a time when the fourth ALPG transmits the seventh calibration signal and a time when the second ALPG receives the seventh calibration signal;
the electronic device is further configured to send an eighth calibration signal to a fourth ALPG, where the eighth calibration signal is used for the fourth ALPG to send the eighth calibration signal to the first calibration device through the fifth chip;
the first calibration device is further configured to send the eighth calibration signal to the third ALPG through the fifth chip;
the electronic device is further configured to determine an eighth transmission time according to a time when the fourth ALPG transmits the eighth calibration signal and a time when the third ALPG receives the eighth calibration signal;
the electronic device is further configured to determine a fourth delay of the second and third ALPGs according to the seventh and eighth transmission times;
the electronic device is further configured to send a ninth calibration signal to a second ALPG, where the ninth calibration signal is used for the second ALPG to send the ninth calibration signal to the first calibration device through the fifth chip;
The first calibration device is further configured to send the ninth calibration signal to the third ALPG through the fifth chip;
the electronic device is further configured to determine a ninth transmission time according to a time when the second ALPG transmits the ninth calibration signal and a time when the third ALPG receives the ninth calibration signal;
the electronic device is further configured to send a tenth calibration signal to a second ALPG, where the tenth calibration signal is used for the second ALPG to send the tenth calibration signal to the first calibration device through a fifth chip;
the first calibration device is further configured to send the tenth calibration signal to the fourth ALPG through the fifth chip;
the electronic device is further configured to determine a tenth transmission time according to a time when the tenth calibration signal is transmitted by the second ALPG and a time when the tenth calibration signal is received by the fourth ALPG;
the electronic device is further configured to determine a fifth delay of the third and fourth ALPGs according to the ninth and tenth transmission times;
the electronic device is further configured to determine a second calibration delay according to the fourth delay and the fifth delay;
The electronic device is further configured to calibrate the second, third, and fourth ALPGs according to the second calibration delay.
3. The multi-chip calibration system of claim 2, wherein the electronics are connected to a plurality of synchronization boards, each synchronization board being connected to at least one set of control boards, each set of control boards comprising a first control board, a second control board, a third control board, and a fourth control board, wherein:
the electronic device is further configured to send a first synchronization signal to the first control board, where the first synchronization signal is used for the first control board to send the first synchronization signal to the first calibration device;
the first calibration device is further configured to send the first synchronization signal to the third control board;
the electronic device is further configured to determine a first synchronization time of the first control board and the third control board according to a time when the first control board transmits the first synchronization signal and a time when the third control board receives the first synchronization signal;
the electronic device is further configured to send a second synchronization signal to the second control board, where the second synchronization signal is used for the second control board to send the second synchronization signal to the first calibration device;
The first calibration device is further configured to send the second synchronization signal to the fourth control board;
the electronic device is further configured to determine a second synchronization time of the second control board and the fourth control board according to a time when the fourth control board transmits the second synchronization signal and a time when the fourth control board receives the second synchronization signal;
the electronic device is further configured to send a third synchronization signal to the first control board, where the third synchronization signal is used for the first control board to send the third synchronization signal to the second calibration device;
the second calibration device is further configured to send the third synchronization signal to the second control board;
the electronic device is further configured to determine a third synchronization time of the first control board and the second control board according to a time when the first control board transmits the third synchronization signal and a time when the second control board receives the third synchronization signal;
the electronic device is further configured to determine a synchronization delay according to the first synchronization time, the second synchronization time, and the third synchronization time;
the electronic device is further configured to calibrate the first control board, the second control board, the third control board, and the fourth control board according to the synchronization delay.
4. The multi-chip calibration system of claim 1, wherein the chip comprises a plurality of IO ports, wherein a plurality of groups of IO ports are included in the plurality of groups of IO ports, wherein an nth group of IO ports in the plurality of groups of IO ports includes a 2n_1th IO port, a 2n_th IO port, a 2n+1th IO port, and a 2n+2nd IO port, n is a positive integer, and wherein the 2n_1th IO port, the 2n_th IO port, the 2n+1th IO port, and the 2n+2nd IO port are adjacent to each other, wherein:
the electronic device is configured to send a first control instruction to the first ALPG, where the first control instruction is used for the first ALPG to send a first calibration instruction to the chip, and the first calibration instruction is used for the chip to send the first calibration instruction to the first calibration device through the 2 nd-1 st IO port;
the first calibration device is configured to send the first calibration instruction to the chip through the 2 nd IO port;
the electronic device is further configured to send a second control instruction to the ALPG, where the second control instruction is used for the ALPG to send a second calibration instruction to the chip, and the second calibration instruction is used for the chip to send the second calibration instruction to the first calibration device through a 2+2nd IO port;
The first calibration device is further configured to send the second calibration instruction to the chip through the 2+1st IO port;
the electronic device is further configured to determine a first calibration time of the 2 nd-1 st IO port and the 2 nd+2 nd IO port when the delays of the 2 nd IO port and the 2 nd+1 st IO port are the same;
the electronic device is further configured to send a third control instruction to the ALPG, where the third control instruction is used for the ALPG to send a third calibration instruction to the chip, where the third calibration instruction is used for the chip to send the third calibration instruction to the first calibration device through a 2+3rd IO port, where the 2+3rd IO port is adjacent to the 2+2nd IO port;
the first calibration device is further configured to send the third calibration instruction to the chip through the 2 nd IO port;
the electronic device is further configured to send a fourth control instruction to the ALPG, where the fourth control instruction is used for the ALPG to send a fourth calibration instruction to the chip, and the fourth calibration instruction is used for the chip to send the fourth calibration instruction to the first calibration device through the 2+2th IO port;
the first calibration device is further configured to send the fourth calibration instruction to the chip through the 2+1st IO port;
The electronic device is further configured to determine a second calibration time of the 2 nd IO port and the 2+1 th IO port when delays of the 2+2 nd IO port and the 2+3 rd IO port are the same;
the electronic device is further configured to send a fifth control instruction to the ALPG, where the fifth control instruction is used for the ALPG to send a fifth calibration instruction to the chip, and the fifth calibration instruction is used for the chip to send the fifth calibration instruction to the second calibration device through the 2 nd IO port;
the second calibration device is configured to send the fifth calibration instruction to the chip through the 2+1st IO port;
the electronic device is further configured to send a sixth control instruction to the ALPG, where the sixth control instruction is used for the ALPG to send a sixth calibration instruction to the chip, and the sixth calibration instruction is used for the chip to send the sixth calibration instruction to the second calibration device through the 2+3rd IO port;
the second calibration device is further configured to send the sixth calibration instruction to the chip through the 2+2nd IO port;
the electronic device is further configured to determine a third calibration time of the 2 nd IO port and the 2+3 rd IO port when delays of the 2+1 th IO port and the 2+2 nd IO port are the same;
The electronic device is further configured to send a seventh control instruction to the ALPG, where the seventh control instruction is used for the ALPG to send a seventh calibration instruction to the chip, and the seventh calibration instruction is used for the chip to send the seventh calibration instruction to the first calibration device through the 2+1st IO port;
the second calibration device is further configured to send the seventh calibration instruction to the chip through the 2 nd IO port;
the electronic device is further configured to send an eighth control instruction to the ALPG, where the eighth control instruction is used for the ALPG to send an eighth calibration instruction to the chip, and the eighth calibration instruction is used for the chip to send the eighth calibration instruction to the second calibration device through the 2+2th IO port;
the second calibration device is further configured to send the eighth calibration instruction to the chip through the 2 nd-1 st IO port;
the electronic device is further configured to determine a fourth calibration time of the 2-1 st IO port and the 2 nd IO port when delays of the 2+1 st IO port and the 2+2 nd IO port are the same;
the electronic equipment is further used for determining a fifth calibration time according to the first calibration time and the third calibration time;
The electronic device is further configured to determine a sixth calibration time according to the second calibration time and the fourth calibration time;
the electronic device is further configured to determine a third calibration delay according to the fifth calibration time and the sixth calibration time;
the electronic device is further configured to calibrate the chip according to the third calibration delay.
5. The multi-chip calibration system of claim 4, further comprising an oscilloscope, wherein:
the electronic device is further configured to send a test instruction to the first ALPG, where the test instruction is used for the first ALPG to send a test signal to the chip, and the test signal is used for the chip to send the test signal to the oscilloscope through a test IO port, where the test IO port is any one of a plurality of IO ports of the chip;
the oscilloscope is used for receiving the test signal;
the electronic equipment is also used for determining path delay according to the time of the test IO port for sending the test signal and the time of the oscilloscope for receiving the test signal;
the electronic device is further configured to determine the third calibration delay based on the fifth calibration time, the sixth calibration time, and the path delay.
6. The multi-chip calibration system of claim 4, further comprising a connector coupled to the chip and the calibration device, wherein:
the first calibration instruction is used for the chip to send the first calibration instruction to the first calibration device through the 2 nd-1 st IO port, and includes:
the first calibration instruction is used for the chip to send the first calibration instruction to the first calibration equipment through the connector through the 2 nd-1 st IO port.
7. The multi-chip calibration system of claim 6, wherein the length of the chip to the connector is equal to the length of the connector to the first calibration device.
8. The multi-chip calibration system of claim 4, further comprising a connector coupled to the chip and the calibration device, wherein;
the fifth calibration instruction is configured to send, by the chip, the fifth calibration instruction to the second calibration device through the 2 nd IO port, and includes:
the fifth calibration instruction is used for the chip to send the fifth calibration instruction to the second calibration device through the connector via the 2 nd IO port.
9. The multi-chip calibration system of claim 8, wherein the length of the chip to the connector is equal to the length of the connector to the second calibration device.
10. A multi-chip calibration method, wherein the method is applied to a multi-chip calibration system comprising an electronic device and a calibration device, the electronic device being connected to a plurality of ALPGs, each ALPG of the plurality of ALPGs being connected to at least one set of chips, each set of chips comprising a first chip, a second chip, a third chip and a fourth chip, the calibration device being connected to the first chip, the second chip, the third chip and the fourth chip, the calibration device comprising a first calibration device and a second calibration device, wherein:
the electronic device sends a first control signal to a first ALPG, wherein the first control signal is used for sending a first calibration signal to the third chip by the first ALPG, the first calibration signal is used for sending the first calibration signal to the first calibration device by the third chip through a first IO port, the first ALPG is any one of the ALPGs, and the first IO port is any one of the IO ports of the third chip;
The first calibration device sends the first calibration signal to the second chip through a second IO port, wherein the second IO port is any one of a plurality of IO ports of the second chip;
the electronic equipment determines a first transmission time according to the time when the first IO port transmits the first calibration signal and the time when the second IO port receives the first calibration signal;
the electronic device sends a second control signal to a first ALPG, the second control signal is used for sending a second calibration signal to the third chip by the first ALPG, the second calibration signal is used for sending the second calibration signal to the first calibration device by the third chip through a third IO port, and the third IO port is an IO port adjacent to the first IO port in a plurality of IO ports of the third chip;
the first calibration device sends the second calibration signal to the first chip through a fourth IO port, wherein the fourth IO port is any IO port in a plurality of IO ports of the first chip;
the electronic equipment determines a second transmission time according to the time when the third IO port transmits the first calibration signal and the time when the fourth IO port receives the first calibration signal;
The electronic device determines a first delay of the first chip and the second chip according to the first transmission time and the second transmission time;
the electronic device sends a third control signal to the first ALPG, wherein the third control signal is used for sending a third calibration signal to the second chip by the first ALPG, and the third calibration signal is used for sending the third calibration signal to the second calibration device by the second chip through the second IO port;
the second calibration device sends the third calibration signal to the first chip through the fourth IO port;
the electronic equipment determines a third transmission time according to the time when the second IO port transmits the third calibration signal and the time when the fourth IO port receives the third calibration signal;
the electronic device sends a fourth control signal to the first ALPG, wherein the fourth control signal is used for sending a fourth calibration signal to the second chip by the first ALPG, the fourth calibration signal is used for sending the fourth calibration signal to the second calibration device by the second chip through a fifth IO port, and the fifth IO port is an IO port adjacent to the second IO port in a plurality of IO ports of the second chip;
The second calibration device sends the fourth calibration signal to the third chip through the first IO port;
the electronic equipment determines a fourth transmission time according to the time when the fifth IO port transmits the fourth calibration signal and the time when the first IO port receives the fourth calibration signal;
the electronic device determines second delays of the first chip and the third chip according to the third transmission time and the fourth transmission time;
the electronic device sends a fifth control signal to the first ALPG, wherein the fifth control signal is used for sending a fifth calibration signal to the third chip by the first ALPG, and the fifth calibration signal is used for sending the fifth calibration signal to the second calibration device by the third chip through the first IO port;
the second calibration device sends the fifth calibration signal to the second chip through the second IO port;
the electronic equipment determines a fifth transmission time according to the time when the first IO port transmits the fifth calibration signal and the time when the second IO port receives the fifth calibration signal;
the electronic device sends a sixth control signal to the first ALPG, wherein the sixth control signal is used for sending a sixth calibration signal to the third chip by the first ALPG, and the sixth calibration signal is used for sending the sixth calibration signal to the second calibration device by the third chip through the third IO port;
The second calibration device sends the sixth calibration signal to the fourth chip through a sixth IO port, wherein the sixth IO port is any IO port in a plurality of IO ports of the fourth chip;
the electronic equipment determines a sixth transmission time according to the time when the third IO port transmits the sixth calibration signal and the time when the sixth IO port receives the sixth calibration signal;
the electronic equipment determines third delays of the second chip and the fourth chip according to the fifth transmission time and the sixth transmission time;
the electronic device determining a first calibration delay from the first delay, the second delay, and the third delay;
the electronic device calibrates the first chip, the second chip, the third chip, and the fourth chip according to the first calibration delay.
CN202310471926.8A 2023-04-26 2023-04-26 Multi-chip calibration system and method Active CN116679186B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020063672A (en) * 2001-01-30 2002-08-05 삼성전자 주식회사 Wafer level burn-in tester having waveform monitoring unit and testing method using thereof
CN112711296A (en) * 2020-12-25 2021-04-27 北京航天测控技术有限公司 Calibration system
CN112865761A (en) * 2019-11-12 2021-05-28 联发科技股份有限公司 Multichip system and pulse width monitoring and calibration method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020063672A (en) * 2001-01-30 2002-08-05 삼성전자 주식회사 Wafer level burn-in tester having waveform monitoring unit and testing method using thereof
CN112865761A (en) * 2019-11-12 2021-05-28 联发科技股份有限公司 Multichip system and pulse width monitoring and calibration method
CN112711296A (en) * 2020-12-25 2021-04-27 北京航天测控技术有限公司 Calibration system

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