CN116669487A - Display panel, preparation method thereof and display device - Google Patents

Display panel, preparation method thereof and display device Download PDF

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Publication number
CN116669487A
CN116669487A CN202310738592.6A CN202310738592A CN116669487A CN 116669487 A CN116669487 A CN 116669487A CN 202310738592 A CN202310738592 A CN 202310738592A CN 116669487 A CN116669487 A CN 116669487A
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Prior art keywords
layer
sub
pixel unit
display panel
metal
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CN202310738592.6A
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Chinese (zh)
Inventor
崔容豪
玄丽燕
赵策
王明
王安君
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to CN202310738592.6A priority Critical patent/CN116669487A/en
Publication of CN116669487A publication Critical patent/CN116669487A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G09F9/335—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes being organic light emitting diodes [OLED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Abstract

The embodiment of the application provides a display panel, a preparation method thereof and a display device, wherein the display panel comprises a substrate, a plurality of sub-pixel units formed on the substrate and a plurality of MIMIMIMI dual resonance structures; each sub-pixel unit comprises an oxide thin film transistor; the MIMIMIMI dual resonance structure comprises a first metal layer, a first insulating layer, a light absorption layer, a second insulating layer and a second metal layer which are sequentially stacked along the direction far away from a substrate; the light absorption layer is used for absorbing incident blue light; a first interval area is formed between the blue sub-pixel unit and the sub-pixel unit adjacent to the blue sub-pixel unit; the MIMIMIMI dual resonance structure is arranged in the first interval region and is positioned between the blue photon pixel unit and the oxide thin film transistor of the adjacent sub-pixel unit. The display panel solves the reliability problems of progressive bright spots, peripheral pixel brightness and the like caused by adding blue light into an oxide thin film transistor.

Description

Display panel, preparation method thereof and display device
Technical Field
The application relates to the technical field of display, in particular to a display panel, a preparation method thereof and a display device.
Background
Compared with a common OLED, WOLED (White Organic Light-emission Diode) has longer service life and higher luminous efficiency, and is widely applied. In the WOLED display device, a pixel unit composed of red sub-pixels (R), green sub-pixels (G), blue sub-pixels (B) and white sub-pixels (W) is included. In use, white is displayed by the combined emission of the above sub-pixels. Blue light having a short wavelength with high energy in WOLED affects the characteristics of the oxide TFT (Thin Film Transistor ), and when blue light is added to the oxide TFT, the carrier density of the channel increases, and the thin film transistor Vth Negative Shift (negative shift of threshold voltage) occurs, which causes reliability problems such as progressive bright spots and peripheral pixel lighting.
Disclosure of Invention
The embodiment of the application aims to provide a display panel, a preparation method thereof and a display device, which are used for solving the reliability problems of progressive bright spots, peripheral pixel brightness and the like caused by adding blue light into an oxide thin film transistor. The specific technical scheme is as follows:
an embodiment of a first aspect of the present application provides a display panel, including a substrate, a plurality of sub-pixel units formed on the substrate, and a plurality of MIMIM dual resonance structures; the plurality of sub-pixel units comprise a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit, and each sub-pixel unit comprises an oxide thin film transistor; the MIMIMIMI dual resonance structure comprises a first metal layer, a first insulating layer, a light absorption layer, a second insulating layer and a second metal layer which are sequentially stacked along the direction far away from the substrate; the first metal layer, the first insulating layer and the light absorption layer form a lower FP cavity; the light absorption layer, the second insulating layer and the second metal layer form an upper FP cavity; a spacing region is formed between adjacent sub-pixel units; the second metal layer comprises a metal signal line arranged in the interval region; the orthographic projection of the light absorption layer on the substrate and the projection of the metal signal wire on the substrate have overlapping areas; the light absorption layer is used for absorbing incident blue light; a first interval area is formed between the blue sub-pixel unit and the sub-pixel unit adjacent to the blue sub-pixel unit; the MIMIM dual resonance structure is disposed within the first spacer region and is located between the blue subpixel unit and the oxide thin film transistor of the subpixel unit adjacent thereto.
In some embodiments of the application, the plurality of sub-pixel units further comprises: a white sub-pixel unit;
a second interval area is formed between the white light sub-pixel unit and the sub-pixel unit adjacent to the white light sub-pixel unit; the MIMIMIMI dual resonance structure is arranged in the second interval region and is positioned between the white light sub-pixel unit and the oxide thin film transistor of the sub-pixel unit adjacent to the white light sub-pixel unit.
In some embodiments of the present application, the oxide thin film transistor includes: an active layer, a gate insulating layer, a gate, an interlayer dielectric layer and a source-drain metal layer which are sequentially stacked along the direction away from the substrate;
the interlayer dielectric layer covers the grid electrode; the interlayer dielectric layer is provided with a via hole;
the source-drain metal layer comprises a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively connected with the active layer through a via hole on the interlayer dielectric layer.
In some embodiments of the present application, the metal signal line and the source-drain metal layer are arranged in the same layer;
the light absorption layer and the active layer are arranged on the same layer, and the interlayer dielectric layer covers the light absorption layer.
In some embodiments of the present application, the first metal layer is disposed between the active layer and the substrate, the first metal layer being a light shielding layer;
the first insulating layer is arranged between the active layer and the first metal layer, and is a buffer layer;
the interlayer dielectric layer is formed into the second insulating layer;
the shading layer, the buffer layer, the light absorption layer, the interlayer dielectric layer and the metal signal line are sequentially contacted and arranged to form a MIMIMIM dual resonance structure.
In some embodiments of the present application, the material of the active layer is partially conductive IGZO; the light absorbing layer is made of all conductive IGZO.
In some embodiments of the present application, the display panel further includes a passivation layer, a color film layer, a planarization layer, and a first electrode sequentially disposed in a direction away from the substrate;
the passivation layer is arranged on one side of the source-drain metal layer far away from the substrate and covers the source-drain metal layer and the metal signal line;
the color film layer comprises a plurality of sub-color films, and each sub-color film is arranged corresponding to one sub-pixel unit;
the flat layer covers the color film layer;
and the flat layer and the passivation layer are provided with trepanning, and the first electrode is connected with the source-drain metal layer through trepanning on the flat layer and the passivation layer.
In some embodiments of the application, the display panel further includes: the grid line is arranged in a crossing way with the metal signal line;
the grid line is connected with the grid electrode of the oxide thin film transistor.
An embodiment of a second aspect of the present application provides a method for manufacturing a display panel, for manufacturing the display panel in the above embodiment, including:
providing a substrate;
preparing a first metal layer on a substrate;
preparing a first insulating layer on the first metal layer;
preparing a light absorption layer, a second insulating layer and an oxide thin film transistor on the first insulating layer; the second insulating layer covers the light absorption layer;
preparing a second metal layer on the second insulating layer;
the first metal layer, the first insulating layer, the light absorbing layer, the second insulating layer and the second metal layer form a MIMIMIM dual resonance structure.
In some embodiments of the present application, an oxide thin film transistor includes an active layer, a gate insulating layer, a gate electrode, an interlayer dielectric layer, and a source drain metal layer;
the preparation of the light absorption layer, the second insulating layer and the oxide thin film transistor on the first insulating layer comprises the following steps:
preparing an IGZO layer on the first insulating layer;
forming a light absorption layer and an active layer of an oxide thin film transistor by adopting a patterning process and a conductor process; the material of the active layer is partially conductive IGZO, and the material of the light absorption layer is conductive IGZO;
preparing a gate insulating layer on the active layer;
preparing a gate electrode on the gate insulating layer; the grid electrode is not contacted with the active layer;
preparing an interlayer dielectric layer on the grid electrode, wherein the interlayer dielectric layer covers the grid electrode and the grid electrode insulating layer and is formed into a second insulating layer;
forming a via hole on the interlayer dielectric layer;
and preparing a source-drain metal layer on the interlayer dielectric layer, wherein the source-drain metal layer is connected with the active layer through a via hole on the interlayer dielectric layer.
In some embodiments of the present application, after the preparing the second metal layer on the second insulating layer, the method further includes:
preparing a metal signal wire on the same layer of the source-drain metal layer, wherein the metal signal wire is formed into a second metal layer;
preparing a passivation layer on the second metal layer;
preparing a color film layer on the passivation layer;
preparing a flat layer on the color film layer, wherein the flat layer covers the color film layer;
forming a trepanning on the planarization layer and the passivation layer;
and preparing a first electrode on the flat layer, wherein the first electrode is connected with the source-drain metal layer through trepanning of the flat layer and the passivation layer.
An embodiment of a third aspect of the application provides a display device comprising the display panel of any of the embodiments of the first aspect.
The embodiment of the application has the beneficial effects that:
the display panel of the application comprises a MIMIMIM dual resonance structure, wherein the MIMIMIM dual resonance structure is formed with an upper FP cavity (Fabry-Perot cavity) and a lower FP cavity which are arranged up and down, light can be reflected in the upper FP cavity or the lower FP cavity, and a light absorption layer is arranged between the upper FP cavity and the lower FP cavity and is used for absorbing incident blue light, so that the MIMIM dual resonance structure in the display panel of the application can absorb the incident blue light and can convert a short wavelength into a long wavelength through wavelength shift. The MIMIMIM dual resonance structure is arranged in a first interval area between the blue photon pixel unit and the adjacent sub-pixel unit and is positioned between the blue photon pixel unit and the oxide thin film transistor of the adjacent sub-pixel unit, so that in the process that blue light irradiates the oxide thin film transistor of the adjacent sub-pixel unit of the blue photon pixel unit, the blue light can be absorbed no matter the blue light passes through the upper FP cavity or the lower FP cavity, and the blue light can not be transmitted to the oxide thin film transistor of the adjacent sub-pixel unit of the blue photon pixel unit, thereby solving the reliability problems of progressive bright spots, peripheral pixel brightening and the like caused by the blue light added into the oxide thin film transistor.
The preparation method of the display panel is used for preparing the display panel in the embodiment, and the display panel comprises the MIMIMI dual resonance structure, so that blue light can be absorbed in the process of being directed to the oxide thin film transistor of the sub-pixel unit adjacent to the blue sub-pixel unit, and cannot be transmitted to the oxide thin film transistor of the sub-pixel unit adjacent to the blue sub-pixel unit.
The display device of the present application includes the display panel in any of the embodiments of the first aspect, and since the display panel of the present application includes the MIMIM dual resonance structure, blue light can be absorbed in a process of directing the blue light to the oxide thin film transistor of the sub-pixel unit adjacent to the blue sub-pixel unit, so that the blue light cannot propagate to the oxide thin film transistor of the sub-pixel unit adjacent to the blue sub-pixel unit, and the reliability problems such as progressive bright point and peripheral pixel lighting caused by adding the blue light to the oxide thin film transistor can be solved.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the application, and other embodiments may be obtained according to these drawings to those skilled in the art.
Fig. 1 is a characteristic change diagram of an oxide thin film transistor when a light source is added to the oxide thin film transistor;
FIG. 2 is a diagram illustrating an image sticking test of a display panel according to the related art;
FIG. 3 is a layout diagram of a display panel according to an embodiment of the present application;
fig. 4 is a schematic diagram of a MIMIM dual resonance structure in a display panel according to an embodiment of the present application;
fig. 5 is a schematic diagram of MIM structure;
fig. 6a is a layer structure relationship diagram of a conventional MIMIM dual resonance structure;
FIG. 6b is an enlarged partial schematic view of the dashed box of FIG. 4;
FIG. 7 is a graph of absorbance of nonconducted IGZO and of conductive IGZO;
fig. 8 is a waveform diagram of white light, blue light, red light, and green light;
fig. 9 is a flowchart of a method for manufacturing a display panel according to an embodiment of the application.
Reference numerals illustrate:
a display panel 10; a thick metal layer 21; an insulating layer 22; a thin metal layer 23; a substrate 100; a MIMIM dual resonance structure 200; upper FP cavity 201; a lower FP cavity 202; a first metal layer 210; a first insulating layer 220; a light absorbing layer 230; a second insulating layer 240; a second metal layer 250; a metal signal line 251; a sub-pixel unit 300; a red sub-pixel unit 301; a green sub-pixel unit 302; a blue sub-pixel unit 303; a white light sub-pixel unit 304; a pixel region 300a; a TFT region 300b; an oxide thin film transistor 310; an active layer 311; a gate insulating layer 312; a gate 313; an interlayer dielectric layer 314; source drain metal layer 315; a passivation layer 400; a color film layer 500; a sub-color film 510; a planarization layer 600; a first electrode 700; a gate line 801; a first spacing region 901; a second spacing region 902.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by the person skilled in the art based on the present application are included in the scope of protection of the present application.
The WOLED display panel uses an Oxide thin film transistor (Oxide TFT) which has a characteristic change such as Vth (-) shift (negative shift of threshold voltage) due to an increase in Carrier density in Oxide Channel when a high-energy short-wavelength Light source (Blue Light) is added.
Specifically, as shown in fig. 1, fig. 1 is a characteristic change diagram of an oxide thin film transistor when a light source is added to the oxide thin film transistor. The three curves in fig. 1 are respectively Initial (Initial), NBTS (Negative bias temperature stress ) and NBTiS (Negativebias temperature illumination stress, negative bias temperature light stress) characteristics, and it is clear that the NBTiS characteristics change the most and the threshold voltage has a large negative shift. In this way, an afterimage problem occurs in the display process, and the characteristic change is caused by adding a light source to the oxide thin film transistor, and the characteristic fluctuation has a problem of poor reliability, namely, poor linearity due to a traveling bright point and poor driving of adjacent GOA (Gate On Array) TFTs, and thus poor reliability of the traveling property occurs.
Specifically, as shown in fig. 2, fig. 2 is a diagram illustrating an afterimage test of a display panel in the related art, wherein two color blocks on the left side represent dark pixels, two color blocks on the right side represent bright pixels, two color blocks above are display images in an initial state, and two color blocks below are display images after the afterimage test. The oxide thin film transistor of the upper left Black color block (Black Pattern) receives the Negative Bias voltage, and the upper right White color block (White Pattern) receives the Positive Bias Stress positive Bias voltage; at this time, light generated from the White Pattern is transmitted to the oxide thin film transistor of the Black Pattern adjacent to the White Pattern, vth (-) shift is generated, and the brightness of the Black Pattern increases due to the variation of the characteristics of the oxide thin film transistor, and the boundary between the Black Pattern and the White Pattern is lighted, thereby generating a bad phenomenon.
In order to solve the reliability problems of progressive bright spots, peripheral pixel brightness and the like caused by blue light added into an oxide thin film transistor, the application provides a display panel, a preparation method thereof and a display device.
As shown in fig. 3 and 4, fig. 3 is a layout diagram of a display panel 10 according to an embodiment of the present application, and fig. 4 is a schematic diagram of a MIMIM dual resonance structure 200 in the display panel 10 according to an embodiment of the present application, an embodiment of a first aspect of the present application proposes a display panel 10, the display panel 10 includes a substrate 100, a plurality of sub-pixel units 300 formed on the substrate 100, and a plurality of MIMIM dual resonance structures 200; the plurality of sub-pixel units 300 includes a red sub-pixel unit 301, a green sub-pixel unit 302, and a blue sub-pixel unit 303, and each sub-pixel unit 300 includes an oxide thin film transistor 310; the MIMIM dual resonance structure 200 includes a first metal layer 210, a first insulating layer 220, a light absorbing layer 230, a second insulating layer 240, and a second metal layer 250 stacked in this order in a direction away from the substrate 100; the first metal layer 210, the first insulating layer 220, and the light absorbing layer 230 constitute the lower FP cavity 202; the light absorbing layer 230, the second insulating layer 240 and the second metal layer 250 constitute the upper FP cavity 201; a space region is formed between adjacent sub-pixel units 300; the second metal layer 250 includes metal signal lines 251 disposed at the spaced regions; the front projection of the light absorbing layer 230 on the substrate 100 and the projection of the metal signal line 251 on the substrate 100 have overlapping areas; the light absorbing layer 230 is used to absorb incident blue light; a first interval region 901 is formed between the blue sub-pixel unit 303 and the sub-pixel unit 300 adjacent thereto; the MIMIM dual resonance structure 200 is disposed within the first spacer region 901 and is located between the blue subpixel unit 303 and the oxide thin film transistor 310 of the subpixel unit 300 adjacent thereto.
As shown in fig. 3, the oxide thin film transistor 310 is disposed in the corresponding TFT region 300b, and light is emitted from the pixel region 300a.
The application introduces a MIM (Metal-Insulator-Metal) structure which can form resonance with a Fabry-Perot cavity (FP cavity) as shown in figure 5. Fig. 5 is a schematic diagram of MIM structure, and the layer structure in fig. 5 is, from top to bottom, a Thin metal layer 23 (Thin metal), an insulating layer 22 (Insulator), and a Thick metal layer 21 (Thick metal), wherein the Thick metal layer 21 serves as a Back reflector (Back reflector) for reflecting light. Such a resonant structure can selectively remove light wavelengths or can perform Phase Shift by adjusting the thickness of an Insulator in the MIM structure. Based on this, the display panel 10 of the present application is provided with a MIMIM (Metal-Insulator-Thin Film Metal-Insulator-Metal) dual resonance structure as shown in fig. 6a, and fig. 6a is a layer structure relationship diagram of a conventional MIMIM dual resonance structure, which sequentially includes, from top to bottom, a Metal layer, an insulating layer, a Metal Thin Film layer, an insulating layer, and a Metal layer, wherein the upper three layers form an upper cavity, the lower three layers form a lower cavity, and the Metal Thin Film layer serves as a common Film layer of the two cavities. As shown in fig. 6b, fig. 6b is a partially enlarged schematic view of the dashed line box in fig. 4, in which a second metal layer 250, a second insulating layer 240, a light absorbing layer 230, a first insulating layer 220 and a first metal layer 210 are sequentially stacked from top to bottom, and the film layers shown in fig. 6b correspond to those shown in fig. 6a one-to-one from top to bottom.
The display panel 10 of the present application includes the MIMIM dual resonance structure 200, and the MIMIM dual resonance structure 200 is formed with an upper FP cavity 201 (Fabry-Perot cavity) and a lower FP cavity 202 arranged up and down, light may be internally reflected in the upper FP cavity 201 or the lower FP cavity 202, and a light absorbing layer 230 is provided between the upper FP cavity 201 and the lower FP cavity 202, and the light absorbing layer 230 is used to absorb incident blue light, so that the MIMIM dual resonance structure 200 in the display panel 10 of the present application may absorb the incident blue light and may convert the short wavelength into the long wavelength by wavelength shift. The MIMIM dual resonance structure 200 is disposed in the first spacer region 901 between the blue sub-pixel unit 303 and the sub-pixel unit 300 adjacent thereto, and is located between the blue sub-pixel unit 303 and the oxide thin film transistor 310 of the sub-pixel unit 300 adjacent thereto, so that in the process of emitting blue light to the oxide thin film transistor 310 of the sub-pixel unit 300 adjacent to the blue sub-pixel unit 303, the blue light needs to pass through the MIMIM dual resonance structure 200, and the blue light cannot be transmitted to the oxide thin film transistor 310 of the sub-pixel adjacent to the blue sub-pixel unit 303 no matter the blue light passes through the upper FP cavity 201 or the lower FP cavity 202, thereby solving the reliability problems such as progressive bright spots and peripheral pixel brightness caused by adding the blue light to the oxide thin film transistor 310.
In some embodiments of the present application, the material of the light absorbing layer 230 may be all conductive IGZO (indium gallium zinc oxide). Since all the conductive IGZO has a metallic property, the MIMIM dual resonance structure 200 can be formed as a thin metal film layer together with other film layers. As shown in fig. 7, fig. 7 is a graph of the absorbance of non-conductive IGZO and conductive IGZO. In fig. 7, the Low-doping curve is a curve of nonconductive IGZO, the High-doping curve is a curve of conductive IGZO, and the horizontal axis represents Wavelength (Wavelength) and the vertical axis represents extinction coefficient (Extinction coefficient). As can be seen from FIG. 7, the conducted IGZO can absorb the short wavelengths of 400-600nm (the short wavelength blue light is 400-480 nm). When the MIMIM dual resonance structure 200 of such a resonance structure is used, internal reflected light applied from the adjacent Sub-Pixel units 300 (Sub-Pixel) can be blocked. In addition, by using the conductive IGZO layer, a light source blocking a short wavelength region of 400 to 600nm can be additionally provided, so that the influence of an internal reflection light source on the oxide thin film transistor 310 can be minimized.
In some embodiments of the present application, as shown in fig. 2 and 3, the plurality of sub-pixel units 300 further includes a white sub-pixel unit 304; a second interval region 902 is formed between the white sub-pixel unit 304 and the sub-pixel unit 300 adjacent thereto; the MIMIM dual resonance structure 200 is disposed in the second spacer region 902 and is located between the white light sub-pixel cell 304 and the oxide thin film transistor 310 of the sub-pixel cell 300 adjacent thereto.
As shown in fig. 8, fig. 8 is a waveform diagram of white light, blue light, red light and green light, and fig. 8 shows waveforms of white light, which has three light sources of blue light, green light and red light, and the MIMIM dual resonance structure 200 is disposed between the white sub-pixel unit 304 and the oxide thin film transistor 310 of the sub-pixel unit 300 adjacent thereto in the second interval region 902, so that short wavelength light related to the blue light can be reduced and long wavelength can be formed by Phase Shift.
Specifically, the light absorbing layer 230 may be disposed within a dashed box as shown in fig. 3, and then the front projection of the light absorbing layer 230 on the substrate 100 falls within the front projection of the metal signal line 251 on the substrate 100, so that the MIMIM dual resonance structure 200 is formed within the dashed box. It is understood that the front projection of the light absorbing layer 230 on the substrate 100 may also exceed the front projection of the metal signal line 251 on the substrate 100, so long as the front projection of the first metal layer 210, the first insulating layer 220, the light absorbing layer 230, the second insulating layer 240 and the second metal layer 250 on the substrate 100 has an overlapping area, and the overlapping area is located between the blue sub-pixel unit 303 or the white sub-pixel unit 304 and the oxide thin film transistor 310 of the sub-pixel unit 300 adjacent thereto, so as to form the MIMIM dual resonance structure 200 capable of absorbing blue light.
If the MIMIM dual resonance structure 200 is provided to be filled with a dotted line frame as shown in fig. 3, i.e., disposed in left and right Metal signal lines 251 (Metal) regions of the Blue Sub-Pixel unit 303 and the white Sub-Pixel unit 304, the influence of the light source on the adjacent Sub-Pixel unit 300 can be minimized, so that the characteristics of the oxide thin film transistor 310 can be stabilized and the reliability defect can be improved.
In some embodiments of the present application, as shown in fig. 4, the oxide thin film transistor 310 includes an active layer 311, a gate insulating layer 312, a gate electrode 313, an interlayer dielectric layer 314, and a source-drain metal layer 315, which are sequentially stacked in a direction away from the substrate 100; an interlayer dielectric layer 314 covers the gate 313; the interlayer dielectric layer 314 is provided with a via hole; the source-drain metal layer 315 includes a source electrode and a drain electrode, which are respectively connected to the active layer 311 through vias on the interlayer dielectric layer 314.
In some embodiments of the present application, as shown in fig. 4, the metal signal line 251 and the source drain metal layer 315 are disposed in the same layer; the light absorbing layer 230 is disposed in the same layer as the active layer 311, and an interlayer dielectric layer 314 covers the light absorbing layer 230. Thus, when the material of the metal signal line 251 and the source/drain metal layer 315 is the same, two film layers can be formed by one-step preparation, which is beneficial to improving the production efficiency. The light absorbing layer 230 and the active layer 311 are the same.
In some embodiments of the present application, as shown in fig. 4, a first metal layer 210 is disposed between an active layer 311 and a substrate 100, and the first metal layer 210 is a Light shielding layer (Light Shield); the first insulating layer 220 is disposed between the active layer 311 and the first metal layer 210, and the first insulating layer 220 is a Buffer insulating layer; an interlayer dielectric layer 314 (ILD insulating layer) is formed as a second insulating layer 240; the light shielding layer, the buffer layer, the light absorbing layer 230, the interlayer dielectric layer 314 and the metal signal line 251 are sequentially in contact with each other, so as to form the MIMIM dual resonance structure 200. By adding the light absorption layer 230, the MIMIMIM dual resonance structure 200 is formed together with other existing film layers, and a plurality of film layers are not required to be additionally prepared to form the MIMIMIM dual resonance structure 200, so that the production efficiency is improved.
In some embodiments of the present application, the material of the active layer 311 may be partially conductive IGZO. Specifically, portions of the active layer 311 that directly contact the source and drain electrodes of the oxide thin film transistor 310 may be electrically conductive.
The active layer 311 is made of partially conductive IGZO, the light-absorbing layer 230 is made of fully conductive IGZO, and the active layer 311 and the light-absorbing layer 230 are arranged in the same layer. Thus, the light absorbing layer 230 can be formed using a general oxide thin film transistor 310 process without additional processes, which is advantageous in improving production efficiency.
In some embodiments of the present application, as shown in fig. 4, the display panel 10 further includes a passivation layer 400 (PVX layer), a color film layer 500 (CF), a planarization layer 600 (Resin layer), and a first electrode 700 sequentially disposed in a direction away from the substrate 100; the passivation layer 400 is disposed on a side of the source drain metal layer 315 away from the substrate 100, and covers the source drain metal layer 315 and the metal signal line 251; the color film layer 500 includes a plurality of sub-color films 510, where each sub-color film 510 is disposed corresponding to one sub-pixel unit 300; the planarization layer 600 covers the color film layer 500; the planarization layer 600 and the passivation layer 400 are provided with a via hole, and the first electrode 700 is connected to the source drain metal layer 315 through the via hole on the planarization layer 600 and the passivation layer 400.
Specifically, the color film layer 500 may include a blue color sub-film, a green color sub-film, and a red color sub-film, and white light passes through the different color sub-films 510 to represent different colors of light. The first electrode 700 may be a cathode or an Anode (Anode), and the first electrode 700 may be connected to a source or a drain of the source drain metal layer 315. The sub-color film 510 is disposed in the pixel area 300a.
In some embodiments of the present application, as shown in fig. 3, the display panel 10 further includes a gate line 801, and the gate line 801 and the metal signal line 251 are disposed to cross each other; the gate line 801 is connected to the gate electrode 313 of the oxide thin film transistor 310.
As shown in fig. 3, the lines extending in the up-down direction are metal signal lines 251, which may be Vdd lines (voltage lines), vdate lines (data signal lines), vref lines (reference signal lines), vdate lines, and Vdd lines in order from left to right; two lines extending in the left-right direction are gate lines 801 (gate lines).
As shown in fig. 9, fig. 9 is a flowchart of a method for manufacturing a display panel 10 according to an embodiment of the present application, and an embodiment of a second aspect of the present application provides a method for manufacturing a display panel 10 according to the above embodiment, including:
s1, providing a substrate 100;
s2, preparing a first metal layer 210 on the substrate 100;
s3, preparing a first insulating layer 220 on the first metal layer 210;
s4, preparing a light absorption layer 230, a second insulating layer 240 and an oxide thin film transistor 310 on the first insulating layer 220; the second insulating layer 240 covers the light absorbing layer 230;
s5, preparing a second metal layer 250 on the second insulating layer 240;
the first metal layer 210, the first insulating layer 220, the light absorbing layer 230, the second insulating layer 240, and the second metal layer 250 form the MIMIM dual resonance structure 200.
The preparation method of the display panel 10 according to the present application is used for preparing the display panel 10 in the above embodiment, and since the display panel 10 according to the present application includes the MIMIM dual resonance structure 200, blue light can be absorbed in the process of being directed to the oxide thin film transistor 310 of the sub-pixel unit 300 adjacent to the blue sub-pixel unit 303, so that blue light cannot be transmitted to the oxide thin film transistor 310 of the sub-pixel unit 300 adjacent to the blue sub-pixel unit 303, and thus the display panel 10 prepared by adopting the preparation method of the present application solves the reliability problems such as progressive bright point and peripheral pixel brightening caused by adding blue light to the oxide thin film transistor 310.
In some embodiments of the present application, referring to fig. 4, an oxide thin film transistor 310 includes an active layer 311, a gate insulating layer 312, a gate 313, an interlayer dielectric layer 314, and a source drain metal layer 315; the above-described preparation of the light absorbing layer 230, the second insulating layer 240, and the oxide thin film transistor 310 on the first insulating layer 220 includes:
preparing an IGZO layer on the first insulating layer 220;
forming the light absorbing layer 230 and the active layer 311 of the oxide thin film transistor 310 using a patterning process and a conductive process; the material of the active layer 311 is partially conductive IGZO, and the material of the light absorbing layer 230 is entirely conductive IGZO;
a gate insulating layer 312 is prepared on the active layer 311;
preparing a gate electrode 313 on the gate insulating layer 312; the gate electrode 313 is not in contact with the active layer 311;
an interlayer dielectric layer 314 is prepared on the gate electrode 313, and the interlayer dielectric layer 314 covers the gate electrode 313 and the gate insulating layer 312 to form a second insulating layer 240;
forming a via hole on the interlayer dielectric layer 314;
a source-drain metal layer 315 is formed on the interlayer dielectric layer 314, and the source-drain metal layer 315 is connected to the active layer 311 through a via hole on the interlayer dielectric layer 314.
The active layer 311 is made of partially conductive IGZO, the light-absorbing layer 230 is made of fully conductive IGZO, and the active layer 311 and the light-absorbing layer 230 are arranged in the same layer. Thus, the light absorbing layer 230 can be formed using a general oxide thin film transistor 310 process without additional processes, which is advantageous in improving production efficiency.
In some embodiments of the present application, after preparing the second metal layer 250 on the second insulating layer 240, further comprising:
preparing a metal signal line 251 on the same layer of the source drain metal layer 315, wherein the metal signal line 251 becomes a second metal layer 250;
preparing a passivation layer 400 on the second metal layer 250;
preparing a color film layer 500 on the passivation layer 400;
preparing a flat layer 600 on the color film layer 500, wherein the flat layer 600 covers the color film layer 500;
forming a trepanning on the planarization layer 600 and the passivation layer 400;
the first electrode 700 is prepared on the planarization layer 600, and the first electrode 700 is connected to the source drain metal layer 315 through the trepanning of the planarization layer 600 and the passivation layer 400.
An embodiment of a third aspect of the present application proposes a display device comprising the display panel 10 of any of the embodiments of the first aspect.
The display device of the present application includes the display panel 10 according to any of the embodiments of the first aspect, since the display panel 10 of the present application includes the MIMIM dual resonance structure 200, blue light can be absorbed during the process of blue light being directed to the oxide thin film transistor 310 of the sub-pixel unit 300 adjacent to the blue sub-pixel unit 303, such that blue light cannot be transmitted to the oxide thin film transistor 310 of the sub-pixel unit 300 adjacent to the blue sub-pixel unit 303, and thus the display device of the present application can solve the reliability problems such as progressive bright spots and surrounding pixel brightness caused by blue light being added to the oxide thin film transistor 310.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims (12)

1. A display panel, comprising: a substrate, a plurality of sub-pixel units formed on the substrate, and a plurality of MIMIM dual resonance structures;
the plurality of sub-pixel units includes: a red subpixel unit, a green subpixel unit, and a blue subpixel unit, each of the subpixel units including an oxide thin film transistor;
the MIMIM dual resonance structure includes: the first metal layer, the first insulating layer, the light absorption layer, the second insulating layer and the second metal layer are sequentially stacked along the direction away from the substrate; the first metal layer, the first insulating layer and the light absorption layer form a lower FP cavity; the light absorption layer, the second insulating layer and the second metal layer form an upper FP cavity;
a spacing region is formed between adjacent sub-pixel units;
the second metal layer includes: a metal signal line disposed in the space region; the orthographic projection of the light absorption layer on the substrate and the projection of the metal signal wire on the substrate have overlapping areas; the light absorption layer is used for absorbing incident blue light;
a first interval area is formed between the blue sub-pixel unit and the sub-pixel unit adjacent to the blue sub-pixel unit; the MIMIM dual resonance structure is disposed within the first spacer region and is located between the blue subpixel unit and the oxide thin film transistor of the subpixel unit adjacent thereto.
2. The display panel of claim 1, wherein the plurality of sub-pixel units further comprises: a white sub-pixel unit;
a second interval area is formed between the white light sub-pixel unit and the sub-pixel unit adjacent to the white light sub-pixel unit; the MIMIMIMI dual resonance structure is arranged in the second interval region and is positioned between the white light sub-pixel unit and the oxide thin film transistor of the sub-pixel unit adjacent to the white light sub-pixel unit.
3. The display panel according to claim 1 or 2, wherein the oxide thin film transistor includes: an active layer, a gate insulating layer, a gate, an interlayer dielectric layer and a source-drain metal layer which are sequentially stacked along the direction away from the substrate;
the interlayer dielectric layer covers the grid electrode; the interlayer dielectric layer is provided with a via hole;
the source-drain metal layer comprises a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively connected with the active layer through a via hole on the interlayer dielectric layer.
4. The display panel according to claim 3, wherein the metal signal line and the source-drain metal layer are provided in the same layer;
the light absorption layer and the active layer are arranged on the same layer, and the interlayer dielectric layer covers the light absorption layer.
5. The display panel of claim 4, wherein the display panel comprises,
the first metal layer is arranged between the active layer and the substrate, and is a shading layer;
the first insulating layer is arranged between the active layer and the first metal layer, and is a buffer layer;
the interlayer dielectric layer is formed into the second insulating layer;
the shading layer, the buffer layer, the light absorption layer, the interlayer dielectric layer and the metal signal line are sequentially contacted and arranged to form a MIMIMIM dual resonance structure.
6. The display panel according to claim 1, wherein the material of the active layer is partially conductive IGZO; the light absorbing layer is made of all conductive IGZO.
7. The display panel of claim 5, further comprising a passivation layer, a color film layer, a planarization layer, and a first electrode sequentially disposed in a direction away from the substrate;
the passivation layer is arranged on one side of the source-drain metal layer far away from the substrate and covers the source-drain metal layer and the metal signal line;
the color film layer comprises a plurality of sub-color films, and each sub-color film is arranged corresponding to one sub-pixel unit;
the flat layer covers the color film layer;
and the flat layer and the passivation layer are provided with trepanning, and the first electrode is connected with the source-drain metal layer through trepanning on the flat layer and the passivation layer.
8. The display panel of claim 7, further comprising: the grid line is arranged in a crossing way with the metal signal line;
the grid line is connected with the grid electrode of the oxide thin film transistor.
9. A method for manufacturing a display panel, characterized in that it is used for manufacturing the display panel according to claim 1, comprising:
providing a substrate;
preparing a first metal layer on a substrate;
preparing a first insulating layer on the first metal layer;
preparing a light absorption layer, a second insulating layer and an oxide thin film transistor on the first insulating layer; the second insulating layer covers the light absorption layer;
preparing a second metal layer on the second insulating layer;
the first metal layer, the first insulating layer, the light absorbing layer, the second insulating layer and the second metal layer form a MIMIMIM dual resonance structure.
10. The method of manufacturing a display panel according to claim 9, wherein the oxide thin film transistor comprises an active layer, a gate insulating layer, a gate electrode, an interlayer dielectric layer, and a source drain metal layer;
the preparation of the light absorption layer, the second insulating layer and the oxide thin film transistor on the first insulating layer comprises the following steps:
preparing an IGZO layer on the first insulating layer;
forming a light absorption layer and an active layer of an oxide thin film transistor by adopting a patterning process and a conductor process; the material of the active layer is partially conductive IGZO, and the material of the light absorption layer is conductive IGZO;
preparing a gate insulating layer on the active layer;
preparing a gate electrode on the gate insulating layer; the grid electrode is not contacted with the active layer;
preparing an interlayer dielectric layer on the grid electrode, wherein the interlayer dielectric layer covers the grid electrode and the grid electrode insulating layer and is formed into a second insulating layer;
forming a via hole on the interlayer dielectric layer;
and preparing a source-drain metal layer on the interlayer dielectric layer, wherein the source-drain metal layer is connected with the active layer through a via hole on the interlayer dielectric layer.
11. The method of manufacturing a display panel according to claim 10, wherein after the second metal layer is manufactured on the second insulating layer, further comprising:
preparing a metal signal wire on the same layer of the source-drain metal layer, wherein the metal signal wire is formed into a second metal layer;
preparing a passivation layer on the second metal layer;
preparing a color film layer on the passivation layer;
preparing a flat layer on the color film layer, wherein the flat layer covers the color film layer;
forming a trepanning on the planarization layer and the passivation layer;
and preparing a first electrode on the flat layer, wherein the first electrode is connected with the source-drain metal layer through trepanning of the flat layer and the passivation layer.
12. A display device comprising the display panel according to any one of claims 1 to 8.
CN202310738592.6A 2023-06-19 2023-06-19 Display panel, preparation method thereof and display device Pending CN116669487A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310738592.6A CN116669487A (en) 2023-06-19 2023-06-19 Display panel, preparation method thereof and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310738592.6A CN116669487A (en) 2023-06-19 2023-06-19 Display panel, preparation method thereof and display device

Publications (1)

Publication Number Publication Date
CN116669487A true CN116669487A (en) 2023-08-29

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