CN116666370A - Power module and preparation method thereof - Google Patents

Power module and preparation method thereof Download PDF

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Publication number
CN116666370A
CN116666370A CN202310742193.7A CN202310742193A CN116666370A CN 116666370 A CN116666370 A CN 116666370A CN 202310742193 A CN202310742193 A CN 202310742193A CN 116666370 A CN116666370 A CN 116666370A
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China
Prior art keywords
copper
clad
pattern
chip
power module
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Pending
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CN202310742193.7A
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Chinese (zh)
Inventor
李泽昆
赵永强
暴杰
解锟
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FAW Group Corp
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FAW Group Corp
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Priority to CN202310742193.7A priority Critical patent/CN116666370A/en
Publication of CN116666370A publication Critical patent/CN116666370A/en
Priority to JP2024000054U priority patent/JP3245990U/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The embodiment of the invention discloses a power module and a preparation method thereof, wherein the power module comprises a plurality of groups of bridge arms, and each group of bridge arms comprises a plurality of SiCMOSFET chips; a plurality of bonding copper sheets, a lining copper layer, a ceramic lining board, a heat dissipation bottom plate and a metal terminal; the lining plate copper-clad layer comprises a first copper-clad pattern and a second copper-clad pattern, and the first copper-clad pattern and the second copper-clad pattern are mutually insulated; the first surface of the chip is connected with the first copper-clad pattern, and the second surface of the chip is connected with the second copper-clad pattern through a bonding copper sheet; the metal terminal is electrically connected with the second copper-clad pattern; according to the technical scheme provided by the embodiment of the invention, one surface of the SiCNOSFET chip is directly connected to the first copper-clad pattern of the lining plate copper-clad layer, and the bonding copper sheet is used for connecting the SiCNOSFET chip and the second copper-clad pattern, so that the current capacity and the heat dissipation efficiency of the power module are greatly improved, the process cost and the process complexity are greatly reduced, and the product yield is improved.

Description

Power module and preparation method thereof
Technical Field
The embodiment of the invention relates to the technical field of electronic devices, in particular to a power module and a preparation method thereof.
Background
The power module is used as a core energy conversion part of the electric automobile, has high cost ratio, has great influence on the power performance and economy of the whole automobile, and plays a very important role in the technical field of automobile power electronics. The power module is also widely applied to industries such as photovoltaic, energy storage, industrial frequency conversion and the like, and has wide market prospect.
The application of the electric automobile power module is towards the trend of high power density and small volume, and SiCNOSFETs replace the traditional Si-IGBT and are increasingly applied to the electric automobile power module. In the existing electric automobile power module, the connection between the grid electrode and the source electrode between SiCNOSFET chips and between the chips and the copper-clad layer of the lining plate is realized in a lead bonding mode, so that larger parasitic inductance is brought, meanwhile, the current capacity is weaker, and the heat dissipation efficiency is poorer.
Disclosure of Invention
The invention provides a power module and a preparation method thereof, wherein a bonding copper sheet is used for connecting a SiCNOSFET chip and a copper-clad layer of a lining plate, so that parasitic inductance is reduced, and current capacity and heat dissipation efficiency are enhanced.
In a first aspect, an embodiment of the present invention provides a power module, including a plurality of groups of bridge arms, each group of bridge arms including a plurality of SiCMOSFET chips; the power module further includes: a plurality of bonding copper sheets, a lining copper layer, a ceramic lining board, a heat dissipation bottom plate and a metal terminal; the ceramic lining plate and the radiating bottom plate are arranged in a stacked mode, and the copper-clad layer of the lining plate is positioned on one side, far away from the radiating bottom plate, of the ceramic lining plate; the SiCNOSFET chip is arranged on the surface of one side of the copper-clad layer of the lining board, which is far away from the ceramic lining board; the lining plate copper-clad layer comprises a first copper-clad pattern and a second copper-clad pattern, and the first copper-clad pattern and the second copper-clad pattern are mutually insulated; the first surface of the SiCNOSFET chip is connected with the first copper-clad pattern, and the second surface of the SiCNOSFET chip is connected with the second copper-clad pattern through the bonding copper sheet; the metal terminal is electrically connected with the second copper-clad pattern.
Optionally, each group of bridge arms comprises an upper bridge SiCMOSFET chip and a lower bridge SiCMOSFET chip which are connected in series, the upper bridge SiCMOSFET chips in different groups of bridge arms are connected in parallel, and the lower bridge SiCMOSFET chips in different groups of bridge arms are connected in parallel;
the upper SiCNOSFET chips in each group of bridge arms and the lower SiCNOSFET chips in each group of bridge arms are arranged in an array;
the first copper-clad pattern comprises a first copper-clad sub-pattern and a second copper-clad sub-pattern; the second copper-clad pattern comprises a third copper-clad sub-pattern and a fourth copper-clad sub-pattern; the first surface of the upper bridge SiCNOSFET chip is connected with the first copper-clad sub-pattern, and the second surface of the upper bridge SiCNOSFET chip is connected with the third copper-clad sub-pattern through the bonding copper sheet; the first surface of the lower bridge SiCNOSFET chip is connected with the second copper-clad sub-pattern; and the second surface of the lower bridge SiCNMOSFET chip is connected with the fourth copper-clad sub-pattern through the bonding copper sheet.
Optionally, the bonding copper sheet includes connection branch, arch branch and draws forth the branch, connection branch with SiCNOSFET chip is connected, adjacent connection branch or connection branch with draw forth the branch and pass through arch branch links to each other.
Optionally, the bonding copper sheet comprises a first bonding copper sheet and a second bonding copper sheet, the first copper sheet comprises one extraction subsection, and the extraction subsection is connected with the third copper-clad sub-pattern; the second copper sheet comprises two leading-out subsections, and the two leading-out subsections are respectively connected with the first copper-clad sub-pattern and the fourth copper-clad sub-pattern.
Optionally, the metal terminal includes a power terminal, the power terminal includes a direct current terminal and an alternating current terminal, the direct current terminal and the alternating current terminal set up respectively in the power module is along the both sides that deviate from each other of first direction.
Optionally, the direct current terminals include one direct current negative electrode terminal and two direct current positive electrode terminals arranged in the second direction, and the two direct current positive electrode terminals are respectively located at two sides of the direct current negative electrode terminal; the first direction and the second direction are two directions which are parallel to the plane of the substrate copper-clad layer and perpendicular to each other.
Optionally, the metal terminal further includes a signal terminal disposed on the same side of the ac terminal relative to the power module in the first direction.
Optionally, one side of the heat dissipation bottom plate, which is close to the ceramic lining plate, is provided with a plurality of elliptical cooling pin fins arranged in an array manner, and the projection of the SiCMOSFET chip on the heat dissipation bottom plate is located in the area where the plurality of elliptical cooling pin fins are located.
Optionally, the plurality of elliptical cooling pin fins are divided into two elliptical cooling pin fin groups which are arranged side by side, the projection of the upper bridge SiCMOS chip on the heat dissipation bottom plate is located in the area where the first elliptical cooling pin fin group is located, and the projection of the lower bridge SiCMOS chip on the heat dissipation bottom plate is located in the area where the second elliptical cooling pin fin group is located.
In a second aspect, an embodiment of the present invention further provides a method for manufacturing a power module, which is applied to the power module according to any one of the first aspect of the present invention, including:
fixing the radiating bottom plate on one side of the ceramic lining plate;
forming a lining plate copper-clad layer on the surface of one side of the ceramic lining plate far away from the radiating bottom plate, wherein the lining plate copper-clad layer comprises a first copper-clad pattern and a second copper-clad pattern, and the first copper-clad pattern and the second copper-clad pattern are mutually insulated;
a plurality of groups of bridge arms are arranged on one side, far away from the ceramic lining plate, of the lining plate copper-clad layer, each group of bridge arms comprises a plurality of SiCNMOSFET chips, so that the first surface of each SiCNMOSFET chip is connected to the first copper-clad pattern, and the second surface of each SiCNMOSFET chip is connected with the second copper-clad pattern through the bonding copper sheet; the metal terminal is electrically connected with the second copper-clad pattern.
Optionally, a copper-clad layer is formed on a surface of a side of the ceramic liner away from the heat dissipation bottom plate, including:
forming a whole copper-clad substrate layer on the surface of one side of the ceramic lining plate, which is far away from the radiating bottom plate;
and etching the copper-clad layer of the lining plate to form the first copper-clad pattern and the second copper-clad pattern.
The embodiment of the invention provides a power module and a preparation method thereof, wherein the power module comprises a plurality of groups of bridge arms, and each group of bridge arms comprises a plurality of SiCMOSFET chips; the power module further includes: a plurality of bonding copper sheets, a lining copper layer, a ceramic lining board, a heat dissipation bottom plate and a metal terminal; the ceramic lining plate and the radiating bottom plate are arranged in a lamination way, and the copper-clad layer of the lining plate is positioned on one side of the ceramic lining plate far away from the radiating bottom plate; the SiCNOSFET chip is arranged on the surface of one side of the copper-clad layer of the lining board, which is far away from the ceramic lining board; the lining plate copper-clad layer comprises a first copper-clad pattern and a second copper-clad pattern, and the first copper-clad pattern and the second copper-clad pattern are mutually insulated; the first surface of the SiCMOSFET chip is connected with the first copper-clad pattern, and the second surface of the SiCMOSFET chip is connected with the second copper-clad pattern through a bonding copper sheet; the metal terminal is electrically connected with the second copper-clad pattern; according to the technical scheme provided by the embodiment of the invention, one surface of the SiCNOSFET chip is directly connected to the first copper-clad pattern of the lining plate copper-clad layer, and the bonding copper sheet is used for connecting the SiCNOSFET chip and the second copper-clad pattern, so that the current capacity and the heat dissipation efficiency of the power module are greatly improved, the process cost and the process complexity are greatly reduced, and the product yield is improved.
Drawings
Fig. 1 is a schematic structural diagram of a power module according to an embodiment of the present invention;
FIG. 2 is an overall view of a power module provided by an embodiment of the present invention;
FIG. 3 is a side view of a power module according to an embodiment of the present invention;
FIG. 4 is a schematic structural view of a first bonding copper sheet according to an embodiment of the present invention;
FIG. 5 is a schematic view of a second bonding copper sheet according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a single bridge arm circuit of a power module according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a heat dissipation base plate according to an embodiment of the present invention;
FIG. 8 is an overall view of a heat dissipating base plate provided by an embodiment of the present invention;
fig. 9 is a flowchart of a method for manufacturing a power module according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. It should be noted that, the terms "upper", "lower", "left", "right", and the like in the embodiments of the present invention are described in terms of the angles shown in the drawings, and should not be construed as limiting the embodiments of the present invention. In addition, in the context, it will also be understood that when an element is referred to as being formed "on" or "under" another element, it can be directly formed "on" or "under" the other element or be indirectly formed "on" or "under" the other element through intervening elements. The terms "first," "second," and the like, are used for descriptive purposes only and not for any order, quantity, or importance, but rather are used to distinguish between different components. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
The term "comprising" and variants thereof as used herein is intended to be open ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment".
It should be noted that the terms "first," "second," and the like herein are merely used for distinguishing between corresponding contents and not for defining a sequential or interdependent relationship.
It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those skilled in the art will appreciate that "one or more" is intended to be construed as "one or more" unless the context clearly indicates otherwise.
Fig. 1 is a schematic structural diagram of a power module according to an embodiment of the present invention, and fig. 2 is an overall view of a power module according to an embodiment of the present invention, and referring to fig. 1 and fig. 2, the power module includes multiple groups of bridge arms, each group of bridge arms including multiple SiCMOSFET chips 20; fig. 3 is a side view of a power module according to an embodiment of the present invention, and referring to fig. 1 to fig. 3, the power module further includes: a plurality of bonding copper sheets 30, a backing copper layer 40, a ceramic backing 50, a heat dissipating base 60, and metal terminals 70; the ceramic lining plate 30 and the heat dissipation base plate 60 are arranged in a stacked manner, and the lining plate copper-clad layer 40 is positioned on one side of the ceramic lining plate 50 away from the heat dissipation base plate 60; the SiCNOSFET chip 20 is arranged on one side surface of the lining copper-clad layer 40 away from the ceramic lining 50; the liner copper-clad layer 40 includes a first copper-clad pattern 41 and a second copper-clad pattern 42, the first copper-clad pattern 41 and the second copper-clad pattern 42 being insulated from each other; the first surface of the SiCNOSFET chip 20 is connected with the first copper-clad pattern 41, and the second surface of the SiCNOSFET chip 20 is connected with the second copper-clad pattern 42 through the bonding copper sheet 30; the metal terminal 70 is electrically connected to the second copper-clad pattern 42.
Specifically, referring to fig. 1 and 2, the liner copper-clad layer 40 includes a first copper-clad pattern 41 and a second copper-clad pattern 42 insulated from each other, the metal terminal 70 is electrically connected to the second copper-clad pattern 42, the first surface of the SiCMOSFET chip 20 is connected to the first copper-clad pattern 41, and the second surface of the SiCMOSFET chip 20 is connected to the second copper-clad pattern 42 through the bonding copper sheet 30; in an embodiment of the present invention, the drain electrode of the SiCMOSFET chip 20 is located on the first surface thereof, the source electrode and the gate electrode are located on the second surface thereof, and the first copper-clad pattern 41 connected to the SiCMOSFET chip 20 and the second copper-clad pattern 42 connected to the metal terminal 70 are connected by the bonding copper sheet 30, so that the metal terminal 70 is electrically connected to the SiCMOSFET chip 20, so as to input a dc signal to the plurality of bridge arm circuits and input an ac signal to the load through the metal terminal 70. Alternatively, the first surface of the SiCMOSFET die 20 may be connected to the first copper-clad pattern 41 by a nano silver sintering process, and the metal terminal 70 is made of copper metal and may be connected to the second copper-clad pattern 42 by laser welding, ultrasonic welding, or the like, which is not limited in the embodiment of the present invention.
In an embodiment of the present invention, the ceramic lining plate 50 is made of an aluminum nitride ceramic plate, the lining plate copper-clad layer 40 and the aluminum nitride ceramic plate are connected by adopting a titanium-containing active brazing paste, the lower surface of the aluminum nitride ceramic plate is directly connected with the upper surface of the heat dissipation bottom plate 60 by adopting a lead-free solder, sintering, soldering and other modes, compared with the similar products, a lining plate copper-clad layer and a welding layer are reduced, the overall thermal resistance of the power module is greatly reduced, meanwhile, the process links are further reduced, and the process cost is reduced.
The power module provided by the embodiment of the invention comprises a plurality of groups of bridge arms, wherein each group of bridge arms comprises a plurality of SiCNOSFET chips; the power module further includes: a plurality of bonding copper sheets, a lining copper layer, a ceramic lining board, a heat dissipation bottom plate and a metal terminal; the ceramic lining plate and the radiating bottom plate are arranged in a lamination way, and the copper-clad layer of the lining plate is positioned on one side of the ceramic lining plate far away from the radiating bottom plate; the SiCNOSFET chip is arranged on the surface of one side of the copper-clad layer of the lining board, which is far away from the ceramic lining board; the lining plate copper-clad layer comprises a first copper-clad pattern and a second copper-clad pattern, and the first copper-clad pattern and the second copper-clad pattern are mutually insulated; the first surface of the SiCMOSFET chip is connected with the first copper-clad pattern, and the second surface of the SiCMOSFET chip is connected with the second copper-clad pattern through a bonding copper sheet; the metal terminal is electrically connected with the second copper-clad pattern; according to the technical scheme provided by the embodiment of the invention, one surface of the SiCNOSFET chip is directly connected to the first copper-clad pattern of the lining plate copper-clad layer, and the bonding copper sheet is used for connecting the SiCNOSFET chip and the second copper-clad pattern, so that the current capacity and the heat dissipation efficiency of the power module are greatly improved, the process cost and the process complexity are greatly reduced, and the product yield is improved.
In an embodiment of the present invention, referring to fig. 2, each set of bridge arms includes an upper bridge SiCMOSFET chip 21 and a lower bridge SiCMOSFET chip 22 connected in series, the upper bridge SiCMOSFET chips 21 in different sets of bridge arms are connected in parallel, and the lower bridge SiCMOSFET chips 22 in different sets of bridge arms are connected in parallel; the upper SiCNOSFET chips 21 in each group of bridge arms and the lower SiCNOSFET chips 22 in each group of bridge arms are arranged in an array; the first copper-clad pattern 41 includes a first copper-clad sub-pattern 411 and a second copper-clad sub-pattern 412; the second copper-clad pattern 42 includes a third copper-clad sub-pattern 421 and a fourth copper-clad sub-pattern 422; the first surface of the upper bridge SiCNOSFET chip 21 is connected with the first copper-clad sub-pattern 411, and the second surface of the upper bridge SiCNOSFET chip is connected with the third copper-clad sub-pattern 421 through the bonding copper sheet 30; the first surface of the lower bridge SiCMOSFET die 22 is connected to the second copper clad sub-pattern 412; the second surface of the lower bridge SiCMOSFET die 22 is connected to the fourth copper clad sub-pattern 422 by a bonding copper sheet 30.
Fig. 4 is a schematic structural diagram of a first bonding copper sheet according to an embodiment of the present invention, where the bonding copper sheet 30 includes a connection portion 31, an arch portion 32, and an extraction portion 33, the connection portion 31 is connected to the SiCMOSFET chip 20, and adjacent connection portions or connection portions are connected to the extraction portion through the arch portion. The bonding copper sheet 30 comprises a first bonding copper sheet 301 and a second bonding copper sheet 302, referring to fig. 1 and 4, the first bonding copper sheet 301 comprises an extraction portion 33, and the extraction portion 33 is connected with a third copper-clad sub-pattern 421; fig. 5 is a schematic structural diagram of a second bonding copper sheet according to an embodiment of the present invention, referring to fig. 1 and 5, the second bonding copper sheet 302 includes two lead-out portions 33, and the two lead-out portions 33 are respectively connected to the first copper-clad sub-pattern 411 and the fourth copper-clad sub-pattern 422.
The metal terminal 70 includes a power terminal 71, the power terminal 71 includes a dc terminal 711 and an ac terminal 712, the dc terminal 711 and the ac terminal 712 are respectively disposed on two sides of the power module along the first direction x, the dc terminal 711 includes one dc negative terminal 7112 and two dc positive terminals 7111 arranged in the second direction y, and the two dc positive terminals 7111 are respectively disposed on two sides of the dc negative terminal 7111; the first direction x and the second direction y are two directions which are parallel to the plane of the copper-clad layer of the substrate and perpendicular to each other. The metal terminal 70 further includes a signal terminal 72, and the signal terminal 72 is disposed at the same side of the ac terminal 712 with respect to the power module in the first direction x to input a control signal and output a detection signal.
Specifically, the first surface of the upper bridge SiCMOSFET chip 21 in a set of bridge arms is connected to the first copper-clad sub-pattern 411, and the second surface of the upper bridge SiCMOSFET chip 21 is connected to the third copper-clad sub-pattern 421 through the first bonding copper sheet 301; the third copper-clad sub-pattern 421 is electrically connected to the dc positive terminal 7111 such that one end of the upper bridge SiCMOSFET chip 21 is electrically connected to the dc positive terminal 7111; the first surface of the lower bridge SiCMOSFET die 22 is connected to the second copper clad sub-pattern 412; the first copper-clad sub-pattern 411 and the second copper-clad sub-pattern 412 are connected through the second bonding copper sheet 302, so that the upper bridge SiCMOSFET chip 21 and the lower bridge SiCMOSFET chip 22 are connected in series, the second surface of the lower bridge SiCMOSFET chip 22 is connected with the fourth copper-clad sub-pattern 422 through the bonding copper sheet 30, the fourth copper-clad sub-pattern 422 is electrically connected with the dc negative terminal 7112, so that the other end of the upper bridge SiCMOSFET chip 21 is electrically connected with the dc negative terminal 7112, thereby forming a single bridge arm circuit, and fig. 6 is a schematic diagram of a single bridge arm circuit of a power module according to the embodiment of the present invention, and referring to fig. 6, the upper bridge SiCMOSFET chip 21 and the lower bridge SiCMOSFET chip 22 are connected in series between the dc positive terminal 7111 and the dc negative terminal 7112 to input dc signals to the multi-group bridge arm circuit, and the lead-out terminal between the upper bridge SiCMOSFET chip 21 and the lower bridge SiCMOSFET chip 22 is connected with the ac terminal 712 to input ac signals to a load.
Fig. 7 is a schematic structural diagram of a heat dissipation base plate according to an embodiment of the present invention, and fig. 8 is an overall view of a heat dissipation base plate according to an embodiment of the present invention, referring to fig. 7 and 8, a plurality of elliptical cooling pin fins 601 arranged in an array are disposed on a side of the heat dissipation base plate 60 close to the ceramic liner 50, and a projection of the sicmosfet chip 20 on the heat dissipation base plate 60 is located in a region where the plurality of elliptical cooling pin fins 601 are located.
In an embodiment of the present invention, the plurality of elliptical cooling pin fins 601 are divided into a first elliptical cooling pin fin group 61 and a second elliptical cooling pin fin group 62 that are arranged side by side, the projection of the upper bridge SiCMOSFET chip 21 on the heat dissipation base 60 is located in the area where the first elliptical cooling pin fin group 61 is located, and the projection of the lower bridge SiCMOSFET chip 22 on the heat dissipation base 60 is located in the area where the second elliptical cooling pin fin group 62 is located.
Specifically, by introducing the cooling liquid into the plurality of elliptical cooling pin fins 601 to achieve the cooling effect, the cooling liquid flows in from the dc terminal side of the power module, flows through the two elliptical cooling pin fin group areas and flows towards the ac terminal side at the same time, the projection of the SiCMOSFET chip 20 on the heat dissipation bottom plate 60 is located in the area where the plurality of elliptical cooling pin fins are located, the cooling liquid flow rate in the area is increased according to the flow tube continuity equation, the heat dissipation efficiency of the SiCMOSFET chip is increased, and compared with the similar product, the module temperature is more uniform.
Fig. 9 is a flowchart of a method for manufacturing a power module according to an embodiment of the present invention, and referring to fig. 9, the method includes:
s110, fixing the heat dissipation bottom plate on one side of the ceramic lining plate.
S120, forming a lining board copper-clad layer on the surface of one side of the ceramic lining board, which is far away from the radiating bottom board, wherein the lining board copper-clad layer comprises a first copper-clad pattern and a second copper-clad pattern, and the first copper-clad pattern and the second copper-clad pattern are mutually insulated.
Specifically, an aluminum nitride ceramic lining plate is fixed on a special fixture, active metal brazing material is printed on the upper surface of the aluminum nitride ceramic lining plate through a screen printing process, then the fixture is turned over, screen printing of the active metal brazing material is carried out on the lower surface of the aluminum nitride ceramic lining plate, the aluminum nitride ceramic lining plate is placed on the upper surface of a copper radiating bottom plate, a lining plate copper-clad layer is placed on the upper surface of the aluminum nitride ceramic lining plate, the aluminum nitride ceramic lining plate enters a vacuum sintering furnace, diffusion pumping is carried out in low vacuum, the vacuum degree reaches a preset value, a diffusion pump starts to heat, after the diffusion pump is heated to a preset temperature, high vacuum is pumped, sintering is started after the preset vacuum degree is reached, and nitrogen is filled into a heat exchanger for forced cooling after sintering is completed. It should be noted that in other embodiments of the present invention, the copper-clad backing plate may also be connected to the ceramic backing plate by eutectic bonding; the ceramic lining plate can also be connected with the heat dissipation base plate by adopting lead-free solder, sintering, soldering and other modes, and the embodiment of the invention is not limited to the above.
S130, arranging a plurality of groups of bridge arms on one side of the copper-clad layer of the lining plate, which is far away from the ceramic lining plate, wherein each group of bridge arms comprises a plurality of SiCNOSFET chips, so that the first surface of each SiCNOSFET chip is connected to the first copper-clad pattern, and the second surface of each SiCNOSFET chip is connected with the second copper-clad pattern through a bonding copper sheet; the metal terminal is electrically connected with the second copper-clad pattern.
Specifically, a first copper-clad pattern on one side surface of the copper-clad layer of the lining plate, which is far away from the ceramic lining plate, is connected with the first surfaces of the SiCMOSFET chips of a plurality of groups of bridge arms by adopting a nano silver sintering process, and a bonding copper sheet is connected with the second surface of the SiCMOSFET chip and the second copper-clad pattern by adopting a vacuum reflow soldering process, so that the SiCMOSFET chip is electrically connected with a metal terminal, and can receive an electric signal input by the metal terminal; in other embodiments of the present invention, the second surface of the SiCMOSFET die and the second copper-clad pattern may also be connected by means of lead-free solder, vacuum reflow, nano-silver sintering, etc., which embodiments of the present invention are not limited thereto.
According to the preparation method of the power module, firstly, a radiating bottom plate is fixed on one side of a ceramic lining plate, then a lining plate copper-clad layer is formed on the surface of one side, far away from the radiating bottom plate, of the ceramic lining plate, the lining plate copper-clad layer comprises a first copper-clad pattern and a second copper-clad pattern, the first copper-clad pattern and the second copper-clad pattern are mutually insulated, finally, a plurality of groups of bridge arms are arranged on one side, far away from the ceramic lining plate, of the lining plate copper-clad layer, each group of bridge arms comprises a plurality of SiCMOSFET chips, so that the first surface of the SiCMOSFET chips is connected to the first copper-clad pattern, and the second surface of the SiCMOSFET chips is connected with the second copper-clad pattern through a bonding copper sheet; the metal terminal is electrically connected with the second copper-clad pattern, so that the through-flow capacity and the heat dissipation efficiency of the connection are greatly improved, the process cost and the process complexity are greatly reduced, and the product yield is improved.
Optionally, in step S120, forming a copper-clad layer on a surface of the ceramic liner away from the heat dissipation base plate, including:
forming a whole copper-clad substrate layer on the surface of one side of the ceramic lining plate, which is far away from the radiating bottom plate;
and etching the copper-clad layer of the lining plate to form a first copper-clad pattern and a second copper-clad pattern.
Specifically, since the SiCMOSFET chip and the metal terminal are connected to different areas of the copper-clad layer of the liner, the copper-clad layer of the liner needs to be etched to form a first copper-clad pattern connected to the SiCMOSFET chip and a second copper-clad pattern connected to the metal terminal, specifically, the aluminum nitride ceramic liner is fixed on a special fixture, and the surface of the copper-clad layer of the liner is subjected to one copper etching and then to one titanium nitride etching.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims (11)

1. The power module is characterized by comprising a plurality of groups of bridge arms, wherein each group of bridge arms comprises a plurality of SiCNOSFET chips;
the power module further includes: a plurality of bonding copper sheets, a lining copper layer, a ceramic lining board, a heat dissipation bottom plate and a metal terminal; the ceramic lining plate and the radiating bottom plate are arranged in a stacked mode, and the copper-clad layer of the lining plate is positioned on one side, far away from the radiating bottom plate, of the ceramic lining plate; the SiCNOSFET chip is arranged on the surface of one side of the copper-clad layer of the lining board, which is far away from the ceramic lining board;
the lining plate copper-clad layer comprises a first copper-clad pattern and a second copper-clad pattern, and the first copper-clad pattern and the second copper-clad pattern are mutually insulated;
the first surface of the SiCNOSFET chip is connected with the first copper-clad pattern, and the second surface of the SiCNOSFET chip is connected with the second copper-clad pattern through the bonding copper sheet; the metal terminal is electrically connected with the second copper-clad pattern.
2. The power module of claim 1 wherein each set of legs includes upper and lower SiCMOSFET chips connected in series with each other, the upper SiCMOSFET chips in different sets of legs being connected in parallel with each other, the lower SiCMOSFET chips in different sets of legs being connected in parallel with each other;
the upper SiCNOSFET chips in each group of bridge arms and the lower SiCNOSFET chips in each group of bridge arms are arranged in an array;
the first copper-clad pattern comprises a first copper-clad sub-pattern and a second copper-clad sub-pattern; the second copper-clad pattern comprises a third copper-clad sub-pattern and a fourth copper-clad sub-pattern; the first surface of the upper bridge SiCNOSFET chip is connected with the first copper-clad sub-pattern, and the second surface of the upper bridge SiCNOSFET chip is connected with the third copper-clad sub-pattern through the bonding copper sheet; the first surface of the lower bridge SiCNOSFET chip is connected with the second copper-clad sub-pattern; and the second surface of the lower bridge SiCNMOSFET chip is connected with the fourth copper-clad sub-pattern through the bonding copper sheet.
3. The power module of claim 2 wherein the bonding copper sheet comprises a connection section, an arch section and an extraction section, the connection section being connected to the SiCMOSFET chip, adjacent the connection section or connection section being connected to the extraction section by the arch section.
4. The power module of claim 3 wherein the bonding copper sheets include a first bonding copper sheet and a second bonding copper sheet, the first copper sheet including one of the lead-out sections, the lead-out section being connected to the third copper-clad sub-pattern; the second copper sheet comprises two leading-out subsections, and the two leading-out subsections are respectively connected with the first copper-clad sub-pattern and the fourth copper-clad sub-pattern.
5. The power module of claim 1, wherein the metal terminals comprise power terminals, the power terminals comprise direct current terminals and alternating current terminals, the direct current terminals and the alternating current terminals are respectively disposed on two sides of the power module facing away from each other in a first direction.
6. The power module of claim 5, wherein the dc terminals include one dc negative terminal and two dc positive terminals arranged in a second direction, the two dc positive terminals being located on either side of the dc negative terminal; the first direction and the second direction are two directions which are parallel to the plane of the substrate copper-clad layer and perpendicular to each other.
7. The power module of claim 5, wherein the metal terminals further comprise signal terminals disposed on a same side of the ac terminals relative to the power module in the first direction.
8. The power module of claim 2, wherein a plurality of elliptical cooling pin fins arranged in an array are arranged on a side of the heat dissipation base plate, which is close to the ceramic lining plate, and the projection of the SiCMOSFET chip on the heat dissipation base plate is located in the area where the plurality of elliptical cooling pin fins are located.
9. The power module of claim 8 wherein the plurality of elliptical cooling pin fins is divided into two elliptical cooling pin fin groups disposed side by side, wherein a projection of the upper bridge SiCMOSFET die on the heat sink base plate is located in a region of a first elliptical cooling pin fin group, and wherein a projection of the lower bridge SiCMOSFET die on the heat sink base plate is located in a region of a second elliptical cooling pin fin group.
10. A method for manufacturing a power module according to any one of claims 1 to 9, comprising:
fixing the radiating bottom plate on one side of the ceramic lining plate;
forming a lining plate copper-clad layer on the surface of one side of the ceramic lining plate far away from the radiating bottom plate, wherein the lining plate copper-clad layer comprises a first copper-clad pattern and a second copper-clad pattern, and the first copper-clad pattern and the second copper-clad pattern are mutually insulated;
a plurality of groups of bridge arms are arranged on one side, far away from the ceramic lining plate, of the lining plate copper-clad layer, each group of bridge arms comprises a plurality of SiCNMOSFET chips, so that the first surface of each SiCNMOSFET chip is connected to the first copper-clad pattern, and the second surface of each SiCNMOSFET chip is connected with the second copper-clad pattern through the bonding copper sheet; the metal terminal is electrically connected with the second copper-clad pattern.
11. The method of claim 10, wherein forming a copper clad liner on a surface of the ceramic liner on a side of the ceramic liner remote from the heat sink base plate comprises:
forming a whole copper-clad substrate layer on the surface of one side of the ceramic lining plate, which is far away from the radiating bottom plate;
and etching the copper-clad layer of the lining plate to form the first copper-clad pattern and the second copper-clad pattern.
CN202310742193.7A 2023-06-21 2023-06-21 Power module and preparation method thereof Pending CN116666370A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117577610A (en) * 2024-01-17 2024-02-20 中国第一汽车股份有限公司 Power module and signal processing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117577610A (en) * 2024-01-17 2024-02-20 中国第一汽车股份有限公司 Power module and signal processing method

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